diff --git a/ch32v003fun/ch32v003fun.c b/ch32v003fun/ch32v003fun.c
index 0ef8f65816ec975fbd22cbf5114c5862de09c5fe..199fba79035d0ab4bc28eea12491a684384c99b7 100644
--- a/ch32v003fun/ch32v003fun.c
+++ b/ch32v003fun/ch32v003fun.c
@@ -807,10 +807,10 @@ asm volatile(
 void SystemInit48HSI( void )
 {
 	// Values lifted from the EVT.  There is little to no documentation on what this does.
-	RCC->CFGR0 = RCC_HPRE_DIV1 | RCC_PLLSRC_HSI_Mul2;     // PLLCLK = HSI * 2 = 48 MHz; HCLK = SYSCLK = APB1
-	RCC->CTLR  |= RCC_HSION | RCC_PLLON | (3 << HSITRIM); // Use HSI, but enable PLL.
-	FLASH->ACTLR = FLASH_ACTLR_LATENCY_1;                 // 1 Cycle Latency
-	RCC->INTR  = 0x009F0000;                              // Clear PLL, CSSC, HSE, HSI and LSI ready flags.
+	RCC->CFGR0 = RCC_HPRE_DIV1 | RCC_PLLSRC_HSI_Mul2;    // PLLCLK = HSI * 2 = 48 MHz; HCLK = SYSCLK = APB1
+	RCC->CTLR  = RCC_HSION | RCC_PLLON | (3 << HSITRIM); // Use HSI, but enable PLL.
+	FLASH->ACTLR = FLASH_ACTLR_LATENCY_1;                // 1 Cycle Latency
+	RCC->INTR  = 0x009F0000;                             // Clear PLL, CSSC, HSE, HSI and LSI ready flags.
 
 	// From SetSysClockTo_48MHZ_HSI
 	while((RCC->CTLR & RCC_PLLRDY) == 0);                                      // Wait till PLL is ready