From 012aabdbf310ff6f6fdb592a1dfce92a5c86c205 Mon Sep 17 00:00:00 2001
From: Carsten Thiele <software@carsten-thiele.de>
Date: Tue, 21 Mar 2023 22:34:01 +0100
Subject: [PATCH] configurable HSITRIM value in SystemInit48HSI()
---
ch32v003fun/ch32v003fun.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/ch32v003fun/ch32v003fun.c b/ch32v003fun/ch32v003fun.c
index 0ef8f65..199fba7 100644
--- a/ch32v003fun/ch32v003fun.c
+++ b/ch32v003fun/ch32v003fun.c
@@ -807,10 +807,10 @@ asm volatile(
void SystemInit48HSI( void )
{
// Values lifted from the EVT. There is little to no documentation on what this does.
- RCC->CFGR0 = RCC_HPRE_DIV1 | RCC_PLLSRC_HSI_Mul2; // PLLCLK = HSI * 2 = 48 MHz; HCLK = SYSCLK = APB1
- RCC->CTLR |= RCC_HSION | RCC_PLLON | (3 << HSITRIM); // Use HSI, but enable PLL.
- FLASH->ACTLR = FLASH_ACTLR_LATENCY_1; // 1 Cycle Latency
- RCC->INTR = 0x009F0000; // Clear PLL, CSSC, HSE, HSI and LSI ready flags.
+ RCC->CFGR0 = RCC_HPRE_DIV1 | RCC_PLLSRC_HSI_Mul2; // PLLCLK = HSI * 2 = 48 MHz; HCLK = SYSCLK = APB1
+ RCC->CTLR = RCC_HSION | RCC_PLLON | (3 << HSITRIM); // Use HSI, but enable PLL.
+ FLASH->ACTLR = FLASH_ACTLR_LATENCY_1; // 1 Cycle Latency
+ RCC->INTR = 0x009F0000; // Clear PLL, CSSC, HSE, HSI and LSI ready flags.
// From SetSysClockTo_48MHZ_HSI
while((RCC->CTLR & RCC_PLLRDY) == 0); // Wait till PLL is ready
--
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