diff --git a/barebones/Makefile b/blink/Makefile
similarity index 93%
rename from barebones/Makefile
rename to blink/Makefile
index 3f68c644f4c2c6697cd684611c0429b0e2437ffd..e38c49b49748f97a3f00922b5aa9185e19a452da 100644
--- a/barebones/Makefile
+++ b/blink/Makefile
@@ -1,4 +1,4 @@
-TARGET:=barebones
+TARGET:=blink
all : flash
@@ -22,7 +22,7 @@ LDFLAGS:=-T $(EVT)/ch32v003.ld -Wl,--gc-sections
SYSTEM_C:=$(EVT)/startup_ch32v00x.S $(EVT)/embedlibc.c
-$(TARGET).elf : barebones.c $(SYSTEM_C)
+$(TARGET).elf : $(TARGET).c $(SYSTEM_C)
$(PREFIX)-gcc -o $@ $^ $(CFLAGS) $(LDFLAGS)
$(TARGET).bin : $(TARGET).elf
diff --git a/blink/blink.c b/blink/blink.c
new file mode 100644
index 0000000000000000000000000000000000000000..22d54e504a04ad597c5761b1e36ea466034e632d
--- /dev/null
+++ b/blink/blink.c
@@ -0,0 +1,46 @@
+// Could be defined here, or in the processor defines.
+#define SYSTEM_CORE_CLOCK 48000000
+
+#include "ch32v00x.h"
+#include <stdio.h>
+
+#define APB_CLOCK SYSTEM_CORE_CLOCK
+
+void SystemInit(void)
+{
+ // Values lifted from the EVT. There is little to no documentation on what this does.
+ RCC->CTLR |= (uint32_t)0x00000001;
+ RCC->CFGR0 &= (uint32_t)0xFCFF0000;
+ RCC->CTLR &= (uint32_t)0xFEF6FFFF;
+ RCC->CTLR &= (uint32_t)0xFFFBFFFF;
+ RCC->CFGR0 &= (uint32_t)0xFFFEFFFF;
+ RCC->INTR = 0x009F0000;
+
+ // From SetSysClockTo_48MHZ_HSI
+ // This is some dark stuff. But, I copy-pasted it and it seems towork.
+ FLASH->ACTLR = (FLASH->ACTLR & ((uint32_t)~FLASH_ACTLR_LATENCY)) | FLASH_ACTLR_LATENCY_1; // Flash 0 wait state
+ RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; // HCLK = SYSCLK = APB1
+ RCC->CFGR0 = ( RCC->CFGR0 & ((uint32_t)~(RCC_PLLSRC)) ) | (uint32_t)(RCC_PLLSRC_HSI_Mul2); // PLL configuration: PLLCLK = HSI * 2 = 48 MHz
+ RCC->CTLR |= RCC_PLLON; // Enable PLL
+ while((RCC->CTLR & RCC_PLLRDY) == 0); // Wait till PLL is ready
+ RCC->CFGR0 = ( RCC->CFGR0 & ((uint32_t)~(RCC_SW))) | (uint32_t)RCC_SW_PLL; // Select PLL as system clock source
+ while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08); // Wait till PLL is used as system clock source
+}
+
+int main()
+{
+ // Enable GPIOD.
+ RCC->APB2PCENR |= RCC_APB2Periph_GPIOD;
+
+ // GPIO D0 Push-Pull, 10MHz Output
+ GPIOD->CFGLR &= ~(0xf<<(4*0));
+ GPIOD->CFGLR |= (GPIO_Speed_10MHz | GPIO_CNF_OUT_PP)<<(4*0);
+
+ while(1)
+ {
+ GPIOD->BSHR = 1; // Turn on GPIOD0
+ Delay_Ms( 100 );
+ GPIOD->BSHR = 1<<16; // Turn off GPIOD0
+ Delay_Ms( 100 );
+ }
+}
diff --git a/fulldemo/Makefile b/fulldemo/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..5f1406e859a92fbee59c63590738ae19516f7d8e
--- /dev/null
+++ b/fulldemo/Makefile
@@ -0,0 +1,41 @@
+TARGET:=fulldemo
+
+all : flash
+
+PREFIX:=riscv64-unknown-elf
+
+GPIO_Toggle:=EXAM/GPIO/GPIO_Toggle/User
+
+EVT:=../ch32v003evt
+
+CFLAGS:= \
+ -g -Os -flto -ffunction-sections \
+ -static-libgcc -lgcc \
+ -march=rv32ec \
+ -mabi=ilp32e \
+ -I/usr/include/newlib \
+ -I$(EVT) \
+ -nostdlib \
+ -I.
+
+LDFLAGS:=-T $(EVT)/ch32v003.ld -Wl,--gc-sections
+
+SYSTEM_C:=$(EVT)/startup_ch32v00x.S $(EVT)/embedlibc.c
+
+$(TARGET).elf : $(TARGET).c $(SYSTEM_C)
+ $(PREFIX)-gcc -o $@ $^ $(CFLAGS) $(LDFLAGS)
+
+$(TARGET).bin : $(TARGET).elf
+ $(PREFIX)-size $^
+ $(PREFIX)-objdump -S $^ > $(TARGET).lst
+ $(PREFIX)-objdump -t $^ > $(TARGET).map
+ $(PREFIX)-objcopy -O binary $< $(TARGET).bin
+ $(PREFIX)-objcopy -O ihex $< $(TARGET).hex
+
+flash : $(TARGET).bin
+ make -C ../minichlink all
+ ../minichlink/minichlink -w $< -r
+
+clean :
+ rm -rf $(TARGET).elf $(TARGET).bin $(TARGET).hex $(TARGET).lst $(TARGET).map $(TARGET).hex
+
diff --git a/barebones/barebones.c b/fulldemo/fulldemo.c
similarity index 95%
rename from barebones/barebones.c
rename to fulldemo/fulldemo.c
index f73159450ffd90d6f94b24de1ff3c05435998310..534e97793a13d1153754865ad41aab018be16fef 100644
--- a/barebones/barebones.c
+++ b/fulldemo/fulldemo.c
@@ -20,28 +20,6 @@ int _write(int fd, char *buf, int size)
return size;
}
-static inline void ConfigureDebugUART()
-{
- // Configure UART for debugging.
-
- // Push-Pull, 10MHz Output, GPIO D5, with AutoFunction
- GPIOD->CFGLR &= ~(0xf<<(4*5));
- GPIOD->CFGLR |= (GPIO_Speed_10MHz | GPIO_CNF_OUT_PP_AF)<<(4*5);
-
- // 115200, 8n1. Note if you don't specify a mode, UART remains off even when UE_Set.
- USART1->CTLR1 = USART_WordLength_8b | USART_Parity_No | USART_Mode_Tx;
- USART1->CTLR2 = USART_StopBits_1;
- USART1->CTLR3 = USART_HardwareFlowControl_None;
-
- #define UART_BAUD_RATE 115200
- #define OVER8DIV 4
- #define INTEGER_DIVIDER (((25 * (APB_CLOCK)) / (OVER8DIV * (UART_BAUD_RATE))))
- #define FRACTIONAL_DIVIDER ((INTEGER_DIVIDER)%100)
- USART1->BRR = ((INTEGER_DIVIDER / 100) << 4) | ((((FRACTIONAL_DIVIDER * (OVER8DIV*2)) + 50)/100)&7);
- USART1->CTLR1 |= CTLR1_UE_Set;
-
-}
-
void SystemInit(void)
{
// Values lifted from the EVT. There is little to no documentation on what this does.
@@ -61,14 +39,33 @@ void SystemInit(void)
while((RCC->CTLR & RCC_PLLRDY) == 0); // Wait till PLL is ready
RCC->CFGR0 = ( RCC->CFGR0 & ((uint32_t)~(RCC_SW))) | (uint32_t)RCC_SW_PLL; // Select PLL as system clock source
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08); // Wait till PLL is used as system clock source
-}
-int main()
-{
+ // Once clock is up and running, we can enable the UART for other debugging.
+
// Enable GPIOD and UART.
RCC->APB2PCENR |= RCC_APB2Periph_GPIOD | RCC_APB2Periph_USART1;
+
+ // Push-Pull, 10MHz Output, GPIO D5, with AutoFunction
+ GPIOD->CFGLR &= ~(0xf<<(4*5));
+ GPIOD->CFGLR |= (GPIO_Speed_10MHz | GPIO_CNF_OUT_PP_AF)<<(4*5);
- ConfigureDebugUART();
+ // 115200, 8n1. Note if you don't specify a mode, UART remains off even when UE_Set.
+ USART1->CTLR1 = USART_WordLength_8b | USART_Parity_No | USART_Mode_Tx;
+ USART1->CTLR2 = USART_StopBits_1;
+ USART1->CTLR3 = USART_HardwareFlowControl_None;
+
+ #define UART_BAUD_RATE 115200
+ #define OVER8DIV 4
+ #define INTEGER_DIVIDER (((25 * (APB_CLOCK)) / (OVER8DIV * (UART_BAUD_RATE))))
+ #define FRACTIONAL_DIVIDER ((INTEGER_DIVIDER)%100)
+ USART1->BRR = ((INTEGER_DIVIDER / 100) << 4) | ((((FRACTIONAL_DIVIDER * (OVER8DIV*2)) + 50)/100)&7);
+ USART1->CTLR1 |= CTLR1_UE_Set;
+}
+
+int main()
+{
+ // Enable GPIOD.
+ RCC->APB2PCENR |= RCC_APB2Periph_GPIOD;
// GPIO D0 Push-Pull, 10MHz Output
GPIOD->CFGLR &= ~(0xf<<(4*0));