From 74f4149b2fafefa2026c25eceb83a9690d06f3be Mon Sep 17 00:00:00 2001
From: Jannis Konrad <kabel42@gmail.com>
Date: Mon, 22 May 2023 10:54:12 +0200
Subject: [PATCH] make indr read-onle, add helper helper try to mitigare weird
gcc behaviour
---
ch32v003fun/ch32v003fun.h | 230 +++++++++++++++++++-------------------
1 file changed, 117 insertions(+), 113 deletions(-)
diff --git a/ch32v003fun/ch32v003fun.h b/ch32v003fun/ch32v003fun.h
index 609791b..f2b392a 100644
--- a/ch32v003fun/ch32v003fun.h
+++ b/ch32v003fun/ch32v003fun.h
@@ -198,126 +198,130 @@ typedef struct
/* General Purpose I/O */
typedef enum
{
- GPIO_CFGLR_MODE_IN,
- GPIO_CFGLR_MODE_OUT_10MHz,
- GPIO_CFGLR_MODE_OUT_2MHz,
- GPIO_CFGLR_MODE_OUT_50MHz
+ GPIO_CFGLR_MODE_IN,
+ GPIO_CFGLR_MODE_OUT_10MHz,
+ GPIO_CFGLR_MODE_OUT_2MHz,
+ GPIO_CFGLR_MODE_OUT_50MHz
} GPIO_MODE_TypeDef;
typedef enum
{
- GPIO_CFGLR_CNF_IN_ANALOG = 0,
- GPIO_CFGLR_CNF_IN_FLOAT = 1,
- GPIO_CFGLR_CNF_IN_PULL_UP_DOWN = 2,
- GPIO_CFGLR_CNF_OUT_PP = 0,
- GPIO_CFGLR_CNF_OUT_OD = 1,
- GPIO_CFGLR_CNF_OUT_AF_PP = 2,
- GPIO_CFGLR_CNF_OUT_AF_OD = 3,
+ GPIO_CFGLR_CNF_IN_ANALOG = 0,
+ GPIO_CFGLR_CNF_IN_FLOAT = 1,
+ GPIO_CFGLR_CNF_IN_PULL_UP_DOWN = 2,
+ GPIO_CFGLR_CNF_OUT_PP = 0,
+ GPIO_CFGLR_CNF_OUT_OD = 1,
+ GPIO_CFGLR_CNF_OUT_AF_PP = 2,
+GPIO_CFGLR_CNF_OUT_AF_OD = 3,
} GPIO_CNF_TypeDef;
typedef struct
{
- __IO union {
- uint32_t CFGLR;
- struct CFGLR_t {
- GPIO_MODE_TypeDef MODE0 :2;
- GPIO_CNF_TypeDef CNF0 :2;
- GPIO_MODE_TypeDef MODE1 :2;
- GPIO_CNF_TypeDef CNF1 :2;
- GPIO_MODE_TypeDef MODE2 :2;
- GPIO_CNF_TypeDef CNF2 :2;
- GPIO_MODE_TypeDef MODE3 :2;
- GPIO_CNF_TypeDef CNF3 :2;
- GPIO_MODE_TypeDef MODE4 :2;
- GPIO_CNF_TypeDef CNF4 :2;
- GPIO_MODE_TypeDef MODE5 :2;
- GPIO_CNF_TypeDef CNF5 :2;
- GPIO_MODE_TypeDef MODE6 :2;
- GPIO_CNF_TypeDef CNF6 :2;
- GPIO_MODE_TypeDef MODE7 :2;
- GPIO_CNF_TypeDef CNF7 :2;
- } CFGLR_bits;
- };
- __IO uint32_t CFGHR;
- __IO union {
- uint32_t INDR;
- struct INDR_t {
- uint32_t IDR0 :1;
- uint32_t IDR1 :1;
- uint32_t IDR2 :1;
- uint32_t IDR3 :1;
- uint32_t IDR4 :1;
- uint32_t IDR5 :1;
- uint32_t IDR6 :1;
- uint32_t IDR7 :1;
- uint32_t :24;
- } INDR_bits;
- };
- __IO union {
- uint32_t OUTDR;
- struct OUTDR_t {
- uint32_t ODR0 :1;
- uint32_t ODR1 :1;
- uint32_t ODR2 :1;
- uint32_t ODR3 :1;
- uint32_t ODR4 :1;
- uint32_t ODR5 :1;
- uint32_t ODR6 :1;
- uint32_t ODR7 :1;
- uint32_t :24;
- } OUTDR_bits;
- };
- __IO union {
- uint32_t BSHR;
- struct BSHR_t {
- uint32_t BS0 :1;
- uint32_t BS1 :1;
- uint32_t BS2 :1;
- uint32_t BS3 :1;
- uint32_t BS4 :1;
- uint32_t BS5 :1;
- uint32_t BS6 :1;
- uint32_t BS7 :1;
- uint32_t :8;
- uint32_t BR0 :1;
- uint32_t BR1 :1;
- uint32_t BR2 :1;
- uint32_t BR3 :1;
- uint32_t BR4 :1;
- uint32_t BR5 :1;
- uint32_t BR6 :1;
- uint32_t BR7 :1;
- uint32_t :8;
- } BSHR_bits;
- };
- __IO union {
- uint32_t BCR;
- struct BCR_t {
- uint32_t BR0 :1;
- uint32_t BR1 :1;
- uint32_t BR2 :1;
- uint32_t BR3 :1;
- uint32_t BR4 :1;
- uint32_t BR5 :1;
- uint32_t BR6 :1;
- uint32_t BR7 :1;
- uint32_t :24;
- } BCR_bits;
- };
- __IO union {
- uint32_t LCKR;
- struct LCKR_t {
- uint32_t LCK0 :1;
- uint32_t LCK1 :1;
- uint32_t LCK2 :1;
- uint32_t LCK3 :1;
- uint32_t LCK4 :1;
- uint32_t LCK5 :1;
- uint32_t LCK6 :1;
- uint32_t LCK7 :1;
- uint32_t LCKK :1;
- uint32_t :23;
- } LCK_bits;
- };
+ __IO union {
+ uint32_t CFGLR;
+ struct CFGLR_t {
+ GPIO_MODE_TypeDef MODE0 :2;
+ GPIO_CNF_TypeDef CNF0 :2;
+ GPIO_MODE_TypeDef MODE1 :2;
+ GPIO_CNF_TypeDef CNF1 :2;
+ GPIO_MODE_TypeDef MODE2 :2;
+ GPIO_CNF_TypeDef CNF2 :2;
+ GPIO_MODE_TypeDef MODE3 :2;
+ GPIO_CNF_TypeDef CNF3 :2;
+ GPIO_MODE_TypeDef MODE4 :2;
+ GPIO_CNF_TypeDef CNF4 :2;
+ GPIO_MODE_TypeDef MODE5 :2;
+ GPIO_CNF_TypeDef CNF5 :2;
+ GPIO_MODE_TypeDef MODE6 :2;
+ GPIO_CNF_TypeDef CNF6 :2;
+ GPIO_MODE_TypeDef MODE7 :2;
+ GPIO_CNF_TypeDef CNF7 :2;
+ } CFGLR_bits;
+ };
+ __IO uint32_t CFGHR;
+ __IO union {
+ const uint32_t INDR;
+ const struct INDR_t {
+ uint32_t IDR0 :1;
+ uint32_t IDR1 :1;
+ uint32_t IDR2 :1;
+ uint32_t IDR3 :1;
+ uint32_t IDR4 :1;
+ uint32_t IDR5 :1;
+ uint32_t IDR6 :1;
+ uint32_t IDR7 :1;
+ uint32_t :24;
+ } INDR_bits;
+ };
+ __IO union {
+ uint32_t OUTDR;
+ struct OUTDR_t {
+ uint32_t ODR0 :1;
+ uint32_t ODR1 :1;
+ uint32_t ODR2 :1;
+ uint32_t ODR3 :1;
+ uint32_t ODR4 :1;
+ uint32_t ODR5 :1;
+ uint32_t ODR6 :1;
+ uint32_t ODR7 :1;
+ uint32_t :24;
+ } OUTDR_bits;
+ };
+ __IO union {
+ uint32_t BSHR;
+ struct BSHR_t {
+ uint32_t BS0 :1;
+ uint32_t BS1 :1;
+ uint32_t BS2 :1;
+ uint32_t BS3 :1;
+ uint32_t BS4 :1;
+ uint32_t BS5 :1;
+ uint32_t BS6 :1;
+ uint32_t BS7 :1;
+ uint32_t :8;
+ uint32_t BR0 :1;
+ uint32_t BR1 :1;
+ uint32_t BR2 :1;
+ uint32_t BR3 :1;
+ uint32_t BR4 :1;
+ uint32_t BR5 :1;
+ uint32_t BR6 :1;
+ uint32_t BR7 :1;
+ uint32_t :8;
+ } BSHR_bits;
+ };
+ __IO union {
+ uint32_t BCR;
+ struct BCR_t {
+ uint32_t BR0 :1;
+ uint32_t BR1 :1;
+ uint32_t BR2 :1;
+ uint32_t BR3 :1;
+ uint32_t BR4 :1;
+ uint32_t BR5 :1;
+ uint32_t BR6 :1;
+ uint32_t BR7 :1;
+ uint32_t :24;
+ } BCR_bits;
+ };
+ __IO union {
+ uint32_t LCKR;
+ struct LCKR_t {
+ uint32_t LCK0 :1;
+ uint32_t LCK1 :1;
+ uint32_t LCK2 :1;
+ uint32_t LCK3 :1;
+ uint32_t LCK4 :1;
+ uint32_t LCK5 :1;
+ uint32_t LCK6 :1;
+ uint32_t LCK7 :1;
+ uint32_t LCKK :1;
+ uint32_t :23;
+ } LCK_bits;
+ };
} GPIO_TypeDef;
+static inline void GPIOset(GPIO_TypeDef *gpio, uint8_t pins) {gpio->BSHR = pins;}
+static inline void GPIOreset(GPIO_TypeDef *gpio, uint8_t pins) {gpio->BCR = pins;}
+static inline void GPIOsetReset(GPIO_TypeDef *gpio, uint8_t set_pins, uint8_t reset_pins) {gpio->BSHR = set_pins|(reset_pins<<16);}
+#define DYN_GPIO_WRITE(gpio, reg, field, value) { const struct reg##_t tmp = {.##field = value ,}; gpio##->##reg = tmp;}
/* Alternate Function I/O */
typedef struct
--
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