diff --git a/EVT/Makefile b/EVT/Makefile
index 01968ca0ff1e74ebc25a2456afe962978e004526..a7938f429bba0d04cb40f9cfc528737d0ca3b3a6 100644
--- a/EVT/Makefile
+++ b/EVT/Makefile
@@ -27,7 +27,7 @@ SYSTEM_C:=EXAM/SRC/Startup/startup_ch32v00x.S \
EXAM/SRC/Peripheral/src/ch32v00x_rcc.c \
EXAM/SRC/Peripheral/src/ch32v00x_usart.c \
EXAM/SRC/Peripheral/src/ch32v00x_misc.c \
- embedlibc.c
+ ../ch32v003evt/embedlibc.c
$(TARGET).elf : $(GPIO_Toggle)/ch32v00x_it.c $(GPIO_Toggle)/main.c $(GPIO_Toggle)/system_ch32v00x.c $(SYSTEM_C)
$(PREFIX)-gcc -o $@ $^ $(CFLAGS) $(LDFLAGS)
diff --git a/barebones/Makefile b/barebones/Makefile
index 700a037bf74534da1595907735004f9f46582220..dbab07120acd8ce83e802e0c0a9e96880f2ffe4c 100644
--- a/barebones/Makefile
+++ b/barebones/Makefile
@@ -6,7 +6,7 @@ PREFIX:=riscv64-unknown-elf
GPIO_Toggle:=EXAM/GPIO/GPIO_Toggle/User
-EVT:=../ch32v003evt/
+EVT:=../ch32v003evt
CFLAGS:= \
-g -Os -flto -ffunction-sections \
@@ -18,9 +18,9 @@ CFLAGS:= \
-nostdlib \
-I.
-LDFLAGS:=-T $(EVT)/ch32v003.ld
+LDFLAGS:=-T $(EVT)/ch32v003.ld -Wl,--gc-sections
-SYSTEM_C:=$(EVT)/startup_ch32v00x.S
+SYSTEM_C:=$(EVT)/startup_ch32v00x.S $(EVT)/embedlibc.c
$(TARGET).elf : barebones.c $(SYSTEM_C)
$(PREFIX)-gcc -o $@ $^ $(CFLAGS) $(LDFLAGS)
@@ -32,7 +32,6 @@ $(TARGET).hex : $(TARGET).elf
$(PREFIX)-objcopy -O binary $< $(TARGET).bin
$(PREFIX)-objcopy -O ihex $< $@
-
flash : $(TARGET).hex
clean :
diff --git a/barebones/barebones.c b/barebones/barebones.c
index 3beba546698bbd3feb9341cbb03f20274388f1aa..3ae0efa9d57ab0380053d53fb8f0041ec791ea70 100644
--- a/barebones/barebones.c
+++ b/barebones/barebones.c
@@ -1,7 +1,50 @@
+// Really basic self-contained demo for the ch32v003
+// Doesn't rely on any of the weird HAL stuff from CH
+// Final executable is ~1/4th the size.
+
+// Could be defined here, or in the processor defines.
+#define SYSTEM_CORE_CLOCK 48000000
+
#include "ch32v00x.h"
+#include <stdio.h>
+
+#define APB_CLOCK SYSTEM_CORE_CLOCK
+
+// For debug writing to the UART.
+int _write(int fd, char *buf, int size)
+{
+ for(int i = 0; i < size; i++){
+ while( !(USART1->STATR & USART_FLAG_TC));
+ USART1->DATAR = *buf++;
+ }
+ return size;
+}
+
+static inline void ConfigureDebugUART()
+{
+ // Configure UART for debugging.
+
+ // Push-Pull, 10MHz Output, GPIO D5, with AutoFunction
+ GPIOD->CFGLR &= ~(0xf<<(4*5));
+ GPIOD->CFGLR |= (GPIO_Speed_10MHz | GPIO_CNF_OUT_PP_AF)<<(4*5);
+
+ // 115200, 8n1. Note if you don't specify a mode, UART remains off even when UE_Set.
+ USART1->CTLR1 = USART_WordLength_8b | USART_Parity_No | USART_Mode_Tx;
+ USART1->CTLR2 = USART_StopBits_1;
+ USART1->CTLR3 = USART_HardwareFlowControl_None;
+
+ #define UART_BAUD_RATE 115200
+ #define OVER8DIV 4
+ #define INTEGER_DIVIDER (((25 * (APB_CLOCK)) / (OVER8DIV * (UART_BAUD_RATE))))
+ #define FRACTIONAL_DIVIDER ((INTEGER_DIVIDER)%100)
+ USART1->BRR = ((INTEGER_DIVIDER / 100) << 4) | ((((FRACTIONAL_DIVIDER * (OVER8DIV*2)) + 50)/100)&7);
+ USART1->CTLR1 |= CTLR1_UE_Set;
+
+}
void SystemInit(void)
{
+ // Values lifted from the EVT. There is little to no documentation on what this does.
RCC->CTLR |= (uint32_t)0x00000001;
RCC->CFGR0 &= (uint32_t)0xFCFF0000;
RCC->CTLR &= (uint32_t)0xFEF6FFFF;
@@ -10,6 +53,7 @@ void SystemInit(void)
RCC->INTR = 0x009F0000;
// From SetSysClockTo_48MHZ_HSI
+ // This is some dark stuff. But, I copy-pasted it and it seems towork.
FLASH->ACTLR = (FLASH->ACTLR & ((uint32_t)~FLASH_ACTLR_LATENCY)) | FLASH_ACTLR_LATENCY_1; // Flash 0 wait state
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; // HCLK = SYSCLK = APB1
RCC->CFGR0 = ( RCC->CFGR0 & ((uint32_t)~(RCC_PLLSRC)) ) | (uint32_t)(RCC_PLLSRC_HSI_Mul2); // PLL configuration: PLLCLK = HSI * 2 = 48 MHz
@@ -19,22 +63,23 @@ void SystemInit(void)
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08); // Wait till PLL is used as system clock source
}
-static const uint8_t array[384] = { 0xff };
-
int main()
{
- // Enable GPIOD.
- RCC->APB2PCENR |= 0x20; //RCC_APB2Periph_GPIOD
-
- // Push-Pull, 50MHz Output
- GPIOD->CFGLR = (GPIOD->CFGLR & 0xfffffff0) | 3;
-
-
- GPIOD->BSHR = array[GPIOD->BSHR];
+ // Enable GPIOD and UART.
+ RCC->APB2PCENR |= RCC_APB2Periph_GPIOD | RCC_APB2Periph_USART1;
+ ConfigureDebugUART();
+
+ // GPIO D0 Push-Pull, 10MHz Output
+ GPIOD->CFGLR &= ~(0xf<<(4*0));
+ GPIOD->CFGLR |= (GPIO_Speed_10MHz | GPIO_CNF_OUT_PP)<<(4*0);
+
while(1)
{
GPIOD->BSHR = 1; // Turn on GPIOD0
+ puts( "Hello" );
+ Delay_Ms( 100 );
GPIOD->BSHR = 1<<16; // Turn off GPIOD0
+ Delay_Ms( 100 );
}
-}
\ No newline at end of file
+}
diff --git a/ch32v003evt/ch32v00x_conf.h b/ch32v003evt/ch32v00x_conf.h
index 43c2aa4ffb8363853bd6458992ce0d15dbd74773..095acdaf997f50e58ae9224a0c6924fa076476c8 100644
--- a/ch32v003evt/ch32v00x_conf.h
+++ b/ch32v003evt/ch32v00x_conf.h
@@ -1,5 +1,14 @@
-/********************************** (C) COPYRIGHT *******************************
- * File Name : ch32v00x_conf.h
+/*
+ * This file contains the contents of various parts of the evt.
+ *
+ * The collection of this file was generated by cnlohr, 2023-02-18
+ *
+ * Contents subject to below copyright where applicable by law.
+ *
+ * (IANAL, BUT Because it is an interface, it is unlikely protected by copyright)
+ *
+ *********************************** (C) COPYRIGHT *******************************
+ * File Name : ------------------
* Author : WCH
* Version : V1.0.0
* Date : 2020/08/08
@@ -12,7 +21,1770 @@
#ifndef __CH32V00x_CONF_H
#define __CH32V00x_CONF_H
- // We don't use the conf file in this setup.
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* ch32v00x_gpio.c -----------------------------------------------------------*/
+/* MASK */
+#define LSB_MASK ((uint16_t)0xFFFF)
+#define DBGAFR_POSITION_MASK ((uint32_t)0x000F0000)
+#define DBGAFR_SDI_MASK ((uint32_t)0xF8FFFFFF)
+#define DBGAFR_LOCATION_MASK ((uint32_t)0x00200000)
+#define DBGAFR_NUMBITS_MASK ((uint32_t)0x00100000)
+
+
+/* ch32v00x_adc.c ------------------------------------------------------------*/
+/*
+/* ADC DISCNUM mask */
+#define CTLR1_DISCNUM_Reset ((uint32_t)0xFFFF1FFF)
+
+/* ADC DISCEN mask */
+#define CTLR1_DISCEN_Set ((uint32_t)0x00000800)
+#define CTLR1_DISCEN_Reset ((uint32_t)0xFFFFF7FF)
+
+/* ADC JAUTO mask */
+#define CTLR1_JAUTO_Set ((uint32_t)0x00000400)
+#define CTLR1_JAUTO_Reset ((uint32_t)0xFFFFFBFF)
+
+/* ADC JDISCEN mask */
+#define CTLR1_JDISCEN_Set ((uint32_t)0x00001000)
+#define CTLR1_JDISCEN_Reset ((uint32_t)0xFFFFEFFF)
+
+/* ADC AWDCH mask */
+#define CTLR1_AWDCH_Reset ((uint32_t)0xFFFFFFE0)
+
+/* ADC Analog watchdog enable mode mask */
+#define CTLR1_AWDMode_Reset ((uint32_t)0xFF3FFDFF)
+
+///* CTLR1 register Mask */
+//Editor's Note: Overloaded Definition
+#define ADC_CTLR1_CLEAR_Mask ((uint32_t)0xFFF0FEFF)
+
+/* ADC ADON mask */
+#define CTLR2_ADON_Set ((uint32_t)0x00000001)
+#define CTLR2_ADON_Reset ((uint32_t)0xFFFFFFFE)
+
+/* ADC DMA mask */
+#define CTLR2_DMA_Set ((uint32_t)0x00000100)
+#define CTLR2_DMA_Reset ((uint32_t)0xFFFFFEFF)
+
+/* ADC RSTCAL mask */
+#define CTLR2_RSTCAL_Set ((uint32_t)0x00000008)
+
+/* ADC CAL mask */
+#define CTLR2_CAL_Set ((uint32_t)0x00000004)
+
+/* ADC SWSTART mask */
+#define CTLR2_SWSTART_Set ((uint32_t)0x00400000)
+
+/* ADC EXTTRIG mask */
+#define CTLR2_EXTTRIG_Set ((uint32_t)0x00100000)
+#define CTLR2_EXTTRIG_Reset ((uint32_t)0xFFEFFFFF)
+
+/* ADC Software start mask */
+#define CTLR2_EXTTRIG_SWSTART_Set ((uint32_t)0x00500000)
+#define CTLR2_EXTTRIG_SWSTART_Reset ((uint32_t)0xFFAFFFFF)
+
+/* ADC JEXTSEL mask */
+#define CTLR2_JEXTSEL_Reset ((uint32_t)0xFFFF8FFF)
+
+/* ADC JEXTTRIG mask */
+#define CTLR2_JEXTTRIG_Set ((uint32_t)0x00008000)
+#define CTLR2_JEXTTRIG_Reset ((uint32_t)0xFFFF7FFF)
+
+/* ADC JSWSTART mask */
+#define CTLR2_JSWSTART_Set ((uint32_t)0x00200000)
+
+/* ADC injected software start mask */
+#define CTLR2_JEXTTRIG_JSWSTART_Set ((uint32_t)0x00208000)
+#define CTLR2_JEXTTRIG_JSWSTART_Reset ((uint32_t)0xFFDF7FFF)
+
+/* ADC TSPD mask */
+#define CTLR2_TSVREFE_Set ((uint32_t)0x00800000)
+#define CTLR2_TSVREFE_Reset ((uint32_t)0xFF7FFFFF)
+
+/* CTLR2 register Mask */
+#define CTLR2_CLEAR_Mask ((uint32_t)0xFFF1F7FD)
+
+/* ADC SQx mask */
+#define RSQR3_SQ_Set ((uint32_t)0x0000001F)
+#define RSQR2_SQ_Set ((uint32_t)0x0000001F)
+#define RSQR1_SQ_Set ((uint32_t)0x0000001F)
+
+/* RSQR1 register Mask */
+#define RSQR1_CLEAR_Mask ((uint32_t)0xFF0FFFFF)
+
+/* ADC JSQx mask */
+#define ISQR_JSQ_Set ((uint32_t)0x0000001F)
+
+/* ADC JL mask */
+#define ISQR_JL_Set ((uint32_t)0x00300000)
+#define ISQR_JL_Reset ((uint32_t)0xFFCFFFFF)
+
+/* ADC SMPx mask */
+#define SAMPTR1_SMP_Set ((uint32_t)0x00000007)
+#define SAMPTR2_SMP_Set ((uint32_t)0x00000007)
+
+/* ADC IDATARx registers offset */
+#define IDATAR_Offset ((uint8_t)0x28)
+
+
+/* ch32v00x_dbgmcu.c ---------------------------------------------------------*/
+#define IDCODE_DEVID_MASK ((uint32_t)0x0000FFFF)
+
+
+/* ch32v00x_dma.c ------------------------------------------------------------*/
+
+/* DMA1 Channelx interrupt pending bit masks */
+#define DMA1_Channel1_IT_Mask ((uint32_t)(DMA_GIF1 | DMA_TCIF1 | DMA_HTIF1 | DMA_TEIF1))
+#define DMA1_Channel2_IT_Mask ((uint32_t)(DMA_GIF2 | DMA_TCIF2 | DMA_HTIF2 | DMA_TEIF2))
+#define DMA1_Channel3_IT_Mask ((uint32_t)(DMA_GIF3 | DMA_TCIF3 | DMA_HTIF3 | DMA_TEIF3))
+#define DMA1_Channel4_IT_Mask ((uint32_t)(DMA_GIF4 | DMA_TCIF4 | DMA_HTIF4 | DMA_TEIF4))
+#define DMA1_Channel5_IT_Mask ((uint32_t)(DMA_GIF5 | DMA_TCIF5 | DMA_HTIF5 | DMA_TEIF5))
+#define DMA1_Channel6_IT_Mask ((uint32_t)(DMA_GIF6 | DMA_TCIF6 | DMA_HTIF6 | DMA_TEIF6))
+#define DMA1_Channel7_IT_Mask ((uint32_t)(DMA_GIF7 | DMA_TCIF7 | DMA_HTIF7 | DMA_TEIF7))
+
+/* DMA2 FLAG mask */
+// Editor's note: Overloaded Definition.
+#define DMA2_FLAG_Mask ((uint32_t)0x10000000)
+
+/* DMA registers Masks */
+#define CFGR_CLEAR_Mask ((uint32_t)0xFFFF800F)
+
+/* ch32v00x_exti.c -----------------------------------------------------------*/
+
+
+/* No interrupt selected */
+#define EXTI_LINENONE ((uint32_t)0x00000)
+
+/* ch32v00x_flash.c ----------------------------------------------------------*/
+
+/* Flash Access Control Register bits */
+#define ACR_LATENCY_Mask ((uint32_t)0x00000038)
+
+/* Flash Control Register bits */
+#define CR_PG_Set ((uint32_t)0x00000001)
+#define CR_PG_Reset ((uint32_t)0xFFFFFFFE)
+#define CR_PER_Set ((uint32_t)0x00000002)
+#define CR_PER_Reset ((uint32_t)0xFFFFFFFD)
+#define CR_MER_Set ((uint32_t)0x00000004)
+#define CR_MER_Reset ((uint32_t)0xFFFFFFFB)
+#define CR_OPTPG_Set ((uint32_t)0x00000010)
+#define CR_OPTPG_Reset ((uint32_t)0xFFFFFFEF)
+#define CR_OPTER_Set ((uint32_t)0x00000020)
+#define CR_OPTER_Reset ((uint32_t)0xFFFFFFDF)
+#define CR_STRT_Set ((uint32_t)0x00000040)
+#define CR_LOCK_Set ((uint32_t)0x00000080)
+#define CR_PAGE_PG ((uint32_t)0x00010000)
+#define CR_PAGE_ER ((uint32_t)0x00020000)
+#define CR_BUF_LOAD ((uint32_t)0x00040000)
+#define CR_BUF_RST ((uint32_t)0x00080000)
+
+/* FLASH Status Register bits */
+#define SR_BSY ((uint32_t)0x00000001)
+#define SR_WRPRTERR ((uint32_t)0x00000010)
+#define SR_EOP ((uint32_t)0x00000020)
+
+/* FLASH Mask */
+#define RDPRT_Mask ((uint32_t)0x00000002)
+#define WRP0_Mask ((uint32_t)0x000000FF)
+#define WRP1_Mask ((uint32_t)0x0000FF00)
+#define WRP2_Mask ((uint32_t)0x00FF0000)
+#define WRP3_Mask ((uint32_t)0xFF000000)
+
+/* FLASH Keys */
+#define RDP_Key ((uint16_t)0x00A5)
+#define FLASH_KEY1 ((uint32_t)0x45670123)
+#define FLASH_KEY2 ((uint32_t)0xCDEF89AB)
+
+/* FLASH BANK address */
+#define FLASH_BANK1_END_ADDRESS ((uint32_t)0x807FFFF)
+
+/* Delay definition */
+#define EraseTimeout ((uint32_t)0x000B0000)
+#define ProgramTimeout ((uint32_t)0x00002000)
+
+/* Flash Program Vaild Address */
+#define ValidAddrStart (FLASH_BASE)
+#define ValidAddrEnd (FLASH_BASE + 0x4000)
+
+/* ch32v00x_i2c.c ------------------------------------------------------------*/
+
+
+/* I2C SPE mask */
+#define CTLR1_PE_Set ((uint16_t)0x0001)
+#define CTLR1_PE_Reset ((uint16_t)0xFFFE)
+
+/* I2C START mask */
+#define CTLR1_START_Set ((uint16_t)0x0100)
+#define CTLR1_START_Reset ((uint16_t)0xFEFF)
+
+/* I2C STOP mask */
+#define CTLR1_STOP_Set ((uint16_t)0x0200)
+#define CTLR1_STOP_Reset ((uint16_t)0xFDFF)
+
+/* I2C ACK mask */
+#define CTLR1_ACK_Set ((uint16_t)0x0400)
+#define CTLR1_ACK_Reset ((uint16_t)0xFBFF)
+
+/* I2C ENGC mask */
+#define CTLR1_ENGC_Set ((uint16_t)0x0040)
+#define CTLR1_ENGC_Reset ((uint16_t)0xFFBF)
+
+/* I2C SWRST mask */
+#define CTLR1_SWRST_Set ((uint16_t)0x8000)
+#define CTLR1_SWRST_Reset ((uint16_t)0x7FFF)
+
+/* I2C PEC mask */
+#define CTLR1_PEC_Set ((uint16_t)0x1000)
+#define CTLR1_PEC_Reset ((uint16_t)0xEFFF)
+
+/* I2C ENPEC mask */
+#define CTLR1_ENPEC_Set ((uint16_t)0x0020)
+#define CTLR1_ENPEC_Reset ((uint16_t)0xFFDF)
+
+/* I2C ENARP mask */
+#define CTLR1_ENARP_Set ((uint16_t)0x0010)
+#define CTLR1_ENARP_Reset ((uint16_t)0xFFEF)
+
+/* I2C NOSTRETCH mask */
+#define CTLR1_NOSTRETCH_Set ((uint16_t)0x0080)
+#define CTLR1_NOSTRETCH_Reset ((uint16_t)0xFF7F)
+
+////* I2C registers Masks */
+// Editor's note: Overloaded Definition.
+#define I2C_CTLR1_CLEAR_Mask ((uint16_t)0xFBF5)
+
+/* I2C DMAEN mask */
+#define CTLR2_DMAEN_Set ((uint16_t)0x0800)
+#define CTLR2_DMAEN_Reset ((uint16_t)0xF7FF)
+
+/* I2C LAST mask */
+#define CTLR2_LAST_Set ((uint16_t)0x1000)
+#define CTLR2_LAST_Reset ((uint16_t)0xEFFF)
+
+/* I2C FREQ mask */
+#define CTLR2_FREQ_Reset ((uint16_t)0xFFC0)
+
+/* I2C ADD0 mask */
+#define OADDR1_ADD0_Set ((uint16_t)0x0001)
+#define OADDR1_ADD0_Reset ((uint16_t)0xFFFE)
+
+/* I2C ENDUAL mask */
+#define OADDR2_ENDUAL_Set ((uint16_t)0x0001)
+#define OADDR2_ENDUAL_Reset ((uint16_t)0xFFFE)
+
+/* I2C ADD2 mask */
+#define OADDR2_ADD2_Reset ((uint16_t)0xFF01)
+
+/* I2C F/S mask */
+#define CKCFGR_FS_Set ((uint16_t)0x8000)
+
+/* I2C CCR mask */
+#define CKCFGR_CCR_Set ((uint16_t)0x0FFF)
+
+/* I2C FLAG mask */
+//Editor's Note: Overloaded Definition
+#define I2c_FLAG_Mask ((uint32_t)0x00FFFFFF)
+
+/* I2C Interrupt Enable mask */
+#define ITEN_Mask ((uint32_t)0x07000000)
+
+/* ch32v00x_iwdg.c -----------------------------------------------------------*/
+
+/* CTLR register bit mask */
+#define CTLR_KEY_Reload ((uint16_t)0xAAAA)
+#define CTLR_KEY_Enable ((uint16_t)0xCCCC)
+
+/* ch32v00x_pwr.c ------------------------------------------------------------*/
+
+
+/* PWR registers bit mask */
+/* CTLR register bit mask */
+#define CTLR_DS_MASK ((uint32_t)0xFFFFFFFD)
+#define CTLR_PLS_MASK ((uint32_t)0xFFFFFF1F)
+#define AWUPSC_MASK ((uint32_t)0xFFFFFFF0)
+#define AWUWR_MASK ((uint32_t)0xFFFFFFC0)
+
+/* ch32v00x_rcc.c ------------------------------------------------------------*/
+
+/* RCC registers bit address in the alias region */
+#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
+
+/* BDCTLR Register */
+#define BDCTLR_OFFSET (RCC_OFFSET + 0x20)
+
+/* RCC registers bit mask */
+
+/* CTLR register bit mask */
+#define CTLR_HSEBYP_Reset ((uint32_t)0xFFFBFFFF)
+#define CTLR_HSEBYP_Set ((uint32_t)0x00040000)
+#define CTLR_HSEON_Reset ((uint32_t)0xFFFEFFFF)
+#define CTLR_HSEON_Set ((uint32_t)0x00010000)
+#define CTLR_HSITRIM_Mask ((uint32_t)0xFFFFFF07)
+
+#define CFGR0_PLL_Mask ((uint32_t)0xFFC0FFFF)
+#define CFGR0_PLLMull_Mask ((uint32_t)0x003C0000)
+#define CFGR0_PLLSRC_Mask ((uint32_t)0x00010000)
+#define CFGR0_PLLXTPRE_Mask ((uint32_t)0x00020000)
+#define CFGR0_SWS_Mask ((uint32_t)0x0000000C)
+#define CFGR0_SW_Mask ((uint32_t)0xFFFFFFFC)
+#define CFGR0_HPRE_Reset_Mask ((uint32_t)0xFFFFFF0F)
+#define CFGR0_HPRE_Set_Mask ((uint32_t)0x000000F0)
+#define CFGR0_PPRE1_Reset_Mask ((uint32_t)0xFFFFF8FF)
+#define CFGR0_PPRE1_Set_Mask ((uint32_t)0x00000700)
+#define CFGR0_PPRE2_Reset_Mask ((uint32_t)0xFFFFC7FF)
+#define CFGR0_PPRE2_Set_Mask ((uint32_t)0x00003800)
+#define CFGR0_ADCPRE_Reset_Mask ((uint32_t)0xFFFF07FF)
+#define CFGR0_ADCPRE_Set_Mask ((uint32_t)0x0000F800)
+
+/* RSTSCKR register bit mask */
+#define RSTSCKR_RMVF_Set ((uint32_t)0x01000000)
+
+/* RCC Flag Mask */
+//Editor's Note: Overloaded Definition
+#define RCC_FLAG_Mask ((uint8_t)0x1F)
+
+/* INTR register byte 2 (Bits[15:8]) base address */
+#define INTR_BYTE2_ADDRESS ((uint32_t)0x40021009)
+
+/* INTR register byte 3 (Bits[23:16]) base address */
+#define INTR_BYTE3_ADDRESS ((uint32_t)0x4002100A)
+
+/* CFGR0 register byte 4 (Bits[31:24]) base address */
+#define CFGR0_BYTE4_ADDRESS ((uint32_t)0x40021007)
+
+/* BDCTLR register base address */
+#define BDCTLR_ADDRESS (PERIPH_BASE + BDCTLR_OFFSET)
+
+static __I uint8_t APBAHBPrescTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8};
+static __I uint8_t ADCPrescTable[20] = {2, 4, 6, 8, 4, 8, 12, 16, 8, 16, 24, 32, 16, 32, 48, 64, 32, 64, 96, 128};
+
+
+/* ch32v00x_spi.c ------------------------------------------------------------*/
+
+
+/* SPI SPE mask */
+#define CTLR1_SPE_Set ((uint16_t)0x0040)
+#define CTLR1_SPE_Reset ((uint16_t)0xFFBF)
+
+/* SPI CRCNext mask */
+#define CTLR1_CRCNext_Set ((uint16_t)0x1000)
+
+/* SPI CRCEN mask */
+#define CTLR1_CRCEN_Set ((uint16_t)0x2000)
+#define CTLR1_CRCEN_Reset ((uint16_t)0xDFFF)
+
+/* SPI SSOE mask */
+#define CTLR2_SSOE_Set ((uint16_t)0x0004)
+#define CTLR2_SSOE_Reset ((uint16_t)0xFFFB)
+
+/* SPI registers Masks */
+//Editor's Note: Overloaded Definition
+#define SPI_CTLR1_CLEAR_Mask ((uint16_t)0x3040)
+#define I2SCFGR_CLEAR_Mask ((uint16_t)0xF040)
+
+
+/* ch32v00x_tim.c ------------------------------------------------------------*/
+
+/* TIM registers bit mask */
+#define SMCFGR_ETR_Mask ((uint16_t)0x00FF)
+#define CHCTLR_Offset ((uint16_t)0x0018)
+#define CCER_CCE_Set ((uint16_t)0x0001)
+#define CCER_CCNE_Set ((uint16_t)0x0004)
+
+/* ch32v00x_usart.c ----------------------------------------------------------*/
+
+/* USART_Private_Defines */
+#define CTLR1_UE_Set ((uint16_t)0x2000) /* USART Enable Mask */
+#define CTLR1_UE_Reset ((uint16_t)0xDFFF) /* USART Disable Mask */
+
+#define CTLR1_WAKE_Mask ((uint16_t)0xF7FF) /* USART WakeUp Method Mask */
+
+#define CTLR1_RWU_Set ((uint16_t)0x0002) /* USART mute mode Enable Mask */
+#define CTLR1_RWU_Reset ((uint16_t)0xFFFD) /* USART mute mode Enable Mask */
+#define CTLR1_SBK_Set ((uint16_t)0x0001) /* USART Break Character send Mask */
+//Editor's Note: Overloaded Definition
+#define USART_CTLR1_CLEAR_Mask ((uint16_t)0xE9F3) /* USART CR1 Mask */
+#define CTLR2_Address_Mask ((uint16_t)0xFFF0) /* USART address Mask */
+
+#define CTLR2_LINEN_Set ((uint16_t)0x4000) /* USART LIN Enable Mask */
+#define CTLR2_LINEN_Reset ((uint16_t)0xBFFF) /* USART LIN Disable Mask */
+
+#define CTLR2_LBDL_Mask ((uint16_t)0xFFDF) /* USART LIN Break detection Mask */
+#define CTLR2_STOP_CLEAR_Mask ((uint16_t)0xCFFF) /* USART CR2 STOP Bits Mask */
+#define CTLR2_CLOCK_CLEAR_Mask ((uint16_t)0xF0FF) /* USART CR2 Clock Mask */
+
+#define CTLR3_SCEN_Set ((uint16_t)0x0020) /* USART SC Enable Mask */
+#define CTLR3_SCEN_Reset ((uint16_t)0xFFDF) /* USART SC Disable Mask */
+
+#define CTLR3_NACK_Set ((uint16_t)0x0010) /* USART SC NACK Enable Mask */
+#define CTLR3_NACK_Reset ((uint16_t)0xFFEF) /* USART SC NACK Disable Mask */
+
+#define CTLR3_HDSEL_Set ((uint16_t)0x0008) /* USART Half-Duplex Enable Mask */
+#define CTLR3_HDSEL_Reset ((uint16_t)0xFFF7) /* USART Half-Duplex Disable Mask */
+
+#define CTLR3_IRLP_Mask ((uint16_t)0xFFFB) /* USART IrDA LowPower mode Mask */
+#define CTLR3_CLEAR_Mask ((uint16_t)0xFCFF) /* USART CR3 Mask */
+
+#define CTLR3_IREN_Set ((uint16_t)0x0002) /* USART IrDA Enable Mask */
+#define CTLR3_IREN_Reset ((uint16_t)0xFFFD) /* USART IrDA Disable Mask */
+#define GPR_LSB_Mask ((uint16_t)0x00FF) /* Guard Time Register LSB Mask */
+#define GPR_MSB_Mask ((uint16_t)0xFF00) /* Guard Time Register MSB Mask */
+#define IT_Mask ((uint16_t)0x001F) /* USART Interrupt Mask */
+
+/* USART OverSampling-8 Mask */
+#define CTLR1_OVER8_Set ((uint16_t)0x8000) /* USART OVER8 mode Enable Mask */
+#define CTLR1_OVER8_Reset ((uint16_t)0x7FFF) /* USART OVER8 mode Disable Mask */
+
+/* USART One Bit Sampling Mask */
+#define CTLR3_ONEBITE_Set ((uint16_t)0x0800) /* USART ONEBITE mode Enable Mask */
+#define CTLR3_ONEBITE_Reset ((uint16_t)0xF7FF) /* USART ONEBITE mode Disable Mask */
+
+/* ch32v00x_wwdg.c ------------------------------------------------------------*/
+
+
+/* CTLR register bit mask */
+#define CTLR_WDGA_Set ((uint32_t)0x00000080)
+
+/* CFGR register bit mask */
+#define CFGR_WDGTB_Mask ((uint32_t)0xFFFFFE7F)
+#define CFGR_W_Mask ((uint32_t)0xFFFFFF80)
+#define BIT_Mask ((uint8_t)0x7F)
+
+
+/* ch32v00x_adc.h ------------------------------------------------------------*/
+
+
+
+/* ADC_mode */
+#define ADC_Mode_Independent ((uint32_t)0x00000000)
+
+/* ADC_external_trigger_sources_for_regular_channels_conversion */
+#define ADC_ExternalTrigConv_T1_TRGO ((uint32_t)0x00000000)
+#define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00020000)
+#define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x00040000)
+#define ADC_ExternalTrigConv_T2_TRGO ((uint32_t)0x00060000)
+#define ADC_ExternalTrigConv_T2_CC1 ((uint32_t)0x00080000)
+#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x000A0000)
+#define ADC_ExternalTrigConv_Ext_PD3_PC2 ((uint32_t)0x000C0000)
+#define ADC_ExternalTrigConv_None ((uint32_t)0x000E0000)
+
+/* ADC_data_align */
+#define ADC_DataAlign_Right ((uint32_t)0x00000000)
+#define ADC_DataAlign_Left ((uint32_t)0x00000800)
+
+/* ADC_channels */
+#define ADC_Channel_0 ((uint8_t)0x00)
+#define ADC_Channel_1 ((uint8_t)0x01)
+#define ADC_Channel_2 ((uint8_t)0x02)
+#define ADC_Channel_3 ((uint8_t)0x03)
+#define ADC_Channel_4 ((uint8_t)0x04)
+#define ADC_Channel_5 ((uint8_t)0x05)
+#define ADC_Channel_6 ((uint8_t)0x06)
+#define ADC_Channel_7 ((uint8_t)0x07)
+#define ADC_Channel_8 ((uint8_t)0x08)
+#define ADC_Channel_9 ((uint8_t)0x09)
+
+#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_8)
+#define ADC_Channel_Vcalint ((uint8_t)ADC_Channel_9)
+
+/* ADC_sampling_time */
+#define ADC_SampleTime_3Cycles ((uint8_t)0x00)
+#define ADC_SampleTime_9Cycles ((uint8_t)0x01)
+#define ADC_SampleTime_15Cycles ((uint8_t)0x02)
+#define ADC_SampleTime_30Cycles ((uint8_t)0x03)
+#define ADC_SampleTime_43Cycles ((uint8_t)0x04)
+#define ADC_SampleTime_57Cycles ((uint8_t)0x05)
+#define ADC_SampleTime_73Cycles ((uint8_t)0x06)
+#define ADC_SampleTime_241Cycles ((uint8_t)0x07)
+
+/* ADC_external_trigger_sources_for_injected_channels_conversion */
+#define ADC_ExternalTrigInjecConv_T1_CC3 ((uint32_t)0x00000000)
+#define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00001000)
+#define ADC_ExternalTrigInjecConv_T2_CC3 ((uint32_t)0x00002000)
+#define ADC_ExternalTrigInjecConv_T2_CC4 ((uint32_t)0x00003000)
+#define ADC_ExternalTrigInjecConv_Ext_PD1_PA2 ((uint32_t)0x00006000)
+#define ADC_ExternalTrigInjecConv_None ((uint32_t)0x00007000)
+
+/* ADC_injected_channel_selection */
+#define ADC_InjectedChannel_1 ((uint8_t)0x14)
+#define ADC_InjectedChannel_2 ((uint8_t)0x18)
+#define ADC_InjectedChannel_3 ((uint8_t)0x1C)
+#define ADC_InjectedChannel_4 ((uint8_t)0x20)
+
+/* ADC_analog_watchdog_selection */
+#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200)
+#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200)
+#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200)
+#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000)
+#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000)
+#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000)
+#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000)
+
+/* ADC_interrupts_definition */
+#define ADC_IT_EOC ((uint16_t)0x0220)
+#define ADC_IT_AWD ((uint16_t)0x0140)
+#define ADC_IT_JEOC ((uint16_t)0x0480)
+
+/* ADC_flags_definition */
+#define ADC_FLAG_AWD ((uint8_t)0x01)
+#define ADC_FLAG_EOC ((uint8_t)0x02)
+#define ADC_FLAG_JEOC ((uint8_t)0x04)
+#define ADC_FLAG_JSTRT ((uint8_t)0x08)
+#define ADC_FLAG_STRT ((uint8_t)0x10)
+
+/* ADC_calibration_voltage_definition */
+#define ADC_CALVOL_50PERCENT ((uint32_t)0x02000000)
+#define ADC_CALVOL_75PERCENT ((uint32_t)0x04000000)
+
+/* ADC_external_trigger_sources_delay_channels_definition */
+#define ADC_ExternalTrigRegul_DLY ((uint32_t)0x00000000)
+#define ADC_ExternalTrigInjec_DLY ((uint32_t)0x00020000)
+
+
+
+/* ch32v00x_dbgmcu.h ---------------------------------------------------------*/
+
+/* CFGR0 Register */
+#define DBGMCU_IWDG_STOP ((uint32_t)0x00000001)
+#define DBGMCU_WWDG_STOP ((uint32_t)0x00000002)
+#define DBGMCU_TIM1_STOP ((uint32_t)0x00000010)
+#define DBGMCU_TIM2_STOP ((uint32_t)0x00000020)
+
+/* ch32v00x_dma.h ------------------------------------------------------------*/
+
+/* DMA_data_transfer_direction */
+#define DMA_DIR_PeripheralDST ((uint32_t)0x00000010)
+#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000)
+
+/* DMA_peripheral_incremented_mode */
+#define DMA_PeripheralInc_Enable ((uint32_t)0x00000040)
+#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000)
+
+/* DMA_memory_incremented_mode */
+#define DMA_MemoryInc_Enable ((uint32_t)0x00000080)
+#define DMA_MemoryInc_Disable ((uint32_t)0x00000000)
+
+/* DMA_peripheral_data_size */
+#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000)
+#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100)
+#define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200)
+
+/* DMA_memory_data_size */
+#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000)
+#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400)
+#define DMA_MemoryDataSize_Word ((uint32_t)0x00000800)
+
+/* DMA_circular_normal_mode */
+#define DMA_Mode_Circular ((uint32_t)0x00000020)
+#define DMA_Mode_Normal ((uint32_t)0x00000000)
+
+/* DMA_priority_level */
+#define DMA_Priority_VeryHigh ((uint32_t)0x00003000)
+#define DMA_Priority_High ((uint32_t)0x00002000)
+#define DMA_Priority_Medium ((uint32_t)0x00001000)
+#define DMA_Priority_Low ((uint32_t)0x00000000)
+
+/* DMA_memory_to_memory */
+#define DMA_M2M_Enable ((uint32_t)0x00004000)
+#define DMA_M2M_Disable ((uint32_t)0x00000000)
+
+/* DMA_interrupts_definition */
+#define DMA_IT_TC ((uint32_t)0x00000002)
+#define DMA_IT_HT ((uint32_t)0x00000004)
+#define DMA_IT_TE ((uint32_t)0x00000008)
+
+#define DMA1_IT_GL1 ((uint32_t)0x00000001)
+#define DMA1_IT_TC1 ((uint32_t)0x00000002)
+#define DMA1_IT_HT1 ((uint32_t)0x00000004)
+#define DMA1_IT_TE1 ((uint32_t)0x00000008)
+#define DMA1_IT_GL2 ((uint32_t)0x00000010)
+#define DMA1_IT_TC2 ((uint32_t)0x00000020)
+#define DMA1_IT_HT2 ((uint32_t)0x00000040)
+#define DMA1_IT_TE2 ((uint32_t)0x00000080)
+#define DMA1_IT_GL3 ((uint32_t)0x00000100)
+#define DMA1_IT_TC3 ((uint32_t)0x00000200)
+#define DMA1_IT_HT3 ((uint32_t)0x00000400)
+#define DMA1_IT_TE3 ((uint32_t)0x00000800)
+#define DMA1_IT_GL4 ((uint32_t)0x00001000)
+#define DMA1_IT_TC4 ((uint32_t)0x00002000)
+#define DMA1_IT_HT4 ((uint32_t)0x00004000)
+#define DMA1_IT_TE4 ((uint32_t)0x00008000)
+#define DMA1_IT_GL5 ((uint32_t)0x00010000)
+#define DMA1_IT_TC5 ((uint32_t)0x00020000)
+#define DMA1_IT_HT5 ((uint32_t)0x00040000)
+#define DMA1_IT_TE5 ((uint32_t)0x00080000)
+#define DMA1_IT_GL6 ((uint32_t)0x00100000)
+#define DMA1_IT_TC6 ((uint32_t)0x00200000)
+#define DMA1_IT_HT6 ((uint32_t)0x00400000)
+#define DMA1_IT_TE6 ((uint32_t)0x00800000)
+#define DMA1_IT_GL7 ((uint32_t)0x01000000)
+#define DMA1_IT_TC7 ((uint32_t)0x02000000)
+#define DMA1_IT_HT7 ((uint32_t)0x04000000)
+#define DMA1_IT_TE7 ((uint32_t)0x08000000)
+
+/* DMA_flags_definition */
+#define DMA1_FLAG_GL1 ((uint32_t)0x00000001)
+#define DMA1_FLAG_TC1 ((uint32_t)0x00000002)
+#define DMA1_FLAG_HT1 ((uint32_t)0x00000004)
+#define DMA1_FLAG_TE1 ((uint32_t)0x00000008)
+#define DMA1_FLAG_GL2 ((uint32_t)0x00000010)
+#define DMA1_FLAG_TC2 ((uint32_t)0x00000020)
+#define DMA1_FLAG_HT2 ((uint32_t)0x00000040)
+#define DMA1_FLAG_TE2 ((uint32_t)0x00000080)
+#define DMA1_FLAG_GL3 ((uint32_t)0x00000100)
+#define DMA1_FLAG_TC3 ((uint32_t)0x00000200)
+#define DMA1_FLAG_HT3 ((uint32_t)0x00000400)
+#define DMA1_FLAG_TE3 ((uint32_t)0x00000800)
+#define DMA1_FLAG_GL4 ((uint32_t)0x00001000)
+#define DMA1_FLAG_TC4 ((uint32_t)0x00002000)
+#define DMA1_FLAG_HT4 ((uint32_t)0x00004000)
+#define DMA1_FLAG_TE4 ((uint32_t)0x00008000)
+#define DMA1_FLAG_GL5 ((uint32_t)0x00010000)
+#define DMA1_FLAG_TC5 ((uint32_t)0x00020000)
+#define DMA1_FLAG_HT5 ((uint32_t)0x00040000)
+#define DMA1_FLAG_TE5 ((uint32_t)0x00080000)
+#define DMA1_FLAG_GL6 ((uint32_t)0x00100000)
+#define DMA1_FLAG_TC6 ((uint32_t)0x00200000)
+#define DMA1_FLAG_HT6 ((uint32_t)0x00400000)
+#define DMA1_FLAG_TE6 ((uint32_t)0x00800000)
+#define DMA1_FLAG_GL7 ((uint32_t)0x01000000)
+#define DMA1_FLAG_TC7 ((uint32_t)0x02000000)
+#define DMA1_FLAG_HT7 ((uint32_t)0x04000000)
+#define DMA1_FLAG_TE7 ((uint32_t)0x08000000)
+
+/* ch32v00x_exti.h -----------------------------------------------------------*/
+
+/* EXTI mode enumeration */
+typedef enum
+{
+ EXTI_Mode_Interrupt = 0x00,
+ EXTI_Mode_Event = 0x04
+} EXTIMode_TypeDef;
+
+/* EXTI Trigger enumeration */
+typedef enum
+{
+ EXTI_Trigger_Rising = 0x08,
+ EXTI_Trigger_Falling = 0x0C,
+ EXTI_Trigger_Rising_Falling = 0x10
+} EXTITrigger_TypeDef;
+
+/* EXTI_Lines */
+#define EXTI_Line0 ((uint32_t)0x00001) /* External interrupt line 0 */
+#define EXTI_Line1 ((uint32_t)0x00002) /* External interrupt line 1 */
+#define EXTI_Line2 ((uint32_t)0x00004) /* External interrupt line 2 */
+#define EXTI_Line3 ((uint32_t)0x00008) /* External interrupt line 3 */
+#define EXTI_Line4 ((uint32_t)0x00010) /* External interrupt line 4 */
+#define EXTI_Line5 ((uint32_t)0x00020) /* External interrupt line 5 */
+#define EXTI_Line6 ((uint32_t)0x00040) /* External interrupt line 6 */
+#define EXTI_Line7 ((uint32_t)0x00080) /* External interrupt line 7 */
+#define EXTI_Line8 ((uint32_t)0x00100) /* External interrupt line 8 Connected to the PVD Output */
+#define EXTI_Line9 ((uint32_t)0x00200) /* External interrupt line 9 Connected to the PWR Auto Wake-up event*/
+
+
+/* ch32v00x_flash.h ----------------------------------------------------------*/
+
+
+/* FLASH Status */
+typedef enum
+{
+ FLASH_BUSY = 1,
+ FLASH_ERROR_PG,
+ FLASH_ERROR_WRP,
+ FLASH_COMPLETE,
+ FLASH_TIMEOUT
+} FLASH_Status;
+
+
+/* Flash_Latency */
+#define FLASH_Latency_0 ((uint32_t)0x00000000) /* FLASH Zero Latency cycle */
+#define FLASH_Latency_1 ((uint32_t)0x00000001) /* FLASH One Latency cycle */
+#define FLASH_Latency_2 ((uint32_t)0x00000002) /* FLASH Two Latency cycles */
+
+/* Values to be used with CH32V00x devices (1page = 64Byte) */
+#define FLASH_WRProt_Pages0to15 ((uint32_t)0x00000001) /* CH32 Low and Medium density devices: Write protection of page 0 to 15 */
+#define FLASH_WRProt_Pages16to31 ((uint32_t)0x00000002) /* CH32 Low and Medium density devices: Write protection of page 16 to 31 */
+#define FLASH_WRProt_Pages32to47 ((uint32_t)0x00000004) /* CH32 Low and Medium density devices: Write protection of page 32 to 47 */
+#define FLASH_WRProt_Pages48to63 ((uint32_t)0x00000008) /* CH32 Low and Medium density devices: Write protection of page 48 to 63 */
+#define FLASH_WRProt_Pages64to79 ((uint32_t)0x00000010) /* CH32 Low and Medium density devices: Write protection of page 64 to 79 */
+#define FLASH_WRProt_Pages80to95 ((uint32_t)0x00000020) /* CH32 Low and Medium density devices: Write protection of page 80 to 95 */
+#define FLASH_WRProt_Pages96to111 ((uint32_t)0x00000040) /* CH32 Low and Medium density devices: Write protection of page 96 to 111 */
+#define FLASH_WRProt_Pages112to127 ((uint32_t)0x00000080) /* CH32 Low and Medium density devices: Write protection of page 112 to 127 */
+#define FLASH_WRProt_Pages128to143 ((uint32_t)0x00000100) /* CH32 Medium-density devices: Write protection of page 128 to 143 */
+#define FLASH_WRProt_Pages144to159 ((uint32_t)0x00000200) /* CH32 Medium-density devices: Write protection of page 144 to 159 */
+#define FLASH_WRProt_Pages160to175 ((uint32_t)0x00000400) /* CH32 Medium-density devices: Write protection of page 160 to 175 */
+#define FLASH_WRProt_Pages176to191 ((uint32_t)0x00000800) /* CH32 Medium-density devices: Write protection of page 176 to 191 */
+#define FLASH_WRProt_Pages192to207 ((uint32_t)0x00001000) /* CH32 Medium-density devices: Write protection of page 192 to 207 */
+#define FLASH_WRProt_Pages208to223 ((uint32_t)0x00002000) /* CH32 Medium-density devices: Write protection of page 208 to 223 */
+#define FLASH_WRProt_Pages224to239 ((uint32_t)0x00004000) /* CH32 Medium-density devices: Write protection of page 224 to 239 */
+#define FLASH_WRProt_Pages240to255 ((uint32_t)0x00008000) /* CH32 Medium-density devices: Write protection of page 240 to 255 */
+
+#define FLASH_WRProt_AllPages ((uint32_t)0x0000FFFF) /* Write protection of all Pages */
+
+/* Option_Bytes_IWatchdog */
+#define OB_IWDG_SW ((uint16_t)0x0001) /* Software IWDG selected */
+#define OB_IWDG_HW ((uint16_t)0x0000) /* Hardware IWDG selected */
+
+/* Option_Bytes_nRST_STOP */
+#define OB_STOP_NoRST ((uint16_t)0x0002) /* No reset generated when entering in STOP */
+#define OB_STOP_RST ((uint16_t)0x0000) /* Reset generated when entering in STOP */
+
+/* Option_Bytes_nRST_STDBY */
+#define OB_STDBY_NoRST ((uint16_t)0x0004) /* No reset generated when entering in STANDBY */
+#define OB_STDBY_RST ((uint16_t)0x0000) /* Reset generated when entering in STANDBY */
+
+/* Option_Bytes_RST_ENandDT */
+#define OB_RST_NoEN ((uint16_t)0x0018) /* Reset IO disable (PD7)*/
+#define OB_RST_EN_DT12ms ((uint16_t)0x0010) /* Reset IO enable (PD7) and Ignore delay time 12ms */
+#define OB_RST_EN_DT1ms ((uint16_t)0x0008) /* Reset IO enable (PD7) and Ignore delay time 1ms */
+#define OB_RST_EN_DT128ms ((uint16_t)0x0000) /* Reset IO enable (PD7) and Ignore delay time 128ms */
+
+/* FLASH_Interrupts */
+#define FLASH_IT_ERROR ((uint32_t)0x00000400) /* FPEC error interrupt source */
+#define FLASH_IT_EOP ((uint32_t)0x00001000) /* End of FLASH Operation Interrupt source */
+#define FLASH_IT_BANK1_ERROR FLASH_IT_ERROR /* FPEC BANK1 error interrupt source */
+#define FLASH_IT_BANK1_EOP FLASH_IT_EOP /* End of FLASH BANK1 Operation Interrupt source */
+
+/* FLASH_Flags */
+#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /* FLASH Busy flag */
+#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /* FLASH End of Operation flag */
+#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /* FLASH Write protected error flag */
+#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /* FLASH Option Byte error flag */
+
+#define FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY /* FLASH BANK1 Busy flag*/
+#define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP /* FLASH BANK1 End of Operation flag */
+#define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /* FLASH BANK1 Write protected error flag */
+
+/* System_Reset_Start_Mode */
+#define Start_Mode_USER ((uint32_t)0x00000000)
+#define Start_Mode_BOOT ((uint32_t)0x00004000)
+
+
+/* ch32v00x_gpio.h ------------------------------------------------------------*/
+
+/* Output Maximum frequency selection */
+typedef enum
+{
+ GPIO_Speed_10MHz = 1,
+ GPIO_Speed_2MHz,
+ GPIO_Speed_50MHz
+} GPIOSpeed_TypeDef;
+
+#define GPIO_SPEED_IN 0
+
+#define GPIO_CNF_IN_ANALOG 0
+#define GPIO_CNF_IN_FLOATING 4
+#define GPIO_CNF_IN_PUPD 8
+#define GPIO_CNF_OUT_PP 0
+#define GPIO_CNF_OUT_OD 4
+#define GPIO_CNF_OUT_PP_AF 8
+#define GPIO_CNF_OUT_OD_AF 12
+
+/* Configuration Mode enumeration */
+/*
+typedef enum
+{
+ GPIO_Mode_AIN = 0x0,
+ GPIO_Mode_IN_FLOATING = 0x04,
+ GPIO_Mode_IPD = 0x28,
+ GPIO_Mode_IPU = 0x48,
+ GPIO_Mode_Out_OD = 0x14,
+ GPIO_Mode_Out_PP = 0x10,
+ GPIO_Mode_AF_OD = 0x1C,
+ GPIO_Mode_AF_PP = 0x18
+} GPIOMode_TypeDef;
+*/
+
+
+/* Bit_SET and Bit_RESET enumeration */
+typedef enum
+{
+ Bit_RESET = 0,
+ Bit_SET
+} BitAction;
+
+/* GPIO_pins_define */
+#define GPIO_Pin_0 ((uint16_t)0x0001) /* Pin 0 selected */
+#define GPIO_Pin_1 ((uint16_t)0x0002) /* Pin 1 selected */
+#define GPIO_Pin_2 ((uint16_t)0x0004) /* Pin 2 selected */
+#define GPIO_Pin_3 ((uint16_t)0x0008) /* Pin 3 selected */
+#define GPIO_Pin_4 ((uint16_t)0x0010) /* Pin 4 selected */
+#define GPIO_Pin_5 ((uint16_t)0x0020) /* Pin 5 selected */
+#define GPIO_Pin_6 ((uint16_t)0x0040) /* Pin 6 selected */
+#define GPIO_Pin_7 ((uint16_t)0x0080) /* Pin 7 selected */
+#define GPIO_Pin_All ((uint16_t)0xFFFF) /* All pins selected */
+
+/* GPIO_Remap_define */
+#define GPIO_Remap_SPI1 ((uint32_t)0x00000001) /* SPI1 Alternate Function mapping */
+#define GPIO_PartialRemap_I2C1 ((uint32_t)0x10000002) /* I2C1 Partial Alternate Function mapping */
+#define GPIO_FullRemap_I2C1 ((uint32_t)0x10400002) /* I2C1 Full Alternate Function mapping */
+#define GPIO_PartialRemap1_USART1 ((uint32_t)0x80000004) /* USART1 Partial1 Alternate Function mapping */
+#define GPIO_PartialRemap2_USART1 ((uint32_t)0x80200000) /* USART1 Partial2 Alternate Function mapping */
+#define GPIO_FullRemap_USART1 ((uint32_t)0x80200004) /* USART1 Full Alternate Function mapping */
+#define GPIO_PartialRemap1_TIM1 ((uint32_t)0x00160040) /* TIM1 Partial1 Alternate Function mapping */
+#define GPIO_PartialRemap2_TIM1 ((uint32_t)0x00160080) /* TIM1 Partial2 Alternate Function mapping */
+#define GPIO_FullRemap_TIM1 ((uint32_t)0x001600C0) /* TIM1 Full Alternate Function mapping */
+#define GPIO_PartialRemap1_TIM2 ((uint32_t)0x00180100) /* TIM2 Partial1 Alternate Function mapping */
+#define GPIO_PartialRemap2_TIM2 ((uint32_t)0x00180200) /* TIM2 Partial2 Alternate Function mapping */
+#define GPIO_FullRemap_TIM2 ((uint32_t)0x00180300) /* TIM2 Full Alternate Function mapping */
+#define GPIO_Remap_PA1_2 ((uint32_t)0x00008000) /* PA1 and PA2 Alternate Function mapping */
+#define GPIO_Remap_ADC1_ETRGINJ ((uint32_t)0x00200002) /* ADC1 External Trigger Injected Conversion remapping */
+#define GPIO_Remap_ADC1_ETRGREG ((uint32_t)0x00200004) /* ADC1 External Trigger Regular Conversion remapping */
+#define GPIO_Remap_LSI_CAL ((uint32_t)0x00200080) /* LSI calibration Alternate Function mapping */
+#define GPIO_Remap_SDI_Disable ((uint32_t)0x00300400) /* SDI Disabled */
+
+/* GPIO_Port_Sources */
+#define GPIO_PortSourceGPIOA ((uint8_t)0x00)
+#define GPIO_PortSourceGPIOC ((uint8_t)0x02)
+#define GPIO_PortSourceGPIOD ((uint8_t)0x03)
+
+/* GPIO_Pin_sources */
+#define GPIO_PinSource0 ((uint8_t)0x00)
+#define GPIO_PinSource1 ((uint8_t)0x01)
+#define GPIO_PinSource2 ((uint8_t)0x02)
+#define GPIO_PinSource3 ((uint8_t)0x03)
+#define GPIO_PinSource4 ((uint8_t)0x04)
+#define GPIO_PinSource5 ((uint8_t)0x05)
+#define GPIO_PinSource6 ((uint8_t)0x06)
+#define GPIO_PinSource7 ((uint8_t)0x07)
+
+/* ch32v00x_i2c.h ------------------------------------------------------------*/
+
+/* I2C_mode */
+#define I2C_Mode_I2C ((uint16_t)0x0000)
+
+/* I2C_duty_cycle_in_fast_mode */
+#define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /* I2C fast mode Tlow/Thigh = 16/9 */
+#define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /* I2C fast mode Tlow/Thigh = 2 */
+
+/* I2C_acknowledgement */
+#define I2C_Ack_Enable ((uint16_t)0x0400)
+#define I2C_Ack_Disable ((uint16_t)0x0000)
+
+/* I2C_transfer_direction */
+#define I2C_Direction_Transmitter ((uint8_t)0x00)
+#define I2C_Direction_Receiver ((uint8_t)0x01)
+
+/* I2C_acknowledged_address */
+#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000)
+#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000)
+
+/* I2C_registers */
+#define I2C_Register_CTLR1 ((uint8_t)0x00)
+#define I2C_Register_CTLR2 ((uint8_t)0x04)
+#define I2C_Register_OADDR1 ((uint8_t)0x08)
+#define I2C_Register_OADDR2 ((uint8_t)0x0C)
+#define I2C_Register_DATAR ((uint8_t)0x10)
+#define I2C_Register_STAR1 ((uint8_t)0x14)
+#define I2C_Register_STAR2 ((uint8_t)0x18)
+#define I2C_Register_CKCFGR ((uint8_t)0x1C)
+
+/* I2C_PEC_position */
+#define I2C_PECPosition_Next ((uint16_t)0x0800)
+#define I2C_PECPosition_Current ((uint16_t)0xF7FF)
+
+/* I2C_NACK_position */
+#define I2C_NACKPosition_Next ((uint16_t)0x0800)
+#define I2C_NACKPosition_Current ((uint16_t)0xF7FF)
+
+/* I2C_interrupts_definition */
+#define I2C_IT_BUF ((uint16_t)0x0400)
+#define I2C_IT_EVT ((uint16_t)0x0200)
+#define I2C_IT_ERR ((uint16_t)0x0100)
+
+/* I2C_interrupts_definition */
+#define I2C_IT_PECERR ((uint32_t)0x01001000)
+#define I2C_IT_OVR ((uint32_t)0x01000800)
+#define I2C_IT_AF ((uint32_t)0x01000400)
+#define I2C_IT_ARLO ((uint32_t)0x01000200)
+#define I2C_IT_BERR ((uint32_t)0x01000100)
+#define I2C_IT_TXE ((uint32_t)0x06000080)
+#define I2C_IT_RXNE ((uint32_t)0x06000040)
+#define I2C_IT_STOPF ((uint32_t)0x02000010)
+#define I2C_IT_ADD10 ((uint32_t)0x02000008)
+#define I2C_IT_BTF ((uint32_t)0x02000004)
+#define I2C_IT_ADDR ((uint32_t)0x02000002)
+#define I2C_IT_SB ((uint32_t)0x02000001)
+
+/* SR2 register flags */
+#define I2C_FLAG_DUALF ((uint32_t)0x00800000)
+#define I2C_FLAG_GENCALL ((uint32_t)0x00100000)
+#define I2C_FLAG_TRA ((uint32_t)0x00040000)
+#define I2C_FLAG_BUSY ((uint32_t)0x00020000)
+#define I2C_FLAG_MSL ((uint32_t)0x00010000)
+
+/* SR1 register flags */
+#define I2C_FLAG_PECERR ((uint32_t)0x10001000)
+#define I2C_FLAG_OVR ((uint32_t)0x10000800)
+#define I2C_FLAG_AF ((uint32_t)0x10000400)
+#define I2C_FLAG_ARLO ((uint32_t)0x10000200)
+#define I2C_FLAG_BERR ((uint32_t)0x10000100)
+#define I2C_FLAG_TXE ((uint32_t)0x10000080)
+#define I2C_FLAG_RXNE ((uint32_t)0x10000040)
+#define I2C_FLAG_STOPF ((uint32_t)0x10000010)
+#define I2C_FLAG_ADD10 ((uint32_t)0x10000008)
+#define I2C_FLAG_BTF ((uint32_t)0x10000004)
+#define I2C_FLAG_ADDR ((uint32_t)0x10000002)
+#define I2C_FLAG_SB ((uint32_t)0x10000001)
+
+/****************I2C Master Events (Events grouped in order of communication)********************/
+
+/********************************************************************************************************************
+ * @brief Start communicate
+ *
+ * After master use I2C_GenerateSTART() function sending the START condition,the master
+ * has to wait for event 5(the Start condition has been correctly
+ * released on the I2C bus ).
+ *
+ */
+/* EVT5 */
+#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */
+
+/********************************************************************************************************************
+ * @brief Address Acknowledge
+ *
+ * When start condition correctly released on the bus(check EVT5), the
+ * master use I2C_Send7bitAddress() function sends the address of the slave(s) with which it will communicate
+ * it also determines master as transmitter or Receiver. Then the master has to wait that a slave acknowledges
+ * his address. If an acknowledge is sent on the bus, one of the following events will be set:
+ *
+ *
+ *
+ * 1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED
+ * event is set.
+ *
+ * 2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED
+ * is set
+ *
+ * 3) In case of 10-Bit addressing mode, the master (after generating the START
+ * and checking on EVT5) use I2C_SendData() function send the header of 10-bit addressing mode.
+ * Then master wait EVT9. EVT9 means that the 10-bit addressing header has been correctly sent
+ * on the bus. Then master should use the function I2C_Send7bitAddress() to send the second part
+ * of the 10-bit address (LSB) . Then master should wait for event 6.
+ *
+ *
+ */
+
+/* EVT6 */
+#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */
+#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */
+/*EVT9 */
+#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */
+
+/********************************************************************************************************************
+ * @brief Communication events
+ *
+ * If START condition has generated and slave address
+ * been acknowledged. then the master has to check one of the following events for
+ * communication procedures:
+ *
+ * 1) Master Receiver mode: The master has to wait on the event EVT7 then use
+ * I2C_ReceiveData() function to read the data received from the slave .
+ *
+ * 2) Master Transmitter mode: The master use I2C_SendData() function to send data
+ * then to wait on event EVT8 or EVT8_2.
+ * These two events are similar:
+ * - EVT8 means that the data has been written in the data register and is
+ * being shifted out.
+ * - EVT8_2 means that the data has been physically shifted out and output
+ * on the bus.
+ * In most cases, using EVT8 is sufficient for the application.
+ * Using EVT8_2 will leads to a slower communication speed but will more reliable .
+ * EVT8_2 is also more suitable than EVT8 for testing on the last data transmission
+ *
+ *
+ * Note:
+ * In case the user software does not guarantee that this event EVT7 is managed before
+ * the current byte end of transfer, then user may check on I2C_EVENT_MASTER_BYTE_RECEIVED
+ * and I2C_FLAG_BTF flag at the same time .But in this case the communication may be slower.
+ *
+ *
+ */
+
+/* Master Receive mode */
+/* EVT7 */
+#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */
+
+/* Master Transmitter mode*/
+/* EVT8 */
+#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */
+/* EVT8_2 */
+#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */
+
+/******************I2C Slave Events (Events grouped in order of communication)******************/
+
+/********************************************************************************************************************
+ * @brief Start Communicate events
+ *
+ * Wait on one of these events at the start of the communication. It means that
+ * the I2C peripheral detected a start condition of master device generate on the bus.
+ * If the acknowledge feature is enabled through function I2C_AcknowledgeConfig()),The peripheral generates an ACK condition on the bus.
+ *
+ *
+ *
+ * a) In normal case (only one address managed by the slave), when the address
+ * sent by the master matches the own address of the peripheral (configured by
+ * I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set
+ * (where XXX could be TRANSMITTER or RECEIVER).
+ *
+ * b) In case the address sent by the master matches the second address of the
+ * peripheral (configured by the function I2C_OwnAddress2Config() and enabled
+ * by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED
+ * (where XXX could be TRANSMITTER or RECEIVER) are set.
+ *
+ * c) In case the address sent by the master is General Call (address 0x00) and
+ * if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd())
+ * the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED.
+ *
+ */
+
+/* EVT1 */
+/* a) Case of One Single Address managed by the slave */
+#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */
+#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */
+
+/* b) Case of Dual address managed by the slave */
+#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */
+#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */
+
+/* c) Case of General Call enabled for the slave */
+#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */
+
+/********************************************************************************************************************
+ * @brief Communication events
+ *
+ * Wait on one of these events when EVT1 has already been checked :
+ *
+ * - Slave Receiver mode:
+ * - EVT2--The device is expecting to receive a data byte .
+ * - EVT4--The device is expecting the end of the communication: master
+ * sends a stop condition and data transmission is stopped.
+ *
+ * - Slave Transmitter mode:
+ * - EVT3--When a byte has been transmitted by the slave and the Master is expecting
+ * the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and
+ * I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. If the user software doesn't guarantee
+ * the EVT3 is managed before the current byte end of transfer The second one can optionally
+ * be used.
+ * - EVT3_2--When the master sends a NACK to tell slave device that data transmission
+ * shall end . The slave device has to stop sending
+ * data bytes and wait a Stop condition from bus.
+ *
+ * Note:
+ * If the user software does not guarantee that the event 2 is
+ * managed before the current byte end of transfer, User may check on I2C_EVENT_SLAVE_BYTE_RECEIVED
+ * and I2C_FLAG_BTF flag at the same time .
+ * In this case the communication will be slower.
+ *
+ */
+
+/* Slave Receiver mode*/
+/* EVT2 */
+#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */
+/* EVT4 */
+#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */
+
+/* Slave Transmitter mode -----------------------*/
+/* EVT3 */
+#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */
+#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */
+/*EVT3_2 */
+#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */
+
+
+/* ch32v00x_iwdg.h -----------------------------------------------------------*/
+
+/* IWDG_WriteAccess */
+#define IWDG_WriteAccess_Enable ((uint16_t)0x5555)
+#define IWDG_WriteAccess_Disable ((uint16_t)0x0000)
+
+/* IWDG_prescaler */
+#define IWDG_Prescaler_4 ((uint8_t)0x00)
+#define IWDG_Prescaler_8 ((uint8_t)0x01)
+#define IWDG_Prescaler_16 ((uint8_t)0x02)
+#define IWDG_Prescaler_32 ((uint8_t)0x03)
+#define IWDG_Prescaler_64 ((uint8_t)0x04)
+#define IWDG_Prescaler_128 ((uint8_t)0x05)
+#define IWDG_Prescaler_256 ((uint8_t)0x06)
+
+/* IWDG_Flag */
+#define IWDG_FLAG_PVU ((uint16_t)0x0001)
+#define IWDG_FLAG_RVU ((uint16_t)0x0002)
+
+
+/* ch32v00x_misc.h -----------------------------------------------------------*/
+
+/* Preemption_Priority_Group */
+#define NVIC_PriorityGroup_0 ((uint32_t)0x00)
+#define NVIC_PriorityGroup_1 ((uint32_t)0x01)
+#define NVIC_PriorityGroup_2 ((uint32_t)0x02)
+#define NVIC_PriorityGroup_3 ((uint32_t)0x03)
+#define NVIC_PriorityGroup_4 ((uint32_t)0x04)
+
+
+/* ch32v00x_opa.h ------------------------------------------------------------*/
+
+/* Editor's note: I don't know if this is actually useful */
+
+/* OPA PSEL enumeration */
+typedef enum
+{
+ CHP0 = 0,
+ CHP1
+} OPA_PSEL_TypeDef;
+
+/* OPA NSEL enumeration */
+typedef enum
+{
+ CHN0 = 0,
+ CHN1
+} OPA_NSEL_TypeDef;
+
+
+/* OPA Init Structure definition */
+typedef struct
+{
+ OPA_PSEL_TypeDef PSEL; /* Specifies the positive channel of OPA */
+ OPA_NSEL_TypeDef NSEL; /* Specifies the negative channel of OPA */
+} OPA_InitTypeDef;
+
+
+/* ch32v00x_pwr.h ------------------------------------------------------------*/
+
+
+/* PVD_detection_level */
+#define PWR_PVDLevel_2V9 ((uint32_t)0x00000000)
+#define PWR_PVDLevel_3V1 ((uint32_t)0x00000020)
+#define PWR_PVDLevel_3V3 ((uint32_t)0x00000040)
+#define PWR_PVDLevel_3V5 ((uint32_t)0x00000060)
+#define PWR_PVDLevel_3V7 ((uint32_t)0x00000080)
+#define PWR_PVDLevel_3V9 ((uint32_t)0x000000A0)
+#define PWR_PVDLevel_4V1 ((uint32_t)0x000000C0)
+#define PWR_PVDLevel_4V4 ((uint32_t)0x000000E0)
+
+/* PWR_AWU_Prescaler */
+#define PWR_AWU_Prescaler_1 ((uint32_t)0x00000000)
+#define PWR_AWU_Prescaler_2 ((uint32_t)0x00000002)
+#define PWR_AWU_Prescaler_4 ((uint32_t)0x00000003)
+#define PWR_AWU_Prescaler_8 ((uint32_t)0x00000004)
+#define PWR_AWU_Prescaler_16 ((uint32_t)0x00000005)
+#define PWR_AWU_Prescaler_32 ((uint32_t)0x00000006)
+#define PWR_AWU_Prescaler_64 ((uint32_t)0x00000007)
+#define PWR_AWU_Prescaler_128 ((uint32_t)0x00000008)
+#define PWR_AWU_Prescaler_256 ((uint32_t)0x00000009)
+#define PWR_AWU_Prescaler_512 ((uint32_t)0x0000000A)
+#define PWR_AWU_Prescaler_1024 ((uint32_t)0x0000000B)
+#define PWR_AWU_Prescaler_2048 ((uint32_t)0x0000000C)
+#define PWR_AWU_Prescaler_4096 ((uint32_t)0x0000000D)
+#define PWR_AWU_Prescaler_10240 ((uint32_t)0x0000000E)
+#define PWR_AWU_Prescaler_61440 ((uint32_t)0x0000000F)
+
+/* STOP_mode_entry */
+#define PWR_STANDBYEntry_WFI ((uint8_t)0x01)
+#define PWR_STANDBYEntry_WFE ((uint8_t)0x02)
+
+/* PWR_Flag */
+#define PWR_FLAG_PVDO ((uint32_t)0x00000004)
+
+
+/* ch32v00x_rcc.h ------------------------------------------------------------*/
+
+
+/* HSE_configuration */
+#define RCC_HSE_OFF ((uint32_t)0x00000000)
+#define RCC_HSE_ON ((uint32_t)0x00010000)
+#define RCC_HSE_Bypass ((uint32_t)0x00040000)
+
+/* PLL_entry_clock_source */
+#define RCC_PLLSource_HSI_MUL2 ((uint32_t)0x00000000)
+#define RCC_PLLSource_HSE_MUL2 ((uint32_t)0x00030000)
+
+/* System_clock_source */
+#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000)
+#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001)
+#define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002)
+
+/* AHB_clock_source */
+#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000)
+#define RCC_SYSCLK_Div2 ((uint32_t)0x00000010)
+#define RCC_SYSCLK_Div3 ((uint32_t)0x00000020)
+#define RCC_SYSCLK_Div4 ((uint32_t)0x00000030)
+#define RCC_SYSCLK_Div5 ((uint32_t)0x00000040)
+#define RCC_SYSCLK_Div6 ((uint32_t)0x00000050)
+#define RCC_SYSCLK_Div7 ((uint32_t)0x00000060)
+#define RCC_SYSCLK_Div8 ((uint32_t)0x00000070)
+#define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0)
+#define RCC_SYSCLK_Div32 ((uint32_t)0x000000C0)
+#define RCC_SYSCLK_Div64 ((uint32_t)0x000000D0)
+#define RCC_SYSCLK_Div128 ((uint32_t)0x000000E0)
+#define RCC_SYSCLK_Div256 ((uint32_t)0x000000F0)
+
+/* RCC_Interrupt_source */
+#define RCC_IT_LSIRDY ((uint8_t)0x01)
+#define RCC_IT_HSIRDY ((uint8_t)0x04)
+#define RCC_IT_HSERDY ((uint8_t)0x08)
+#define RCC_IT_PLLRDY ((uint8_t)0x10)
+#define RCC_IT_CSS ((uint8_t)0x80)
+
+/* ADC_clock_source */
+#define RCC_PCLK2_Div2 ((uint32_t)0x00000000)
+#define RCC_PCLK2_Div4 ((uint32_t)0x00004000)
+#define RCC_PCLK2_Div6 ((uint32_t)0x00008000)
+#define RCC_PCLK2_Div8 ((uint32_t)0x0000C000)
+#define RCC_PCLK2_Div12 ((uint32_t)0x0000A000)
+#define RCC_PCLK2_Div16 ((uint32_t)0x0000E000)
+#define RCC_PCLK2_Div24 ((uint32_t)0x0000A800)
+#define RCC_PCLK2_Div32 ((uint32_t)0x0000E800)
+#define RCC_PCLK2_Div48 ((uint32_t)0x0000B000)
+#define RCC_PCLK2_Div64 ((uint32_t)0x0000F000)
+#define RCC_PCLK2_Div96 ((uint32_t)0x0000B800)
+#define RCC_PCLK2_Div128 ((uint32_t)0x0000F800)
+
+/* AHB_peripheral */
+#define RCC_AHBPeriph_DMA1 ((uint32_t)0x00000001)
+#define RCC_AHBPeriph_SRAM ((uint32_t)0x00000004)
+
+/* APB2_peripheral */
+#define RCC_APB2Periph_AFIO ((uint32_t)0x00000001)
+#define RCC_APB2Periph_GPIOA ((uint32_t)0x00000004)
+#define RCC_APB2Periph_GPIOC ((uint32_t)0x00000010)
+#define RCC_APB2Periph_GPIOD ((uint32_t)0x00000020)
+#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000200)
+#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000800)
+#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000)
+#define RCC_APB2Periph_USART1 ((uint32_t)0x00004000)
+
+/* APB1_peripheral */
+#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001)
+#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800)
+#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000)
+#define RCC_APB1Periph_PWR ((uint32_t)0x10000000)
+
+/* Clock_source_to_output_on_MCO_pin */
+#define RCC_MCO_NoClock ((uint8_t)0x00)
+#define RCC_MCO_SYSCLK ((uint8_t)0x04)
+#define RCC_MCO_HSI ((uint8_t)0x05)
+#define RCC_MCO_HSE ((uint8_t)0x06)
+#define RCC_MCO_PLLCLK ((uint8_t)0x07)
+
+/* RCC_Flag */
+#define RCC_FLAG_HSIRDY ((uint8_t)0x21)
+#define RCC_FLAG_HSERDY ((uint8_t)0x31)
+#define RCC_FLAG_PLLRDY ((uint8_t)0x39)
+#define RCC_FLAG_LSIRDY ((uint8_t)0x61)
+#define RCC_FLAG_PINRST ((uint8_t)0x7A)
+#define RCC_FLAG_PORRST ((uint8_t)0x7B)
+#define RCC_FLAG_SFTRST ((uint8_t)0x7C)
+#define RCC_FLAG_IWDGRST ((uint8_t)0x7D)
+#define RCC_FLAG_WWDGRST ((uint8_t)0x7E)
+#define RCC_FLAG_LPWRRST ((uint8_t)0x7F)
+
+/* SysTick_clock_source */
+#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB)
+#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004)
+
+
+/* ch32v00x_spi.h ------------------------------------------------------------*/
+
+
+/* SPI_data_direction */
+#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000)
+#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400)
+#define SPI_Direction_1Line_Rx ((uint16_t)0x8000)
+#define SPI_Direction_1Line_Tx ((uint16_t)0xC000)
+
+/* SPI_mode */
+#define SPI_Mode_Master ((uint16_t)0x0104)
+#define SPI_Mode_Slave ((uint16_t)0x0000)
+
+/* SPI_data_size */
+#define SPI_DataSize_16b ((uint16_t)0x0800)
+#define SPI_DataSize_8b ((uint16_t)0x0000)
+
+/* SPI_Clock_Polarity */
+#define SPI_CPOL_Low ((uint16_t)0x0000)
+#define SPI_CPOL_High ((uint16_t)0x0002)
+
+/* SPI_Clock_Phase */
+#define SPI_CPHA_1Edge ((uint16_t)0x0000)
+#define SPI_CPHA_2Edge ((uint16_t)0x0001)
+
+/* SPI_Slave_Select_management */
+#define SPI_NSS_Soft ((uint16_t)0x0200)
+#define SPI_NSS_Hard ((uint16_t)0x0000)
+
+/* SPI_BaudRate_Prescaler */
+#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000)
+#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008)
+#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010)
+#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018)
+#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020)
+#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028)
+#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030)
+#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038)
+
+/* SPI_MSB transmission */
+#define SPI_FirstBit_MSB ((uint16_t)0x0000)
+
+/* SPI_I2S_DMA_transfer_requests */
+#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002)
+#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001)
+
+/* SPI_NSS_internal_software_management */
+#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100)
+#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF)
+
+/* SPI_CRC_Transmit_Receive */
+#define SPI_CRC_Tx ((uint8_t)0x00)
+#define SPI_CRC_Rx ((uint8_t)0x01)
+
+/* SPI_direction_transmit_receive */
+#define SPI_Direction_Rx ((uint16_t)0xBFFF)
+#define SPI_Direction_Tx ((uint16_t)0x4000)
+
+/* SPI_I2S_interrupts_definition */
+#define SPI_I2S_IT_TXE ((uint8_t)0x71)
+#define SPI_I2S_IT_RXNE ((uint8_t)0x60)
+#define SPI_I2S_IT_ERR ((uint8_t)0x50)
+#define SPI_I2S_IT_OVR ((uint8_t)0x56)
+#define SPI_IT_MODF ((uint8_t)0x55)
+#define SPI_IT_CRCERR ((uint8_t)0x54)
+#define I2S_IT_UDR ((uint8_t)0x53)
+
+/* SPI_I2S_flags_definition */
+#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001)
+#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002)
+#define I2S_FLAG_CHSIDE ((uint16_t)0x0004)
+#define I2S_FLAG_UDR ((uint16_t)0x0008)
+#define SPI_FLAG_CRCERR ((uint16_t)0x0010)
+#define SPI_FLAG_MODF ((uint16_t)0x0020)
+#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040)
+#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080)
+
+
+/* ch32v00x_tim.h ------------------------------------------------------------*/
+
+/* TIM_Output_Compare_and_PWM_modes */
+#define TIM_OCMode_Timing ((uint16_t)0x0000)
+#define TIM_OCMode_Active ((uint16_t)0x0010)
+#define TIM_OCMode_Inactive ((uint16_t)0x0020)
+#define TIM_OCMode_Toggle ((uint16_t)0x0030)
+#define TIM_OCMode_PWM1 ((uint16_t)0x0060)
+#define TIM_OCMode_PWM2 ((uint16_t)0x0070)
+
+/* TIM_One_Pulse_Mode */
+#define TIM_OPMode_Single ((uint16_t)0x0008)
+#define TIM_OPMode_Repetitive ((uint16_t)0x0000)
+
+/* TIM_Channel */
+#define TIM_Channel_1 ((uint16_t)0x0000)
+#define TIM_Channel_2 ((uint16_t)0x0004)
+#define TIM_Channel_3 ((uint16_t)0x0008)
+#define TIM_Channel_4 ((uint16_t)0x000C)
+
+/* TIM_Clock_Division_CKD */
+#define TIM_CKD_DIV1 ((uint16_t)0x0000)
+#define TIM_CKD_DIV2 ((uint16_t)0x0100)
+#define TIM_CKD_DIV4 ((uint16_t)0x0200)
+
+/* TIM_Counter_Mode */
+#define TIM_CounterMode_Up ((uint16_t)0x0000)
+#define TIM_CounterMode_Down ((uint16_t)0x0010)
+#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020)
+#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040)
+#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060)
+
+/* TIM_Output_Compare_Polarity */
+#define TIM_OCPolarity_High ((uint16_t)0x0000)
+#define TIM_OCPolarity_Low ((uint16_t)0x0002)
+
+/* TIM_Output_Compare_N_Polarity */
+#define TIM_OCNPolarity_High ((uint16_t)0x0000)
+#define TIM_OCNPolarity_Low ((uint16_t)0x0008)
+
+/* TIM_Output_Compare_state */
+#define TIM_OutputState_Disable ((uint16_t)0x0000)
+#define TIM_OutputState_Enable ((uint16_t)0x0001)
+
+/* TIM_Output_Compare_N_state */
+#define TIM_OutputNState_Disable ((uint16_t)0x0000)
+#define TIM_OutputNState_Enable ((uint16_t)0x0004)
+
+/* TIM_Capture_Compare_state */
+#define TIM_CCx_Enable ((uint16_t)0x0001)
+#define TIM_CCx_Disable ((uint16_t)0x0000)
+
+/* TIM_Capture_Compare_N_state */
+#define TIM_CCxN_Enable ((uint16_t)0x0004)
+#define TIM_CCxN_Disable ((uint16_t)0x0000)
+
+/* Break_Input_enable_disable */
+#define TIM_Break_Enable ((uint16_t)0x1000)
+#define TIM_Break_Disable ((uint16_t)0x0000)
+
+/* Break_Polarity */
+#define TIM_BreakPolarity_Low ((uint16_t)0x0000)
+#define TIM_BreakPolarity_High ((uint16_t)0x2000)
+
+/* TIM_AOE_Bit_Set_Reset */
+#define TIM_AutomaticOutput_Enable ((uint16_t)0x4000)
+#define TIM_AutomaticOutput_Disable ((uint16_t)0x0000)
+
+/* Lock_level */
+#define TIM_LOCKLevel_OFF ((uint16_t)0x0000)
+#define TIM_LOCKLevel_1 ((uint16_t)0x0100)
+#define TIM_LOCKLevel_2 ((uint16_t)0x0200)
+#define TIM_LOCKLevel_3 ((uint16_t)0x0300)
+
+/* OSSI_Off_State_Selection_for_Idle_mode_state */
+#define TIM_OSSIState_Enable ((uint16_t)0x0400)
+#define TIM_OSSIState_Disable ((uint16_t)0x0000)
+
+/* OSSR_Off_State_Selection_for_Run_mode_state */
+#define TIM_OSSRState_Enable ((uint16_t)0x0800)
+#define TIM_OSSRState_Disable ((uint16_t)0x0000)
+
+/* TIM_Output_Compare_Idle_State */
+#define TIM_OCIdleState_Set ((uint16_t)0x0100)
+#define TIM_OCIdleState_Reset ((uint16_t)0x0000)
+
+/* TIM_Output_Compare_N_Idle_State */
+#define TIM_OCNIdleState_Set ((uint16_t)0x0200)
+#define TIM_OCNIdleState_Reset ((uint16_t)0x0000)
+
+/* TIM_Input_Capture_Polarity */
+#define TIM_ICPolarity_Rising ((uint16_t)0x0000)
+#define TIM_ICPolarity_Falling ((uint16_t)0x0002)
+#define TIM_ICPolarity_BothEdge ((uint16_t)0x000A)
+
+/* TIM_Input_Capture_Selection */
+#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /* TIM Input 1, 2, 3 or 4 is selected to be \
+ connected to IC1, IC2, IC3 or IC4, respectively */
+#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /* TIM Input 1, 2, 3 or 4 is selected to be \
+ connected to IC2, IC1, IC4 or IC3, respectively. */
+#define TIM_ICSelection_TRC ((uint16_t)0x0003) /* TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */
+
+/* TIM_Input_Capture_Prescaler */
+#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /* Capture performed each time an edge is detected on the capture input. */
+#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /* Capture performed once every 2 events. */
+#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /* Capture performed once every 4 events. */
+#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /* Capture performed once every 8 events. */
+
+/* TIM_interrupt_sources */
+#define TIM_IT_Update ((uint16_t)0x0001)
+#define TIM_IT_CC1 ((uint16_t)0x0002)
+#define TIM_IT_CC2 ((uint16_t)0x0004)
+#define TIM_IT_CC3 ((uint16_t)0x0008)
+#define TIM_IT_CC4 ((uint16_t)0x0010)
+#define TIM_IT_COM ((uint16_t)0x0020)
+#define TIM_IT_Trigger ((uint16_t)0x0040)
+#define TIM_IT_Break ((uint16_t)0x0080)
+
+/* TIM_DMA_Base_address */
+#define TIM_DMABase_CR1 ((uint16_t)0x0000)
+#define TIM_DMABase_CR2 ((uint16_t)0x0001)
+#define TIM_DMABase_SMCR ((uint16_t)0x0002)
+#define TIM_DMABase_DIER ((uint16_t)0x0003)
+#define TIM_DMABase_SR ((uint16_t)0x0004)
+#define TIM_DMABase_EGR ((uint16_t)0x0005)
+#define TIM_DMABase_CCMR1 ((uint16_t)0x0006)
+#define TIM_DMABase_CCMR2 ((uint16_t)0x0007)
+#define TIM_DMABase_CCER ((uint16_t)0x0008)
+#define TIM_DMABase_CNT ((uint16_t)0x0009)
+#define TIM_DMABase_PSC ((uint16_t)0x000A)
+#define TIM_DMABase_ARR ((uint16_t)0x000B)
+#define TIM_DMABase_RCR ((uint16_t)0x000C)
+#define TIM_DMABase_CCR1 ((uint16_t)0x000D)
+#define TIM_DMABase_CCR2 ((uint16_t)0x000E)
+#define TIM_DMABase_CCR3 ((uint16_t)0x000F)
+#define TIM_DMABase_CCR4 ((uint16_t)0x0010)
+#define TIM_DMABase_BDTR ((uint16_t)0x0011)
+#define TIM_DMABase_DCR ((uint16_t)0x0012)
+
+/* TIM_DMA_Burst_Length */
+#define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000)
+#define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100)
+#define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200)
+#define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300)
+#define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400)
+#define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500)
+#define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600)
+#define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700)
+#define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800)
+#define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900)
+#define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00)
+#define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00)
+#define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00)
+#define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00)
+#define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00)
+#define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00)
+#define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000)
+#define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100)
+
+/* TIM_DMA_sources */
+#define TIM_DMA_Update ((uint16_t)0x0100)
+#define TIM_DMA_CC1 ((uint16_t)0x0200)
+#define TIM_DMA_CC2 ((uint16_t)0x0400)
+#define TIM_DMA_CC3 ((uint16_t)0x0800)
+#define TIM_DMA_CC4 ((uint16_t)0x1000)
+#define TIM_DMA_COM ((uint16_t)0x2000)
+#define TIM_DMA_Trigger ((uint16_t)0x4000)
+
+/* TIM_External_Trigger_Prescaler */
+#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000)
+#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000)
+#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000)
+#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000)
+
+/* TIM_Internal_Trigger_Selection */
+#define TIM_TS_ITR0 ((uint16_t)0x0000)
+#define TIM_TS_ITR1 ((uint16_t)0x0010)
+#define TIM_TS_ITR2 ((uint16_t)0x0020)
+#define TIM_TS_ITR3 ((uint16_t)0x0030)
+#define TIM_TS_TI1F_ED ((uint16_t)0x0040)
+#define TIM_TS_TI1FP1 ((uint16_t)0x0050)
+#define TIM_TS_TI2FP2 ((uint16_t)0x0060)
+#define TIM_TS_ETRF ((uint16_t)0x0070)
+
+/* TIM_TIx_External_Clock_Source */
+#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050)
+#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060)
+#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040)
+
+/* TIM_External_Trigger_Polarity */
+#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000)
+#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000)
+
+/* TIM_Prescaler_Reload_Mode */
+#define TIM_PSCReloadMode_Update ((uint16_t)0x0000)
+#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001)
+
+/* TIM_Forced_Action */
+#define TIM_ForcedAction_Active ((uint16_t)0x0050)
+#define TIM_ForcedAction_InActive ((uint16_t)0x0040)
+
+/* TIM_Encoder_Mode */
+#define TIM_EncoderMode_TI1 ((uint16_t)0x0001)
+#define TIM_EncoderMode_TI2 ((uint16_t)0x0002)
+#define TIM_EncoderMode_TI12 ((uint16_t)0x0003)
+
+/* TIM_Event_Source */
+#define TIM_EventSource_Update ((uint16_t)0x0001)
+#define TIM_EventSource_CC1 ((uint16_t)0x0002)
+#define TIM_EventSource_CC2 ((uint16_t)0x0004)
+#define TIM_EventSource_CC3 ((uint16_t)0x0008)
+#define TIM_EventSource_CC4 ((uint16_t)0x0010)
+#define TIM_EventSource_COM ((uint16_t)0x0020)
+#define TIM_EventSource_Trigger ((uint16_t)0x0040)
+#define TIM_EventSource_Break ((uint16_t)0x0080)
+
+/* TIM_Update_Source */
+#define TIM_UpdateSource_Global ((uint16_t)0x0000) /* Source of update is the counter overflow/underflow \
+ or the setting of UG bit, or an update generation \
+ through the slave mode controller. */
+#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /* Source of update is counter overflow/underflow. */
+
+/* TIM_Output_Compare_Preload_State */
+#define TIM_OCPreload_Enable ((uint16_t)0x0008)
+#define TIM_OCPreload_Disable ((uint16_t)0x0000)
+
+/* TIM_Output_Compare_Fast_State */
+#define TIM_OCFast_Enable ((uint16_t)0x0004)
+#define TIM_OCFast_Disable ((uint16_t)0x0000)
+
+/* TIM_Output_Compare_Clear_State */
+#define TIM_OCClear_Enable ((uint16_t)0x0080)
+#define TIM_OCClear_Disable ((uint16_t)0x0000)
+
+/* TIM_Trigger_Output_Source */
+#define TIM_TRGOSource_Reset ((uint16_t)0x0000)
+#define TIM_TRGOSource_Enable ((uint16_t)0x0010)
+#define TIM_TRGOSource_Update ((uint16_t)0x0020)
+#define TIM_TRGOSource_OC1 ((uint16_t)0x0030)
+#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040)
+#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050)
+#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060)
+#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070)
+
+/* TIM_Slave_Mode */
+#define TIM_SlaveMode_Reset ((uint16_t)0x0004)
+#define TIM_SlaveMode_Gated ((uint16_t)0x0005)
+#define TIM_SlaveMode_Trigger ((uint16_t)0x0006)
+#define TIM_SlaveMode_External1 ((uint16_t)0x0007)
+
+/* TIM_Master_Slave_Mode */
+#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080)
+#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000)
+
+/* TIM_Flags */
+#define TIM_FLAG_Update ((uint16_t)0x0001)
+#define TIM_FLAG_CC1 ((uint16_t)0x0002)
+#define TIM_FLAG_CC2 ((uint16_t)0x0004)
+#define TIM_FLAG_CC3 ((uint16_t)0x0008)
+#define TIM_FLAG_CC4 ((uint16_t)0x0010)
+#define TIM_FLAG_COM ((uint16_t)0x0020)
+#define TIM_FLAG_Trigger ((uint16_t)0x0040)
+#define TIM_FLAG_Break ((uint16_t)0x0080)
+#define TIM_FLAG_CC1OF ((uint16_t)0x0200)
+#define TIM_FLAG_CC2OF ((uint16_t)0x0400)
+#define TIM_FLAG_CC3OF ((uint16_t)0x0800)
+#define TIM_FLAG_CC4OF ((uint16_t)0x1000)
+
+/* TIM_Legacy */
+#define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer
+#define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers
+#define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers
+#define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers
+#define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers
+#define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers
+#define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers
+#define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers
+#define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers
+#define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers
+#define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers
+#define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers
+#define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers
+#define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers
+#define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers
+#define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers
+#define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers
+#define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers
+
+
+/* ch32v00x_usart.h ----------------------------------------------------------*/
+
+/* USART_Word_Length */
+#define USART_WordLength_8b ((uint16_t)0x0000)
+#define USART_WordLength_9b ((uint16_t)0x1000)
+
+/* USART_Stop_Bits */
+#define USART_StopBits_1 ((uint16_t)0x0000)
+#define USART_StopBits_0_5 ((uint16_t)0x1000)
+#define USART_StopBits_2 ((uint16_t)0x2000)
+#define USART_StopBits_1_5 ((uint16_t)0x3000)
+
+/* USART_Parity */
+#define USART_Parity_No ((uint16_t)0x0000)
+#define USART_Parity_Even ((uint16_t)0x0400)
+#define USART_Parity_Odd ((uint16_t)0x0600)
+
+/* USART_Mode */
+#define USART_Mode_Rx ((uint16_t)0x0004)
+#define USART_Mode_Tx ((uint16_t)0x0008)
+
+/* USART_Hardware_Flow_Control */
+#define USART_HardwareFlowControl_None ((uint16_t)0x0000)
+#define USART_HardwareFlowControl_RTS ((uint16_t)0x0100)
+#define USART_HardwareFlowControl_CTS ((uint16_t)0x0200)
+#define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300)
+
+/* USART_Clock */
+#define USART_Clock_Disable ((uint16_t)0x0000)
+#define USART_Clock_Enable ((uint16_t)0x0800)
+
+/* USART_Clock_Polarity */
+#define USART_CPOL_Low ((uint16_t)0x0000)
+#define USART_CPOL_High ((uint16_t)0x0400)
+
+/* USART_Clock_Phase */
+#define USART_CPHA_1Edge ((uint16_t)0x0000)
+#define USART_CPHA_2Edge ((uint16_t)0x0200)
+
+/* USART_Last_Bit */
+#define USART_LastBit_Disable ((uint16_t)0x0000)
+#define USART_LastBit_Enable ((uint16_t)0x0100)
+
+/* USART_Interrupt_definition */
+#define USART_IT_PE ((uint16_t)0x0028)
+#define USART_IT_TXE ((uint16_t)0x0727)
+#define USART_IT_TC ((uint16_t)0x0626)
+#define USART_IT_RXNE ((uint16_t)0x0525)
+#define USART_IT_ORE_RX ((uint16_t)0x0325)
+#define USART_IT_IDLE ((uint16_t)0x0424)
+#define USART_IT_LBD ((uint16_t)0x0846)
+#define USART_IT_CTS ((uint16_t)0x096A)
+#define USART_IT_ERR ((uint16_t)0x0060)
+#define USART_IT_ORE_ER ((uint16_t)0x0360)
+#define USART_IT_NE ((uint16_t)0x0260)
+#define USART_IT_FE ((uint16_t)0x0160)
+
+#define USART_IT_ORE USART_IT_ORE_ER
+
+/* USART_DMA_Requests */
+#define USART_DMAReq_Tx ((uint16_t)0x0080)
+#define USART_DMAReq_Rx ((uint16_t)0x0040)
+
+/* USART_WakeUp_methods */
+#define USART_WakeUp_IdleLine ((uint16_t)0x0000)
+#define USART_WakeUp_AddressMark ((uint16_t)0x0800)
+
+/* USART_LIN_Break_Detection_Length */
+#define USART_LINBreakDetectLength_10b ((uint16_t)0x0000)
+#define USART_LINBreakDetectLength_11b ((uint16_t)0x0020)
+
+/* USART_IrDA_Low_Power */
+#define USART_IrDAMode_LowPower ((uint16_t)0x0004)
+#define USART_IrDAMode_Normal ((uint16_t)0x0000)
+
+/* USART_Flags */
+#define USART_FLAG_CTS ((uint16_t)0x0200)
+#define USART_FLAG_LBD ((uint16_t)0x0100)
+#define USART_FLAG_TXE ((uint16_t)0x0080)
+#define USART_FLAG_TC ((uint16_t)0x0040)
+#define USART_FLAG_RXNE ((uint16_t)0x0020)
+#define USART_FLAG_IDLE ((uint16_t)0x0010)
+#define USART_FLAG_ORE ((uint16_t)0x0008)
+#define USART_FLAG_NE ((uint16_t)0x0004)
+#define USART_FLAG_FE ((uint16_t)0x0002)
+#define USART_FLAG_PE ((uint16_t)0x0001)
+
+/* ch32v00x_wwdg.h -----------------------------------------------------------*/
+
+
+/* WWDG_Prescaler */
+#define WWDG_Prescaler_1 ((uint32_t)0x00000000)
+#define WWDG_Prescaler_2 ((uint32_t)0x00000080)
+#define WWDG_Prescaler_4 ((uint32_t)0x00000100)
+#define WWDG_Prescaler_8 ((uint32_t)0x00000180)
+
+
+/* from debug.h/.c ------------------------------------------------------*/
+
+#ifndef __DEBUG_H
+#define __DEBUG_H
+
+// Functions rewritten by cnlohr
+
+#define DELAY_US_TIME (SYSTEM_CORE_CLOCK / 8000000)
+#define DELAY_MS_TIME (SYSTEM_CORE_CLOCK / 8000)
+
+static void DelaySysTick( uint32_t n )
+{
+ SysTick->SR &= ~(1 << 0);
+ SysTick->CMP = n;
+ SysTick->CNT = 0;
+ SysTick->CTLR |=(1 << 0);
+ while(!(SysTick->SR & (1 << 0)));
+ SysTick->CTLR &= ~(1 << 0);
+}
+
+#define Delay_Us(n) DelaySysTick( n * DELAY_US_TIME )
+#define Delay_Ms(n) DelaySysTick( n * DELAY_MS_TIME )
+
+#endif
+
+
+#ifdef __cplusplus
+};
+#endif
+
+
+
+
#endif /* __CH32V00x_CONF_H */
diff --git a/EVT/embedlibc.c b/ch32v003evt/embedlibc.c
similarity index 100%
rename from EVT/embedlibc.c
rename to ch32v003evt/embedlibc.c
diff --git a/minichlink/test.bat b/minichlink/test.bat
new file mode 100644
index 0000000000000000000000000000000000000000..3f9a1bfd1df10365d470a54bc608834c137a23f8
--- /dev/null
+++ b/minichlink/test.bat
@@ -0,0 +1,9 @@
+
+
+tcc wch_erase.c libusb-1.0.dll
+tcc wch_reset.c libusb-1.0.dll
+tcc wch_write_simple.c libusb-1.0.dll
+
+wch_erase.exe
+wch_write_simple.exe ..\barebones\barebones.bin
+wch_reset.exe
diff --git a/minichlink/wch_erase.c b/minichlink/wch_erase.c
index e14d1325c0134754c59e77380d6b8c19892f0518..96452041c447f22e7429972772025f9b83fc484b 100644
--- a/minichlink/wch_erase.c
+++ b/minichlink/wch_erase.c
@@ -5,14 +5,14 @@
int main()
{
+ uint8_t rbuff[1024];
libusb_device_handle * devh = wch_link_base_setup();
int transferred;
int status;
- WCHCHECK( libusb_bulk_transfer( devh, 0x01, "\x81\x0d\x01\x01", 4, &transferred, WCHTIMEOUT ) );
- WCHCHECK( libusb_bulk_transfer( devh, 0x01, "\x81\x0c\x02\x09\x01", 5, &transferred, WCHTIMEOUT ) );
- WCHCHECK( libusb_bulk_transfer( devh, 0x01, "\x81\x0d\x01\x02", 4, &transferred, WCHTIMEOUT) );
- WCHCHECK( libusb_bulk_transfer( devh, 0x01, "\x81\x11\x01\x09", 4, &transferred, WCHTIMEOUT) );
WCHCHECK( libusb_bulk_transfer( devh, 0x01, "\x81\x02\x01\x01", 4, &transferred, WCHTIMEOUT) );
+ WCHCHECK( libusb_bulk_transfer( devh, 0x81, rbuff, 1024, &transferred, 500 ) ); // Ignore respone.
WCHCHECK( libusb_bulk_transfer( devh, 0x01, "\x81\x0d\x01\x02", 4, &transferred, WCHTIMEOUT) );
+ WCHCHECK( libusb_bulk_transfer( devh, 0x81, rbuff, 1024, &transferred, 500 ) ); // Ignore respone.
WCHCHECK( libusb_bulk_transfer( devh, 0x01, "\x81\x0d\x01\xff", 4, &transferred, WCHTIMEOUT) );
+ WCHCHECK( libusb_bulk_transfer( devh, 0x81, rbuff, 1024, &transferred, 500 ) ); // Ignore respone.
}
diff --git a/minichlink/wch_link_base.h b/minichlink/wch_link_base.h
index 1a1125d28490ae41d8ddd47865dc082af084f06c..515d9521ef863413a2d9208bb47c4bfc50b13c9f 100644
--- a/minichlink/wch_link_base.h
+++ b/minichlink/wch_link_base.h
@@ -6,7 +6,37 @@
#include "libusb.h"
#define WCHTIMEOUT 5000
-#define WCHCHECK(x) if( status = x ) { fprintf( stderr, "Bad USB Operation on line %d (%d)\n", __LINE__, status ); exit( status ); }
+#define WCHCHECK(x) if( status = x ) { fprintf( stderr, "Bad USB Operation on " __FILE__ ":%d (%d)\n", __LINE__, status ); exit( status ); }
+
+void wch_link_command( libusb_device_handle * devh, const uint8_t * command, int commandlen, int * transferred, uint8_t * reply, int replymax )
+{
+ uint8_t buffer[1024];
+ int got_to_recv = 0;
+ int status;
+ int transferred_local;
+ if( !transferred ) transferred = &transferred_local;
+ status = libusb_bulk_transfer( devh, 0x01, (char*)command, commandlen, transferred, WCHTIMEOUT );
+ if( status ) goto sendfail;
+
+ got_to_recv = 1;
+ if( !reply )
+ {
+ reply = buffer; replymax = sizeof( buffer );
+ }
+
+ status = libusb_bulk_transfer( devh, 0x81, (char*)reply, replymax, transferred, WCHTIMEOUT );
+ if( status ) goto sendfail;
+ return;
+sendfail:
+ fprintf( stderr, "Error sending WCH command (%s): ", got_to_recv?"on recv":"on send" );
+ int i;
+ for( i = 0; i < commandlen; i++ )
+ {
+ printf( "%02x ", command[i] );
+ }
+ printf( "\n" );
+ exit( status );
+}
static inline libusb_device_handle * wch_link_base_setup()
{
@@ -49,12 +79,23 @@ static inline libusb_device_handle * wch_link_base_setup()
}
WCHCHECK( libusb_claim_interface(devh, 0) );
- //uint8_t setup_magic_1[] = { 0xcc, 0x08, 0x38, 0xff, 0x80, 0x00, 0x0a };
- //status = libusb_control_transfer(devh, 0x21 /*bmRequestType*/, 0x09 /*bmRequest*/, 0x3cc, 0, setup_magic_1, sizeof(setup_magic_1), TIMEOUT);
- //printf( "Status0: %d\n", status );
- //uint8_t setup_magic_2[] = { 0xcc, 0x08, 0x0f, 0xff, 0x80, 0x00, 0x0a };
- //status = libusb_control_transfer(devh, 0x21 /*bmRequestType*/, 0x09 /*bmRequest*/, 0x3cc, 0, setup_magic_1, sizeof(setup_magic_1), TIMEOUT);
- //printf( "Status1: %d\n", status );
+
+ uint8_t rbuff[1024];
+ int transferred;
+ libusb_bulk_transfer( devh, 0x81, rbuff, 1024, &transferred, 1 ); // Clear out any pending transfers. Don't wait though.
+
+ wch_link_command( devh, "\x81\x0d\x01\x01", 4, 0, 0, 0 ); // Reply is: "\x82\x0d\x04\x02\x08\x02\x00"
+ wch_link_command( devh, "\x81\x0c\x02\x09\x01", 5, 0, 0, 0 ); //Reply is: 820c0101
+ wch_link_command( devh, "\x81\x0d\x01\x02", 4, 0, 0, 0 ); // Reply: Ignored, 820d050900300500
+ wch_link_command( devh, "\x81\x11\x01\x09", 4, &transferred, rbuff, 1024 ); // Reply: Chip ID + Other data (see below)
+ if( transferred != 20 )
+ {
+ fprintf( stderr, "Error: could not get part status\n" );
+ exit( -99 );
+ }
+ fprintf( stderr, "Part Type: 0x%02x%02x\n", rbuff[1], rbuff[2] );
+ fprintf( stderr, "Part UUID: %02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x\n", rbuff[3], rbuff[4], rbuff[5], rbuff[6], rbuff[7], rbuff[8], rbuff[9], rbuff[10] );
+
return devh;
}
diff --git a/minichlink/wch_query.c b/minichlink/wch_query.c
index fdb9e53e9fb9c322f603dad64cfc3692d2fbd283..844f3e53170739eb2a660fc3ee31e01343aed210 100644
--- a/minichlink/wch_query.c
+++ b/minichlink/wch_query.c
@@ -10,23 +10,6 @@ int main()
int transferred;
int status;
char rbuff[1024];
- libusb_bulk_transfer( devh, 0x81, rbuff, 1024, &transferred, 1 ); // Clear out any pending transfers.
-
- WCHCHECK( libusb_bulk_transfer( devh, 0x01, "\x81\x0d\x01\x01", 4, &transferred, WCHTIMEOUT ) ); // Checkme with BULK_IN
- WCHCHECK( libusb_bulk_transfer( devh, 0x81, rbuff, 1024, &transferred, 500 ) ); // Ignore respone.
-// "\x1b\x00\x20\xda\x62\x67\x86\xe0\xff\xff\x00\x00\x00\x00\x09\x00" \
-"\x01\x02\x00\x2f\x00\x81\x03\x07\x00\x00\x00\x82\x0d\x04\x02\x08" \
-"\x02\x00" << Back in
-
- WCHCHECK( libusb_bulk_transfer( devh, 0x01, "\x81\x0c\x02\x09\x01", 5, &transferred, WCHTIMEOUT ) ); // Checkme with BULK_IN
- WCHCHECK( libusb_bulk_transfer( devh, 0x81, rbuff, 1024, &transferred, 500 ) ); // Ignore respone.
-//"\x82\x0c\x01\x01" << Back In
-
-
- WCHCHECK( libusb_bulk_transfer( devh, 0x01, "\x81\x0d\x01\x02", 4, &transferred, WCHTIMEOUT) ); // Checkme with BULK_IN
- WCHCHECK( libusb_bulk_transfer( devh, 0x81, rbuff, 1024, &transferred, 500 ) ); // Ignore respone.
-//"\x82\x0d\x05\x09\x00\x30\x05\x00" << back in.
-
WCHCHECK( libusb_bulk_transfer( devh, 0x01, "\x81\x06\x01\x01", 4, &transferred, WCHTIMEOUT) );
WCHCHECK( libusb_bulk_transfer( devh, 0x81, rbuff, 1024, &transferred, 500 ) ); // Ignore respone.
diff --git a/minichlink/wch_reset.c b/minichlink/wch_reset.c
index 51ee17288384739109c27dcd06fb26ddf0424f90..0a3ee17fcf6426c2bd17686e2265a716aa0b246e 100644
--- a/minichlink/wch_reset.c
+++ b/minichlink/wch_reset.c
@@ -9,11 +9,10 @@ int main()
{
libusb_device_handle * devh = wch_link_base_setup();
int transferred;
+ uint8_t rbuff[1024];
int status;
- WCHCHECK( libusb_bulk_transfer( devh, 0x01, "\x81\x0d\x01\x01", 4, &transferred, WCHTIMEOUT ) );
- WCHCHECK( libusb_bulk_transfer( devh, 0x01, "\x81\x0c\x02\x09\x01", 5, &transferred, WCHTIMEOUT ) );
- WCHCHECK( libusb_bulk_transfer( devh, 0x01, "\x81\x0d\x01\x02", 4, &transferred, WCHTIMEOUT) );
- WCHCHECK( libusb_bulk_transfer( devh, 0x01, "\x81\x11\x01\x09", 4, &transferred, WCHTIMEOUT) );
WCHCHECK( libusb_bulk_transfer( devh, 0x01, "\x81\x0b\x01\x01", 4, &transferred, WCHTIMEOUT) );
+ WCHCHECK( libusb_bulk_transfer( devh, 0x81, rbuff, 1024, &transferred, 500 ) );
WCHCHECK( libusb_bulk_transfer( devh, 0x01, "\x81\x0d\x01\xff", 4, &transferred, WCHTIMEOUT) );
+ WCHCHECK( libusb_bulk_transfer( devh, 0x81, rbuff, 1024, &transferred, 500 ) );
}
\ No newline at end of file
diff --git a/minichlink/wch_write_demo.c b/minichlink/wch_write_demo.c
deleted file mode 100644
index 317cef3769ac01242993891bfdb5a8547cab6342..0000000000000000000000000000000000000000
--- a/minichlink/wch_write_demo.c
+++ /dev/null
@@ -1,135 +0,0 @@
-#include <stdio.h>
-#include "wch_link_base.h"
-
-// TESTED BUT FLAKEY.
-// Flashes a "hummer" to pin D0 (not an arbitrary binary).
-
-int main()
-{
- libusb_device_handle * devh = wch_link_base_setup();
- int transferred;
- int status;
- WCHCHECK( libusb_bulk_transfer( devh, 0x01, "\x81\x0d\x01\x01", 4, &transferred, WCHTIMEOUT ) ); // Checkme with BULK_IN
- WCHCHECK( libusb_bulk_transfer( devh, 0x01, "\x81\x0c\x02\x09\x01", 5, &transferred, WCHTIMEOUT ) ); // Checkme with BULK_IN
- WCHCHECK( libusb_bulk_transfer( devh, 0x01, "\x81\x0d\x01\x02", 4, &transferred, WCHTIMEOUT) ); // Checkme with BULK_IN
- WCHCHECK( libusb_bulk_transfer( devh, 0x01, "\x81\x11\x01\x09", 4, &transferred, WCHTIMEOUT) ); // Checkme with BULK_IN
- WCHCHECK( libusb_bulk_transfer( devh, 0x01, "\x81\x06\x01\x01", 4, &transferred, WCHTIMEOUT) );
- WCHCHECK( libusb_bulk_transfer( devh, 0x01, "\x81\x06\x01\x01", 4, &transferred, WCHTIMEOUT) ); // Odd that it did it twice - maybe something took too long on the proc.
-
- // This contains the write data quantity, in bytes. (The last 2 octets)
- // Then it just rollllls on in.
- WCHCHECK( libusb_bulk_transfer( devh, 0x01, "\x81\x01\x08\x08\x00\x00\x00\x00\x00\x02\x0c", 11, &transferred, WCHTIMEOUT) ); // Still check me.
- WCHCHECK( libusb_bulk_transfer( devh, 0x01, "\x81\x02\x01\x05", 4, &transferred, WCHTIMEOUT) ); // Last checkme til data.
-
- // then just stream this. This is some sort of propreitary image.
- WCHCHECK( libusb_bulk_transfer( devh, 0x01,
-"\x21\x11\x22\xca\x26\xc8\x93\x77\x15\x00\x99\xcf\xb7\x06\x67\x45" \
-"\xb7\x27\x02\x40\x93\x86\x36\x12\x37\x97\xef\xcd\xd4\xc3\x13\x07" \
-"\xb7\x9a\xd8\xc3\xd4\xd3\xd8\xd3\x93\x77\x25\x00\x9d\xc7\xb7\x27" \
-"\x02\x40\x98\x4b\xad\x66\x37\x33\x00\x40\x13\x67\x47\x00\x98\xcb" \
-"\x98\x4b\x93\x86\xa6\xaa\x13\x67\x07\x04\x98\xcb\xd8\x47\x05\x8b" \
-"\x63\x16\x07\x10\x98\x4b\x6d\x9b\x98\xcb\x93\x77\x45\x00\xa9\xcb" \
-"\x93\x07\xf6\x03\x99\x83\x2e\xc0\x2d\x63\x81\x76\x3e\xc4\xb7\x32" \
-"\x00\x40\xb7\x27\x02\x40\x13\x03\xa3\xaa\xfd\x16\x98\x4b\xb7\x03", 128, &transferred, WCHTIMEOUT ) );
-
- WCHCHECK( libusb_bulk_transfer( devh, 0x01,
-"\x02\x00\x33\x67\x77\x00\x98\xcb\x02\x47\xd8\xcb\x98\x4b\x13\x67" \
-"\x07\x04\x98\xcb\xd8\x47\x05\x8b\x69\xe7\x98\x4b\x75\x8f\x98\xcb" \
-"\x02\x47\x13\x07\x07\x04\x3a\xc0\x22\x47\x7d\x17\x3a\xc4\x79\xf7" \
-"\x93\x77\x85\x00\xf1\xcf\x93\x07\xf6\x03\x2e\xc0\x99\x83\x37\x27" \
-"\x02\x40\x3e\xc4\x1c\x4b\xc1\x66\x2d\x63\xd5\x8f\x1c\xcb\x37\x07" \
-"\x00\x20\x13\x07\x07\x20\xb7\x27\x02\x40\xb7\x03\x08\x00\xb7\x32" \
-"\x00\x40\x13\x03\xa3\xaa\x94\x4b\xb3\xe6\x76\x00\x94\xcb\xd4\x47" \
-"\x85\x8a\xf5\xfe\x82\x46\xba\x84\x37\x04\x04\x00\x36\xc2\xc1\x46", 128, &transferred, WCHTIMEOUT ) );
-
- WCHCHECK( libusb_bulk_transfer( devh, 0x01,
-"\x36\xc6\x92\x46\x84\x40\x11\x07\x84\xc2\x94\x4b\xc1\x8e\x94\xcb" \
-"\xd4\x47\x85\x8a\xb1\xea\x92\x46\xba\x84\x91\x06\x36\xc2\xb2\x46" \
-"\xfd\x16\x36\xc6\xf9\xfe\x82\x46\xd4\xcb\x94\x4b\x93\xe6\x06\x04" \
-"\x94\xcb\xd4\x47\x85\x8a\x85\xee\xd4\x47\xc1\x8a\x85\xce\xd8\x47" \
-"\xb7\x06\xf3\xff\xfd\x16\x13\x67\x07\x01\xd8\xc7\x98\x4b\x21\x45" \
-"\x75\x8f\x98\xcb\x52\x44\xc2\x44\x61\x01\x02\x90\x23\x20\xd3\x00" \
-"\xf5\xb5\x23\xa0\x62\x00\x3d\xb7\x23\xa0\x62\x00\x55\xb7\x23\xa0" \
-"\x62\x00\xc1\xb7\x82\x46\x93\x86\x06\x04\x36\xc0\xa2\x46\xfd\x16", 128, &transferred, WCHTIMEOUT ) );
-
- WCHCHECK( libusb_bulk_transfer( devh, 0x01,
-"\x36\xc4\xb5\xf2\x98\x4b\xb7\x06\xf3\xff\xfd\x16\x75\x8f\x98\xcb" \
-"\x41\x89\x05\xcd\x2e\xc0\x0d\x06\x02\xc4\x09\x82\xb7\x07\x00\x20" \
-"\x32\xc6\x93\x87\x07\x20\x98\x43\x13\x86\x47\x00\xa2\x47\x82\x46" \
-"\x8a\x07\xb6\x97\x9c\x43\x63\x1c\xf7\x00\xa2\x47\x85\x07\x3e\xc4" \
-"\xa2\x46\x32\x47\xb2\x87\xe3\xe0\xe6\xfe\x01\x45\x61\xb7\x41\x45" \
-"\x51\xb7\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff" \
-"\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff" \
-"\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff", 128, &transferred, WCHTIMEOUT ) );
-
- WCHCHECK( libusb_bulk_transfer( devh, 0x01, "\x81\x02\x01\x07", 4, &transferred, WCHTIMEOUT) ); // checkme.
- WCHCHECK( libusb_bulk_transfer( devh, 0x01, "\x81\x02\x01\x02", 4, &transferred, WCHTIMEOUT) ); // checkme.
-
-
-
- WCHCHECK( libusb_bulk_transfer( devh, 0x02,
-"\x6f\x00\x80\x18\x00\x00\x00\x00\x52\x01\x00\x00\x54\x01\x00\x00" \
-"\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" \
-"\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00" \
-"\x56\x01\x00\x00\x00\x00\x00\x00\x58\x01\x00\x00\x00\x00\x00\x00", 64, &transferred, WCHTIMEOUT ) );
-
- WCHCHECK( libusb_bulk_transfer( devh, 0x02,
-"\x5a\x01\x00\x00\x5c\x01\x00\x00\x5e\x01\x00\x00\x60\x01\x00\x00" \
-"\x62\x01\x00\x00\x64\x01\x00\x00\x66\x01\x00\x00\x68\x01\x00\x00" \
-"\x6a\x01\x00\x00\x6c\x01\x00\x00\x6e\x01\x00\x00\x70\x01\x00\x00" \
-"\x72\x01\x00\x00\x74\x01\x00\x00\x76\x01\x00\x00\x78\x01\x00\x00", 64, &transferred, WCHTIMEOUT ) );
-
- WCHCHECK( libusb_bulk_transfer( devh, 0x02,
-"\x7a\x01\x00\x00\x7c\x01\x00\x00\x7e\x01\x00\x00\x80\x01\x00\x00" \
-"\x82\x01\x00\x00\x84\x01\x00\x00\x86\x01\x00\x00\x00\x00\x00\x00" \
-"\x37\x17\x02\x40\x1c\x4f\x85\x46\x93\xe7\x07\x02\x1c\xcf\xb7\x17" \
-"\x01\x40\x03\xa7\x07\x40\x93\x87\x07\x40\x41\x9b\x13\x67\x37\x00", 64, &transferred, WCHTIMEOUT ) );
-
- WCHCHECK( libusb_bulk_transfer( devh, 0x02,
-"\x98\xc3\x41\x67\x94\xcb\x98\xcb\xf5\xbf\xb7\x17\x02\x40\x98\x43" \
-"\xb7\x06\xff\xfc\x37\x26\x02\x40\x13\x67\x17\x00\x98\xc3\xd8\x43" \
-"\x75\x8f\xd8\xc3\x98\x43\xb7\x06\xf7\xfe\xfd\x16\x75\x8f\x98\xc3" \
-"\x98\x43\xb7\x06\xfc\xff\xfd\x16\x75\x8f\x98\xc3\xd8\x43\xc1\x76", 64, &transferred, WCHTIMEOUT ) );
-
- WCHCHECK( libusb_bulk_transfer( devh, 0x02,
-"\xfd\x16\x75\x8f\xd8\xc3\x37\x07\x9f\x00\x98\xc7\x18\x42\x71\x9b" \
-"\x13\x67\x17\x00\x18\xc2\xd8\x43\xd8\xc3\xd8\x43\xf9\x8e\xd4\xc3" \
-"\x98\x43\xb7\x06\x00\x01\x55\x8f\x98\xc3\x37\x17\x02\x40\x1c\x43" \
-"\x93\x96\x67\x00\xe3\xdd\x06\xfe\x5c\x43\xb7\x16\x02\x40\xf1\x9b", 64, &transferred, WCHTIMEOUT ) );
-
- WCHCHECK( libusb_bulk_transfer( devh, 0x02,
-"\x93\xe7\x27\x00\x5c\xc3\x21\x47\xdc\x42\xb1\x8b\xe3\x9e\xe7\xfe" \
-"\x82\x80\x01\xa0\x01\xa0\x01\xa0\x01\xa0\x01\xa0\x01\xa0\x01\xa0" \
-"\x01\xa0\x01\xa0\x01\xa0\x01\xa0\x01\xa0\x01\xa0\x01\xa0\x01\xa0" \
-"\x01\xa0\x01\xa0\x01\xa0\x01\xa0\x01\xa0\x01\xa0\x01\xa0\x01\xa0", 64, &transferred, WCHTIMEOUT ) );
-
- WCHCHECK( libusb_bulk_transfer( devh, 0x02,
-"\x01\xa0\x01\xa0\x01\xa0\x01\xa0\x97\x01\x00\x20\x93\x81\x81\x67" \
-"\x13\x81\x01\x00\x13\x05\xc0\x20\x97\x05\x00\x20\x93\x85\x85\xe6" \
-"\x17\x06\x00\x20\x13\x06\x06\xe6\x63\xfa\xc5\x00\x83\x22\x05\x00" \
-"\x23\xa0\x55\x00\x11\x05\x91\x05\xe3\xea\xc5\xfe\x17\x05\x00\x20", 64, &transferred, WCHTIMEOUT ) );
-
- WCHCHECK( libusb_bulk_transfer( devh, 0x02,
-"\x13\x05\x45\xe4\x97\x05\x00\x20\x93\x85\xc5\xe3\x63\x77\xb5\x00" \
-"\x23\x20\x05\x00\x11\x05\xe3\x6d\xb5\xfe\x93\x02\x00\x08\x73\x90" \
-"\x02\x30\x8d\x42\x73\x90\x42\x80\x97\x02\x00\x00\x93\x82\x82\xe1" \
-"\x93\xe2\x32\x00\x73\x90\x52\x30\xef\xf0\x3f\xed\x97\x02\x00\x00", 64, &transferred, WCHTIMEOUT ) );
-
- WCHCHECK( libusb_bulk_transfer( devh, 0x02,
-"\x93\x82\x42\xea\x73\x90\x12\x34\x73\x00\x20\x30\xff\xff\xff\xff" \
-"\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff" \
-"\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff" \
-"\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff", 64, &transferred, WCHTIMEOUT ) );
-
-
-
-
- // Waiting or something on 2.46.2???????
-
- WCHCHECK( libusb_bulk_transfer( devh, 0x01, "\x81\x0d\x01\xff", 4, &transferred, WCHTIMEOUT) ); // checkme.
-
-
-
- //211122ca26c89377150099cfb7066745b7270240938636123797efcdd4c31307b79ad8c3d4d3d8d3937725009dc7b7270240984bad66373300401367470098cb984b9386a6aa1367070498cbd847058b63160710984b6d9b98cb93774500a9cb9307f60399832ec02d6381763ec4b7320040b72702401303a3aafd16984bb703
-// WCHCHECK( libusb_bulk_transfer( devh, 0x01, "\x81\x02\x01\x05", 4, &transferred, WCHTIMEOUT) );
-}
diff --git a/minichlink/wch_write_simple.c b/minichlink/wch_write_simple.c
index 072a3559a2e33b9af3d9cc5aed34145757fb1a2a..1b097567bf42444378990a1dfbec1150bc48c349 100644
--- a/minichlink/wch_write_simple.c
+++ b/minichlink/wch_write_simple.c
@@ -4,9 +4,48 @@
// UNTESTED
// Having some difficulty with the base.
+const char * bootloader =
+"\x21\x11\x22\xca\x26\xc8\x93\x77\x15\x00\x99\xcf\xb7\x06\x67\x45" \
+"\xb7\x27\x02\x40\x93\x86\x36\x12\x37\x97\xef\xcd\xd4\xc3\x13\x07" \
+"\xb7\x9a\xd8\xc3\xd4\xd3\xd8\xd3\x93\x77\x25\x00\x9d\xc7\xb7\x27" \
+"\x02\x40\x98\x4b\xad\x66\x37\x33\x00\x40\x13\x67\x47\x00\x98\xcb" \
+"\x98\x4b\x93\x86\xa6\xaa\x13\x67\x07\x04\x98\xcb\xd8\x47\x05\x8b" \
+"\x63\x16\x07\x10\x98\x4b\x6d\x9b\x98\xcb\x93\x77\x45\x00\xa9\xcb" \
+"\x93\x07\xf6\x03\x99\x83\x2e\xc0\x2d\x63\x81\x76\x3e\xc4\xb7\x32" \
+"\x00\x40\xb7\x27\x02\x40\x13\x03\xa3\xaa\xfd\x16\x98\x4b\xb7\x03" \
+"\x02\x00\x33\x67\x77\x00\x98\xcb\x02\x47\xd8\xcb\x98\x4b\x13\x67" \
+"\x07\x04\x98\xcb\xd8\x47\x05\x8b\x69\xe7\x98\x4b\x75\x8f\x98\xcb" \
+"\x02\x47\x13\x07\x07\x04\x3a\xc0\x22\x47\x7d\x17\x3a\xc4\x79\xf7" \
+"\x93\x77\x85\x00\xf1\xcf\x93\x07\xf6\x03\x2e\xc0\x99\x83\x37\x27" \
+"\x02\x40\x3e\xc4\x1c\x4b\xc1\x66\x2d\x63\xd5\x8f\x1c\xcb\x37\x07" \
+"\x00\x20\x13\x07\x07\x20\xb7\x27\x02\x40\xb7\x03\x08\x00\xb7\x32" \
+"\x00\x40\x13\x03\xa3\xaa\x94\x4b\xb3\xe6\x76\x00\x94\xcb\xd4\x47" \
+"\x85\x8a\xf5\xfe\x82\x46\xba\x84\x37\x04\x04\x00\x36\xc2\xc1\x46" \
+"\x36\xc6\x92\x46\x84\x40\x11\x07\x84\xc2\x94\x4b\xc1\x8e\x94\xcb" \
+"\xd4\x47\x85\x8a\xb1\xea\x92\x46\xba\x84\x91\x06\x36\xc2\xb2\x46" \
+"\xfd\x16\x36\xc6\xf9\xfe\x82\x46\xd4\xcb\x94\x4b\x93\xe6\x06\x04" \
+"\x94\xcb\xd4\x47\x85\x8a\x85\xee\xd4\x47\xc1\x8a\x85\xce\xd8\x47" \
+"\xb7\x06\xf3\xff\xfd\x16\x13\x67\x07\x01\xd8\xc7\x98\x4b\x21\x45" \
+"\x75\x8f\x98\xcb\x52\x44\xc2\x44\x61\x01\x02\x90\x23\x20\xd3\x00" \
+"\xf5\xb5\x23\xa0\x62\x00\x3d\xb7\x23\xa0\x62\x00\x55\xb7\x23\xa0" \
+"\x62\x00\xc1\xb7\x82\x46\x93\x86\x06\x04\x36\xc0\xa2\x46\xfd\x16" \
+"\x36\xc4\xb5\xf2\x98\x4b\xb7\x06\xf3\xff\xfd\x16\x75\x8f\x98\xcb" \
+"\x41\x89\x05\xcd\x2e\xc0\x0d\x06\x02\xc4\x09\x82\xb7\x07\x00\x20" \
+"\x32\xc6\x93\x87\x07\x20\x98\x43\x13\x86\x47\x00\xa2\x47\x82\x46" \
+"\x8a\x07\xb6\x97\x9c\x43\x63\x1c\xf7\x00\xa2\x47\x85\x07\x3e\xc4" \
+"\xa2\x46\x32\x47\xb2\x87\xe3\xe0\xe6\xfe\x01\x45\x61\xb7\x41\x45" \
+"\x51\xb7\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff" \
+"\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff" \
+"\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff";
+
+int bootloader_len = 512;
+
int main( int argc, char ** argv )
{
+ int i;
+ uint8_t rbuff[1024];
+
if( argc != 2 )
{
fprintf( stderr, "Usage: wch_write_simple [binfile]\n" );
@@ -31,78 +70,53 @@ int main( int argc, char ** argv )
libusb_device_handle * devh = wch_link_base_setup();
int transferred;
int status;
- WCHCHECK( libusb_bulk_transfer( devh, 0x01, "\x81\x0d\x01\x01", 4, &transferred, WCHTIMEOUT ) ); // Checkme with BULK_IN
- WCHCHECK( libusb_bulk_transfer( devh, 0x01, "\x81\x0c\x02\x09\x01", 5, &transferred, WCHTIMEOUT ) ); // Checkme with BULK_IN
- WCHCHECK( libusb_bulk_transfer( devh, 0x01, "\x81\x0d\x01\x02", 4, &transferred, WCHTIMEOUT) ); // Checkme with BULK_IN
- WCHCHECK( libusb_bulk_transfer( devh, 0x01, "\x81\x11\x01\x09", 4, &transferred, WCHTIMEOUT) ); // Checkme with BULK_IN
- WCHCHECK( libusb_bulk_transfer( devh, 0x01, "\x81\x06\x01\x01", 4, &transferred, WCHTIMEOUT) );
- WCHCHECK( libusb_bulk_transfer( devh, 0x01, "\x81\x06\x01\x01", 4, &transferred, WCHTIMEOUT) ); // Odd that it did it twice - maybe something took too long on the proc.
+ wch_link_command( devh, "\x81\x06\x01\x01", 4, 0, 0, 0 );
+ wch_link_command( devh, "\x81\x06\x01\x01", 4, 0, 0, 0 ); // Not sure why but it seems to work better when we request twice.
// This contains the write data quantity, in bytes. (The last 2 octets)
// Then it just rollllls on in.
char rksbuff[11] = { 0x81, 0x01, 0x08, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
rksbuff[9] = len >> 8;
rksbuff[10] = len & 0xff;
- WCHCHECK( libusb_bulk_transfer( devh, 0x01, rksbuff, 11, &transferred, WCHTIMEOUT) ); // Still check me.
- WCHCHECK( libusb_bulk_transfer( devh, 0x01, "\x81\x02\x01\x05", 4, &transferred, WCHTIMEOUT) ); // Last checkme til data.
+ wch_link_command( devh, rksbuff, 11, 0, 0, 0 );
+
+ wch_link_command( devh, "\x81\x02\x01\x05", 4, 0, 0, 0 );
+
+ int pplace = 0;
+ for( pplace = 0; pplace < bootloader_len; pplace += 64 )
+ {
+ WCHCHECK( libusb_bulk_transfer( devh, 0x02, bootloader+pplace, 64, &transferred, WCHTIMEOUT ) );
+ }
+
+ for( i = 0; i < 10; i++ )
+ {
+ wch_link_command( devh, "\x81\x02\x01\x07", 4, &transferred, rbuff, 1024 );
+ if( transferred == 4 && rbuff[0] == 0x82 && rbuff[1] == 0x02 && rbuff[2] == 0x01 && rbuff[3] == 0x07 )
+ {
+ break;
+ }
+ }
+ if( i == 10 )
+ {
+ fprintf( stderr, "Error, confusing respones to 02/01/07\n" );
+ exit( -109 );
+ }
- // then just stream this. This is some sort of propreitary image.
- WCHCHECK( libusb_bulk_transfer( devh, 0x01,
-"\x21\x11\x22\xca\x26\xc8\x93\x77\x15\x00\x99\xcf\xb7\x06\x67\x45" \
-"\xb7\x27\x02\x40\x93\x86\x36\x12\x37\x97\xef\xcd\xd4\xc3\x13\x07" \
-"\xb7\x9a\xd8\xc3\xd4\xd3\xd8\xd3\x93\x77\x25\x00\x9d\xc7\xb7\x27" \
-"\x02\x40\x98\x4b\xad\x66\x37\x33\x00\x40\x13\x67\x47\x00\x98\xcb" \
-"\x98\x4b\x93\x86\xa6\xaa\x13\x67\x07\x04\x98\xcb\xd8\x47\x05\x8b" \
-"\x63\x16\x07\x10\x98\x4b\x6d\x9b\x98\xcb\x93\x77\x45\x00\xa9\xcb" \
-"\x93\x07\xf6\x03\x99\x83\x2e\xc0\x2d\x63\x81\x76\x3e\xc4\xb7\x32" \
-"\x00\x40\xb7\x27\x02\x40\x13\x03\xa3\xaa\xfd\x16\x98\x4b\xb7\x03", 128, &transferred, WCHTIMEOUT ) );
-
- WCHCHECK( libusb_bulk_transfer( devh, 0x01,
-"\x02\x00\x33\x67\x77\x00\x98\xcb\x02\x47\xd8\xcb\x98\x4b\x13\x67" \
-"\x07\x04\x98\xcb\xd8\x47\x05\x8b\x69\xe7\x98\x4b\x75\x8f\x98\xcb" \
-"\x02\x47\x13\x07\x07\x04\x3a\xc0\x22\x47\x7d\x17\x3a\xc4\x79\xf7" \
-"\x93\x77\x85\x00\xf1\xcf\x93\x07\xf6\x03\x2e\xc0\x99\x83\x37\x27" \
-"\x02\x40\x3e\xc4\x1c\x4b\xc1\x66\x2d\x63\xd5\x8f\x1c\xcb\x37\x07" \
-"\x00\x20\x13\x07\x07\x20\xb7\x27\x02\x40\xb7\x03\x08\x00\xb7\x32" \
-"\x00\x40\x13\x03\xa3\xaa\x94\x4b\xb3\xe6\x76\x00\x94\xcb\xd4\x47" \
-"\x85\x8a\xf5\xfe\x82\x46\xba\x84\x37\x04\x04\x00\x36\xc2\xc1\x46", 128, &transferred, WCHTIMEOUT ) );
-
- WCHCHECK( libusb_bulk_transfer( devh, 0x01,
-"\x36\xc6\x92\x46\x84\x40\x11\x07\x84\xc2\x94\x4b\xc1\x8e\x94\xcb" \
-"\xd4\x47\x85\x8a\xb1\xea\x92\x46\xba\x84\x91\x06\x36\xc2\xb2\x46" \
-"\xfd\x16\x36\xc6\xf9\xfe\x82\x46\xd4\xcb\x94\x4b\x93\xe6\x06\x04" \
-"\x94\xcb\xd4\x47\x85\x8a\x85\xee\xd4\x47\xc1\x8a\x85\xce\xd8\x47" \
-"\xb7\x06\xf3\xff\xfd\x16\x13\x67\x07\x01\xd8\xc7\x98\x4b\x21\x45" \
-"\x75\x8f\x98\xcb\x52\x44\xc2\x44\x61\x01\x02\x90\x23\x20\xd3\x00" \
-"\xf5\xb5\x23\xa0\x62\x00\x3d\xb7\x23\xa0\x62\x00\x55\xb7\x23\xa0" \
-"\x62\x00\xc1\xb7\x82\x46\x93\x86\x06\x04\x36\xc0\xa2\x46\xfd\x16", 128, &transferred, WCHTIMEOUT ) );
-
- WCHCHECK( libusb_bulk_transfer( devh, 0x01,
-"\x36\xc4\xb5\xf2\x98\x4b\xb7\x06\xf3\xff\xfd\x16\x75\x8f\x98\xcb" \
-"\x41\x89\x05\xcd\x2e\xc0\x0d\x06\x02\xc4\x09\x82\xb7\x07\x00\x20" \
-"\x32\xc6\x93\x87\x07\x20\x98\x43\x13\x86\x47\x00\xa2\x47\x82\x46" \
-"\x8a\x07\xb6\x97\x9c\x43\x63\x1c\xf7\x00\xa2\x47\x85\x07\x3e\xc4" \
-"\xa2\x46\x32\x47\xb2\x87\xe3\xe0\xe6\xfe\x01\x45\x61\xb7\x41\x45" \
-"\x51\xb7\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff" \
-"\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff" \
-"\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff", 128, &transferred, WCHTIMEOUT ) );
-
- WCHCHECK( libusb_bulk_transfer( devh, 0x01, "\x81\x02\x01\x07", 4, &transferred, WCHTIMEOUT) ); // checkme.
WCHCHECK( libusb_bulk_transfer( devh, 0x01, "\x81\x02\x01\x02", 4, &transferred, WCHTIMEOUT) ); // checkme.
+ WCHCHECK( libusb_bulk_transfer( devh, 0x81, rbuff, 1024, &transferred, 2000 ) ); // Ignore respone.
- int pplace = 0;
for( pplace = 0; pplace < padlen; pplace += 64 )
{
WCHCHECK( libusb_bulk_transfer( devh, 0x02,image+pplace, 64, &transferred, WCHTIMEOUT ) );
}
// Waiting or something on 2.46.2???????
+ WCHCHECK( libusb_bulk_transfer( devh, 0x82, rbuff, 1024, &transferred, 2000 ) ); // Ignore respone.
WCHCHECK( libusb_bulk_transfer( devh, 0x01, "\x81\x0d\x01\xff", 4, &transferred, WCHTIMEOUT) ); // checkme.
+ WCHCHECK( libusb_bulk_transfer( devh, 0x81, rbuff, 1024, &transferred, 2000 ) ); // Ignore respone.
-
-
//211122ca26c89377150099cfb7066745b7270240938636123797efcdd4c31307b79ad8c3d4d3d8d3937725009dc7b7270240984bad66373300401367470098cb984b9386a6aa1367070498cbd847058b63160710984b6d9b98cb93774500a9cb9307f60399832ec02d6381763ec4b7320040b72702401303a3aafd16984bb703
// WCHCHECK( libusb_bulk_transfer( devh, 0x01, "\x81\x02\x01\x05", 4, &transferred, WCHTIMEOUT) );
}