diff --git a/ch32v003fun/ch32v003fun.c b/ch32v003fun/ch32v003fun.c
index 9cd09fa1c8609e02a33e17295eb04e4a3319880d..80cf09f3dba47d9f63b0a4df0a9ff8468b0ae47c 100644
--- a/ch32v003fun/ch32v003fun.c
+++ b/ch32v003fun/ch32v003fun.c
@@ -1352,6 +1352,65 @@ void SystemInit72HSE( void )
 	while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) {}
 }
 
+void SystemInit80HSI( void )
+{
+	EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
+
+	/* Enable Prefetch Buffer */
+    FLASH->ACTLR |= FLASH_ACTLR_PRFTBE;
+
+	/* Flash 1 wait state */
+    FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY);
+    FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_1;
+
+	RCC->CFGR0 = RCC_HPRE_DIV1 | RCC_PPRE2_DIV1 | RCC_PPRE1_DIV2;
+	RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+	RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL10);
+
+	/* Enable PLL */
+	RCC->CTLR |= RCC_PLLON;
+
+	/* Wait till PLL is ready */
+	while((RCC->CTLR & RCC_PLLRDY) == 0) {}
+
+	/* Select PLL as system clock source */
+	RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+	RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+
+	/* Wait till PLL is used as system clock source */
+	while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) {}
+}
+
+void SystemInit80HSE( void )
+{
+	RCC->CTLR |= ((uint32_t)RCC_HSEON);
+	while(!(RCC->CTLR&RCC_HSERDY));
+
+	/* Enable Prefetch Buffer */
+	FLASH->ACTLR |= FLASH_ACTLR_PRFTBE;
+
+	/* Flash 2 wait state */
+	FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY);
+	FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_2;
+
+	RCC->CFGR0 = RCC_HPRE_DIV1 | RCC_PPRE2_DIV1 | RCC_PPRE1_DIV2;
+	RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+	RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLMULL10);
+
+	/* Enable PLL */
+	RCC->CTLR |= RCC_PLLON;
+
+	/* Wait till PLL is ready */
+	while((RCC->CTLR & RCC_PLLRDY) == 0) {}
+
+	/* Select PLL as system clock source */
+	RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+	RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+
+	/* Wait till PLL is used as system clock source */
+	while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) {}
+}
+
 #endif // defined(CH32V10x)
 
 #ifdef CH32V003
diff --git a/ch32v003fun/ch32v003fun.h b/ch32v003fun/ch32v003fun.h
index 847c96862b43bc73715f861dd27bbb064a39d83a..0828f0b2b69bd1cd36f28bcabb3198c14d0bbade 100644
--- a/ch32v003fun/ch32v003fun.h
+++ b/ch32v003fun/ch32v003fun.h
@@ -12173,6 +12173,8 @@ void SystemInit144HSE( void );
 // Initialization functions
 void SystemInit72HSI( void );
 void SystemInit72HSE( void );
+void SystemInit80HSI( void );
+void SystemInit80HSE( void );
 
 #endif
 
diff --git a/examples_v10x/blink/blink.c b/examples_v10x/blink/blink.c
index 886146157a962744512d5463de97354768df3221..ba1eecc0acb5d7a9b4d936242139cfa40a7d8388 100644
--- a/examples_v10x/blink/blink.c
+++ b/examples_v10x/blink/blink.c
@@ -1,12 +1,12 @@
 // Could be defined here, or in the processor defines.
-#define SYSTEM_CORE_CLOCK 72000000
+#define SYSTEM_CORE_CLOCK 80000000
 
 #include "ch32v003fun.h"
 #include <stdio.h>
 
 int main()
 {
-	SystemInit72HSE();
+	SystemInit80HSE();
 
 	// Enable GPIOs
 	//RCC->APB2PCENR |= RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOC;