From c01ffcd2f3209a489effdca897ba030976cebefa Mon Sep 17 00:00:00 2001
From: Alexander Mandera <alexander@mandera.eu>
Date: Tue, 27 Jun 2023 13:54:15 +0200
Subject: [PATCH] Add 80MHz init for V103
---
ch32v003fun/ch32v003fun.c | 59 +++++++++++++++++++++++++++++++++++++
ch32v003fun/ch32v003fun.h | 2 ++
examples_v10x/blink/blink.c | 4 +--
3 files changed, 63 insertions(+), 2 deletions(-)
diff --git a/ch32v003fun/ch32v003fun.c b/ch32v003fun/ch32v003fun.c
index 9cd09fa..80cf09f 100644
--- a/ch32v003fun/ch32v003fun.c
+++ b/ch32v003fun/ch32v003fun.c
@@ -1352,6 +1352,65 @@ void SystemInit72HSE( void )
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) {}
}
+void SystemInit80HSI( void )
+{
+ EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
+
+ /* Enable Prefetch Buffer */
+ FLASH->ACTLR |= FLASH_ACTLR_PRFTBE;
+
+ /* Flash 1 wait state */
+ FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY);
+ FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_1;
+
+ RCC->CFGR0 = RCC_HPRE_DIV1 | RCC_PPRE2_DIV1 | RCC_PPRE1_DIV2;
+ RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+ RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL10);
+
+ /* Enable PLL */
+ RCC->CTLR |= RCC_PLLON;
+
+ /* Wait till PLL is ready */
+ while((RCC->CTLR & RCC_PLLRDY) == 0) {}
+
+ /* Select PLL as system clock source */
+ RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+ RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+
+ /* Wait till PLL is used as system clock source */
+ while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) {}
+}
+
+void SystemInit80HSE( void )
+{
+ RCC->CTLR |= ((uint32_t)RCC_HSEON);
+ while(!(RCC->CTLR&RCC_HSERDY));
+
+ /* Enable Prefetch Buffer */
+ FLASH->ACTLR |= FLASH_ACTLR_PRFTBE;
+
+ /* Flash 2 wait state */
+ FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY);
+ FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_2;
+
+ RCC->CFGR0 = RCC_HPRE_DIV1 | RCC_PPRE2_DIV1 | RCC_PPRE1_DIV2;
+ RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+ RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLMULL10);
+
+ /* Enable PLL */
+ RCC->CTLR |= RCC_PLLON;
+
+ /* Wait till PLL is ready */
+ while((RCC->CTLR & RCC_PLLRDY) == 0) {}
+
+ /* Select PLL as system clock source */
+ RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+ RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+
+ /* Wait till PLL is used as system clock source */
+ while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) {}
+}
+
#endif // defined(CH32V10x)
#ifdef CH32V003
diff --git a/ch32v003fun/ch32v003fun.h b/ch32v003fun/ch32v003fun.h
index 847c968..0828f0b 100644
--- a/ch32v003fun/ch32v003fun.h
+++ b/ch32v003fun/ch32v003fun.h
@@ -12173,6 +12173,8 @@ void SystemInit144HSE( void );
// Initialization functions
void SystemInit72HSI( void );
void SystemInit72HSE( void );
+void SystemInit80HSI( void );
+void SystemInit80HSE( void );
#endif
diff --git a/examples_v10x/blink/blink.c b/examples_v10x/blink/blink.c
index 8861461..ba1eecc 100644
--- a/examples_v10x/blink/blink.c
+++ b/examples_v10x/blink/blink.c
@@ -1,12 +1,12 @@
// Could be defined here, or in the processor defines.
-#define SYSTEM_CORE_CLOCK 72000000
+#define SYSTEM_CORE_CLOCK 80000000
#include "ch32v003fun.h"
#include <stdio.h>
int main()
{
- SystemInit72HSE();
+ SystemInit80HSE();
// Enable GPIOs
//RCC->APB2PCENR |= RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOC;
--
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