diff --git a/attic/EVT/Makefile b/attic/EVT/Makefile
deleted file mode 100644
index a7938f429bba0d04cb40f9cfc528737d0ca3b3a6..0000000000000000000000000000000000000000
--- a/attic/EVT/Makefile
+++ /dev/null
@@ -1,47 +0,0 @@
-TARGET:=GPIO_Toggle
-
-all : flash
-
-PREFIX:=riscv64-unknown-elf
-
-GPIO_Toggle:=EXAM/GPIO/GPIO_Toggle/User
-
-CFLAGS:= \
- -g -Os -flto -ffunction-sections \
- -static-libgcc -lgcc \
- -march=rv32ec \
- -mabi=ilp32e \
- -I/usr/include/newlib \
- -nostdlib \
- -I$(GPIO_Toggle) \
- -IEXAM/SRC/Core \
- -IEXAM/SRC/Debug \
- -IEXAM/SRC/Debug \
- -IEXAM/SRC/Peripheral/inc
-
-LDFLAGS:=-T EXAM/SRC/Ld/Link.ld
-
-SYSTEM_C:=EXAM/SRC/Startup/startup_ch32v00x.S \
- EXAM/SRC/Debug/debug.c \
- EXAM/SRC/Peripheral/src/ch32v00x_gpio.c \
- EXAM/SRC/Peripheral/src/ch32v00x_rcc.c \
- EXAM/SRC/Peripheral/src/ch32v00x_usart.c \
- EXAM/SRC/Peripheral/src/ch32v00x_misc.c \
- ../ch32v003evt/embedlibc.c
-
-$(TARGET).elf : $(GPIO_Toggle)/ch32v00x_it.c $(GPIO_Toggle)/main.c $(GPIO_Toggle)/system_ch32v00x.c $(SYSTEM_C)
- $(PREFIX)-gcc -o $@ $^ $(CFLAGS) $(LDFLAGS)
-
-$(TARGET).hex : GPIO_Toggle.elf
- $(PREFIX)-size $^
- $(PREFIX)-objdump -S $^ > $(TARGET).lst
- $(PREFIX)-objdump -t $^ > $(TARGET).map
- #$(PREFIX)-objcopy -O binary $< $@
- $(PREFIX)-objcopy -O ihex $< $@
-
-
-flash : $(TARGET).hex
-
-clean :
- rm -rf $(TARGET).elf $(TARGET).bin $(TARGET).lst $(TARGET).map
-
diff --git a/attic/EVT/README.md b/attic/EVT/README.md
deleted file mode 100644
index e46758c3d99ed7730d46f608e39b9065e6326069..0000000000000000000000000000000000000000
--- a/attic/EVT/README.md
+++ /dev/null
@@ -1,28 +0,0 @@
-# General Tooling Notes For Using Official EVT With GCC but without Moun River
-
-This shows how to build the CH32V003 demo binaries without the horrifying MounRiver Studio.
-
-* Product page: https://www.wch.cn/products/CH32V003.html
-* or English: http://www.wch-ic.com/products/CH32V003.html
-* It has, for the English datasheet http://www.wch-ic.com/downloads/file/359.html "CH32V003DS0.PDF"
-* It also has the TRM http://www.wch-ic.com/downloads/CH32V003RM_PDF.html in English
-* Sadly, the EVT is CN only. https://www.wch.cn/downloads/CH32V003EVT_ZIP.html - It contains schematics for the devboard, evaluation board reference (instructions) and the rest of the dev system, minus the MounRiver Studio (MRS).
-* Software from WCH for WCH-Link: https://www.wch-ic.com/products/WCH-Link.html
-* Get https://www.wch.cn/downloads/WCH-LinkUtility_ZIP.html
-
-## Steps to run an EVT sample
-
-1. Install WCHLinkDrv_WHQL_S.exe from Wch-LinkUtil/Drv_Link
-2. Copy contents of EVT (CH32V003EVT.ZIP) "EXAM" Folder in to the EVT folder.
-3. On WSL or Debian based OSes `apt-get install build-essential libnewlib-dev gcc-riscv64-unknown-elf`
-4. cd into `EVT` on WSL or Linux
-5. Type `make`
-6. Open Wch-LinkUtil
-7. Select series "CH32V00X" from pull-down.
-8. Open the produced .hex file.
-9. Target->Program (F10)
-10. Target->Reset (F12)
-
-Profit.
-
-
diff --git a/attic/NHC-Link042/LibUSB/LibUSB.c b/attic/NHC-Link042/LibUSB/LibUSB.c
deleted file mode 100644
index 548bdbc5abb85e54a349e48207921cffaacd7102..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/LibUSB/LibUSB.c
+++ /dev/null
@@ -1,430 +0,0 @@
-/**
- ******************************************************************************
- * @file usbd_hid_core.c
- * @author MCD Application Team
- * @version V1.0.1
- * @date 31-January-2014
- * @brief This file provides the HID core functions.
- *
- * @verbatim
- *
- * ===================================================================
- * HID Class Description
- * ===================================================================
- * This module manages the HID class V1.11 following the "Device Class Definition
- * for Human Interface Devices (HID) Version 1.11 Jun 27, 2001".
- * This driver implements the following aspects of the specification:
- * - The Boot Interface Subclass
- * - The Mouse protocol
- * - Usage Page : Generic Desktop
- * - Usage : Joystick
- * - Collection : Application
- *
- *
- * @endverbatim
- *
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "LibUSB.h"
-#include "NHC_WCH_SDI.h"
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-static uint8_t USBD_HID_Init (void *pdev,
- uint8_t cfgidx);
-
-static uint8_t USBD_HID_DeInit (void *pdev,
- uint8_t cfgidx);
-
-static uint8_t USBD_HID_Setup (void *pdev,
- USB_SETUP_REQ *req);
-
-static uint8_t *USBD_HID_GetCfgDesc (uint8_t speed, uint16_t *length);
-
-static uint8_t USBD_HID_DataIn (void *pdev, uint8_t epnum);
-
-static uint8_t USBD_HID_DataOut (void *pdev, uint8_t epnum);
-
-USBD_Class_cb_TypeDef USBD_HID_cb =
-{
- USBD_HID_Init,
- USBD_HID_DeInit,
- USBD_HID_Setup,
- NULL, /*EP0_TxSent*/
- NULL, /*EP0_RxReady*/
- USBD_HID_DataIn, /*DataIn*/
- USBD_HID_DataOut, /*DataOut*/
- NULL, /*SOF */
- USBD_HID_GetCfgDesc,
-};
-
-static uint32_t USBD_HID_AltSet = 0;
-
-static uint32_t USBD_HID_Protocol = 0;
-
-static uint32_t USBD_HID_IdleState = 0;
-
-uint8_t rxBuff[64];
-uint8_t txBuff[64];
-
-/* USB HID device Configuration Descriptor */
-const uint8_t USBD_HID_CfgDesc[USB_HID_CONFIG_DESC_SIZ] =
-{
- 0x09, /* bLength: Configuration Descriptor size */
- USB_CONFIGURATION_DESCRIPTOR_TYPE, /* bDescriptorType: Configuration */
- USB_HID_CONFIG_DESC_SIZ,
- /* wTotalLength: Bytes returned */
- 0x00,
- 0x01, /*bNumInterfaces: 1 interface*/
- 0x01, /*bConfigurationValue: Configuration value*/
- 0x00, /*iConfiguration: Index of string descriptor describing
- the configuration*/
- 0xC0, /*bmAttributes: bus powered and Support Remote Wake-up */
- 0xfa, /*MaxPower 100 mA: this current is used for detecting Vbus*/
-
- /************** Descriptor of Joystick Mouse interface ****************/
- /* 09 */
- 0x09, /*bLength: Interface Descriptor size*/
- USB_INTERFACE_DESCRIPTOR_TYPE,/*bDescriptorType: Interface descriptor type*/
- 0x00, /*bInterfaceNumber: Number of Interface*/
- 0x00, /*bAlternateSetting: Alternate setting*/
- 0x02, /*bNumEndpoints*/
- 0xff, /*bInterfaceClass: HID*/
- 0xff, /*bInterfaceSubClass : 1=BOOT, 0=no boot*/
- 0xff, /*nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse*/
- 0, /*iInterface: Index of string descriptor*/
- /******************** Descriptor of Joystick Mouse HID ********************/
- /* 18 */
-
- 0x07, /*bLength: Endpoint Descriptor size*/
- USB_ENDPOINT_DESCRIPTOR_TYPE, /*bDescriptorType:*/
-
- HID_IN_EP, /*bEndpointAddress: Endpoint Address (IN)*/
- 0x02, /*bmAttributes: Interrupt endpoint*/
- 0x40,//HID_IN_PACKET, /*wMaxPacketSize: 4 Byte max */
- 0x00,
- 0x01, /*bInterval: Polling Interval (10 ms)*/
- /* 34 */
- 0x07, /* bLength: Endpoint Descriptor size */
- USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: */
- /* Endpoint descriptor type */
- 0x01, /* bEndpointAddress: */
- /* Endpoint Address (OUT) */
- 0x02, /* bmAttributes: Interrupt endpoint */
- 0x40, /* wMaxPacketSize: 2 Bytes max */
- 0x00,
- 0x01, /* bInterval: Polling Interval (20 ms) */
- /* 41 */
-} ;
-
-const uint8_t HID_MOUSE_ReportDesc[HID_MOUSE_REPORT_DESC_SIZE] =
-{
- 0x06, 0x00, 0xFF, // Usage Page = 0xFF00 (Vendor Defined Page 1)
- 0x09, 0x01, // Usage (Vendor Usage 1)
- 0xA1, 0x01, // Collection (Application)
- 0x19, 0x01, // Usage Minimum
- 0x29, 0x40, // Usage Maximum //64 input usages total (0x01 to 0x40)
- 0x15, 0x01, // Logical Minimum (data bytes in the report may have minimum value = 0x00)
- 0x25, 0x40, // Logical Maximum (data bytes in the report may have maximum value = 0x00FF = unsigned 255)
- 0x75, 0x08, // Report Size: 8-bit field size
- 0x95, 0x40, // Report Count: Make sixty-four 8-bit fields (the next time the parser hits an "Input", "Output", or "Feature" item)
- 0x81, 0x00, // Input (Data, Array, Abs): Instantiates input packet fields based on the above report size, count, logical min/max, and usage.
- 0x19, 0x01, // Usage Minimum
- 0x29, 0x40, // Usage Maximum //64 output usages total (0x01 to 0x40)
- 0x91, 0x00, // Output (Data, Array, Abs): Instantiates output packet fields. Uses same report size and count as "Input" fields, since nothing new/different was specified to the parser since the "Input" item.
- 0xC0
-};
-
-/* Private function ----------------------------------------------------------*/
-/**
- * @brief USBD_HID_Init
- * Initialize the HID interface
- * @param pdev: device instance
- * @param cfgidx: Configuration index
- * @retval status
- */
-static uint8_t USBD_HID_Init (void *pdev,
- uint8_t cfgidx)
-{
- DCD_PMA_Config(pdev , HID_IN_EP,USB_SNG_BUF,HID_IN_TX_ADDRESS);
- DCD_PMA_Config(pdev , HID_OUT_EP,USB_SNG_BUF,HID_IN_TX_ADDRESS+0x40);
- /* Open EP IN */
- DCD_EP_Open(pdev,
- HID_IN_EP,
- /*HID_IN_PACKET*/0x40,
- USB_EP_BULK);
-
- /* Open EP OUT */
- DCD_EP_Open(pdev,
- HID_OUT_EP,
- /*HID_OUT_PACKET*/0x40,
- USB_EP_BULK);
- DCD_EP_PrepareRx(pdev, HID_OUT_EP, rxBuff, 0x40);
- return USBD_OK;
-}
-
-/**
- * @brief USBD_HID_Init
- * DeInitialize the HID layer
- * @param pdev: device instance
- * @param cfgidx: Configuration index
- * @retval status
- */
-static uint8_t USBD_HID_DeInit (void *pdev,
- uint8_t cfgidx)
-{
- /* Close HID EPs */
- DCD_EP_Close (pdev , HID_IN_EP);
- DCD_EP_Close (pdev , HID_OUT_EP);
-
-
- return USBD_OK;
-}
-
-/**
- * @brief USBD_HID_Setup
- * Handle the HID specific requests
- * @param pdev: instance
- * @param req: usb requests
- * @retval status
- */
-static uint8_t USBD_HID_Setup (void *pdev,
- USB_SETUP_REQ *req)
-{
- uint16_t len = 0;
- uint8_t *pbuf = NULL;
-
- switch (req->bmRequest & USB_REQ_TYPE_MASK)
- {
- case USB_REQ_TYPE_CLASS :
- switch (req->bRequest)
- {
- case HID_REQ_SET_PROTOCOL:
- USBD_HID_Protocol = (uint8_t)(req->wValue);
- break;
-
- case HID_REQ_GET_PROTOCOL:
- USBD_CtlSendData (pdev,
- (uint8_t *)&USBD_HID_Protocol,
- 1);
- break;
-
- case HID_REQ_SET_IDLE:
- USBD_HID_IdleState = (uint8_t)(req->wValue >> 8);
- break;
-
- case HID_REQ_GET_IDLE:
- USBD_CtlSendData (pdev,
- (uint8_t *)&USBD_HID_IdleState,
- 1);
- break;
-
- default:
- USBD_CtlError (pdev, req);
- return USBD_FAIL;
- }
- break;
-
- case USB_REQ_TYPE_STANDARD:
- switch (req->bRequest)
- {
- case USB_REQ_GET_DESCRIPTOR:
- if( req->wValue >> 8 == HID_REPORT_DESC)
- {
- len = MIN(HID_MOUSE_REPORT_DESC_SIZE , req->wLength);
- pbuf = (uint8_t *)HID_MOUSE_ReportDesc;
- }
- else if( req->wValue >> 8 == HID_DESCRIPTOR_TYPE)
- {
- pbuf = (uint8_t *)USBD_HID_CfgDesc + 0x12;
- len = MIN(USB_HID_DESC_SIZ , req->wLength);
- }
-
- USBD_CtlSendData (pdev,
- pbuf,
- len);
-
- break;
-
- case USB_REQ_GET_INTERFACE :
- USBD_CtlSendData (pdev,
- (uint8_t *)&USBD_HID_AltSet,
- 1);
- break;
-
- case USB_REQ_SET_INTERFACE :
- USBD_HID_AltSet = (uint8_t)(req->wValue);
- break;
- }
- }
- return USBD_OK;
-}
-
-/**
- * @brief USBD_HID_GetCfgDesc
- * return configuration descriptor
- * @param speed : current device speed
- * @param length : pointer data length
- * @retval pointer to descriptor buffer
- */
-static uint8_t *USBD_HID_GetCfgDesc (uint8_t speed, uint16_t *length)
-{
- *length = sizeof (USBD_HID_CfgDesc);
- return (uint8_t *)USBD_HID_CfgDesc;
-}
-
-static uint8_t USBD_HID_DataIn (void *pdev,
- uint8_t epnum)
-{
-
- /* Ensure that the FIFO is empty before a new transfer, this condition could
- be caused by a new transfer before the end of the previous transfer */
- //DCD_EP_Flush(pdev, HID_IN_EP);
- return USBD_OK;
-}
-
-uint8_t u8Buff[4 * 1024];
-#define WCH_SDI_INIT 0xA0
-#define WCH_SDI_EXIT 0xA1
-#define WCH_SDI_READ 0xA2
-#define WCH_SDI_WRITE 0xA3
-#define WCH_SDI_READ_MEM 0xA4
-#define WCH_SDI_WRITE_MEM 0xA5
-#define DELAY_US_CMD 0xA6
-
-/**
- * @brief USBD_HID_DataOut
- * handle data OUT Stage
- * @param pdev: device instance
- * @param epnum: endpoint index
- * @retval status
- */
-
-uint32_t u32Check = 1;
-
-#define busy_on GPIO_SetBits(GPIOA, GPIO_Pin_1)
-#define busy_off GPIO_ResetBits(GPIOA, GPIO_Pin_1)
-
-uint32_t u8tou32(uint8_t *p)
-{
- uint32_t u32Tmp;
-
- u32Tmp = p[3];
- u32Tmp <<= 8;
- u32Tmp += p[2];
- u32Tmp <<= 8;
- u32Tmp += p[1];
- u32Tmp <<= 8;
- u32Tmp += p[0];
-
- return u32Tmp;
-}
-
-#define BUSY_1() GPIO_ResetBits(GPIOC, GPIO_Pin_9)
-#define BUSY_0() GPIO_SetBits(GPIOC, GPIO_Pin_9)
-
-void u32tou8(uint32_t u32In, uint8_t *p)
-{
- p[0] = u32In;
- u32In >>= 8;
- p[1] = u32In;
- u32In >>= 8;
- p[2] = u32In;
- u32In >>= 8;
- p[3] = u32In;
-}
-
-void NHC_Delay_Us(uint16_t u16Delay);
-
-static uint8_t USBD_HID_DataOut (void *pdev,
- uint8_t epnum)
-{
- uint32_t u32Address;
- //uint32_t u32Len;
- uint32_t u32Tmp;
- //uint32_t *pu32;
- uint32_t i;
- uint32_t n;
- //uint8_t *p;
-
- busy_on;
-
- switch (rxBuff[0]) {
- case WCH_SDI_INIT:
- NHC_WchSdi_Init();
- break;
- case WCH_SDI_EXIT:
- NHC_WchSdi_Exit();
- break;
- case WCH_SDI_READ:
- u32Tmp = u8tou32(rxBuff + 2);
- txBuff[0] = NHC_WchSdi_Read(rxBuff[1], &u32Tmp);
- u32tou8(u32Tmp, txBuff + 1);
- DCD_EP_Tx(pdev, HID_IN_EP, txBuff, 0x40);
- break;
- case WCH_SDI_WRITE:
- u32Tmp = u8tou32(rxBuff + 2);
- NHC_WchSdi_Write(rxBuff[1], u32Tmp);
- break;
- case WCH_SDI_READ_MEM:
- u32Address = u8tou32(rxBuff + 1);
- txBuff[0] = NHC_WchSdi_ReadMem(u32Address, &u32Tmp, rxBuff[5]);
- u32tou8(u32Tmp, txBuff + 1);
- DCD_EP_Tx(pdev, HID_IN_EP, txBuff, 0x40);
- break;
- case WCH_SDI_WRITE_MEM:
- u32Address = u8tou32(rxBuff + 1);
- u32Tmp = u8tou32(rxBuff + 5);
- NHC_WchSdi_WriteMem(u32Address, u32Tmp, rxBuff[9]);
- break;
- case DELAY_US_CMD:
- u32Tmp = u8tou32(rxBuff + 1);
- if (u32Tmp < 50000)
- {
- NHC_Delay_Us(u32Tmp);
- }
- else
- {
- n = u32Tmp / 50000;
- for (i = 0; i < n; ++i)
- {
- NHC_Delay_Us(50000);
- }
- n = u32Tmp % 50000;
- if (n)
- {
- NHC_Delay_Us(n);
- }
- }
- break;
- }
-
- busy_off;
-
- DCD_EP_PrepareRx(pdev, HID_OUT_EP, rxBuff, 0x40);
- return USBD_OK;
-}
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/LibUSB/LibUSB.h b/attic/NHC-Link042/LibUSB/LibUSB.h
deleted file mode 100644
index 5216d0a8c141aed42f4bb8da1c12c2adfac84793..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/LibUSB/LibUSB.h
+++ /dev/null
@@ -1,64 +0,0 @@
-/**
- ******************************************************************************
- * @file usbd_hid_core.h
- * @author MCD Application Team
- * @version V1.0.1
- * @date 31-January-2014
- * @brief header file for the usbd_hid_core.c file.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __USB_HID_CORE_H_
-#define __USB_HID_CORE_H_
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_req.h"
-
-/* Exported defines ----------------------------------------------------------*/
-#define USB_HID_CONFIG_DESC_SIZ 0x20
-#define USB_HID_DESC_SIZ 9
-#define HID_MOUSE_REPORT_DESC_SIZE 28
-
-#define HID_DESCRIPTOR_TYPE 0x21
-#define HID_REPORT_DESC 0x22
-
-
-#define HID_REQ_SET_PROTOCOL 0x0B
-#define HID_REQ_GET_PROTOCOL 0x03
-
-#define HID_REQ_SET_IDLE 0x0A
-#define HID_REQ_GET_IDLE 0x02
-
-#define HID_REQ_SET_REPORT 0x09
-#define HID_REQ_GET_REPORT 0x01
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported macros -----------------------------------------------------------*/
-/* Exported variables --------------------------------------------------------*/
-extern USBD_Class_cb_TypeDef USBD_HID_cb;
-
-/* Exported functions ------------------------------------------------------- */
-
-uint8_t USBD_HID_SendReport (USB_CORE_HANDLE *pdev,
- uint8_t *report,
- uint16_t len);
-#endif /* __USB_HID_CORE_H_ */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/NHC-Link042.uvprojx b/attic/NHC-Link042/NHC-Link042.uvprojx
deleted file mode 100644
index b35aa43076a06fc0c6ff09bff5bd4333a696aecd..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/NHC-Link042.uvprojx
+++ /dev/null
@@ -1,564 +0,0 @@
-<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
-
- <SchemaVersion>2.1</SchemaVersion>
-
- <Header>### uVision Project, (C) Keil Software</Header>
-
- <Targets>
- <Target>
- <TargetName>NHC-Link042</TargetName>
- <ToolsetNumber>0x4</ToolsetNumber>
- <ToolsetName>ARM-ADS</ToolsetName>
- <pCCUsed>5060960::V5.06 update 7 (build 960)::.\v6</pCCUsed>
- <uAC6>0</uAC6>
- <TargetOption>
- <TargetCommonOption>
- <Device>STM32F042F6</Device>
- <Vendor>STMicroelectronics</Vendor>
- <PackID>Keil.STM32F0xx_DFP.2.1.1</PackID>
- <PackURL>https://www.keil.com/pack/</PackURL>
- <Cpu>IROM(0x08000000,0x8000) IRAM(0x20000000,0x1800) CPUTYPE("Cortex-M0") CLOCK(12000000) ELITTLE</Cpu>
- <FlashUtilSpec></FlashUtilSpec>
- <StartupFile></StartupFile>
- <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F0xx_32 -FS08000000 -FL08000 -FP0($$Device:STM32F042F6$Flash\STM32F0xx_32.FLM))</FlashDriverDll>
- <DeviceId>0</DeviceId>
- <RegisterFile>$$Device:STM32F042F6$Device\Include\stm32f0xx.h</RegisterFile>
- <MemoryEnv></MemoryEnv>
- <Cmp></Cmp>
- <Asm></Asm>
- <Linker></Linker>
- <OHString></OHString>
- <InfinionOptionDll></InfinionOptionDll>
- <SLE66CMisc></SLE66CMisc>
- <SLE66AMisc></SLE66AMisc>
- <SLE66LinkerMisc></SLE66LinkerMisc>
- <SFDFile>$$Device:STM32F042F6$SVD\STM32F042x.svd</SFDFile>
- <bCustSvd>0</bCustSvd>
- <UseEnv>0</UseEnv>
- <BinPath></BinPath>
- <IncludePath></IncludePath>
- <LibPath></LibPath>
- <RegisterFilePath></RegisterFilePath>
- <DBRegisterFilePath></DBRegisterFilePath>
- <TargetStatus>
- <Error>0</Error>
- <ExitCodeStop>0</ExitCodeStop>
- <ButtonStop>0</ButtonStop>
- <NotGenerated>0</NotGenerated>
- <InvalidFlash>1</InvalidFlash>
- </TargetStatus>
- <OutputDirectory>.\obj\</OutputDirectory>
- <OutputName>NHC-Link042</OutputName>
- <CreateExecutable>1</CreateExecutable>
- <CreateLib>0</CreateLib>
- <CreateHexFile>1</CreateHexFile>
- <DebugInformation>1</DebugInformation>
- <BrowseInformation>1</BrowseInformation>
- <ListingPath>.\lst\</ListingPath>
- <HexFormatSelection>1</HexFormatSelection>
- <Merge32K>0</Merge32K>
- <CreateBatchFile>0</CreateBatchFile>
- <BeforeCompile>
- <RunUserProg1>0</RunUserProg1>
- <RunUserProg2>0</RunUserProg2>
- <UserProg1Name></UserProg1Name>
- <UserProg2Name></UserProg2Name>
- <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
- <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
- <nStopU1X>0</nStopU1X>
- <nStopU2X>0</nStopU2X>
- </BeforeCompile>
- <BeforeMake>
- <RunUserProg1>0</RunUserProg1>
- <RunUserProg2>0</RunUserProg2>
- <UserProg1Name></UserProg1Name>
- <UserProg2Name></UserProg2Name>
- <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
- <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
- <nStopB1X>0</nStopB1X>
- <nStopB2X>0</nStopB2X>
- </BeforeMake>
- <AfterMake>
- <RunUserProg1>0</RunUserProg1>
- <RunUserProg2>0</RunUserProg2>
- <UserProg1Name></UserProg1Name>
- <UserProg2Name></UserProg2Name>
- <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
- <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
- <nStopA1X>0</nStopA1X>
- <nStopA2X>0</nStopA2X>
- </AfterMake>
- <SelectedForBatchBuild>0</SelectedForBatchBuild>
- <SVCSIdString></SVCSIdString>
- </TargetCommonOption>
- <CommonProperty>
- <UseCPPCompiler>0</UseCPPCompiler>
- <RVCTCodeConst>0</RVCTCodeConst>
- <RVCTZI>0</RVCTZI>
- <RVCTOtherData>0</RVCTOtherData>
- <ModuleSelection>0</ModuleSelection>
- <IncludeInBuild>1</IncludeInBuild>
- <AlwaysBuild>0</AlwaysBuild>
- <GenerateAssemblyFile>0</GenerateAssemblyFile>
- <AssembleAssemblyFile>0</AssembleAssemblyFile>
- <PublicsOnly>0</PublicsOnly>
- <StopOnExitCode>3</StopOnExitCode>
- <CustomArgument></CustomArgument>
- <IncludeLibraryModules></IncludeLibraryModules>
- <ComprImg>1</ComprImg>
- </CommonProperty>
- <DllOption>
- <SimDllName>SARMCM3.DLL</SimDllName>
- <SimDllArguments> </SimDllArguments>
- <SimDlgDll>DARMCM1.DLL</SimDlgDll>
- <SimDlgDllArguments>-pCM0</SimDlgDllArguments>
- <TargetDllName>SARMCM3.DLL</TargetDllName>
- <TargetDllArguments> </TargetDllArguments>
- <TargetDlgDll>TARMCM1.DLL</TargetDlgDll>
- <TargetDlgDllArguments>-pCM0</TargetDlgDllArguments>
- </DllOption>
- <DebugOption>
- <OPTHX>
- <HexSelection>1</HexSelection>
- <HexRangeLowAddress>0</HexRangeLowAddress>
- <HexRangeHighAddress>0</HexRangeHighAddress>
- <HexOffset>0</HexOffset>
- <Oh166RecLen>16</Oh166RecLen>
- </OPTHX>
- </DebugOption>
- <Utilities>
- <Flash1>
- <UseTargetDll>1</UseTargetDll>
- <UseExternalTool>0</UseExternalTool>
- <RunIndependent>0</RunIndependent>
- <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
- <Capability>1</Capability>
- <DriverSelection>4096</DriverSelection>
- </Flash1>
- <bUseTDR>1</bUseTDR>
- <Flash2>BIN\UL2CM3.DLL</Flash2>
- <Flash3></Flash3>
- <Flash4></Flash4>
- <pFcarmOut></pFcarmOut>
- <pFcarmGrp></pFcarmGrp>
- <pFcArmRoot></pFcArmRoot>
- <FcArmLst>0</FcArmLst>
- </Utilities>
- <TargetArmAds>
- <ArmAdsMisc>
- <GenerateListings>0</GenerateListings>
- <asHll>1</asHll>
- <asAsm>1</asAsm>
- <asMacX>1</asMacX>
- <asSyms>1</asSyms>
- <asFals>1</asFals>
- <asDbgD>1</asDbgD>
- <asForm>1</asForm>
- <ldLst>0</ldLst>
- <ldmm>1</ldmm>
- <ldXref>1</ldXref>
- <BigEnd>0</BigEnd>
- <AdsALst>1</AdsALst>
- <AdsACrf>1</AdsACrf>
- <AdsANop>0</AdsANop>
- <AdsANot>0</AdsANot>
- <AdsLLst>1</AdsLLst>
- <AdsLmap>1</AdsLmap>
- <AdsLcgr>1</AdsLcgr>
- <AdsLsym>1</AdsLsym>
- <AdsLszi>1</AdsLszi>
- <AdsLtoi>1</AdsLtoi>
- <AdsLsun>1</AdsLsun>
- <AdsLven>1</AdsLven>
- <AdsLsxf>1</AdsLsxf>
- <RvctClst>0</RvctClst>
- <GenPPlst>0</GenPPlst>
- <AdsCpuType>"Cortex-M0"</AdsCpuType>
- <RvctDeviceName></RvctDeviceName>
- <mOS>0</mOS>
- <uocRom>0</uocRom>
- <uocRam>0</uocRam>
- <hadIROM>1</hadIROM>
- <hadIRAM>1</hadIRAM>
- <hadXRAM>0</hadXRAM>
- <uocXRam>0</uocXRam>
- <RvdsVP>0</RvdsVP>
- <RvdsMve>0</RvdsMve>
- <RvdsCdeCp>0</RvdsCdeCp>
- <nBranchProt>0</nBranchProt>
- <hadIRAM2>0</hadIRAM2>
- <hadIROM2>0</hadIROM2>
- <StupSel>8</StupSel>
- <useUlib>1</useUlib>
- <EndSel>0</EndSel>
- <uLtcg>0</uLtcg>
- <nSecure>0</nSecure>
- <RoSelD>3</RoSelD>
- <RwSelD>3</RwSelD>
- <CodeSel>0</CodeSel>
- <OptFeed>0</OptFeed>
- <NoZi1>0</NoZi1>
- <NoZi2>0</NoZi2>
- <NoZi3>0</NoZi3>
- <NoZi4>0</NoZi4>
- <NoZi5>0</NoZi5>
- <Ro1Chk>0</Ro1Chk>
- <Ro2Chk>0</Ro2Chk>
- <Ro3Chk>0</Ro3Chk>
- <Ir1Chk>1</Ir1Chk>
- <Ir2Chk>0</Ir2Chk>
- <Ra1Chk>0</Ra1Chk>
- <Ra2Chk>0</Ra2Chk>
- <Ra3Chk>0</Ra3Chk>
- <Im1Chk>1</Im1Chk>
- <Im2Chk>0</Im2Chk>
- <OnChipMemories>
- <Ocm1>
- <Type>0</Type>
- <StartAddress>0x0</StartAddress>
- <Size>0x0</Size>
- </Ocm1>
- <Ocm2>
- <Type>0</Type>
- <StartAddress>0x0</StartAddress>
- <Size>0x0</Size>
- </Ocm2>
- <Ocm3>
- <Type>0</Type>
- <StartAddress>0x0</StartAddress>
- <Size>0x0</Size>
- </Ocm3>
- <Ocm4>
- <Type>0</Type>
- <StartAddress>0x0</StartAddress>
- <Size>0x0</Size>
- </Ocm4>
- <Ocm5>
- <Type>0</Type>
- <StartAddress>0x0</StartAddress>
- <Size>0x0</Size>
- </Ocm5>
- <Ocm6>
- <Type>0</Type>
- <StartAddress>0x0</StartAddress>
- <Size>0x0</Size>
- </Ocm6>
- <IRAM>
- <Type>0</Type>
- <StartAddress>0x20000000</StartAddress>
- <Size>0x1800</Size>
- </IRAM>
- <IROM>
- <Type>1</Type>
- <StartAddress>0x8000000</StartAddress>
- <Size>0x8000</Size>
- </IROM>
- <XRAM>
- <Type>0</Type>
- <StartAddress>0x0</StartAddress>
- <Size>0x0</Size>
- </XRAM>
- <OCR_RVCT1>
- <Type>1</Type>
- <StartAddress>0x0</StartAddress>
- <Size>0x0</Size>
- </OCR_RVCT1>
- <OCR_RVCT2>
- <Type>1</Type>
- <StartAddress>0x0</StartAddress>
- <Size>0x0</Size>
- </OCR_RVCT2>
- <OCR_RVCT3>
- <Type>1</Type>
- <StartAddress>0x0</StartAddress>
- <Size>0x0</Size>
- </OCR_RVCT3>
- <OCR_RVCT4>
- <Type>1</Type>
- <StartAddress>0x8000000</StartAddress>
- <Size>0x4000</Size>
- </OCR_RVCT4>
- <OCR_RVCT5>
- <Type>1</Type>
- <StartAddress>0x0</StartAddress>
- <Size>0x0</Size>
- </OCR_RVCT5>
- <OCR_RVCT6>
- <Type>0</Type>
- <StartAddress>0x0</StartAddress>
- <Size>0x0</Size>
- </OCR_RVCT6>
- <OCR_RVCT7>
- <Type>0</Type>
- <StartAddress>0x0</StartAddress>
- <Size>0x0</Size>
- </OCR_RVCT7>
- <OCR_RVCT8>
- <Type>0</Type>
- <StartAddress>0x0</StartAddress>
- <Size>0x0</Size>
- </OCR_RVCT8>
- <OCR_RVCT9>
- <Type>0</Type>
- <StartAddress>0x20000000</StartAddress>
- <Size>0x2000</Size>
- </OCR_RVCT9>
- <OCR_RVCT10>
- <Type>0</Type>
- <StartAddress>0x0</StartAddress>
- <Size>0x0</Size>
- </OCR_RVCT10>
- </OnChipMemories>
- <RvctStartVector></RvctStartVector>
- </ArmAdsMisc>
- <Cads>
- <interw>1</interw>
- <Optim>4</Optim>
- <oTime>0</oTime>
- <SplitLS>0</SplitLS>
- <OneElfS>0</OneElfS>
- <Strict>0</Strict>
- <EnumInt>0</EnumInt>
- <PlainCh>0</PlainCh>
- <Ropi>0</Ropi>
- <Rwpi>0</Rwpi>
- <wLevel>0</wLevel>
- <uThumb>0</uThumb>
- <uSurpInc>0</uSurpInc>
- <uC99>0</uC99>
- <uGnu>0</uGnu>
- <useXO>0</useXO>
- <v6Lang>1</v6Lang>
- <v6LangP>1</v6LangP>
- <vShortEn>1</vShortEn>
- <vShortWch>1</vShortWch>
- <v6Lto>0</v6Lto>
- <v6WtE>0</v6WtE>
- <v6Rtti>0</v6Rtti>
- <VariousControls>
- <MiscControls></MiscControls>
- <Define>USE_STDPERIPH_DRIVER,STM32F042, INTERNAL_PULLUP, USB_CLOCK_SOURCE_CRS</Define>
- <Undefine></Undefine>
- <IncludePath>.\User;.\STM32F0x2_USB-FS-Device_Lib V1.0.0\Libraries\CMSIS\Device\ST\STM32F0xx\Include;.\STM32F0x2_USB-FS-Device_Lib V1.0.0\Libraries\STM32F0xx_StdPeriph_Driver\inc;.\STM32F0x2_USB-FS-Device_Lib V1.0.0\Libraries\STM32_USB_Device_Driver\inc;.\STM32F0x2_USB-FS-Device_Lib V1.0.0\Libraries\STM32_USB_Device_Library\Core\inc;.\LibUSB;.\STM32F0x2_USB-FS-Device_Lib V1.0.0\Libraries\CMSIS\Include</IncludePath>
- </VariousControls>
- </Cads>
- <Aads>
- <interw>1</interw>
- <Ropi>0</Ropi>
- <Rwpi>0</Rwpi>
- <thumb>0</thumb>
- <SplitLS>0</SplitLS>
- <SwStkChk>0</SwStkChk>
- <NoWarn>0</NoWarn>
- <uSurpInc>0</uSurpInc>
- <useXO>0</useXO>
- <ClangAsOpt>1</ClangAsOpt>
- <VariousControls>
- <MiscControls></MiscControls>
- <Define></Define>
- <Undefine></Undefine>
- <IncludePath></IncludePath>
- </VariousControls>
- </Aads>
- <LDads>
- <umfTarg>1</umfTarg>
- <Ropi>0</Ropi>
- <Rwpi>0</Rwpi>
- <noStLib>0</noStLib>
- <RepFail>1</RepFail>
- <useFile>0</useFile>
- <TextAddressRange>0x08000000</TextAddressRange>
- <DataAddressRange>0x20000000</DataAddressRange>
- <pXoBase></pXoBase>
- <ScatterFile></ScatterFile>
- <IncludeLibs></IncludeLibs>
- <IncludeLibsPath></IncludeLibsPath>
- <Misc></Misc>
- <LinkerInputFile></LinkerInputFile>
- <DisabledWarnings></DisabledWarnings>
- </LDads>
- </TargetArmAds>
- </TargetOption>
- <Groups>
- <Group>
- <GroupName>User</GroupName>
- <Files>
- <File>
- <FileName>it.c</FileName>
- <FileType>1</FileType>
- <FilePath>.\User\it.c</FilePath>
- </File>
- <File>
- <FileName>main.c</FileName>
- <FileType>1</FileType>
- <FilePath>.\User\main.c</FilePath>
- </File>
- <File>
- <FileName>usb_bsp.c</FileName>
- <FileType>1</FileType>
- <FilePath>.\User\usb_bsp.c</FilePath>
- </File>
- <File>
- <FileName>usbd_pwr.c</FileName>
- <FileType>1</FileType>
- <FilePath>.\User\usbd_pwr.c</FilePath>
- </File>
- <File>
- <FileName>usbd_desc.c</FileName>
- <FileType>1</FileType>
- <FilePath>.\User\usbd_desc.c</FilePath>
- </File>
- <File>
- <FileName>usbd_usr.c</FileName>
- <FileType>1</FileType>
- <FilePath>.\User\usbd_usr.c</FilePath>
- </File>
- <File>
- <FileName>stm32_it.c</FileName>
- <FileType>1</FileType>
- <FilePath>.\User\stm32_it.c</FilePath>
- </File>
- <File>
- <FileName>NHC_WCH_SDI.c</FileName>
- <FileType>1</FileType>
- <FilePath>.\User\NHC_WCH_SDI.c</FilePath>
- </File>
- <File>
- <FileName>NHC_WCH_SDI.h</FileName>
- <FileType>5</FileType>
- <FilePath>.\User\NHC_WCH_SDI.h</FilePath>
- </File>
- <File>
- <FileName>config.h</FileName>
- <FileType>5</FileType>
- <FilePath>.\User\config.h</FilePath>
- </File>
- <File>
- <FileName>usbd_desc.h</FileName>
- <FileType>5</FileType>
- <FilePath>.\User\usbd_desc.h</FilePath>
- </File>
- </Files>
- </Group>
- <Group>
- <GroupName>USB_Class</GroupName>
- <Files>
- <File>
- <FileName>LibUSB.c</FileName>
- <FileType>1</FileType>
- <FilePath>.\LibUSB\LibUSB.c</FilePath>
- </File>
- </Files>
- </Group>
- <Group>
- <GroupName>CMSIS</GroupName>
- <Files>
- <File>
- <FileName>system_stm32f0xx.c</FileName>
- <FileType>1</FileType>
- <FilePath>.\User\system_stm32f0xx.c</FilePath>
- </File>
- <File>
- <FileName>startup_stm32f042.s</FileName>
- <FileType>2</FileType>
- <FilePath>.\STM32F0x2_USB-FS-Device_Lib V1.0.0\Libraries\CMSIS\Device\ST\STM32F0xx\Source\Templates\arm\startup_stm32f042.s</FilePath>
- </File>
- </Files>
- </Group>
- <Group>
- <GroupName>LIB</GroupName>
- <Files>
- <File>
- <FileName>stm32f0xx_crs.c</FileName>
- <FileType>1</FileType>
- <FilePath>.\STM32F0x2_USB-FS-Device_Lib V1.0.0\Libraries\STM32F0xx_StdPeriph_Driver\src\stm32f0xx_crs.c</FilePath>
- </File>
- <File>
- <FileName>stm32f0xx_exti.c</FileName>
- <FileType>1</FileType>
- <FilePath>.\STM32F0x2_USB-FS-Device_Lib V1.0.0\Libraries\STM32F0xx_StdPeriph_Driver\src\stm32f0xx_exti.c</FilePath>
- </File>
- <File>
- <FileName>stm32f0xx_gpio.c</FileName>
- <FileType>1</FileType>
- <FilePath>.\STM32F0x2_USB-FS-Device_Lib V1.0.0\Libraries\STM32F0xx_StdPeriph_Driver\src\stm32f0xx_gpio.c</FilePath>
- </File>
- <File>
- <FileName>stm32f0xx_rcc.c</FileName>
- <FileType>1</FileType>
- <FilePath>.\STM32F0x2_USB-FS-Device_Lib V1.0.0\Libraries\STM32F0xx_StdPeriph_Driver\src\stm32f0xx_rcc.c</FilePath>
- </File>
- <File>
- <FileName>stm32f0xx_syscfg.c</FileName>
- <FileType>1</FileType>
- <FilePath>.\STM32F0x2_USB-FS-Device_Lib V1.0.0\Libraries\STM32F0xx_StdPeriph_Driver\src\stm32f0xx_syscfg.c</FilePath>
- </File>
- <File>
- <FileName>stm32f0xx_tim.c</FileName>
- <FileType>1</FileType>
- <FilePath>.\STM32F0x2_USB-FS-Device_Lib V1.0.0\Libraries\STM32F0xx_StdPeriph_Driver\src\stm32f0xx_tim.c</FilePath>
- </File>
- <File>
- <FileName>stm32f0xx_misc.c</FileName>
- <FileType>1</FileType>
- <FilePath>.\STM32F0x2_USB-FS-Device_Lib V1.0.0\Libraries\STM32F0xx_StdPeriph_Driver\src\stm32f0xx_misc.c</FilePath>
- </File>
- </Files>
- </Group>
- <Group>
- <GroupName>USB_Lib</GroupName>
- <Files>
- <File>
- <FileName>usb_core.c</FileName>
- <FileType>1</FileType>
- <FilePath>.\STM32F0x2_USB-FS-Device_Lib V1.0.0\Libraries\STM32_USB_Device_Driver\src\usb_core.c</FilePath>
- </File>
- <File>
- <FileName>usb_dcd.c</FileName>
- <FileType>1</FileType>
- <FilePath>.\STM32F0x2_USB-FS-Device_Lib V1.0.0\Libraries\STM32_USB_Device_Driver\src\usb_dcd.c</FilePath>
- </File>
- <File>
- <FileName>usb_dcd_int.c</FileName>
- <FileType>1</FileType>
- <FilePath>.\STM32F0x2_USB-FS-Device_Lib V1.0.0\Libraries\STM32_USB_Device_Driver\src\usb_dcd_int.c</FilePath>
- </File>
- <File>
- <FileName>usbd_core.c</FileName>
- <FileType>1</FileType>
- <FilePath>.\STM32F0x2_USB-FS-Device_Lib V1.0.0\Libraries\STM32_USB_Device_Library\Core\src\usbd_core.c</FilePath>
- </File>
- <File>
- <FileName>usbd_ioreq.c</FileName>
- <FileType>1</FileType>
- <FilePath>.\STM32F0x2_USB-FS-Device_Lib V1.0.0\Libraries\STM32_USB_Device_Library\Core\src\usbd_ioreq.c</FilePath>
- </File>
- <File>
- <FileName>usbd_req.c</FileName>
- <FileType>1</FileType>
- <FilePath>.\STM32F0x2_USB-FS-Device_Lib V1.0.0\Libraries\STM32_USB_Device_Library\Core\src\usbd_req.c</FilePath>
- </File>
- </Files>
- </Group>
- </Groups>
- </Target>
- </Targets>
-
- <RTE>
- <apis/>
- <components/>
- <files/>
- </RTE>
-
- <LayerInfo>
- <Layers>
- <Layer>
- <LayName>Template</LayName>
- <LayTarg>0</LayTarg>
- <LayPrjMark>1</LayPrjMark>
- </Layer>
- </Layers>
- </LayerInfo>
-
-</Project>
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h
deleted file mode 100644
index 53c8c0111a8494e635ae6de6f25d5f7194ba3a19..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h
+++ /dev/null
@@ -1,5111 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f0xx.h
- * @author MCD Application Team
- * @version V1.3.1
- * @date 17-January-2014
- * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File.
- * This file contains all the peripheral register's definitions, bits
- * definitions and memory mapping for STM32F0xx devices.
- *
- * The file is the unique include file that the application programmer
- * is using in the C source code, usually in main.c. This file contains:
- * - Configuration section that allows to select:
- * - The device used in the target application
- * - To use or not the peripheral’s drivers in application code(i.e.
- * code will be based on direct access to peripheral’s registers
- * rather than drivers API), this option is controlled by
- * "#define USE_STDPERIPH_DRIVER"
- * - To change few application-specific parameters such as the HSE
- * crystal frequency
- * - Data structures and the address mapping for all peripherals
- * - Peripheral's registers declarations and bits definition
- * - Macros to access peripheral’s registers hardware
- *
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/** @addtogroup CMSIS
- * @{
- */
-
-/** @addtogroup stm32f0xx
- * @{
- */
-
-#ifndef __STM32F0XX_H
-#define __STM32F0XX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/** @addtogroup Library_configuration_section
- * @{
- */
-
-/* Uncomment the line below according to the target STM32F0 device used in your
- application
- */
-
-#if !defined (STM32F030) && !defined (STM32F031) && !defined (STM32F051) && !defined (STM32F072) && !defined (STM32F042)
- /* #define STM32F030 */
- /* #define STM32F031 */
- /* #define STM32F051 */
- #define STM32F072
- /* #define STM32F042 */
-#endif
-
-/* Tip: To avoid modifying this file each time you need to switch between these
- devices, you can define the device in your toolchain compiler preprocessor.
- */
-
-/* Old STM32F0XX definition, maintained for legacy purpose */
-#if defined(STM32F0XX) || defined(STM32F0XX_MD)
- #define STM32F051
-#endif /* STM32F0XX */
-
-/* Old STM32F0XX_LD definition, maintained for legacy purpose */
-#ifdef STM32F0XX_LD
- #define STM32F031
-#endif /* STM32F0XX_LD */
-
-/* Old STM32F0XX_HD definition, maintained for legacy purpose */
-#ifdef STM32F0XX_HD
- #define STM32F072
-#endif /* STM32F0XX_HD */
-
-/* Old STM32F030X6/X8 definition, maintained for legacy purpose */
-#if defined (STM32F030X8) || defined (STM32F030X6)
- #define STM32F030
-#endif /* STM32F030X8 or STM32F030X6 */
-
-
-#if !defined (STM32F030) && !defined (STM32F031) && !defined (STM32F051) && !defined (STM32F072) && !defined (STM32F042)
- #error "Please select first the target STM32F0xx device used in your application (in stm32f0xx.h file)"
-#endif
-
-#if !defined USE_STDPERIPH_DRIVER
-/**
- * @brief Comment the line below if you will not use the peripherals drivers.
- In this case, these drivers will not be included and the application code will
- be based on direct access to peripherals registers
- */
- /*#define USE_STDPERIPH_DRIVER*/
-#endif /* USE_STDPERIPH_DRIVER */
-
-/**
- * @brief In the following line adjust the value of External High Speed oscillator (HSE)
- used in your application
-
- Tip: To avoid modifying this file each time you need to use different HSE, you
- can define the HSE value in your toolchain compiler preprocessor.
- */
-#if !defined (HSE_VALUE)
-#define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz*/
-#endif /* HSE_VALUE */
-
-/**
- * @brief In the following line adjust the External High Speed oscillator (HSE) Startup
- Timeout value
- */
-#if !defined (HSE_STARTUP_TIMEOUT)
-#define HSE_STARTUP_TIMEOUT ((uint16_t)0x5000) /*!< Time out for HSE start up */
-#endif /* HSE_STARTUP_TIMEOUT */
-
-/**
- * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup
- Timeout value
- */
-#if !defined (HSI_STARTUP_TIMEOUT)
-#define HSI_STARTUP_TIMEOUT ((uint16_t)0x5000) /*!< Time out for HSI start up */
-#endif /* HSI_STARTUP_TIMEOUT */
-
-#if !defined (HSI_VALUE)
-#define HSI_VALUE ((uint32_t)8000000) /*!< Value of the Internal High Speed oscillator in Hz.
- The real value may vary depending on the variations
- in voltage and temperature. */
-#endif /* HSI_VALUE */
-
-#if !defined (HSI14_VALUE)
-#define HSI14_VALUE ((uint32_t)14000000) /*!< Value of the Internal High Speed oscillator for ADC in Hz.
- The real value may vary depending on the variations
- in voltage and temperature. */
-#endif /* HSI14_VALUE */
-
-#if !defined (HSI48_VALUE)
-#define HSI48_VALUE ((uint32_t)48000000) /*!< Value of the Internal High Speed oscillator for USB in Hz.
- The real value may vary depending on the variations
- in voltage and temperature. */
-#endif /* HSI48_VALUE */
-
-#if !defined (LSI_VALUE)
-#define LSI_VALUE ((uint32_t)40000) /*!< Value of the Internal Low Speed oscillator in Hz
- The real value may vary depending on the variations
- in voltage and temperature. */
-#endif /* LSI_VALUE */
-
-#if !defined (LSE_VALUE)
-#define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */
-#endif /* LSE_VALUE */
-
-/**
- * @brief STM32F0xx Standard Peripheral Library version number V1.3.1
- */
-#define __STM32F0XX_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */
-#define __STM32F0XX_STDPERIPH_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
-#define __STM32F0XX_STDPERIPH_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */
-#define __STM32F0XX_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */
-#define __STM32F0XX_STDPERIPH_VERSION ((__STM32F0XX_STDPERIPH_VERSION_MAIN << 24)\
- |(__STM32F0XX_STDPERIPH_VERSION_SUB1 << 16)\
- |(__STM32F0XX_STDPERIPH_VERSION_SUB2 << 8)\
- |(__STM32F0XX_STDPERIPH_VERSION_RC))
-
-/**
- * @}
- */
-
-/** @addtogroup Configuration_section_for_CMSIS
- * @{
- */
-
-/**
- * @brief STM32F0xx Interrupt Number Definition, according to the selected device
- * in @ref Library_configuration_section
- */
-#define __CM0_REV 0 /*!< Core Revision r0p0 */
-#define __MPU_PRESENT 0 /*!< STM32F0xx do not provide MPU */
-#define __NVIC_PRIO_BITS 2 /*!< STM32F0xx uses 2 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
-
-/*!< Interrupt Number Definition */
-typedef enum IRQn
-{
-/****** Cortex-M0 Processor Exceptions Numbers ******************************************************/
- NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
- HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */
- SVC_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
- PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
- SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
-
-#if defined (STM32F051)
-/****** STM32F051 specific Interrupt Numbers *************************************/
- WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
- PVD_IRQn = 1, /*!< PVD through EXTI Line detect Interrupt */
- RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */
- FLASH_IRQn = 3, /*!< FLASH Interrupt */
- RCC_IRQn = 4, /*!< RCC Interrupt */
- EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */
- EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */
- EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */
- TS_IRQn = 8, /*!< Touch sense controller Interrupt */
- DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */
- DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */
- DMA1_Channel4_5_IRQn = 11, /*!< DMA1 Channel 4 and Channel 5 Interrupts */
- ADC1_COMP_IRQn = 12, /*!< ADC1, COMP1 and COMP2 Interrupts */
- TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */
- TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */
- TIM2_IRQn = 15, /*!< TIM2 Interrupt */
- TIM3_IRQn = 16, /*!< TIM3 Interrupt */
- TIM6_DAC_IRQn = 17, /*!< TIM6 and DAC Interrupts */
- TIM14_IRQn = 19, /*!< TIM14 Interrupt */
- TIM15_IRQn = 20, /*!< TIM15 Interrupt */
- TIM16_IRQn = 21, /*!< TIM16 Interrupt */
- TIM17_IRQn = 22, /*!< TIM17 Interrupt */
- I2C1_IRQn = 23, /*!< I2C1 Interrupt */
- I2C2_IRQn = 24, /*!< I2C2 Interrupt */
- SPI1_IRQn = 25, /*!< SPI1 Interrupt */
- SPI2_IRQn = 26, /*!< SPI2 Interrupt */
- USART1_IRQn = 27, /*!< USART1 Interrupt */
- USART2_IRQn = 28, /*!< USART2 Interrupt */
- CEC_IRQn = 30 /*!< CEC Interrupt */
-#elif defined (STM32F031)
-/****** STM32F031 specific Interrupt Numbers *************************************/
- WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
- PVD_IRQn = 1, /*!< PVD through EXTI Line detect Interrupt */
- RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */
- FLASH_IRQn = 3, /*!< FLASH Interrupt */
- RCC_IRQn = 4, /*!< RCC Interrupt */
- EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */
- EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */
- EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */
- DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */
- DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */
- DMA1_Channel4_5_IRQn = 11, /*!< DMA1 Channel 4 and Channel 5 Interrupts */
- ADC1_IRQn = 12, /*!< ADC1 Interrupt */
- TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */
- TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */
- TIM2_IRQn = 15, /*!< TIM2 Interrupt */
- TIM3_IRQn = 16, /*!< TIM3 Interrupt */
- TIM14_IRQn = 19, /*!< TIM14 Interrupt */
- TIM16_IRQn = 21, /*!< TIM16 Interrupt */
- TIM17_IRQn = 22, /*!< TIM17 Interrupt */
- I2C1_IRQn = 23, /*!< I2C1 Interrupt */
- SPI1_IRQn = 25, /*!< SPI1 Interrupt */
- USART1_IRQn = 27 /*!< USART1 Interrupt */
-#elif defined (STM32F030)
-/****** STM32F030 specific Interrupt Numbers *************************************/
- WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
- RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */
- FLASH_IRQn = 3, /*!< FLASH Interrupt */
- RCC_IRQn = 4, /*!< RCC Interrupt */
- EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */
- EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */
- EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */
- DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */
- DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */
- DMA1_Channel4_5_IRQn = 11, /*!< DMA1 Channel 4 and Channel 5 Interrupts */
- ADC1_IRQn = 12, /*!< ADC1 Interrupt */
- TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */
- TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */
- TIM3_IRQn = 16, /*!< TIM3 Interrupt */
- TIM14_IRQn = 19, /*!< TIM14 Interrupt */
- TIM15_IRQn = 20, /*!< TIM15 Interrupt */
- TIM16_IRQn = 21, /*!< TIM16 Interrupt */
- TIM17_IRQn = 22, /*!< TIM17 Interrupt */
- I2C1_IRQn = 23, /*!< I2C1 Interrupt */
- I2C2_IRQn = 24, /*!< I2C2 Interrupt */
- SPI1_IRQn = 25, /*!< SPI1 Interrupt */
- SPI2_IRQn = 26, /*!< SPI2 Interrupt */
- USART1_IRQn = 27, /*!< USART1 Interrupt */
- USART2_IRQn = 28 /*!< USART2 Interrupt */
-#elif defined (STM32F072)
- WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
- PVD_VDDIO2_IRQn = 1, /*!< PVD and VDDIO2 supply comparator through EXTI Line detect Interrupt */
- RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */
- FLASH_IRQn = 3, /*!< FLASH Interrupt */
- RCC_CRS_IRQn = 4, /*!< RCC and CRS Interrupts */
- EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */
- EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */
- EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */
- TSC_IRQn = 8, /*!< TSC Interrupt */
- DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */
- DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */
- DMA1_Channel4_5_6_7_IRQn = 11, /*!< DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 Interrupts */
- ADC1_COMP_IRQn = 12, /*!< ADC1, COMP1 and COMP2 Interrupts */
- TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */
- TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */
- TIM2_IRQn = 15, /*!< TIM2 Interrupt */
- TIM3_IRQn = 16, /*!< TIM3 Interrupt */
- TIM6_DAC_IRQn = 17, /*!< TIM6 and DAC Interrupts */
- TIM7_IRQn = 18, /*!< TIM7 Interrupts */
- TIM14_IRQn = 19, /*!< TIM14 Interrupt */
- TIM15_IRQn = 20, /*!< TIM15 Interrupt */
- TIM16_IRQn = 21, /*!< TIM16 Interrupt */
- TIM17_IRQn = 22, /*!< TIM17 Interrupt */
- I2C1_IRQn = 23, /*!< I2C1 Interrupt */
- I2C2_IRQn = 24, /*!< I2C2 Interrupt */
- SPI1_IRQn = 25, /*!< SPI1 Interrupt */
- SPI2_IRQn = 26, /*!< SPI2 Interrupt */
- USART1_IRQn = 27, /*!< USART1 Interrupt */
- USART2_IRQn = 28, /*!< USART2 Interrupt */
- USART3_4_IRQn = 29, /*!< USART3 and USART4 Interrupts */
- CEC_CAN_IRQn = 30, /*!< CEC and CAN Interrupts */
- USB_IRQn = 31 /*!< USB Low Priority global Interrupt */
-#elif defined (STM32F042)
- WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
- PVD_VDDIO2_IRQn = 1, /*!< PVD and VDDIO2 supply comparator through EXTI Line detect Interrupt */
- RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */
- FLASH_IRQn = 3, /*!< FLASH Interrupt */
- RCC_CRS_IRQn = 4, /*!< RCC and CRS Interrupts */
- EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */
- EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */
- EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */
- TSC_IRQn = 8, /*!< TSC Interrupt */
- DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */
- DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */
- DMA1_Channel4_5_IRQn = 11, /*!< DMA1 Channel 4, Channel 5 Interrupts */
- ADC1_IRQn = 12, /*!< ADC1 Interrupts */
- TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */
- TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */
- TIM2_IRQn = 15, /*!< TIM2 Interrupt */
- TIM3_IRQn = 16, /*!< TIM3 Interrupt */
- TIM14_IRQn = 19, /*!< TIM14 Interrupt */
- TIM16_IRQn = 21, /*!< TIM16 Interrupt */
- TIM17_IRQn = 22, /*!< TIM17 Interrupt */
- I2C1_IRQn = 23, /*!< I2C1 Interrupt */
- SPI1_IRQn = 25, /*!< SPI1 Interrupt */
- SPI2_IRQn = 26, /*!< SPI2 Interrupt */
- USART1_IRQn = 27, /*!< USART1 Interrupt */
- USART2_IRQn = 28, /*!< USART2 Interrupt */
- CEC_CAN_IRQn = 30, /*!< CEC and CAN Interrupts */
- USB_IRQn = 31 /*!< USB Low Priority global Interrupt */
-#endif /* STM32F051 */
-} IRQn_Type;
-
-/**
- * @}
- */
-
-#include "core_cm0.h"
-#include "system_stm32f0xx.h"
-#include <stdint.h>
-
-/** @addtogroup Exported_types
- * @{
- */
-
-typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
-
-typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
-#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
-
-typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
-
-/** @addtogroup Peripheral_registers_structures
- * @{
- */
-
-/**
- * @brief Analog to Digital Converter
- */
-
-typedef struct
-{
- __IO uint32_t ISR; /*!< ADC Interrupt and Status register, Address offset:0x00 */
- __IO uint32_t IER; /*!< ADC Interrupt Enable register, Address offset:0x04 */
- __IO uint32_t CR; /*!< ADC Control register, Address offset:0x08 */
- __IO uint32_t CFGR1; /*!< ADC Configuration register 1, Address offset:0x0C */
- __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset:0x10 */
- __IO uint32_t SMPR; /*!< ADC Sampling time register, Address offset:0x14 */
- uint32_t RESERVED1; /*!< Reserved, 0x18 */
- uint32_t RESERVED2; /*!< Reserved, 0x1C */
- __IO uint32_t TR; /*!< ADC watchdog threshold register, Address offset:0x20 */
- uint32_t RESERVED3; /*!< Reserved, 0x24 */
- __IO uint32_t CHSELR; /*!< ADC channel selection register, Address offset:0x28 */
- uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */
- __IO uint32_t DR; /*!< ADC data register, Address offset:0x40 */
-} ADC_TypeDef;
-
-typedef struct
-{
- __IO uint32_t CCR;
-} ADC_Common_TypeDef;
-
-
-/**
- * @brief Controller Area Network TxMailBox
- */
-typedef struct
-{
- __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
- __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
- __IO uint32_t TDLR; /*!< CAN mailbox data low register */
- __IO uint32_t TDHR; /*!< CAN mailbox data high register */
-} CAN_TxMailBox_TypeDef;
-
-/**
- * @brief Controller Area Network FIFOMailBox
- */
-typedef struct
-{
- __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
- __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
- __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
- __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
-} CAN_FIFOMailBox_TypeDef;
-
-/**
- * @brief Controller Area Network FilterRegister
- */
-typedef struct
-{
- __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
- __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
-} CAN_FilterRegister_TypeDef;
-
-/**
- * @brief Controller Area Network
- */
-typedef struct
-{
- __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
- __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
- __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
- __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
- __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
- __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
- __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
- __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
- uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
- CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
- CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
- uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
- __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
- __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
- uint32_t RESERVED2; /*!< Reserved, 0x208 */
- __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
- uint32_t RESERVED3; /*!< Reserved, 0x210 */
- __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
- uint32_t RESERVED4; /*!< Reserved, 0x218 */
- __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
- uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
- CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
-} CAN_TypeDef;
-
-/**
- * @brief HDMI-CEC
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */
- __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */
- __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */
- __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */
- __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */
- __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */
-}CEC_TypeDef;
-
-/**
- * @brief Comparator
- */
-
-typedef struct
-{
- __IO uint32_t CSR; /*!< COMP comparator control and status register, Address offset: 0x1C */
-} COMP_TypeDef;
-
-
-/**
- * @brief CRC calculation unit
- */
-
-typedef struct
-{
- __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
- __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
- uint8_t RESERVED0; /*!< Reserved, 0x05 */
- uint16_t RESERVED1; /*!< Reserved, 0x06 */
- __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
- uint32_t RESERVED2; /*!< Reserved, 0x0C */
- __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
- __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
-} CRC_TypeDef;
-
-/**
- * @brief Clock Recovery System
- */
-typedef struct
-{
-__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */
-__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */
-__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */
-__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */
-} CRS_TypeDef;
-
-/**
- * @brief Digital to Analog Converter
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
- __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
- __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
- __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
- __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
- __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
- __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
- __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
- __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
- __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
- __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
- __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
- __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
- __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
-} DAC_TypeDef;
-
-/**
- * @brief Debug MCU
- */
-
-typedef struct
-{
- __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
- __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
- __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
- __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
-}DBGMCU_TypeDef;
-
-/**
- * @brief DMA Controller
- */
-
-typedef struct
-{
- __IO uint32_t CCR; /*!< DMA channel x configuration register */
- __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
- __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
- __IO uint32_t CMAR; /*!< DMA channel x memory address register */
-} DMA_Channel_TypeDef;
-
-typedef struct
-{
- __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
- __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
-} DMA_TypeDef;
-
-/**
- * @brief External Interrupt/Event Controller
- */
-
-typedef struct
-{
- __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */
- __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */
- __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */
- __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */
- __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */
- __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */
-}EXTI_TypeDef;
-
-/**
- * @brief FLASH Registers
- */
-typedef struct
-{
- __IO uint32_t ACR; /*!<FLASH access control register, Address offset: 0x00 */
- __IO uint32_t KEYR; /*!<FLASH key register, Address offset: 0x04 */
- __IO uint32_t OPTKEYR; /*!<FLASH OPT key register, Address offset: 0x08 */
- __IO uint32_t SR; /*!<FLASH status register, Address offset: 0x0C */
- __IO uint32_t CR; /*!<FLASH control register, Address offset: 0x10 */
- __IO uint32_t AR; /*!<FLASH address register, Address offset: 0x14 */
- __IO uint32_t RESERVED; /*!< Reserved, 0x18 */
- __IO uint32_t OBR; /*!<FLASH option bytes register, Address offset: 0x1C */
- __IO uint32_t WRPR; /*!<FLASH option bytes register, Address offset: 0x20 */
-} FLASH_TypeDef;
-
-
-/**
- * @brief Option Bytes Registers
- */
-typedef struct
-{
- __IO uint16_t RDP; /*!< FLASH option byte Read protection, Address offset: 0x00 */
- __IO uint16_t USER; /*!< FLASH option byte user options, Address offset: 0x02 */
- __IO uint16_t DATA0; /*!< User data byte 0 (stored in FLASH_OBR[23:16]), Address offset: 0x04 */
- __IO uint16_t DATA1; /*!< User data byte 1 (stored in FLASH_OBR[31:24]), Address offset: 0x06 */
- __IO uint16_t WRP0; /*!< FLASH option byte write protection 0, Address offset: 0x08 */
- __IO uint16_t WRP1; /*!< FLASH option byte write protection 1, Address offset: 0x0A */
- __IO uint16_t WRP2; /*!< FLASH option byte write protection 2, Address offset: 0x0C */
- __IO uint16_t WRP3; /*!< FLASH option byte write protection 3, Address offset: 0x0E */
-} OB_TypeDef;
-
-
-/**
- * @brief General Purpose IO
- */
-
-typedef struct
-{
- __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
- __IO uint16_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
- uint16_t RESERVED0; /*!< Reserved, 0x06 */
- __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
- __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
- __IO uint16_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
- uint16_t RESERVED1; /*!< Reserved, 0x12 */
- __IO uint16_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
- uint16_t RESERVED2; /*!< Reserved, 0x16 */
- __IO uint32_t BSRR; /*!< GPIO port bit set/reset registerBSRR, Address offset: 0x18 */
- __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
- __IO uint32_t AFR[2]; /*!< GPIO alternate function low register, Address offset: 0x20-0x24 */
- __IO uint16_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
- uint16_t RESERVED3; /*!< Reserved, 0x2A */
-}GPIO_TypeDef;
-
-/**
- * @brief SysTem Configuration
- */
-
-typedef struct
-{
- __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
- uint32_t RESERVED; /*!< Reserved, 0x04 */
- __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration register, Address offset: 0x14-0x08 */
- __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */
-} SYSCFG_TypeDef;
-
-/**
- * @brief Inter-integrated Circuit Interface
- */
-
-typedef struct
-{
- __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
- __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
- __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
- __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
- __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
- __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
- __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
- __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
- __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
- __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
- __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
-}I2C_TypeDef;
-
-
-/**
- * @brief Independent WATCHDOG
- */
-typedef struct
-{
- __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
- __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
- __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
- __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
- __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
-} IWDG_TypeDef;
-
-/**
- * @brief Power Control
- */
-
-typedef struct
-{
- __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
- __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
-} PWR_TypeDef;
-
-
-/**
- * @brief Reset and Clock Control
- */
-typedef struct
-{
- __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
- __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x04 */
- __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x08 */
- __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x0C */
- __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x10 */
- __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock register, Address offset: 0x14 */
- __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x18 */
- __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x1C */
- __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x20 */
- __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x24 */
- __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x28 */
- __IO uint32_t CFGR2; /*!< RCC clock configuration register 2, Address offset: 0x2C */
- __IO uint32_t CFGR3; /*!< RCC clock configuration register 3, Address offset: 0x30 */
- __IO uint32_t CR2; /*!< RCC clock control register 2, Address offset: 0x34 */
-} RCC_TypeDef;
-
-/**
- * @brief Real-Time Clock
- */
-
-typedef struct
-{
- __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
- __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
- __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
- __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
- __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
- __IO uint32_t WUTR; /*!< RTC wakeup timer register,(only for STM32F072 devices) Address offset: 0x14 */
- uint32_t RESERVED1; /*!< Reserved, Address offset: 0x18 */
- __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
- uint32_t RESERVED2; /*!< Reserved, Address offset: 0x20 */
- __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
- __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
- __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
- __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
- __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
- __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
- __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
- __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
- __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
- uint32_t RESERVED3; /*!< Reserved, Address offset: 0x48 */
- uint32_t RESERVED4; /*!< Reserved, Address offset: 0x4C */
- __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
- __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
- __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
- __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
- __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
-} RTC_TypeDef;
-
-/* Old register name definition maintained for legacy purpose */
-#define CAL CALR
-
-/**
- * @brief Serial Peripheral Interface
- */
-
-typedef struct
-{
- __IO uint16_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
- uint16_t RESERVED0; /*!< Reserved, 0x02 */
- __IO uint16_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
- uint16_t RESERVED1; /*!< Reserved, 0x06 */
- __IO uint16_t SR; /*!< SPI Status register, Address offset: 0x08 */
- uint16_t RESERVED2; /*!< Reserved, 0x0A */
- __IO uint16_t DR; /*!< SPI data register, Address offset: 0x0C */
- uint16_t RESERVED3; /*!< Reserved, 0x0E */
- __IO uint16_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
- uint16_t RESERVED4; /*!< Reserved, 0x12 */
- __IO uint16_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
- uint16_t RESERVED5; /*!< Reserved, 0x16 */
- __IO uint16_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
- uint16_t RESERVED6; /*!< Reserved, 0x1A */
- __IO uint16_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
- uint16_t RESERVED7; /*!< Reserved, 0x1E */
- __IO uint16_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
- uint16_t RESERVED8; /*!< Reserved, 0x22 */
-} SPI_TypeDef;
-
-
-/**
- * @brief TIM
- */
-typedef struct
-{
- __IO uint16_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
- uint16_t RESERVED0; /*!< Reserved, 0x02 */
- __IO uint16_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
- uint16_t RESERVED1; /*!< Reserved, 0x06 */
- __IO uint16_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
- uint16_t RESERVED2; /*!< Reserved, 0x0A */
- __IO uint16_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
- uint16_t RESERVED3; /*!< Reserved, 0x0E */
- __IO uint16_t SR; /*!< TIM status register, Address offset: 0x10 */
- uint16_t RESERVED4; /*!< Reserved, 0x12 */
- __IO uint16_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
- uint16_t RESERVED5; /*!< Reserved, 0x16 */
- __IO uint16_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
- uint16_t RESERVED6; /*!< Reserved, 0x1A */
- __IO uint16_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
- uint16_t RESERVED7; /*!< Reserved, 0x1E */
- __IO uint16_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
- uint16_t RESERVED8; /*!< Reserved, 0x22 */
- __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
- __IO uint16_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
- uint16_t RESERVED10; /*!< Reserved, 0x2A */
- __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
- __IO uint16_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
- uint16_t RESERVED12; /*!< Reserved, 0x32 */
- __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
- __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
- __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
- __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
- __IO uint16_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
- uint16_t RESERVED17; /*!< Reserved, 0x26 */
- __IO uint16_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
- uint16_t RESERVED18; /*!< Reserved, 0x4A */
- __IO uint16_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */
- uint16_t RESERVED19; /*!< Reserved, 0x4E */
- __IO uint16_t OR; /*!< TIM option register, Address offset: 0x50 */
- uint16_t RESERVED20; /*!< Reserved, 0x52 */
-} TIM_TypeDef;
-
-/**
- * @brief Touch Sensing Controller (TSC)
- */
-typedef struct
-{
- __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */
- __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */
- __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */
- __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */
- __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */
- __IO uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
- __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */
- __IO uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */
- __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */
- __IO uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */
- __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */
- __IO uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */
- __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */
- __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */
-} TSC_TypeDef;
-
-/**
- * @brief Universal Synchronous Asynchronous Receiver Transmitter
- */
-
-typedef struct
-{
- __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
- __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
- __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
- __IO uint16_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
- uint16_t RESERVED1; /*!< Reserved, 0x0E */
- __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
- uint16_t RESERVED2; /*!< Reserved, 0x12 */
- __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
- __IO uint16_t RQR; /*!< USART Request register, Address offset: 0x18 */
- uint16_t RESERVED3; /*!< Reserved, 0x1A */
- __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
- __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
- __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
- uint16_t RESERVED4; /*!< Reserved, 0x26 */
- __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
- uint16_t RESERVED5; /*!< Reserved, 0x2A */
-} USART_TypeDef;
-
-
-/**
- * @brief Window WATCHDOG
- */
-typedef struct
-{
- __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
- __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
- __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
-} WWDG_TypeDef;
-
-
-/**
- * @}
- */
-
-/** @addtogroup Peripheral_memory_map
- * @{
- */
-
-#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
-#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
-#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
-
-/*!< Peripheral memory map */
-#define APBPERIPH_BASE PERIPH_BASE
-#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000)
-#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000)
-
-#define TIM2_BASE (APBPERIPH_BASE + 0x00000000)
-#define TIM3_BASE (APBPERIPH_BASE + 0x00000400)
-#define TIM6_BASE (APBPERIPH_BASE + 0x00001000)
-#define TIM7_BASE (APBPERIPH_BASE + 0x00001400)
-#define TIM14_BASE (APBPERIPH_BASE + 0x00002000)
-#define RTC_BASE (APBPERIPH_BASE + 0x00002800)
-#define WWDG_BASE (APBPERIPH_BASE + 0x00002C00)
-#define IWDG_BASE (APBPERIPH_BASE + 0x00003000)
-#define SPI2_BASE (APBPERIPH_BASE + 0x00003800)
-#define USART2_BASE (APBPERIPH_BASE + 0x00004400)
-#define USART3_BASE (APBPERIPH_BASE + 0x00004800)
-#define USART4_BASE (APBPERIPH_BASE + 0x00004C00)
-#define I2C1_BASE (APBPERIPH_BASE + 0x00005400)
-#define I2C2_BASE (APBPERIPH_BASE + 0x00005800)
-#define CAN_BASE (APBPERIPH_BASE + 0x00006400)
-#define CRS_BASE (APBPERIPH_BASE + 0x00006C00)
-#define PWR_BASE (APBPERIPH_BASE + 0x00007000)
-#define DAC_BASE (APBPERIPH_BASE + 0x00007400)
-#define CEC_BASE (APBPERIPH_BASE + 0x00007800)
-
-#define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000)
-#define COMP_BASE (APBPERIPH_BASE + 0x0001001C)
-#define EXTI_BASE (APBPERIPH_BASE + 0x00010400)
-#define ADC1_BASE (APBPERIPH_BASE + 0x00012400)
-#define ADC_BASE (APBPERIPH_BASE + 0x00012708)
-#define TIM1_BASE (APBPERIPH_BASE + 0x00012C00)
-#define SPI1_BASE (APBPERIPH_BASE + 0x00013000)
-#define USART1_BASE (APBPERIPH_BASE + 0x00013800)
-#define TIM15_BASE (APBPERIPH_BASE + 0x00014000)
-#define TIM16_BASE (APBPERIPH_BASE + 0x00014400)
-#define TIM17_BASE (APBPERIPH_BASE + 0x00014800)
-#define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800)
-
-#define DMA1_BASE (AHBPERIPH_BASE + 0x00000000)
-#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008)
-#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001C)
-#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030)
-#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044)
-#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058)
-#define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006C)
-#define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080)
-
-#define RCC_BASE (AHBPERIPH_BASE + 0x00001000)
-#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000) /*!< FLASH registers base address */
-#define OB_BASE ((uint32_t)0x1FFFF800) /*!< FLASH Option Bytes base address */
-#define CRC_BASE (AHBPERIPH_BASE + 0x00003000)
-#define TSC_BASE (AHBPERIPH_BASE + 0x00004000)
-
-#define GPIOA_BASE (AHB2PERIPH_BASE + 0x00000000)
-#define GPIOB_BASE (AHB2PERIPH_BASE + 0x00000400)
-#define GPIOC_BASE (AHB2PERIPH_BASE + 0x00000800)
-#define GPIOD_BASE (AHB2PERIPH_BASE + 0x00000C00)
-#define GPIOE_BASE (AHB2PERIPH_BASE + 0x00001000)
-#define GPIOF_BASE (AHB2PERIPH_BASE + 0x00001400)
-
-/**
- * @}
- */
-
-/** @addtogroup Peripheral_declaration
- * @{
- */
-
-#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
-#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
-#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
-#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
-#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
-#define RTC ((RTC_TypeDef *) RTC_BASE)
-#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
-#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
-#define USART2 ((USART_TypeDef *) USART2_BASE)
-#define USART3 ((USART_TypeDef *) USART3_BASE)
-#define USART4 ((USART_TypeDef *) USART4_BASE)
-#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
-#define CAN ((CAN_TypeDef *) CAN_BASE)
-#define CRS ((CRS_TypeDef *) CRS_BASE)
-#define PWR ((PWR_TypeDef *) PWR_BASE)
-#define DAC ((DAC_TypeDef *) DAC_BASE)
-#define CEC ((CEC_TypeDef *) CEC_BASE)
-
-#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
-#define COMP ((COMP_TypeDef *) COMP_BASE)
-#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
-#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
-#define ADC ((ADC_Common_TypeDef *) ADC_BASE)
-#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
-#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
-#define USART1 ((USART_TypeDef *) USART1_BASE)
-#define TIM15 ((TIM_TypeDef *) TIM15_BASE)
-#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
-#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
-#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
-
-#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
-#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
-#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
-#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
-#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
-#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
-#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
-#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
-#define OB ((OB_TypeDef *) OB_BASE)
-#define RCC ((RCC_TypeDef *) RCC_BASE)
-#define CRC ((CRC_TypeDef *) CRC_BASE)
-#define TSC ((TSC_TypeDef *) TSC_BASE)
-
-#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
-#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
-#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
-
-/**
- * @}
- */
-
-/** @addtogroup Exported_constants
- * @{
- */
-
- /** @addtogroup Peripheral_Registers_Bits_Definition
- * @{
- */
-
-/******************************************************************************/
-/* Peripheral Registers Bits Definition */
-/******************************************************************************/
-/******************************************************************************/
-/* */
-/* Analog to Digital Converter (ADC) */
-/* */
-/******************************************************************************/
-/******************** Bits definition for ADC_ISR register ******************/
-#define ADC_ISR_AWD ((uint32_t)0x00000080) /*!< Analog watchdog flag */
-#define ADC_ISR_OVR ((uint32_t)0x00000010) /*!< Overrun flag */
-#define ADC_ISR_EOSEQ ((uint32_t)0x00000008) /*!< End of Sequence flag */
-#define ADC_ISR_EOC ((uint32_t)0x00000004) /*!< End of Conversion */
-#define ADC_ISR_EOSMP ((uint32_t)0x00000002) /*!< End of sampling flag */
-#define ADC_ISR_ADRDY ((uint32_t)0x00000001) /*!< ADC Ready */
-
-/* Old EOSEQ bit definition, maintained for legacy purpose */
-#define ADC_ISR_EOS ADC_ISR_EOSEQ
-
-/******************** Bits definition for ADC_IER register ******************/
-#define ADC_IER_AWDIE ((uint32_t)0x00000080) /*!< Analog Watchdog interrupt enable */
-#define ADC_IER_OVRIE ((uint32_t)0x00000010) /*!< Overrun interrupt enable */
-#define ADC_IER_EOSEQIE ((uint32_t)0x00000008) /*!< End of Sequence of conversion interrupt enable */
-#define ADC_IER_EOCIE ((uint32_t)0x00000004) /*!< End of Conversion interrupt enable */
-#define ADC_IER_EOSMPIE ((uint32_t)0x00000002) /*!< End of sampling interrupt enable */
-#define ADC_IER_ADRDYIE ((uint32_t)0x00000001) /*!< ADC Ready interrupt enable */
-
-/* Old EOSEQIE bit definition, maintained for legacy purpose */
-#define ADC_IER_EOSIE ADC_IER_EOSEQIE
-
-/******************** Bits definition for ADC_CR register *******************/
-#define ADC_CR_ADCAL ((uint32_t)0x80000000) /*!< ADC calibration */
-#define ADC_CR_ADSTP ((uint32_t)0x00000010) /*!< ADC stop of conversion command */
-#define ADC_CR_ADSTART ((uint32_t)0x00000004) /*!< ADC start of conversion */
-#define ADC_CR_ADDIS ((uint32_t)0x00000002) /*!< ADC disable command */
-#define ADC_CR_ADEN ((uint32_t)0x00000001) /*!< ADC enable control */
-
-/******************* Bits definition for ADC_CFGR1 register *****************/
-#define ADC_CFGR1_AWDCH ((uint32_t)0x7C000000) /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
-#define ADC_CFGR1_AWDCH_0 ((uint32_t)0x04000000) /*!< Bit 0 */
-#define ADC_CFGR1_AWDCH_1 ((uint32_t)0x08000000) /*!< Bit 1 */
-#define ADC_CFGR1_AWDCH_2 ((uint32_t)0x10000000) /*!< Bit 2 */
-#define ADC_CFGR1_AWDCH_3 ((uint32_t)0x20000000) /*!< Bit 3 */
-#define ADC_CFGR1_AWDCH_4 ((uint32_t)0x40000000) /*!< Bit 4 */
-#define ADC_CFGR1_AWDEN ((uint32_t)0x00800000) /*!< Analog watchdog enable on regular channels */
-#define ADC_CFGR1_AWDSGL ((uint32_t)0x00400000) /*!< Enable the watchdog on a single channel or on all channels */
-#define ADC_CFGR1_DISCEN ((uint32_t)0x00010000) /*!< Discontinuous mode on regular channels */
-#define ADC_CFGR1_AUTOFF ((uint32_t)0x00008000) /*!< ADC auto power off */
-#define ADC_CFGR1_WAIT ((uint32_t)0x00004000) /*!< ADC wait conversion mode */
-#define ADC_CFGR1_CONT ((uint32_t)0x00002000) /*!< Continuous Conversion */
-#define ADC_CFGR1_OVRMOD ((uint32_t)0x00001000) /*!< Overrun mode */
-#define ADC_CFGR1_EXTEN ((uint32_t)0x00000C00) /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
-#define ADC_CFGR1_EXTEN_0 ((uint32_t)0x00000400) /*!< Bit 0 */
-#define ADC_CFGR1_EXTEN_1 ((uint32_t)0x00000800) /*!< Bit 1 */
-#define ADC_CFGR1_EXTSEL ((uint32_t)0x000001C0) /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
-#define ADC_CFGR1_EXTSEL_0 ((uint32_t)0x00000040) /*!< Bit 0 */
-#define ADC_CFGR1_EXTSEL_1 ((uint32_t)0x00000080) /*!< Bit 1 */
-#define ADC_CFGR1_EXTSEL_2 ((uint32_t)0x00000100) /*!< Bit 2 */
-#define ADC_CFGR1_ALIGN ((uint32_t)0x00000020) /*!< Data Alignment */
-#define ADC_CFGR1_RES ((uint32_t)0x00000018) /*!< RES[1:0] bits (Resolution) */
-#define ADC_CFGR1_RES_0 ((uint32_t)0x00000008) /*!< Bit 0 */
-#define ADC_CFGR1_RES_1 ((uint32_t)0x00000010) /*!< Bit 1 */
-#define ADC_CFGR1_SCANDIR ((uint32_t)0x00000004) /*!< Sequence scan direction */
-#define ADC_CFGR1_DMACFG ((uint32_t)0x00000002) /*!< Direct memory access configuration */
-#define ADC_CFGR1_DMAEN ((uint32_t)0x00000001) /*!< Direct memory access enable */
-
-/* Old WAIT bit definition, maintained for legacy purpose */
-#define ADC_CFGR1_AUTDLY ADC_CFGR1_WAIT
-
-/******************* Bits definition for ADC_CFGR2 register *****************/
-#define ADC_CFGR2_CKMODE ((uint32_t)0xC0000000) /*!< ADC clock mode */
-#define ADC_CFGR2_CKMODE_1 ((uint32_t)0x80000000) /*!< ADC clocked by PCLK div4 */
-#define ADC_CFGR2_CKMODE_0 ((uint32_t)0x40000000) /*!< ADC clocked by PCLK div2 */
-
-/* Old bit definition, maintained for legacy purpose */
-#define ADC_CFGR2_JITOFFDIV4 ADC_CFGR2_CKMODE_1 /*!< ADC clocked by PCLK div4 */
-#define ADC_CFGR2_JITOFFDIV2 ADC_CFGR2_CKMODE_0 /*!< ADC clocked by PCLK div2 */
-
-/****************** Bit definition for ADC_SMPR register ********************/
-#define ADC_SMPR_SMP ((uint32_t)0x00000007) /*!< SMP[2:0] bits (Sampling time selection) */
-#define ADC_SMPR_SMP_0 ((uint32_t)0x00000001) /*!< Bit 0 */
-#define ADC_SMPR_SMP_1 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define ADC_SMPR_SMP_2 ((uint32_t)0x00000004) /*!< Bit 2 */
-
-/* Old bit definition, maintained for legacy purpose */
-#define ADC_SMPR1_SMPR ADC_SMPR_SMP /*!< SMP[2:0] bits (Sampling time selection) */
-#define ADC_SMPR1_SMPR_0 ADC_SMPR_SMP_0 /*!< Bit 0 */
-#define ADC_SMPR1_SMPR_1 ADC_SMPR_SMP_1 /*!< Bit 1 */
-#define ADC_SMPR1_SMPR_2 ADC_SMPR_SMP_2 /*!< Bit 2 */
-
-/******************* Bit definition for ADC_TR register ********************/
-#define ADC_TR_HT ((uint32_t)0x0FFF0000) /*!< Analog watchdog high threshold */
-#define ADC_TR_LT ((uint32_t)0x00000FFF) /*!< Analog watchdog low threshold */
-
-/* Old bit definition, maintained for legacy purpose */
-#define ADC_HTR_HT ADC_TR_HT /*!< Analog watchdog high threshold */
-#define ADC_LTR_LT ADC_TR_LT /*!< Analog watchdog low threshold */
-
-/****************** Bit definition for ADC_CHSELR register ******************/
-#define ADC_CHSELR_CHSEL18 ((uint32_t)0x00040000) /*!< Channel 18 selection */
-#define ADC_CHSELR_CHSEL17 ((uint32_t)0x00020000) /*!< Channel 17 selection */
-#define ADC_CHSELR_CHSEL16 ((uint32_t)0x00010000) /*!< Channel 16 selection */
-#define ADC_CHSELR_CHSEL15 ((uint32_t)0x00008000) /*!< Channel 15 selection */
-#define ADC_CHSELR_CHSEL14 ((uint32_t)0x00004000) /*!< Channel 14 selection */
-#define ADC_CHSELR_CHSEL13 ((uint32_t)0x00002000) /*!< Channel 13 selection */
-#define ADC_CHSELR_CHSEL12 ((uint32_t)0x00001000) /*!< Channel 12 selection */
-#define ADC_CHSELR_CHSEL11 ((uint32_t)0x00000800) /*!< Channel 11 selection */
-#define ADC_CHSELR_CHSEL10 ((uint32_t)0x00000400) /*!< Channel 10 selection */
-#define ADC_CHSELR_CHSEL9 ((uint32_t)0x00000200) /*!< Channel 9 selection */
-#define ADC_CHSELR_CHSEL8 ((uint32_t)0x00000100) /*!< Channel 8 selection */
-#define ADC_CHSELR_CHSEL7 ((uint32_t)0x00000080) /*!< Channel 7 selection */
-#define ADC_CHSELR_CHSEL6 ((uint32_t)0x00000040) /*!< Channel 6 selection */
-#define ADC_CHSELR_CHSEL5 ((uint32_t)0x00000020) /*!< Channel 5 selection */
-#define ADC_CHSELR_CHSEL4 ((uint32_t)0x00000010) /*!< Channel 4 selection */
-#define ADC_CHSELR_CHSEL3 ((uint32_t)0x00000008) /*!< Channel 3 selection */
-#define ADC_CHSELR_CHSEL2 ((uint32_t)0x00000004) /*!< Channel 2 selection */
-#define ADC_CHSELR_CHSEL1 ((uint32_t)0x00000002) /*!< Channel 1 selection */
-#define ADC_CHSELR_CHSEL0 ((uint32_t)0x00000001) /*!< Channel 0 selection */
-
-/******************** Bit definition for ADC_DR register ********************/
-#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!< Regular data */
-
-/******************* Bit definition for ADC_CCR register ********************/
-#define ADC_CCR_VBATEN ((uint32_t)0x01000000) /*!< Voltage battery enable */
-#define ADC_CCR_TSEN ((uint32_t)0x00800000) /*!< Tempurature sensore enable */
-#define ADC_CCR_VREFEN ((uint32_t)0x00400000) /*!< Vrefint enable */
-
-/******************************************************************************/
-/* */
-/* Controller Area Network (CAN ) */
-/* */
-/******************************************************************************/
-/******************* Bit definition for CAN_MCR register ********************/
-#define CAN_MCR_INRQ ((uint16_t)0x0001) /*!<Initialization Request */
-#define CAN_MCR_SLEEP ((uint16_t)0x0002) /*!<Sleep Mode Request */
-#define CAN_MCR_TXFP ((uint16_t)0x0004) /*!<Transmit FIFO Priority */
-#define CAN_MCR_RFLM ((uint16_t)0x0008) /*!<Receive FIFO Locked Mode */
-#define CAN_MCR_NART ((uint16_t)0x0010) /*!<No Automatic Retransmission */
-#define CAN_MCR_AWUM ((uint16_t)0x0020) /*!<Automatic Wakeup Mode */
-#define CAN_MCR_ABOM ((uint16_t)0x0040) /*!<Automatic Bus-Off Management */
-#define CAN_MCR_TTCM ((uint16_t)0x0080) /*!<Time Triggered Communication Mode */
-#define CAN_MCR_RESET ((uint16_t)0x8000) /*!<bxCAN software master reset */
-
-/******************* Bit definition for CAN_MSR register ********************/
-#define CAN_MSR_INAK ((uint16_t)0x0001) /*!<Initialization Acknowledge */
-#define CAN_MSR_SLAK ((uint16_t)0x0002) /*!<Sleep Acknowledge */
-#define CAN_MSR_ERRI ((uint16_t)0x0004) /*!<Error Interrupt */
-#define CAN_MSR_WKUI ((uint16_t)0x0008) /*!<Wakeup Interrupt */
-#define CAN_MSR_SLAKI ((uint16_t)0x0010) /*!<Sleep Acknowledge Interrupt */
-#define CAN_MSR_TXM ((uint16_t)0x0100) /*!<Transmit Mode */
-#define CAN_MSR_RXM ((uint16_t)0x0200) /*!<Receive Mode */
-#define CAN_MSR_SAMP ((uint16_t)0x0400) /*!<Last Sample Point */
-#define CAN_MSR_RX ((uint16_t)0x0800) /*!<CAN Rx Signal */
-
-/******************* Bit definition for CAN_TSR register ********************/
-#define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!<Request Completed Mailbox0 */
-#define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!<Transmission OK of Mailbox0 */
-#define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!<Arbitration Lost for Mailbox0 */
-#define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!<Transmission Error of Mailbox0 */
-#define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!<Abort Request for Mailbox0 */
-#define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!<Request Completed Mailbox1 */
-#define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!<Transmission OK of Mailbox1 */
-#define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!<Arbitration Lost for Mailbox1 */
-#define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!<Transmission Error of Mailbox1 */
-#define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!<Abort Request for Mailbox 1 */
-#define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!<Request Completed Mailbox2 */
-#define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!<Transmission OK of Mailbox 2 */
-#define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!<Arbitration Lost for mailbox 2 */
-#define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!<Transmission Error of Mailbox 2 */
-#define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!<Abort Request for Mailbox 2 */
-#define CAN_TSR_CODE ((uint32_t)0x03000000) /*!<Mailbox Code */
-
-#define CAN_TSR_TME ((uint32_t)0x1C000000) /*!<TME[2:0] bits */
-#define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!<Transmit Mailbox 0 Empty */
-#define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!<Transmit Mailbox 1 Empty */
-#define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!<Transmit Mailbox 2 Empty */
-
-#define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!<LOW[2:0] bits */
-#define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!<Lowest Priority Flag for Mailbox 0 */
-#define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!<Lowest Priority Flag for Mailbox 1 */
-#define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!<Lowest Priority Flag for Mailbox 2 */
-
-/******************* Bit definition for CAN_RF0R register *******************/
-#define CAN_RF0R_FMP0 ((uint8_t)0x03) /*!<FIFO 0 Message Pending */
-#define CAN_RF0R_FULL0 ((uint8_t)0x08) /*!<FIFO 0 Full */
-#define CAN_RF0R_FOVR0 ((uint8_t)0x10) /*!<FIFO 0 Overrun */
-#define CAN_RF0R_RFOM0 ((uint8_t)0x20) /*!<Release FIFO 0 Output Mailbox */
-
-/******************* Bit definition for CAN_RF1R register *******************/
-#define CAN_RF1R_FMP1 ((uint8_t)0x03) /*!<FIFO 1 Message Pending */
-#define CAN_RF1R_FULL1 ((uint8_t)0x08) /*!<FIFO 1 Full */
-#define CAN_RF1R_FOVR1 ((uint8_t)0x10) /*!<FIFO 1 Overrun */
-#define CAN_RF1R_RFOM1 ((uint8_t)0x20) /*!<Release FIFO 1 Output Mailbox */
-
-/******************** Bit definition for CAN_IER register *******************/
-#define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!<Transmit Mailbox Empty Interrupt Enable */
-#define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!<FIFO Message Pending Interrupt Enable */
-#define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!<FIFO Full Interrupt Enable */
-#define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!<FIFO Overrun Interrupt Enable */
-#define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!<FIFO Message Pending Interrupt Enable */
-#define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!<FIFO Full Interrupt Enable */
-#define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!<FIFO Overrun Interrupt Enable */
-#define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error Warning Interrupt Enable */
-#define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error Passive Interrupt Enable */
-#define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-Off Interrupt Enable */
-#define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last Error Code Interrupt Enable */
-#define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error Interrupt Enable */
-#define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!<Wakeup Interrupt Enable */
-#define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!<Sleep Interrupt Enable */
-
-/******************** Bit definition for CAN_ESR register *******************/
-#define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!<Error Warning Flag */
-#define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!<Error Passive Flag */
-#define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!<Bus-Off Flag */
-
-#define CAN_ESR_LEC ((uint32_t)0x00000070) /*!<LEC[2:0] bits (Last Error Code) */
-#define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!<Bit 0 */
-#define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!<Bit 1 */
-#define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!<Bit 2 */
-
-#define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!<Least significant byte of the 9-bit Transmit Error Counter */
-#define CAN_ESR_REC ((uint32_t)0xFF000000) /*!<Receive Error Counter */
-
-/******************* Bit definition for CAN_BTR register ********************/
-#define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!<Baud Rate Prescaler */
-#define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!<Time Segment 1 */
-#define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!<Time Segment 2 */
-#define CAN_BTR_SJW ((uint32_t)0x03000000) /*!<Resynchronization Jump Width */
-#define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!<Loop Back Mode (Debug) */
-#define CAN_BTR_SILM ((uint32_t)0x80000000) /*!<Silent Mode */
-
-/*!<Mailbox registers */
-/****************** Bit definition for CAN_TI0R register ********************/
-#define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
-#define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
-#define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
-#define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
-#define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
-
-/****************** Bit definition for CAN_TDT0R register *******************/
-#define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
-#define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
-#define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
-
-/****************** Bit definition for CAN_TDL0R register *******************/
-#define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
-#define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
-#define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
-#define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
-
-/****************** Bit definition for CAN_TDH0R register *******************/
-#define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
-#define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
-#define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
-#define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
-
-/******************* Bit definition for CAN_TI1R register *******************/
-#define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
-#define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
-#define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
-#define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
-#define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
-
-/******************* Bit definition for CAN_TDT1R register ******************/
-#define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
-#define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
-#define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
-
-/******************* Bit definition for CAN_TDL1R register ******************/
-#define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
-#define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
-#define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
-#define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
-
-/******************* Bit definition for CAN_TDH1R register ******************/
-#define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
-#define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
-#define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
-#define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
-
-/******************* Bit definition for CAN_TI2R register *******************/
-#define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
-#define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
-#define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
-#define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
-#define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
-
-/******************* Bit definition for CAN_TDT2R register ******************/
-#define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
-#define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
-#define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
-
-/******************* Bit definition for CAN_TDL2R register ******************/
-#define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
-#define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
-#define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
-#define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
-
-/******************* Bit definition for CAN_TDH2R register ******************/
-#define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
-#define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
-#define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
-#define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
-
-/******************* Bit definition for CAN_RI0R register *******************/
-#define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
-#define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
-#define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
-#define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
-
-/******************* Bit definition for CAN_RDT0R register ******************/
-#define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
-#define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
-#define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
-
-/******************* Bit definition for CAN_RDL0R register ******************/
-#define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
-#define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
-#define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
-#define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
-
-/******************* Bit definition for CAN_RDH0R register ******************/
-#define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
-#define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
-#define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
-#define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
-
-/******************* Bit definition for CAN_RI1R register *******************/
-#define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
-#define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
-#define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
-#define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
-
-/******************* Bit definition for CAN_RDT1R register ******************/
-#define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
-#define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
-#define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
-
-/******************* Bit definition for CAN_RDL1R register ******************/
-#define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
-#define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
-#define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
-#define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
-
-/******************* Bit definition for CAN_RDH1R register ******************/
-#define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
-#define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
-#define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
-#define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
-
-/*!<CAN filter registers */
-/******************* Bit definition for CAN_FMR register ********************/
-#define CAN_FMR_FINIT ((uint8_t)0x01) /*!<Filter Init Mode */
-
-/******************* Bit definition for CAN_FM1R register *******************/
-#define CAN_FM1R_FBM ((uint16_t)0x3FFF) /*!<Filter Mode */
-#define CAN_FM1R_FBM0 ((uint16_t)0x0001) /*!<Filter Init Mode bit 0 */
-#define CAN_FM1R_FBM1 ((uint16_t)0x0002) /*!<Filter Init Mode bit 1 */
-#define CAN_FM1R_FBM2 ((uint16_t)0x0004) /*!<Filter Init Mode bit 2 */
-#define CAN_FM1R_FBM3 ((uint16_t)0x0008) /*!<Filter Init Mode bit 3 */
-#define CAN_FM1R_FBM4 ((uint16_t)0x0010) /*!<Filter Init Mode bit 4 */
-#define CAN_FM1R_FBM5 ((uint16_t)0x0020) /*!<Filter Init Mode bit 5 */
-#define CAN_FM1R_FBM6 ((uint16_t)0x0040) /*!<Filter Init Mode bit 6 */
-#define CAN_FM1R_FBM7 ((uint16_t)0x0080) /*!<Filter Init Mode bit 7 */
-#define CAN_FM1R_FBM8 ((uint16_t)0x0100) /*!<Filter Init Mode bit 8 */
-#define CAN_FM1R_FBM9 ((uint16_t)0x0200) /*!<Filter Init Mode bit 9 */
-#define CAN_FM1R_FBM10 ((uint16_t)0x0400) /*!<Filter Init Mode bit 10 */
-#define CAN_FM1R_FBM11 ((uint16_t)0x0800) /*!<Filter Init Mode bit 11 */
-#define CAN_FM1R_FBM12 ((uint16_t)0x1000) /*!<Filter Init Mode bit 12 */
-#define CAN_FM1R_FBM13 ((uint16_t)0x2000) /*!<Filter Init Mode bit 13 */
-
-/******************* Bit definition for CAN_FS1R register *******************/
-#define CAN_FS1R_FSC ((uint16_t)0x3FFF) /*!<Filter Scale Configuration */
-#define CAN_FS1R_FSC0 ((uint16_t)0x0001) /*!<Filter Scale Configuration bit 0 */
-#define CAN_FS1R_FSC1 ((uint16_t)0x0002) /*!<Filter Scale Configuration bit 1 */
-#define CAN_FS1R_FSC2 ((uint16_t)0x0004) /*!<Filter Scale Configuration bit 2 */
-#define CAN_FS1R_FSC3 ((uint16_t)0x0008) /*!<Filter Scale Configuration bit 3 */
-#define CAN_FS1R_FSC4 ((uint16_t)0x0010) /*!<Filter Scale Configuration bit 4 */
-#define CAN_FS1R_FSC5 ((uint16_t)0x0020) /*!<Filter Scale Configuration bit 5 */
-#define CAN_FS1R_FSC6 ((uint16_t)0x0040) /*!<Filter Scale Configuration bit 6 */
-#define CAN_FS1R_FSC7 ((uint16_t)0x0080) /*!<Filter Scale Configuration bit 7 */
-#define CAN_FS1R_FSC8 ((uint16_t)0x0100) /*!<Filter Scale Configuration bit 8 */
-#define CAN_FS1R_FSC9 ((uint16_t)0x0200) /*!<Filter Scale Configuration bit 9 */
-#define CAN_FS1R_FSC10 ((uint16_t)0x0400) /*!<Filter Scale Configuration bit 10 */
-#define CAN_FS1R_FSC11 ((uint16_t)0x0800) /*!<Filter Scale Configuration bit 11 */
-#define CAN_FS1R_FSC12 ((uint16_t)0x1000) /*!<Filter Scale Configuration bit 12 */
-#define CAN_FS1R_FSC13 ((uint16_t)0x2000) /*!<Filter Scale Configuration bit 13 */
-
-/****************** Bit definition for CAN_FFA1R register *******************/
-#define CAN_FFA1R_FFA ((uint16_t)0x3FFF) /*!<Filter FIFO Assignment */
-#define CAN_FFA1R_FFA0 ((uint16_t)0x0001) /*!<Filter FIFO Assignment for Filter 0 */
-#define CAN_FFA1R_FFA1 ((uint16_t)0x0002) /*!<Filter FIFO Assignment for Filter 1 */
-#define CAN_FFA1R_FFA2 ((uint16_t)0x0004) /*!<Filter FIFO Assignment for Filter 2 */
-#define CAN_FFA1R_FFA3 ((uint16_t)0x0008) /*!<Filter FIFO Assignment for Filter 3 */
-#define CAN_FFA1R_FFA4 ((uint16_t)0x0010) /*!<Filter FIFO Assignment for Filter 4 */
-#define CAN_FFA1R_FFA5 ((uint16_t)0x0020) /*!<Filter FIFO Assignment for Filter 5 */
-#define CAN_FFA1R_FFA6 ((uint16_t)0x0040) /*!<Filter FIFO Assignment for Filter 6 */
-#define CAN_FFA1R_FFA7 ((uint16_t)0x0080) /*!<Filter FIFO Assignment for Filter 7 */
-#define CAN_FFA1R_FFA8 ((uint16_t)0x0100) /*!<Filter FIFO Assignment for Filter 8 */
-#define CAN_FFA1R_FFA9 ((uint16_t)0x0200) /*!<Filter FIFO Assignment for Filter 9 */
-#define CAN_FFA1R_FFA10 ((uint16_t)0x0400) /*!<Filter FIFO Assignment for Filter 10 */
-#define CAN_FFA1R_FFA11 ((uint16_t)0x0800) /*!<Filter FIFO Assignment for Filter 11 */
-#define CAN_FFA1R_FFA12 ((uint16_t)0x1000) /*!<Filter FIFO Assignment for Filter 12 */
-#define CAN_FFA1R_FFA13 ((uint16_t)0x2000) /*!<Filter FIFO Assignment for Filter 13 */
-
-/******************* Bit definition for CAN_FA1R register *******************/
-#define CAN_FA1R_FACT ((uint16_t)0x3FFF) /*!<Filter Active */
-#define CAN_FA1R_FACT0 ((uint16_t)0x0001) /*!<Filter 0 Active */
-#define CAN_FA1R_FACT1 ((uint16_t)0x0002) /*!<Filter 1 Active */
-#define CAN_FA1R_FACT2 ((uint16_t)0x0004) /*!<Filter 2 Active */
-#define CAN_FA1R_FACT3 ((uint16_t)0x0008) /*!<Filter 3 Active */
-#define CAN_FA1R_FACT4 ((uint16_t)0x0010) /*!<Filter 4 Active */
-#define CAN_FA1R_FACT5 ((uint16_t)0x0020) /*!<Filter 5 Active */
-#define CAN_FA1R_FACT6 ((uint16_t)0x0040) /*!<Filter 6 Active */
-#define CAN_FA1R_FACT7 ((uint16_t)0x0080) /*!<Filter 7 Active */
-#define CAN_FA1R_FACT8 ((uint16_t)0x0100) /*!<Filter 8 Active */
-#define CAN_FA1R_FACT9 ((uint16_t)0x0200) /*!<Filter 9 Active */
-#define CAN_FA1R_FACT10 ((uint16_t)0x0400) /*!<Filter 10 Active */
-#define CAN_FA1R_FACT11 ((uint16_t)0x0800) /*!<Filter 11 Active */
-#define CAN_FA1R_FACT12 ((uint16_t)0x1000) /*!<Filter 12 Active */
-#define CAN_FA1R_FACT13 ((uint16_t)0x2000) /*!<Filter 13 Active */
-
-/******************* Bit definition for CAN_F0R1 register *******************/
-#define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
-
-/******************* Bit definition for CAN_F1R1 register *******************/
-#define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
-
-/******************* Bit definition for CAN_F2R1 register *******************/
-#define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
-
-/******************* Bit definition for CAN_F3R1 register *******************/
-#define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
-
-/******************* Bit definition for CAN_F4R1 register *******************/
-#define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
-
-/******************* Bit definition for CAN_F5R1 register *******************/
-#define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
-
-/******************* Bit definition for CAN_F6R1 register *******************/
-#define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
-
-/******************* Bit definition for CAN_F7R1 register *******************/
-#define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
-
-/******************* Bit definition for CAN_F8R1 register *******************/
-#define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
-
-/******************* Bit definition for CAN_F9R1 register *******************/
-#define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
-
-/******************* Bit definition for CAN_F10R1 register ******************/
-#define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
-
-/******************* Bit definition for CAN_F11R1 register ******************/
-#define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
-
-/******************* Bit definition for CAN_F12R1 register ******************/
-#define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
-
-/******************* Bit definition for CAN_F13R1 register ******************/
-#define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
-
-/******************* Bit definition for CAN_F0R2 register *******************/
-#define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
-
-/******************* Bit definition for CAN_F1R2 register *******************/
-#define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
-
-/******************* Bit definition for CAN_F2R2 register *******************/
-#define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
-
-/******************* Bit definition for CAN_F3R2 register *******************/
-#define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
-
-/******************* Bit definition for CAN_F4R2 register *******************/
-#define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
-
-/******************* Bit definition for CAN_F5R2 register *******************/
-#define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
-
-/******************* Bit definition for CAN_F6R2 register *******************/
-#define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
-
-/******************* Bit definition for CAN_F7R2 register *******************/
-#define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
-
-/******************* Bit definition for CAN_F8R2 register *******************/
-#define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
-
-/******************* Bit definition for CAN_F9R2 register *******************/
-#define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
-
-/******************* Bit definition for CAN_F10R2 register ******************/
-#define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
-
-/******************* Bit definition for CAN_F11R2 register ******************/
-#define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
-
-/******************* Bit definition for CAN_F12R2 register ******************/
-#define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
-
-/******************* Bit definition for CAN_F13R2 register ******************/
-#define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
-#define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
-#define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
-#define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
-#define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
-#define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
-#define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
-#define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
-#define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
-#define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
-#define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
-#define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
-#define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
-#define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
-#define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
-#define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
-#define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
-#define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
-#define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
-#define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
-#define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
-#define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
-#define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
-#define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
-#define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
-#define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
-#define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
-#define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
-#define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
-#define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
-#define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
-#define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
-
-
-/******************************************************************************/
-/* */
-/* HDMI-CEC (CEC) */
-/* */
-/******************************************************************************/
-
-/******************* Bit definition for CEC_CR register *********************/
-#define CEC_CR_CECEN ((uint32_t)0x00000001) /*!< CEC Enable */
-#define CEC_CR_TXSOM ((uint32_t)0x00000002) /*!< CEC Tx Start Of Message */
-#define CEC_CR_TXEOM ((uint32_t)0x00000004) /*!< CEC Tx End Of Message */
-
-/******************* Bit definition for CEC_CFGR register *******************/
-#define CEC_CFGR_SFT ((uint32_t)0x00000007) /*!< CEC Signal Free Time */
-#define CEC_CFGR_RXTOL ((uint32_t)0x00000008) /*!< CEC Tolerance */
-#define CEC_CFGR_BRESTP ((uint32_t)0x00000010) /*!< CEC Rx Stop */
-#define CEC_CFGR_BREGEN ((uint32_t)0x00000020) /*!< CEC Bit Rising Error generation */
-#define CEC_CFGR_LREGEN ((uint32_t)0x00000040) /*!< CEC Long Period Error generation */
-#define CEC_CFGR_BRDNOGEN ((uint32_t)0x00000080) /*!< CEC Broadcast no Error generation */
-#define CEC_CFGR_SFTOPT ((uint32_t)0x00000100) /*!< CEC Signal Free Time optional */
-#define CEC_CFGR_OAR ((uint32_t)0x7FFF0000) /*!< CEC Own Address */
-#define CEC_CFGR_LSTN ((uint32_t)0x80000000) /*!< CEC Listen mode */
-
-/******************* Bit definition for CEC_TXDR register *******************/
-#define CEC_TXDR_TXD ((uint32_t)0x000000FF) /*!< CEC Tx Data */
-
-/******************* Bit definition for CEC_RXDR register *******************/
-#define CEC_TXDR_RXD ((uint32_t)0x000000FF) /*!< CEC Rx Data */
-
-/******************* Bit definition for CEC_ISR register ********************/
-#define CEC_ISR_RXBR ((uint32_t)0x00000001) /*!< CEC Rx-Byte Received */
-#define CEC_ISR_RXEND ((uint32_t)0x00000002) /*!< CEC End Of Reception */
-#define CEC_ISR_RXOVR ((uint32_t)0x00000004) /*!< CEC Rx-Overrun */
-#define CEC_ISR_BRE ((uint32_t)0x00000008) /*!< CEC Rx Bit Rising Error */
-#define CEC_ISR_SBPE ((uint32_t)0x00000010) /*!< CEC Rx Short Bit period Error */
-#define CEC_ISR_LBPE ((uint32_t)0x00000020) /*!< CEC Rx Long Bit period Error */
-#define CEC_ISR_RXACKE ((uint32_t)0x00000040) /*!< CEC Rx Missing Acknowledge */
-#define CEC_ISR_ARBLST ((uint32_t)0x00000080) /*!< CEC Arbitration Lost */
-#define CEC_ISR_TXBR ((uint32_t)0x00000100) /*!< CEC Tx Byte Request */
-#define CEC_ISR_TXEND ((uint32_t)0x00000200) /*!< CEC End of Transmission */
-#define CEC_ISR_TXUDR ((uint32_t)0x00000400) /*!< CEC Tx-Buffer Underrun */
-#define CEC_ISR_TXERR ((uint32_t)0x00000800) /*!< CEC Tx-Error */
-#define CEC_ISR_TXACKE ((uint32_t)0x00001000) /*!< CEC Tx Missing Acknowledge */
-
-/******************* Bit definition for CEC_IER register ********************/
-#define CEC_IER_RXBRIE ((uint32_t)0x00000001) /*!< CEC Rx-Byte Received IT Enable */
-#define CEC_IER_RXENDIE ((uint32_t)0x00000002) /*!< CEC End Of Reception IT Enable */
-#define CEC_IER_RXOVRIE ((uint32_t)0x00000004) /*!< CEC Rx-Overrun IT Enable */
-#define CEC_IER_BREIEIE ((uint32_t)0x00000008) /*!< CEC Rx Bit Rising Error IT Enable */
-#define CEC_IER_SBPEIE ((uint32_t)0x00000010) /*!< CEC Rx Short Bit period Error IT Enable*/
-#define CEC_IER_LBPEIE ((uint32_t)0x00000020) /*!< CEC Rx Long Bit period Error IT Enable */
-#define CEC_IER_RXACKEIE ((uint32_t)0x00000040) /*!< CEC Rx Missing Acknowledge IT Enable */
-#define CEC_IER_ARBLSTIE ((uint32_t)0x00000080) /*!< CEC Arbitration Lost IT Enable */
-#define CEC_IER_TXBRIE ((uint32_t)0x00000100) /*!< CEC Tx Byte Request IT Enable */
-#define CEC_IER_TXENDIE ((uint32_t)0x00000200) /*!< CEC End of Transmission IT Enable */
-#define CEC_IER_TXUDRIE ((uint32_t)0x00000400) /*!< CEC Tx-Buffer Underrun IT Enable */
-#define CEC_IER_TXERRIE ((uint32_t)0x00000800) /*!< CEC Tx-Error IT Enable */
-#define CEC_IER_TXACKEIE ((uint32_t)0x00001000) /*!< CEC Tx Missing Acknowledge IT Enable */
-
-/******************************************************************************/
-/* */
-/* Analog Comparators (COMP) */
-/* */
-/******************************************************************************/
-/*********************** Bit definition for COMP_CSR register ***************/
-/* COMP1 bits definition */
-#define COMP_CSR_COMP1EN ((uint32_t)0x00000001) /*!< COMP1 enable */
-#define COMP_CSR_COMP1SW1 ((uint32_t)0x00000002) /*!< SW1 switch control */
-#define COMP_CSR_COMP1MODE ((uint32_t)0x0000000C) /*!< COMP1 power mode */
-#define COMP_CSR_COMP1MODE_0 ((uint32_t)0x00000004) /*!< COMP1 power mode bit 0 */
-#define COMP_CSR_COMP1MODE_1 ((uint32_t)0x00000008) /*!< COMP1 power mode bit 1 */
-#define COMP_CSR_COMP1INSEL ((uint32_t)0x00000070) /*!< COMP1 inverting input select */
-#define COMP_CSR_COMP1INSEL_0 ((uint32_t)0x00000010) /*!< COMP1 inverting input select bit 0 */
-#define COMP_CSR_COMP1INSEL_1 ((uint32_t)0x00000020) /*!< COMP1 inverting input select bit 1 */
-#define COMP_CSR_COMP1INSEL_2 ((uint32_t)0x00000040) /*!< COMP1 inverting input select bit 2 */
-#define COMP_CSR_COMP1OUTSEL ((uint32_t)0x00000700) /*!< COMP1 output select */
-#define COMP_CSR_COMP1OUTSEL_0 ((uint32_t)0x00000100) /*!< COMP1 output select bit 0 */
-#define COMP_CSR_COMP1OUTSEL_1 ((uint32_t)0x00000200) /*!< COMP1 output select bit 1 */
-#define COMP_CSR_COMP1OUTSEL_2 ((uint32_t)0x00000400) /*!< COMP1 output select bit 2 */
-#define COMP_CSR_COMP1POL ((uint32_t)0x00000800) /*!< COMP1 output polarity */
-#define COMP_CSR_COMP1HYST ((uint32_t)0x00003000) /*!< COMP1 hysteresis */
-#define COMP_CSR_COMP1HYST_0 ((uint32_t)0x00001000) /*!< COMP1 hysteresis bit 0 */
-#define COMP_CSR_COMP1HYST_1 ((uint32_t)0x00002000) /*!< COMP1 hysteresis bit 1 */
-#define COMP_CSR_COMP1OUT ((uint32_t)0x00004000) /*!< COMP1 output level */
-#define COMP_CSR_COMP1LOCK ((uint32_t)0x00008000) /*!< COMP1 lock */
-/* COMP2 bits definition */
-#define COMP_CSR_COMP2EN ((uint32_t)0x00010000) /*!< COMP2 enable */
-#define COMP_CSR_COMP2MODE ((uint32_t)0x000C0000) /*!< COMP2 power mode */
-#define COMP_CSR_COMP2MODE_0 ((uint32_t)0x00040000) /*!< COMP2 power mode bit 0 */
-#define COMP_CSR_COMP2MODE_1 ((uint32_t)0x00080000) /*!< COMP2 power mode bit 1 */
-#define COMP_CSR_COMP2INSEL ((uint32_t)0x00700000) /*!< COMP2 inverting input select */
-#define COMP_CSR_COMP2INSEL_0 ((uint32_t)0x00100000) /*!< COMP2 inverting input select bit 0 */
-#define COMP_CSR_COMP2INSEL_1 ((uint32_t)0x00200000) /*!< COMP2 inverting input select bit 1 */
-#define COMP_CSR_COMP2INSEL_2 ((uint32_t)0x00400000) /*!< COMP2 inverting input select bit 2 */
-#define COMP_CSR_WNDWEN ((uint32_t)0x00800000) /*!< Comparators window mode enable */
-#define COMP_CSR_COMP2OUTSEL ((uint32_t)0x07000000) /*!< COMP2 output select */
-#define COMP_CSR_COMP2OUTSEL_0 ((uint32_t)0x01000000) /*!< COMP2 output select bit 0 */
-#define COMP_CSR_COMP2OUTSEL_1 ((uint32_t)0x02000000) /*!< COMP2 output select bit 1 */
-#define COMP_CSR_COMP2OUTSEL_2 ((uint32_t)0x04000000) /*!< COMP2 output select bit 2 */
-#define COMP_CSR_COMP2POL ((uint32_t)0x08000000) /*!< COMP2 output polarity */
-#define COMP_CSR_COMP2HYST ((uint32_t)0x30000000) /*!< COMP2 hysteresis */
-#define COMP_CSR_COMP2HYST_0 ((uint32_t)0x10000000) /*!< COMP2 hysteresis bit 0 */
-#define COMP_CSR_COMP2HYST_1 ((uint32_t)0x20000000) /*!< COMP2 hysteresis bit 1 */
-#define COMP_CSR_COMP2OUT ((uint32_t)0x40000000) /*!< COMP2 output level */
-#define COMP_CSR_COMP2LOCK ((uint32_t)0x80000000) /*!< COMP2 lock */
-
-/******************************************************************************/
-/* */
-/* CRC calculation unit (CRC) */
-/* */
-/******************************************************************************/
-/******************* Bit definition for CRC_DR register *********************/
-#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
-
-/******************* Bit definition for CRC_IDR register ********************/
-#define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */
-
-/******************** Bit definition for CRC_CR register ********************/
-#define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */
-#define CRC_CR_POLSIZE ((uint32_t)0x00000018) /*!< Polynomial size bits (only for STM32F072 devices)*/
-#define CRC_CR_POLSIZE_0 ((uint32_t)0x00000008) /*!< Polynomial size bit 0 (only for STM32F072 devices) */
-#define CRC_CR_POLSIZE_1 ((uint32_t)0x00000010) /*!< Polynomial size bit 1 (only for STM32F072 devices) */
-#define CRC_CR_REV_IN ((uint32_t)0x00000060) /*!< REV_IN Reverse Input Data bits */
-#define CRC_CR_REV_IN_0 ((uint32_t)0x00000020) /*!< REV_IN Bit 0 */
-#define CRC_CR_REV_IN_1 ((uint32_t)0x00000040) /*!< REV_IN Bit 1 */
-#define CRC_CR_REV_OUT ((uint32_t)0x00000080) /*!< REV_OUT Reverse Output Data bits */
-
-/******************* Bit definition for CRC_INIT register *******************/
-#define CRC_INIT_INIT ((uint32_t)0xFFFFFFFF) /*!< Initial CRC value bits */
-
-/******************* Bit definition for CRC_POL register ********************/
-#define CRC_POL_POL ((uint32_t)0xFFFFFFFF) /*!< Coefficients of the polynomial (only for STM32F072 devices) */
-
-/******************************************************************************/
-/* */
-/* CRS Clock Recovery System */
-/* (Available only for STM32F072 devices) */
-/******************************************************************************/
-
-/******************* Bit definition for CRS_CR register *********************/
-#define CRS_CR_SYNCOKIE ((uint32_t)0x00000001) /* SYNC event OK interrupt enable */
-#define CRS_CR_SYNCWARNIE ((uint32_t)0x00000002) /* SYNC warning interrupt enable */
-#define CRS_CR_ERRIE ((uint32_t)0x00000004) /* SYNC error interrupt enable */
-#define CRS_CR_ESYNCIE ((uint32_t)0x00000008) /* Expected SYNC(ESYNCF) interrupt Enable*/
-#define CRS_CR_CEN ((uint32_t)0x00000020) /* Frequency error counter enable */
-#define CRS_CR_AUTOTRIMEN ((uint32_t)0x00000040) /* Automatic trimming enable */
-#define CRS_CR_SWSYNC ((uint32_t)0x00000080) /* A Software SYNC event is generated */
-#define CRS_CR_TRIM ((uint32_t)0x00003F00) /* HSI48 oscillator smooth trimming */
-
-/******************* Bit definition for CRS_CFGR register *********************/
-#define CRS_CFGR_RELOAD ((uint32_t)0x0000FFFF) /* Counter reload value */
-#define CRS_CFGR_FELIM ((uint32_t)0x00FF0000) /* Frequency error limit */
-#define CRS_CFGR_SYNCDIV ((uint32_t)0x07000000) /* SYNC divider */
-#define CRS_CFGR_SYNCDIV_0 ((uint32_t)0x01000000) /* Bit 0 */
-#define CRS_CFGR_SYNCDIV_1 ((uint32_t)0x02000000) /* Bit 1 */
-#define CRS_CFGR_SYNCDIV_2 ((uint32_t)0x04000000) /* Bit 2 */
-#define CRS_CFGR_SYNCSRC ((uint32_t)0x30000000) /* SYNC signal source selection */
-#define CRS_CFGR_SYNCSRC_0 ((uint32_t)0x10000000) /* Bit 0 */
-#define CRS_CFGR_SYNCSRC_1 ((uint32_t)0x20000000) /* Bit 1 */
-#define CRS_CFGR_SYNCPOL ((uint32_t)0x80000000) /* SYNC polarity selection */
-
-/******************* Bit definition for CRS_ISR register *********************/
-#define CRS_ISR_SYNCOKF ((uint32_t)0x00000001) /* SYNC event OK flag */
-#define CRS_ISR_SYNCWARNF ((uint32_t)0x00000002) /* SYNC warning */
-#define CRS_ISR_ERRF ((uint32_t)0x00000004) /* SYNC error flag */
-#define CRS_ISR_ESYNCF ((uint32_t)0x00000008) /* Expected SYNC flag */
-#define CRS_ISR_SYNCERR ((uint32_t)0x00000100) /* SYNC error */
-#define CRS_ISR_SYNCMISS ((uint32_t)0x00000200) /* SYNC missed */
-#define CRS_ISR_TRIMOVF ((uint32_t)0x00000400) /* Trimming overflow or underflow */
-#define CRS_ISR_FEDIR ((uint32_t)0x00008000) /* Frequency error direction */
-#define CRS_ISR_FECAP ((uint32_t)0xFFFF0000) /* Frequency error capture */
-
-/******************* Bit definition for CRS_ICR register *********************/
-#define CRS_ICR_SYNCOKC ((uint32_t)0x00000001) /* SYNC event OK clear flag */
-#define CRS_ICR_SYNCWARNC ((uint32_t)0x00000002) /* SYNC warning clear flag */
-#define CRS_ICR_ERRC ((uint32_t)0x00000004) /* Error clear flag */
-#define CRS_ICR_ESYNCC ((uint32_t)0x00000008) /* Expected SYNC clear flag */
-
-/******************************************************************************/
-/* */
-/* Digital to Analog Converter (DAC) */
-/* */
-/******************************************************************************/
-/******************** Bit definition for DAC_CR register ********************/
-#define DAC_CR_EN1 ((uint32_t)0x00000001) /*!< DAC channel1 enable */
-#define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!< DAC channel1 output buffer disable */
-#define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!< DAC channel1 Trigger enable */
-
-#define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
-#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!< Bit 0 */
-#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!< Bit 1 */
-#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!< Bit 2 */
-
-#define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable)(only for STM32F072 devices) */
-#define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!< Bit 0 */
-#define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!< Bit 1 */
-
-#define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) (only for STM32F072 devices) */
-#define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!< Bit 0 */
-#define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!< Bit 1 */
-#define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!< Bit 2 */
-#define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!< Bit 3 */
-
-#define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!< DAC channel1 DMA enable */
-#define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000) /*!<DAC channel1 DMA Underrun Interrupt enable */
-#define DAC_CR_EN2 ((uint32_t)0x00010000) /*!< DAC channel2 enable */
-#define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!< DAC channel2 output buffer disable */
-#define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!< DAC channel2 Trigger enable */
-
-#define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */
-#define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!< Bit 0 */
-#define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!< Bit 1 */
-#define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!< Bit 2 */
-
-#define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
-#define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!< Bit 0 */
-#define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!< Bit 1 */
-
-#define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
-#define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!< Bit 0 */
-#define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!< Bit 1 */
-#define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!< Bit 2 */
-#define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!< Bit 3 */
-
-#define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!< DAC channel2 DMA enabled */
-#define DAC_CR_DMAUDRIE2 ((uint32_t)0x20000000) /*!<DAC channel2 DMA Underrun Interrupt enable */
-
-/***************** Bit definition for DAC_SWTRIGR register ******************/
-#define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x00000001) /*!<DAC channel1 software trigger */
-#define DAC_SWTRIGR_SWTRIG2 ((uint32_t)0x00000002) /*!<DAC channel2 software trigger */
-
-/***************** Bit definition for DAC_DHR12R1 register ******************/
-#define DAC_DHR12R1_DACC1DHR ((uint32_t)0x00000FFF) /*!<DAC channel1 12-bit Right aligned data */
-
-/***************** Bit definition for DAC_DHR12L1 register ******************/
-#define DAC_DHR12L1_DACC1DHR ((uint32_t)0x0000FFF0) /*!<DAC channel1 12-bit Left aligned data */
-
-/****************** Bit definition for DAC_DHR8R1 register ******************/
-#define DAC_DHR8R1_DACC1DHR ((uint32_t)0x000000FF) /*!<DAC channel1 8-bit Right aligned data */
-
-/******************* Bit definition for DAC_DOR1 register *******************/
-#define DAC_DOR1_DACC1DOR ((uint32_t)0x00000FFF) /*!<DAC channel1 data output */
-
-/******************** Bit definition for DAC_SR register ********************/
-#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun flag */
-#define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!< DAC channel2 DMA underrun flag (only for STM32F072 and STM32F042 devices) */
-
-/******************************************************************************/
-/* */
-/* Debug MCU (DBGMCU) */
-/* */
-/******************************************************************************/
-
-/**************** Bit definition for DBGMCU_IDCODE register *****************/
-#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) /*!< Device Identifier */
-
-#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) /*!< REV_ID[15:0] bits (Revision Identifier) */
-#define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) /*!< Bit 0 */
-#define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) /*!< Bit 1 */
-#define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) /*!< Bit 2 */
-#define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) /*!< Bit 3 */
-#define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) /*!< Bit 4 */
-#define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) /*!< Bit 5 */
-#define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) /*!< Bit 6 */
-#define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) /*!< Bit 7 */
-#define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) /*!< Bit 8 */
-#define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) /*!< Bit 9 */
-#define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) /*!< Bit 10 */
-#define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) /*!< Bit 11 */
-#define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) /*!< Bit 12 */
-#define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) /*!< Bit 13 */
-#define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) /*!< Bit 14 */
-#define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /*!< Bit 15 */
-
-/****************** Bit definition for DBGMCU_CR register *******************/
-#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /*!< Debug Stop Mode */
-#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /*!< Debug Standby mode */
-
-/****************** Bit definition for DBGMCU_APB1_FZ register **************/
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001) /*!< TIM2 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002) /*!< TIM3 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010) /*!< TIM6 counter stopped when core is halted (not available on STM32F042 devices)*/
-#define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020) /*!< TIM7 counter stopped when core is halted (only for STM32F072 devices) */
-#define DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100) /*!< TIM14 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400) /*!< RTC Calendar frozen when core is halted */
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800) /*!< Debug Window Watchdog stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000) /*!< Debug Independent Watchdog stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000) /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_CAN_STOP ((uint32_t)0x02000000) /*!< CAN debug stopped when Core is halted (only for STM32F072 devices) */
-
-/****************** Bit definition for DBGMCU_APB2_FZ register **************/
-#define DBGMCU_APB2_FZ_DBG_TIM1_STOP ((uint32_t)0x00000800) /*!< TIM1 counter stopped when core is halted */
-#define DBGMCU_APB2_FZ_DBG_TIM15_STOP ((uint32_t)0x00010000) /*!< TIM15 counter stopped when core is halted (not available on STM32F042 devices) */
-#define DBGMCU_APB2_FZ_DBG_TIM16_STOP ((uint32_t)0x00020000) /*!< TIM16 counter stopped when core is halted */
-#define DBGMCU_APB2_FZ_DBG_TIM17_STOP ((uint32_t)0x00040000) /*!< TIM17 counter stopped when core is halted */
-
-/******************************************************************************/
-/* */
-/* DMA Controller (DMA) */
-/* */
-/******************************************************************************/
-
-/******************* Bit definition for DMA_ISR register ********************/
-#define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */
-#define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */
-#define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */
-#define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */
-#define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */
-#define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */
-#define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */
-#define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */
-#define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */
-#define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */
-#define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */
-#define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */
-#define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */
-#define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */
-#define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */
-#define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */
-#define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */
-#define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */
-#define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */
-#define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */
-#define DMA_ISR_GIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag (only for STM32F072 devices) */
-#define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag (only for STM32F072 devices) */
-#define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag (only for STM32F072 devices) */
-#define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag (only for STM32F072 devices) */
-#define DMA_ISR_GIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag (only for STM32F072 devices) */
-#define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag (only for STM32F072 devices) */
-#define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag (only for STM32F072 devices) */
-#define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag (only for STM32F072 devices) */
-
-/******************* Bit definition for DMA_IFCR register *******************/
-#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clear */
-#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */
-#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */
-#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */
-#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */
-#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */
-#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */
-#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */
-#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */
-#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */
-#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */
-#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */
-#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */
-#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */
-#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */
-#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */
-#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */
-#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */
-#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */
-#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */
-#define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear (only for STM32F072 devices) */
-#define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear (only for STM32F072 devices) */
-#define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear (only for STM32F072 devices) */
-#define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear (only for STM32F072 devices) */
-#define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear (only for STM32F072 devices) */
-#define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear (only for STM32F072 devices) */
-#define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear (only for STM32F072 devices) */
-#define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear (only for STM32F072 devices) */
-
-/******************* Bit definition for DMA_CCR register ********************/
-#define DMA_CCR_EN ((uint32_t)0x00000001) /*!< Channel enable */
-#define DMA_CCR_TCIE ((uint32_t)0x00000002) /*!< Transfer complete interrupt enable */
-#define DMA_CCR_HTIE ((uint32_t)0x00000004) /*!< Half Transfer interrupt enable */
-#define DMA_CCR_TEIE ((uint32_t)0x00000008) /*!< Transfer error interrupt enable */
-#define DMA_CCR_DIR ((uint32_t)0x00000010) /*!< Data transfer direction */
-#define DMA_CCR_CIRC ((uint32_t)0x00000020) /*!< Circular mode */
-#define DMA_CCR_PINC ((uint32_t)0x00000040) /*!< Peripheral increment mode */
-#define DMA_CCR_MINC ((uint32_t)0x00000080) /*!< Memory increment mode */
-
-#define DMA_CCR_PSIZE ((uint32_t)0x00000300) /*!< PSIZE[1:0] bits (Peripheral size) */
-#define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100) /*!< Bit 0 */
-#define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200) /*!< Bit 1 */
-
-#define DMA_CCR_MSIZE ((uint32_t)0x00000C00) /*!< MSIZE[1:0] bits (Memory size) */
-#define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400) /*!< Bit 0 */
-#define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800) /*!< Bit 1 */
-
-#define DMA_CCR_PL ((uint32_t)0x00003000) /*!< PL[1:0] bits(Channel Priority level)*/
-#define DMA_CCR_PL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
-#define DMA_CCR_PL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
-
-#define DMA_CCR_MEM2MEM ((uint32_t)0x00004000) /*!< Memory to memory mode */
-
-/****************** Bit definition for DMA_CNDTR register *******************/
-#define DMA_CNDTR_NDT ((uint32_t)0x0000FFFF) /*!< Number of data to Transfer */
-
-/****************** Bit definition for DMA_CPAR register ********************/
-#define DMA_CPAR_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
-
-/****************** Bit definition for DMA_CMAR register ********************/
-#define DMA_CMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
-
-/******************************************************************************/
-/* */
-/* External Interrupt/Event Controller (EXTI) */
-/* */
-/******************************************************************************/
-/******************* Bit definition for EXTI_IMR register *******************/
-#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
-#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
-#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
-#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
-#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
-#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
-#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
-#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
-#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
-#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
-#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
-#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
-#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
-#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
-#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
-#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
-#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
-#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
-#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
-#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
-#define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
-#define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
-#define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
-#define EXTI_IMR_MR23 ((uint32_t)0x00800000) /*!< Interrupt Mask on line 23 */
-#define EXTI_IMR_MR24 ((uint32_t)0x01000000) /*!< Interrupt Mask on line 24 */
-#define EXTI_IMR_MR25 ((uint32_t)0x02000000) /*!< Interrupt Mask on line 25 */
-#define EXTI_IMR_MR26 ((uint32_t)0x04000000) /*!< Interrupt Mask on line 26 */
-#define EXTI_IMR_MR27 ((uint32_t)0x08000000) /*!< Interrupt Mask on line 27 */
-#define EXTI_IMR_MR28 ((uint32_t)0x10000000) /*!< Interrupt Mask on line 28 */
-#define EXTI_IMR_MR29 ((uint32_t)0x20000000) /*!< Interrupt Mask on line 29 */
-#define EXTI_IMR_MR30 ((uint32_t)0x40000000) /*!< Interrupt Mask on line 30 */
-#define EXTI_IMR_MR31 ((uint32_t)0x80000000) /*!< Interrupt Mask on line 31 */
-
-/****************** Bit definition for EXTI_EMR register ********************/
-#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
-#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
-#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
-#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
-#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
-#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
-#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
-#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
-#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
-#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
-#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
-#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
-#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
-#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
-#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
-#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
-#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
-#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
-#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
-#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
-#define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
-#define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
-#define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
-#define EXTI_EMR_MR23 ((uint32_t)0x00800000) /*!< Event Mask on line 23 */
-#define EXTI_EMR_MR24 ((uint32_t)0x01000000) /*!< Event Mask on line 24 */
-#define EXTI_EMR_MR25 ((uint32_t)0x02000000) /*!< Event Mask on line 25 */
-#define EXTI_EMR_MR26 ((uint32_t)0x04000000) /*!< Event Mask on line 26 */
-#define EXTI_EMR_MR27 ((uint32_t)0x08000000) /*!< Event Mask on line 27 */
-#define EXTI_EMR_MR28 ((uint32_t)0x10000000) /*!< Event Mask on line 28 */
-#define EXTI_EMR_MR29 ((uint32_t)0x20000000) /*!< Event Mask on line 29 */
-#define EXTI_EMR_MR30 ((uint32_t)0x40000000) /*!< Event Mask on line 30 */
-#define EXTI_EMR_MR31 ((uint32_t)0x80000000) /*!< Event Mask on line 31 */
-
-/******************* Bit definition for EXTI_RTSR register ******************/
-#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
-#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
-#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
-#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
-#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
-#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
-#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
-#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
-#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
-#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
-#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
-#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
-#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
-#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
-#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
-#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
-#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
-#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
-#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
-#define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
-#define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
-#define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
-
-/******************* Bit definition for EXTI_FTSR register *******************/
-#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
-#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
-#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
-#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
-#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
-#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
-#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
-#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
-#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
-#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
-#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
-#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
-#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
-#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
-#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
-#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
-#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
-#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
-#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
-#define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
-#define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
-#define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
-
-/******************* Bit definition for EXTI_SWIER register *******************/
-#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
-#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
-#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
-#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
-#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
-#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
-#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
-#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
-#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
-#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
-#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
-#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
-#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
-#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
-#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
-#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
-#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
-#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
-#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
-#define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
-#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
-#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
-
-/****************** Bit definition for EXTI_PR register *********************/
-#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit 0 */
-#define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit 1 */
-#define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit 2 */
-#define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit 3 */
-#define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit 4 */
-#define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit 5 */
-#define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit 6 */
-#define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit 7 */
-#define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit 8 */
-#define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit 9 */
-#define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit 10 */
-#define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit 11 */
-#define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit 12 */
-#define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit 13 */
-#define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit 14 */
-#define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit 15 */
-#define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit 16 */
-#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit 17 */
-#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit 19 */
-#define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit 20 */
-#define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit 21 */
-#define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit 22 */
-
-/******************************************************************************/
-/* */
-/* FLASH and Option Bytes Registers */
-/* */
-/******************************************************************************/
-
-/******************* Bit definition for FLASH_ACR register ******************/
-#define FLASH_ACR_LATENCY ((uint32_t)0x00000001) /*!< LATENCY bit (Latency) */
-
-#define FLASH_ACR_PRFTBE ((uint32_t)0x00000010) /*!< Prefetch Buffer Enable */
-#define FLASH_ACR_PRFTBS ((uint32_t)0x00000020) /*!< Prefetch Buffer Status */
-
-/****************** Bit definition for FLASH_KEYR register ******************/
-#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /*!< FPEC Key */
-
-/***************** Bit definition for FLASH_OPTKEYR register ****************/
-#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option Byte Key */
-
-/****************** FLASH Keys **********************************************/
-#define FLASH_FKEY1 ((uint32_t)0x45670123) /*!< Flash program erase key1 */
-#define FLASH_FKEY2 ((uint32_t)0xCDEF89AB) /*!< Flash program erase key2: used with FLASH_PEKEY1
- to unlock the write access to the FPEC. */
-
-#define FLASH_OPTKEY1 ((uint32_t)0x45670123) /*!< Flash option key1 */
-#define FLASH_OPTKEY2 ((uint32_t)0xCDEF89AB) /*!< Flash option key2: used with FLASH_OPTKEY1 to
- unlock the write access to the option byte block */
-
-/****************** Bit definition for FLASH_SR register *******************/
-#define FLASH_SR_BSY ((uint32_t)0x00000001) /*!< Busy */
-#define FLASH_SR_PGERR ((uint32_t)0x00000004) /*!< Programming Error */
-#define FLASH_SR_WRPRTERR ((uint32_t)0x00000010) /*!< Write Protection Error */
-#define FLASH_SR_EOP ((uint32_t)0x00000020) /*!< End of operation */
-#define FLASH_SR_WRPERR FLASH_SR_WRPRTERR /*!< Legacy of Write Protection Error */
-
-/******************* Bit definition for FLASH_CR register *******************/
-#define FLASH_CR_PG ((uint32_t)0x00000001) /*!< Programming */
-#define FLASH_CR_PER ((uint32_t)0x00000002) /*!< Page Erase */
-#define FLASH_CR_MER ((uint32_t)0x00000004) /*!< Mass Erase */
-#define FLASH_CR_OPTPG ((uint32_t)0x00000010) /*!< Option Byte Programming */
-#define FLASH_CR_OPTER ((uint32_t)0x00000020) /*!< Option Byte Erase */
-#define FLASH_CR_STRT ((uint32_t)0x00000040) /*!< Start */
-#define FLASH_CR_LOCK ((uint32_t)0x00000080) /*!< Lock */
-#define FLASH_CR_OPTWRE ((uint32_t)0x00000200) /*!< Option Bytes Write Enable */
-#define FLASH_CR_ERRIE ((uint32_t)0x00000400) /*!< Error Interrupt Enable */
-#define FLASH_CR_EOPIE ((uint32_t)0x00001000) /*!< End of operation interrupt enable */
-#define FLASH_CR_OBL_LAUNCH ((uint32_t)0x00002000) /*!< Option Bytes Loader Launch */
-
-/******************* Bit definition for FLASH_AR register *******************/
-#define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) /*!< Flash Address */
-
-/****************** Bit definition for FLASH_OBR register *******************/
-#define FLASH_OBR_OPTERR ((uint32_t)0x00000001) /*!< Option Byte Error */
-#define FLASH_OBR_RDPRT1 ((uint32_t)0x00000002) /*!< Read protection Level bit 1 */
-#define FLASH_OBR_RDPRT2 ((uint32_t)0x00000004) /*!< Read protection Level bit 2 */
-
-#define FLASH_OBR_USER ((uint32_t)0x00003700) /*!< User Option Bytes */
-#define FLASH_OBR_IWDG_SW ((uint32_t)0x00000100) /*!< IWDG SW */
-#define FLASH_OBR_nRST_STOP ((uint32_t)0x00000200) /*!< nRST_STOP */
-#define FLASH_OBR_nRST_STDBY ((uint32_t)0x00000400) /*!< nRST_STDBY */
-#define FLASH_OBR_nBOOT0 ((uint32_t)0x00000800) /*!< nBOOT0 */
-#define FLASH_OBR_nBOOT1 ((uint32_t)0x00001000) /*!< nBOOT1 */
-#define FLASH_OBR_VDDA_MONITOR ((uint32_t)0x00002000) /*!< VDDA power supply supervisor */
-#define FLASH_OBR_RAM_PARITY_CHECK ((uint32_t)0x00004000) /*!< RAM Parity Check */
-#define FLASH_OBR_nBOOT0_SW ((uint32_t)0x00008000) /*!< nBOOT0 SW (available only in the STM32F042 devices)*/
-#define FLASH_OBR_DATA0 ((uint32_t)0x00FF0000) /*!< DATA0 */
-#define FLASH_OBR_DATA1 ((uint32_t)0xFF000000) /*!< DATA0 */
-
-/* Old BOOT1 bit definition, maintained for legacy purpose */
-#define FLASH_OBR_BOOT1 FLASH_OBR_nBOOT1
-
-/* Old OBR_VDDA bit definition, maintained for legacy purpose */
-#define FLASH_OBR_VDDA_ANALOG FLASH_OBR_VDDA_MONITOR
-
-/****************** Bit definition for FLASH_WRPR register ******************/
-#define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protect */
-
-/*----------------------------------------------------------------------------*/
-
-/****************** Bit definition for OB_RDP register **********************/
-#define OB_RDP_RDP ((uint32_t)0x000000FF) /*!< Read protection option byte */
-#define OB_RDP_nRDP ((uint32_t)0x0000FF00) /*!< Read protection complemented option byte */
-
-/****************** Bit definition for OB_USER register *********************/
-#define OB_USER_USER ((uint32_t)0x00FF0000) /*!< User option byte */
-#define OB_USER_nUSER ((uint32_t)0xFF000000) /*!< User complemented option byte */
-
-/****************** Bit definition for OB_WRP0 register *********************/
-#define OB_WRP0_WRP0 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */
-#define OB_WRP0_nWRP0 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */
-
-/****************** Bit definition for OB_WRP1 register *********************/
-#define OB_WRP1_WRP1 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
-#define OB_WRP1_nWRP1 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
-
-/****************** Bit definition for OB_WRP2 register *********************/
-#define OB_WRP2_WRP2 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes (only for STM32F072 devices) */
-#define OB_WRP2_nWRP2 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes (only for STM32F072 devices) */
-
-/****************** Bit definition for OB_WRP3 register *********************/
-#define OB_WRP3_WRP3 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes (only for STM32F072 devices) */
-#define OB_WRP3_nWRP3 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes (only for STM32F072 devices) */
-
-/******************************************************************************/
-/* */
-/* General Purpose IOs (GPIO) */
-/* */
-/******************************************************************************/
-/******************* Bit definition for GPIO_MODER register *****************/
-#define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
-#define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
-#define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
-#define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
-#define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
-#define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
-#define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
-#define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
-#define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
-#define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
-#define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
-#define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
-#define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
-#define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
-#define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
-#define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
-#define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
-#define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
-#define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
-#define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
-#define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
-#define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
-#define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
-#define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
-#define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
-#define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
-#define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
-#define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
-#define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
-#define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
-#define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
-#define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
-#define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
-#define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
-#define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
-#define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
-#define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
-#define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
-#define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
-#define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
-#define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
-#define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
-#define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
-#define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
-#define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
-#define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
-#define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
-#define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
-
-/****************** Bit definition for GPIO_OTYPER register *****************/
-#define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
-#define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
-#define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
-#define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
-#define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
-#define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
-#define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
-#define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
-#define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
-#define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
-#define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
-#define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
-#define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
-#define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
-#define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
-#define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
-
-/**************** Bit definition for GPIO_OSPEEDR register ******************/
-#define GPIO_OSPEEDR_OSPEEDR0 ((uint32_t)0x00000003)
-#define GPIO_OSPEEDR_OSPEEDR0_0 ((uint32_t)0x00000001)
-#define GPIO_OSPEEDR_OSPEEDR0_1 ((uint32_t)0x00000002)
-#define GPIO_OSPEEDR_OSPEEDR1 ((uint32_t)0x0000000C)
-#define GPIO_OSPEEDR_OSPEEDR1_0 ((uint32_t)0x00000004)
-#define GPIO_OSPEEDR_OSPEEDR1_1 ((uint32_t)0x00000008)
-#define GPIO_OSPEEDR_OSPEEDR2 ((uint32_t)0x00000030)
-#define GPIO_OSPEEDR_OSPEEDR2_0 ((uint32_t)0x00000010)
-#define GPIO_OSPEEDR_OSPEEDR2_1 ((uint32_t)0x00000020)
-#define GPIO_OSPEEDR_OSPEEDR3 ((uint32_t)0x000000C0)
-#define GPIO_OSPEEDR_OSPEEDR3_0 ((uint32_t)0x00000040)
-#define GPIO_OSPEEDR_OSPEEDR3_1 ((uint32_t)0x00000080)
-#define GPIO_OSPEEDR_OSPEEDR4 ((uint32_t)0x00000300)
-#define GPIO_OSPEEDR_OSPEEDR4_0 ((uint32_t)0x00000100)
-#define GPIO_OSPEEDR_OSPEEDR4_1 ((uint32_t)0x00000200)
-#define GPIO_OSPEEDR_OSPEEDR5 ((uint32_t)0x00000C00)
-#define GPIO_OSPEEDR_OSPEEDR5_0 ((uint32_t)0x00000400)
-#define GPIO_OSPEEDR_OSPEEDR5_1 ((uint32_t)0x00000800)
-#define GPIO_OSPEEDR_OSPEEDR6 ((uint32_t)0x00003000)
-#define GPIO_OSPEEDR_OSPEEDR6_0 ((uint32_t)0x00001000)
-#define GPIO_OSPEEDR_OSPEEDR6_1 ((uint32_t)0x00002000)
-#define GPIO_OSPEEDR_OSPEEDR7 ((uint32_t)0x0000C000)
-#define GPIO_OSPEEDR_OSPEEDR7_0 ((uint32_t)0x00004000)
-#define GPIO_OSPEEDR_OSPEEDR7_1 ((uint32_t)0x00008000)
-#define GPIO_OSPEEDR_OSPEEDR8 ((uint32_t)0x00030000)
-#define GPIO_OSPEEDR_OSPEEDR8_0 ((uint32_t)0x00010000)
-#define GPIO_OSPEEDR_OSPEEDR8_1 ((uint32_t)0x00020000)
-#define GPIO_OSPEEDR_OSPEEDR9 ((uint32_t)0x000C0000)
-#define GPIO_OSPEEDR_OSPEEDR9_0 ((uint32_t)0x00040000)
-#define GPIO_OSPEEDR_OSPEEDR9_1 ((uint32_t)0x00080000)
-#define GPIO_OSPEEDR_OSPEEDR10 ((uint32_t)0x00300000)
-#define GPIO_OSPEEDR_OSPEEDR10_0 ((uint32_t)0x00100000)
-#define GPIO_OSPEEDR_OSPEEDR10_1 ((uint32_t)0x00200000)
-#define GPIO_OSPEEDR_OSPEEDR11 ((uint32_t)0x00C00000)
-#define GPIO_OSPEEDR_OSPEEDR11_0 ((uint32_t)0x00400000)
-#define GPIO_OSPEEDR_OSPEEDR11_1 ((uint32_t)0x00800000)
-#define GPIO_OSPEEDR_OSPEEDR12 ((uint32_t)0x03000000)
-#define GPIO_OSPEEDR_OSPEEDR12_0 ((uint32_t)0x01000000)
-#define GPIO_OSPEEDR_OSPEEDR12_1 ((uint32_t)0x02000000)
-#define GPIO_OSPEEDR_OSPEEDR13 ((uint32_t)0x0C000000)
-#define GPIO_OSPEEDR_OSPEEDR13_0 ((uint32_t)0x04000000)
-#define GPIO_OSPEEDR_OSPEEDR13_1 ((uint32_t)0x08000000)
-#define GPIO_OSPEEDR_OSPEEDR14 ((uint32_t)0x30000000)
-#define GPIO_OSPEEDR_OSPEEDR14_0 ((uint32_t)0x10000000)
-#define GPIO_OSPEEDR_OSPEEDR14_1 ((uint32_t)0x20000000)
-#define GPIO_OSPEEDR_OSPEEDR15 ((uint32_t)0xC0000000)
-#define GPIO_OSPEEDR_OSPEEDR15_0 ((uint32_t)0x40000000)
-#define GPIO_OSPEEDR_OSPEEDR15_1 ((uint32_t)0x80000000)
-
-/* Old Bit definition for GPIO_OSPEEDR register maintained for legacy purpose */
-#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0
-#define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEEDR0_0
-#define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEEDR0_1
-#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEEDR1
-#define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEEDR1_0
-#define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEEDR1_1
-#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEEDR2
-#define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEEDR2_0
-#define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEEDR2_1
-#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEEDR3
-#define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEEDR3_0
-#define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEEDR3_1
-#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEEDR4
-#define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEEDR4_0
-#define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEEDR4_1
-#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEEDR5
-#define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEEDR5_0
-#define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEEDR5_1
-#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEEDR6
-#define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEEDR6_0
-#define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEEDR6_1
-#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEEDR7
-#define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEEDR7_0
-#define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEEDR7_1
-#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEEDR8
-#define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEEDR8_0
-#define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEEDR8_1
-#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEEDR9
-#define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEEDR9_0
-#define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEEDR9_1
-#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEEDR10
-#define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEEDR10_0
-#define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEEDR10_1
-#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEEDR11
-#define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEEDR11_0
-#define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEEDR11_1
-#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEEDR12
-#define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEEDR12_0
-#define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEEDR12_1
-#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEEDR13
-#define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEEDR13_0
-#define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEEDR13_1
-#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEEDR14
-#define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEEDR14_0
-#define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEEDR14_1
-#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEEDR15
-#define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEEDR15_0
-#define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEEDR15_1
-
-/******************* Bit definition for GPIO_PUPDR register ******************/
-#define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
-#define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
-#define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
-#define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
-#define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
-#define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
-#define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
-#define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
-#define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
-#define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
-#define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
-#define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
-#define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
-#define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
-#define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
-#define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
-#define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
-#define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
-#define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
-#define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
-#define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
-#define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
-#define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
-#define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
-#define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
-#define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
-#define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
-#define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
-#define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
-#define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
-#define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
-#define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
-#define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
-#define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
-#define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
-#define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
-#define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
-#define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
-#define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
-#define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
-#define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
-#define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
-#define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
-#define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
-#define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
-#define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
-#define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
-#define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
-
-/******************* Bit definition for GPIO_IDR register *******************/
-#define GPIO_IDR_0 ((uint32_t)0x00000001)
-#define GPIO_IDR_1 ((uint32_t)0x00000002)
-#define GPIO_IDR_2 ((uint32_t)0x00000004)
-#define GPIO_IDR_3 ((uint32_t)0x00000008)
-#define GPIO_IDR_4 ((uint32_t)0x00000010)
-#define GPIO_IDR_5 ((uint32_t)0x00000020)
-#define GPIO_IDR_6 ((uint32_t)0x00000040)
-#define GPIO_IDR_7 ((uint32_t)0x00000080)
-#define GPIO_IDR_8 ((uint32_t)0x00000100)
-#define GPIO_IDR_9 ((uint32_t)0x00000200)
-#define GPIO_IDR_10 ((uint32_t)0x00000400)
-#define GPIO_IDR_11 ((uint32_t)0x00000800)
-#define GPIO_IDR_12 ((uint32_t)0x00001000)
-#define GPIO_IDR_13 ((uint32_t)0x00002000)
-#define GPIO_IDR_14 ((uint32_t)0x00004000)
-#define GPIO_IDR_15 ((uint32_t)0x00008000)
-
-/****************** Bit definition for GPIO_ODR register ********************/
-#define GPIO_ODR_0 ((uint32_t)0x00000001)
-#define GPIO_ODR_1 ((uint32_t)0x00000002)
-#define GPIO_ODR_2 ((uint32_t)0x00000004)
-#define GPIO_ODR_3 ((uint32_t)0x00000008)
-#define GPIO_ODR_4 ((uint32_t)0x00000010)
-#define GPIO_ODR_5 ((uint32_t)0x00000020)
-#define GPIO_ODR_6 ((uint32_t)0x00000040)
-#define GPIO_ODR_7 ((uint32_t)0x00000080)
-#define GPIO_ODR_8 ((uint32_t)0x00000100)
-#define GPIO_ODR_9 ((uint32_t)0x00000200)
-#define GPIO_ODR_10 ((uint32_t)0x00000400)
-#define GPIO_ODR_11 ((uint32_t)0x00000800)
-#define GPIO_ODR_12 ((uint32_t)0x00001000)
-#define GPIO_ODR_13 ((uint32_t)0x00002000)
-#define GPIO_ODR_14 ((uint32_t)0x00004000)
-#define GPIO_ODR_15 ((uint32_t)0x00008000)
-
-/****************** Bit definition for GPIO_BSRR register ********************/
-#define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
-#define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
-#define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
-#define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
-#define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
-#define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
-#define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
-#define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
-#define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
-#define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
-#define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
-#define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
-#define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
-#define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
-#define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
-#define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
-#define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
-#define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
-#define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
-#define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
-#define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
-#define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
-#define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
-#define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
-#define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
-#define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
-#define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
-#define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
-#define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
-#define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
-#define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
-#define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
-
-/****************** Bit definition for GPIO_LCKR register ********************/
-#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
-#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
-#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
-#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
-#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
-#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
-#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
-#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
-#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
-#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
-#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
-#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
-#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
-#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
-#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
-#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
-#define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
-
-/****************** Bit definition for GPIO_AFRL register ********************/
-#define GPIO_AFRL_AFR0 ((uint32_t)0x0000000F)
-#define GPIO_AFRL_AFR1 ((uint32_t)0x000000F0)
-#define GPIO_AFRL_AFR2 ((uint32_t)0x00000F00)
-#define GPIO_AFRL_AFR3 ((uint32_t)0x0000F000)
-#define GPIO_AFRL_AFR4 ((uint32_t)0x000F0000)
-#define GPIO_AFRL_AFR5 ((uint32_t)0x00F00000)
-#define GPIO_AFRL_AFR6 ((uint32_t)0x0F000000)
-#define GPIO_AFRL_AFR7 ((uint32_t)0xF0000000)
-
-/****************** Bit definition for GPIO_AFRH register ********************/
-#define GPIO_AFRH_AFR8 ((uint32_t)0x0000000F)
-#define GPIO_AFRH_AFR9 ((uint32_t)0x000000F0)
-#define GPIO_AFRH_AFR10 ((uint32_t)0x00000F00)
-#define GPIO_AFRH_AFR11 ((uint32_t)0x0000F000)
-#define GPIO_AFRH_AFR12 ((uint32_t)0x000F0000)
-#define GPIO_AFRH_AFR13 ((uint32_t)0x00F00000)
-#define GPIO_AFRH_AFR14 ((uint32_t)0x0F000000)
-#define GPIO_AFRH_AFR15 ((uint32_t)0xF0000000)
-
-/* Old Bit definition for GPIO_AFRL register maintained for legacy purpose ****/
-#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFR0
-#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFR1
-#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFR2
-#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFR3
-#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFR4
-#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFR5
-#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFR6
-#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFR7
-
-/* Old Bit definition for GPIO_AFRH register maintained for legacy purpose ****/
-#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFR8
-#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFR9
-#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFR10
-#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFR11
-#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFR12
-#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFR13
-#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFR14
-#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFR15
-
-/****************** Bit definition for GPIO_BRR register *********************/
-#define GPIO_BRR_BR_0 ((uint32_t)0x00000001)
-#define GPIO_BRR_BR_1 ((uint32_t)0x00000002)
-#define GPIO_BRR_BR_2 ((uint32_t)0x00000004)
-#define GPIO_BRR_BR_3 ((uint32_t)0x00000008)
-#define GPIO_BRR_BR_4 ((uint32_t)0x00000010)
-#define GPIO_BRR_BR_5 ((uint32_t)0x00000020)
-#define GPIO_BRR_BR_6 ((uint32_t)0x00000040)
-#define GPIO_BRR_BR_7 ((uint32_t)0x00000080)
-#define GPIO_BRR_BR_8 ((uint32_t)0x00000100)
-#define GPIO_BRR_BR_9 ((uint32_t)0x00000200)
-#define GPIO_BRR_BR_10 ((uint32_t)0x00000400)
-#define GPIO_BRR_BR_11 ((uint32_t)0x00000800)
-#define GPIO_BRR_BR_12 ((uint32_t)0x00001000)
-#define GPIO_BRR_BR_13 ((uint32_t)0x00002000)
-#define GPIO_BRR_BR_14 ((uint32_t)0x00004000)
-#define GPIO_BRR_BR_15 ((uint32_t)0x00008000)
-
-/******************************************************************************/
-/* */
-/* Inter-integrated Circuit Interface (I2C) */
-/* */
-/******************************************************************************/
-
-/******************* Bit definition for I2C_CR1 register *******************/
-#define I2C_CR1_PE ((uint32_t)0x00000001) /*!< Peripheral enable */
-#define I2C_CR1_TXIE ((uint32_t)0x00000002) /*!< TX interrupt enable */
-#define I2C_CR1_RXIE ((uint32_t)0x00000004) /*!< RX interrupt enable */
-#define I2C_CR1_ADDRIE ((uint32_t)0x00000008) /*!< Address match interrupt enable */
-#define I2C_CR1_NACKIE ((uint32_t)0x00000010) /*!< NACK received interrupt enable */
-#define I2C_CR1_STOPIE ((uint32_t)0x00000020) /*!< STOP detection interrupt enable */
-#define I2C_CR1_TCIE ((uint32_t)0x00000040) /*!< Transfer complete interrupt enable */
-#define I2C_CR1_ERRIE ((uint32_t)0x00000080) /*!< Errors interrupt enable */
-#define I2C_CR1_DFN ((uint32_t)0x00000F00) /*!< Digital noise filter */
-#define I2C_CR1_ANFOFF ((uint32_t)0x00001000) /*!< Analog noise filter OFF */
-#define I2C_CR1_SWRST ((uint32_t)0x00002000) /*!< Software reset */
-#define I2C_CR1_TXDMAEN ((uint32_t)0x00004000) /*!< DMA transmission requests enable */
-#define I2C_CR1_RXDMAEN ((uint32_t)0x00008000) /*!< DMA reception requests enable */
-#define I2C_CR1_SBC ((uint32_t)0x00010000) /*!< Slave byte control */
-#define I2C_CR1_NOSTRETCH ((uint32_t)0x00020000) /*!< Clock stretching disable */
-#define I2C_CR1_WUPEN ((uint32_t)0x00040000) /*!< Wakeup from STOP enable */
-#define I2C_CR1_GCEN ((uint32_t)0x00080000) /*!< General call enable */
-#define I2C_CR1_SMBHEN ((uint32_t)0x00100000) /*!< SMBus host address enable */
-#define I2C_CR1_SMBDEN ((uint32_t)0x00200000) /*!< SMBus device default address enable */
-#define I2C_CR1_ALERTEN ((uint32_t)0x00400000) /*!< SMBus alert enable */
-#define I2C_CR1_PECEN ((uint32_t)0x00800000) /*!< PEC enable */
-
-/****************** Bit definition for I2C_CR2 register ********************/
-#define I2C_CR2_SADD ((uint32_t)0x000003FF) /*!< Slave address (master mode) */
-#define I2C_CR2_RD_WRN ((uint32_t)0x00000400) /*!< Transfer direction (master mode) */
-#define I2C_CR2_ADD10 ((uint32_t)0x00000800) /*!< 10-bit addressing mode (master mode) */
-#define I2C_CR2_HEAD10R ((uint32_t)0x00001000) /*!< 10-bit address header only read direction (master mode) */
-#define I2C_CR2_START ((uint32_t)0x00002000) /*!< START generation */
-#define I2C_CR2_STOP ((uint32_t)0x00004000) /*!< STOP generation (master mode) */
-#define I2C_CR2_NACK ((uint32_t)0x00008000) /*!< NACK generation (slave mode) */
-#define I2C_CR2_NBYTES ((uint32_t)0x00FF0000) /*!< Number of bytes */
-#define I2C_CR2_RELOAD ((uint32_t)0x01000000) /*!< NBYTES reload mode */
-#define I2C_CR2_AUTOEND ((uint32_t)0x02000000) /*!< Automatic end mode (master mode) */
-#define I2C_CR2_PECBYTE ((uint32_t)0x04000000) /*!< Packet error checking byte */
-
-/******************* Bit definition for I2C_OAR1 register ******************/
-#define I2C_OAR1_OA1 ((uint32_t)0x000003FF) /*!< Interface own address 1 */
-#define I2C_OAR1_OA1MODE ((uint32_t)0x00000400) /*!< Own address 1 10-bit mode */
-#define I2C_OAR1_OA1EN ((uint32_t)0x00008000) /*!< Own address 1 enable */
-
-/******************* Bit definition for I2C_OAR2 register ******************/
-#define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */
-#define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */
-#define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */
-
-/******************* Bit definition for I2C_TIMINGR register *******************/
-#define I2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /*!< SCL low period (master mode) */
-#define I2C_TIMINGR_SCLH ((uint32_t)0x0000FF00) /*!< SCL high period (master mode) */
-#define I2C_TIMINGR_SDADEL ((uint32_t)0x000F0000) /*!< Data hold time */
-#define I2C_TIMINGR_SCLDEL ((uint32_t)0x00F00000) /*!< Data setup time */
-#define I2C_TIMINGR_PRESC ((uint32_t)0xF0000000) /*!< Timings prescaler */
-
-/******************* Bit definition for I2C_TIMEOUTR register *******************/
-#define I2C_TIMEOUTR_TIMEOUTA ((uint32_t)0x00000FFF) /*!< Bus timeout A */
-#define I2C_TIMEOUTR_TIDLE ((uint32_t)0x00001000) /*!< Idle clock timeout detection */
-#define I2C_TIMEOUTR_TIMOUTEN ((uint32_t)0x00008000) /*!< Clock timeout enable */
-#define I2C_TIMEOUTR_TIMEOUTB ((uint32_t)0x0FFF0000) /*!< Bus timeout B*/
-#define I2C_TIMEOUTR_TEXTEN ((uint32_t)0x80000000) /*!< Extended clock timeout enable */
-
-/****************** Bit definition for I2C_ISR register *********************/
-#define I2C_ISR_TXE ((uint32_t)0x00000001) /*!< Transmit data register empty */
-#define I2C_ISR_TXIS ((uint32_t)0x00000002) /*!< Transmit interrupt status */
-#define I2C_ISR_RXNE ((uint32_t)0x00000004) /*!< Receive data register not empty */
-#define I2C_ISR_ADDR ((uint32_t)0x00000008) /*!< Address matched (slave mode)*/
-#define I2C_ISR_NACKF ((uint32_t)0x00000010) /*!< NACK received flag */
-#define I2C_ISR_STOPF ((uint32_t)0x00000020) /*!< STOP detection flag */
-#define I2C_ISR_TC ((uint32_t)0x00000040) /*!< Transfer complete (master mode) */
-#define I2C_ISR_TCR ((uint32_t)0x00000080) /*!< Transfer complete reload */
-#define I2C_ISR_BERR ((uint32_t)0x00000100) /*!< Bus error */
-#define I2C_ISR_ARLO ((uint32_t)0x00000200) /*!< Arbitration lost */
-#define I2C_ISR_OVR ((uint32_t)0x00000400) /*!< Overrun/Underrun */
-#define I2C_ISR_PECERR ((uint32_t)0x00000800) /*!< PEC error in reception */
-#define I2C_ISR_TIMEOUT ((uint32_t)0x00001000) /*!< Timeout or Tlow detection flag */
-#define I2C_ISR_ALERT ((uint32_t)0x00002000) /*!< SMBus alert */
-#define I2C_ISR_BUSY ((uint32_t)0x00008000) /*!< Bus busy */
-#define I2C_ISR_DIR ((uint32_t)0x00010000) /*!< Transfer direction (slave mode) */
-#define I2C_ISR_ADDCODE ((uint32_t)0x00FE0000) /*!< Address match code (slave mode) */
-
-/****************** Bit definition for I2C_ICR register *********************/
-#define I2C_ICR_ADDRCF ((uint32_t)0x00000008) /*!< Address matched clear flag */
-#define I2C_ICR_NACKCF ((uint32_t)0x00000010) /*!< NACK clear flag */
-#define I2C_ICR_STOPCF ((uint32_t)0x00000020) /*!< STOP detection clear flag */
-#define I2C_ICR_BERRCF ((uint32_t)0x00000100) /*!< Bus error clear flag */
-#define I2C_ICR_ARLOCF ((uint32_t)0x00000200) /*!< Arbitration lost clear flag */
-#define I2C_ICR_OVRCF ((uint32_t)0x00000400) /*!< Overrun/Underrun clear flag */
-#define I2C_ICR_PECCF ((uint32_t)0x00000800) /*!< PAC error clear flag */
-#define I2C_ICR_TIMOUTCF ((uint32_t)0x00001000) /*!< Timeout clear flag */
-#define I2C_ICR_ALERTCF ((uint32_t)0x00002000) /*!< Alert clear flag */
-
-/****************** Bit definition for I2C_PECR register *********************/
-#define I2C_PECR_PEC ((uint32_t)0x000000FF) /*!< PEC register */
-
-/****************** Bit definition for I2C_RXDR register *********************/
-#define I2C_RXDR_RXDATA ((uint32_t)0x000000FF) /*!< 8-bit receive data */
-
-/****************** Bit definition for I2C_TXDR register *********************/
-#define I2C_TXDR_TXDATA ((uint32_t)0x000000FF) /*!< 8-bit transmit data */
-
-/******************************************************************************/
-/* */
-/* Independent WATCHDOG (IWDG) */
-/* */
-/******************************************************************************/
-/******************* Bit definition for IWDG_KR register ********************/
-#define IWDG_KR_KEY ((uint16_t)0xFFFF) /*!< Key value (write only, read 0000h) */
-
-/******************* Bit definition for IWDG_PR register ********************/
-#define IWDG_PR_PR ((uint8_t)0x07) /*!< PR[2:0] (Prescaler divider) */
-#define IWDG_PR_PR_0 ((uint8_t)0x01) /*!< Bit 0 */
-#define IWDG_PR_PR_1 ((uint8_t)0x02) /*!< Bit 1 */
-#define IWDG_PR_PR_2 ((uint8_t)0x04) /*!< Bit 2 */
-
-/******************* Bit definition for IWDG_RLR register *******************/
-#define IWDG_RLR_RL ((uint16_t)0x0FFF) /*!< Watchdog counter reload value */
-
-/******************* Bit definition for IWDG_SR register ********************/
-#define IWDG_SR_PVU ((uint8_t)0x01) /*!< Watchdog prescaler value update */
-#define IWDG_SR_RVU ((uint8_t)0x02) /*!< Watchdog counter reload value update */
-#define IWDG_SR_WVU ((uint8_t)0x04) /*!< Watchdog counter window value update */
-
-/******************* Bit definition for IWDG_KR register ********************/
-#define IWDG_WINR_WIN ((uint16_t)0x0FFF) /*!< Watchdog counter window value */
-
-/******************************************************************************/
-/* */
-/* Power Control (PWR) */
-/* */
-/******************************************************************************/
-
-/******************** Bit definition for PWR_CR register ********************/
-#define PWR_CR_LPDS ((uint16_t)0x0001) /*!< Low-power deepsleep/sleep */
-#define PWR_CR_PDDS ((uint16_t)0x0002) /*!< Power Down Deepsleep */
-#define PWR_CR_CWUF ((uint16_t)0x0004) /*!< Clear Wakeup Flag */
-#define PWR_CR_CSBF ((uint16_t)0x0008) /*!< Clear Standby Flag */
-#define PWR_CR_PVDE ((uint16_t)0x0010) /*!< Power Voltage Detector Enable */
-
-#define PWR_CR_PLS ((uint16_t)0x00E0) /*!< PLS[2:0] bits (PVD Level Selection) */
-#define PWR_CR_PLS_0 ((uint16_t)0x0020) /*!< Bit 0 */
-#define PWR_CR_PLS_1 ((uint16_t)0x0040) /*!< Bit 1 */
-#define PWR_CR_PLS_2 ((uint16_t)0x0080) /*!< Bit 2 */
-/* PVD level configuration */
-#define PWR_CR_PLS_LEV0 ((uint16_t)0x0000) /*!< PVD level 0 */
-#define PWR_CR_PLS_LEV1 ((uint16_t)0x0020) /*!< PVD level 1 */
-#define PWR_CR_PLS_LEV2 ((uint16_t)0x0040) /*!< PVD level 2 */
-#define PWR_CR_PLS_LEV3 ((uint16_t)0x0060) /*!< PVD level 3 */
-#define PWR_CR_PLS_LEV4 ((uint16_t)0x0080) /*!< PVD level 4 */
-#define PWR_CR_PLS_LEV5 ((uint16_t)0x00A0) /*!< PVD level 5 */
-#define PWR_CR_PLS_LEV6 ((uint16_t)0x00C0) /*!< PVD level 6 */
-#define PWR_CR_PLS_LEV7 ((uint16_t)0x00E0) /*!< PVD level 7 */
-
-#define PWR_CR_DBP ((uint16_t)0x0100) /*!< Disable Backup Domain write protection */
-
-/* Old Bit definition maintained for legacy purpose ****/
-#define PWR_CR_LPSDSR PWR_CR_LPDS /*!< Low-power deepsleep */
-
-/******************* Bit definition for PWR_CSR register ********************/
-#define PWR_CSR_WUF ((uint16_t)0x0001) /*!< Wakeup Flag */
-#define PWR_CSR_SBF ((uint16_t)0x0002) /*!< Standby Flag */
-#define PWR_CSR_PVDO ((uint16_t)0x0004) /*!< PVD Output */
-#define PWR_CSR_VREFINTRDY ((uint16_t)0x0008) /*!< Internal voltage reference (VREFINT) ready */
-
-#define PWR_CSR_EWUP1 ((uint16_t)0x0100) /*!< Enable WKUP pin 1 */
-#define PWR_CSR_EWUP2 ((uint16_t)0x0200) /*!< Enable WKUP pin 2 */
-#define PWR_CSR_EWUP3 ((uint16_t)0x0400) /*!< Enable WKUP pin 3 */
-#define PWR_CSR_EWUP4 ((uint16_t)0x0800) /*!< Enable WKUP pin 4 */
-#define PWR_CSR_EWUP5 ((uint16_t)0x1000) /*!< Enable WKUP pin 5 */
-#define PWR_CSR_EWUP6 ((uint16_t)0x2000) /*!< Enable WKUP pin 6 */
-#define PWR_CSR_EWUP7 ((uint16_t)0x4000) /*!< Enable WKUP pin 7 */
-#define PWR_CSR_EWUP8 ((uint16_t)0x8000) /*!< Enable WKUP pin 8 */
-
-/* Old Bit definition maintained for legacy purpose ****/
-#define PWR_CSR_VREFINTRDYF PWR_CSR_VREFINTRDY /*!< Internal voltage reference (VREFINT) ready flag */
-/******************************************************************************/
-/* */
-/* Reset and Clock Control */
-/* */
-/******************************************************************************/
-
-/******************** Bit definition for RCC_CR register ********************/
-#define RCC_CR_HSION ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */
-#define RCC_CR_HSIRDY ((uint32_t)0x00000002) /*!< Internal High Speed clock ready flag */
-#define RCC_CR_HSITRIM ((uint32_t)0x000000F8) /*!< Internal High Speed clock trimming */
-#define RCC_CR_HSICAL ((uint32_t)0x0000FF00) /*!< Internal High Speed clock Calibration */
-#define RCC_CR_HSEON ((uint32_t)0x00010000) /*!< External High Speed clock enable */
-#define RCC_CR_HSERDY ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */
-#define RCC_CR_HSEBYP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */
-#define RCC_CR_CSSON ((uint32_t)0x00080000) /*!< Clock Security System enable */
-#define RCC_CR_PLLON ((uint32_t)0x01000000) /*!< PLL enable */
-#define RCC_CR_PLLRDY ((uint32_t)0x02000000) /*!< PLL clock ready flag */
-
-/******************* Bit definition for RCC_CFGR register *******************/
-#define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
-#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
-#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
-/* SW configuration */
-#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
-#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
-#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
-#define RCC_CFGR_SW_HSI48 ((uint32_t)0x00000003) /*!< HSI48 selected as system clock */
-
-#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
-#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
-/* SWS configuration */
-#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
-#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
-#define RCC_CFGR_SWS_HSI48 ((uint32_t)0x0000000C) /*!< HSI48 used as system clock */
-
-#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
-#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
-#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
-#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
-#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
-/* HPRE configuration */
-#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
-#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
-#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
-#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
-#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
-#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
-#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
-#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
-#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
-
-#define RCC_CFGR_PPRE ((uint32_t)0x00000700) /*!< PRE[2:0] bits (APB prescaler) */
-#define RCC_CFGR_PPRE_0 ((uint32_t)0x00000100) /*!< Bit 0 */
-#define RCC_CFGR_PPRE_1 ((uint32_t)0x00000200) /*!< Bit 1 */
-#define RCC_CFGR_PPRE_2 ((uint32_t)0x00000400) /*!< Bit 2 */
-/* PPRE configuration */
-#define RCC_CFGR_PPRE_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
-#define RCC_CFGR_PPRE_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
-
-#define RCC_CFGR_ADCPRE ((uint32_t)0x00004000) /*!< ADC prescaler: Obsolete. Proper ADC clock selection is
- done inside the ADC_CFGR2 */
-
-#define RCC_CFGR_PLLSRC ((uint32_t)0x00018000) /*!< PLL entry clock source */
-#define RCC_CFGR_PLLSRC_0 ((uint32_t)0x00008000) /*!< Bit 0 (available only in the STM32F072 devices) */
-#define RCC_CFGR_PLLSRC_1 ((uint32_t)0x00010000) /*!< Bit 1 */
-
-#define RCC_CFGR_PLLSRC_PREDIV1 ((uint32_t)0x00010000) /*!< PREDIV1 clock selected as PLL entry clock source;
- Old PREDIV1 bit definition, maintained for legacy purpose */
-#define RCC_CFGR_PLLSRC_HSI_DIV2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */
-#define RCC_CFGR_PLLSRC_HSI_PREDIV ((uint32_t)0x00008000) /*!< HSI PREDIV clock selected as PLL entry clock source
- (This bit and configuration is only available for STM32F072 devices)*/
-#define RCC_CFGR_PLLSRC_HSE_PREDIV ((uint32_t)0x00010000) /*!< HSE PREDIV clock selected as PLL entry clock source */
-#define RCC_CFGR_PLLSRC_HSI48_PREDIV ((uint32_t)0x00018000) /*!< HSI48 PREDIV clock selected as PLL entry clock source */
-
-#define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /*!< HSE divider for PLL entry */
-#define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) /*!< PREDIV1 clock not divided for PLL entry */
-#define RCC_CFGR_PLLXTPRE_PREDIV1_Div2 ((uint32_t)0x00020000) /*!< PREDIV1 clock divided by 2 for PLL entry */
-
-/*!< Old bit definition maintained for legacy purposes */
-#define RCC_CFGR_PLLSRC_HSI_Div2 RCC_CFGR_PLLSRC_HSI_DIV2
-
-/* PLLMUL configuration */
-#define RCC_CFGR_PLLMUL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
-#define RCC_CFGR_PLLMUL_0 ((uint32_t)0x00040000) /*!< Bit 0 */
-#define RCC_CFGR_PLLMUL_1 ((uint32_t)0x00080000) /*!< Bit 1 */
-#define RCC_CFGR_PLLMUL_2 ((uint32_t)0x00100000) /*!< Bit 2 */
-#define RCC_CFGR_PLLMUL_3 ((uint32_t)0x00200000) /*!< Bit 3 */
-
-#define RCC_CFGR_PLLMUL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */
-#define RCC_CFGR_PLLMUL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */
-#define RCC_CFGR_PLLMUL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */
-#define RCC_CFGR_PLLMUL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */
-#define RCC_CFGR_PLLMUL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */
-#define RCC_CFGR_PLLMUL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */
-#define RCC_CFGR_PLLMUL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */
-#define RCC_CFGR_PLLMUL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */
-#define RCC_CFGR_PLLMUL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */
-#define RCC_CFGR_PLLMUL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */
-#define RCC_CFGR_PLLMUL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */
-#define RCC_CFGR_PLLMUL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */
-#define RCC_CFGR_PLLMUL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */
-#define RCC_CFGR_PLLMUL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */
-#define RCC_CFGR_PLLMUL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */
-
-/* Old PLLMUL configuration bit definition maintained for legacy purposes */
-#define RCC_CFGR_PLLMULL RCC_CFGR_PLLMUL /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
-#define RCC_CFGR_PLLMULL_0 RCC_CFGR_PLLMUL_0 /*!< Bit 0 */
-#define RCC_CFGR_PLLMULL_1 RCC_CFGR_PLLMUL_1 /*!< Bit 1 */
-#define RCC_CFGR_PLLMULL_2 RCC_CFGR_PLLMUL_2 /*!< Bit 2 */
-#define RCC_CFGR_PLLMULL_3 RCC_CFGR_PLLMUL_3 /*!< Bit 3 */
-
-#define RCC_CFGR_PLLMULL2 RCC_CFGR_PLLMUL2 /*!< PLL input clock*2 */
-#define RCC_CFGR_PLLMULL3 RCC_CFGR_PLLMUL3 /*!< PLL input clock*3 */
-#define RCC_CFGR_PLLMULL4 RCC_CFGR_PLLMUL4 /*!< PLL input clock*4 */
-#define RCC_CFGR_PLLMULL5 RCC_CFGR_PLLMUL5 /*!< PLL input clock*5 */
-#define RCC_CFGR_PLLMULL6 RCC_CFGR_PLLMUL6 /*!< PLL input clock*6 */
-#define RCC_CFGR_PLLMULL7 RCC_CFGR_PLLMUL7 /*!< PLL input clock*7 */
-#define RCC_CFGR_PLLMULL8 RCC_CFGR_PLLMUL8 /*!< PLL input clock*8 */
-#define RCC_CFGR_PLLMULL9 RCC_CFGR_PLLMUL9 /*!< PLL input clock*9 */
-#define RCC_CFGR_PLLMULL10 RCC_CFGR_PLLMUL10 /*!< PLL input clock10 */
-#define RCC_CFGR_PLLMULL11 RCC_CFGR_PLLMUL11 /*!< PLL input clock*11 */
-#define RCC_CFGR_PLLMULL12 RCC_CFGR_PLLMUL12 /*!< PLL input clock*12 */
-#define RCC_CFGR_PLLMULL13 RCC_CFGR_PLLMUL13 /*!< PLL input clock*13 */
-#define RCC_CFGR_PLLMULL14 RCC_CFGR_PLLMUL14 /*!< PLL input clock*14 */
-#define RCC_CFGR_PLLMULL15 RCC_CFGR_PLLMUL15 /*!< PLL input clock*15 */
-#define RCC_CFGR_PLLMULL16 RCC_CFGR_PLLMUL16 /*!< PLL input clock*16 */
-
-#define RCC_CFGR_MCO ((uint32_t)0x0F000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */
-#define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */
-#define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */
-#define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */
-#define RCC_CFGR_MCO_3 ((uint32_t)0x08000000) /*!< Bit 3 */
-/* MCO configuration */
-#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
-#define RCC_CFGR_MCO_HSI14 ((uint32_t)0x01000000) /*!< HSI14 clock selected as MCO source */
-#define RCC_CFGR_MCO_LSI ((uint32_t)0x02000000) /*!< LSI clock selected as MCO source */
-#define RCC_CFGR_MCO_LSE ((uint32_t)0x03000000) /*!< LSE clock selected as MCO source */
-#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
-#define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
-#define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
-#define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock selected as MCO source */
-#define RCC_CFGR_MCO_HSI48 ((uint32_t)0x08000000) /*!< HSI48 clock selected as MCO source */
-
-#define RCC_CFGR_MCO_PRE ((uint32_t)0x70000000) /*!< MCO prescaler (these bits are not available in the STM32F051 devices)*/
-#define RCC_CFGR_MCO_PRE_1 ((uint32_t)0x00000000) /*!< MCO is divided by 1 (this bit are not available in the STM32F051 devices)*/
-#define RCC_CFGR_MCO_PRE_2 ((uint32_t)0x10000000) /*!< MCO is divided by 2 (this bit are not available in the STM32F051 devices)*/
-#define RCC_CFGR_MCO_PRE_4 ((uint32_t)0x20000000) /*!< MCO is divided by 4 (this bit are not available in the STM32F051 devices)*/
-#define RCC_CFGR_MCO_PRE_8 ((uint32_t)0x30000000) /*!< MCO is divided by 8 (this bit are not available in the STM32F051 devices)*/
-#define RCC_CFGR_MCO_PRE_16 ((uint32_t)0x40000000) /*!< MCO is divided by 16 (this bit are not available in the STM32F051 devices)*/
-#define RCC_CFGR_MCO_PRE_32 ((uint32_t)0x50000000) /*!< MCO is divided by 32 (this bit are not available in the STM32F051 devices)*/
-#define RCC_CFGR_MCO_PRE_64 ((uint32_t)0x60000000) /*!< MCO is divided by 64 (this bit are not available in the STM32F051 devices)*/
-#define RCC_CFGR_MCO_PRE_128 ((uint32_t)0x70000000) /*!< MCO is divided by 128 (this bit are not available in the STM32F051 devices)*/
-
-#define RCC_CFGR_PLLNODIV ((uint32_t)0x80000000) /*!< PLL is not divided to MCO (this bit are not available in the STM32F051 devices) */
-
-/******************* Bit definition for RCC_CIR register ********************/
-#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */
-#define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */
-#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */
-#define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */
-#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */
-#define RCC_CIR_HSI14RDYF ((uint32_t)0x00000020) /*!< HSI14 Ready Interrupt flag */
-#define RCC_CIR_HSI48RDYF ((uint32_t)0x00000040) /*!< HSI48 Ready Interrupt flag */
-#define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */
-#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */
-#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */
-#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */
-#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */
-#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */
-#define RCC_CIR_HSI14RDYIE ((uint32_t)0x00002000) /*!< HSI14 Ready Interrupt Enable */
-#define RCC_CIR_HSI48RDYIE ((uint32_t)0x00004000) /*!< HSI48 Ready Interrupt Enable */
-#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */
-#define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */
-#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */
-#define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */
-#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */
-#define RCC_CIR_HSI14RDYC ((uint32_t)0x00200000) /*!< HSI14 Ready Interrupt Clear */
-#define RCC_CIR_HSI48RDYC ((uint32_t)0x00400000) /*!< HSI48 Ready Interrupt Clear */
-#define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */
-
-/***************** Bit definition for RCC_APB2RSTR register *****************/
-#define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001) /*!< SYSCFG clock reset */
-#define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000200) /*!< ADC clock reset */
-#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) /*!< TIM1 clock reset */
-#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI1 clock reset */
-#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 clock reset */
-#define RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000) /*!< TIM15 clock reset */
-#define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) /*!< TIM16 clock reset */
-#define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) /*!< TIM17 clock reset */
-#define RCC_APB2RSTR_DBGMCURST ((uint32_t)0x00400000) /*!< DBGMCU clock reset */
-
-/* Old ADC1 clock reset bit definition maintained for legacy purpose */
-#define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST
-
-/***************** Bit definition for RCC_APB1RSTR register *****************/
-#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 clock reset */
-#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 clock reset */
-#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 clock reset */
-#define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 clock reset */
-#define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) /*!< Timer 14 clock reset */
-#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog clock reset */
-#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI2 clock reset */
-#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 clock reset */
-#define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< USART 3 clock reset */
-#define RCC_APB1RSTR_USART4RST ((uint32_t)0x00080000) /*!< USART 4 clock reset */
-#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 clock reset */
-#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 clock reset */
-#define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /*!< USB clock reset */
-#define RCC_APB1RSTR_CANRST ((uint32_t)0x02000000) /*!< CAN clock reset */
-#define RCC_APB1RSTR_CRSRST ((uint32_t)0x08000000) /*!< CRS clock reset */
-#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< PWR clock reset */
-#define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC clock reset */
-#define RCC_APB1RSTR_CECRST ((uint32_t)0x40000000) /*!< CEC clock reset */
-
-/****************** Bit definition for RCC_AHBENR register ******************/
-#define RCC_AHBENR_DMAEN ((uint32_t)0x00000001) /*!< DMA clock enable */
-#define RCC_AHBENR_SRAMEN ((uint32_t)0x00000004) /*!< SRAM interface clock enable */
-#define RCC_AHBENR_FLITFEN ((uint32_t)0x00000010) /*!< FLITF clock enable */
-#define RCC_AHBENR_CRCEN ((uint32_t)0x00000040) /*!< CRC clock enable */
-#define RCC_AHBENR_GPIOAEN ((uint32_t)0x00020000) /*!< GPIOA clock enable */
-#define RCC_AHBENR_GPIOBEN ((uint32_t)0x00040000) /*!< GPIOB clock enable */
-#define RCC_AHBENR_GPIOCEN ((uint32_t)0x00080000) /*!< GPIOC clock enable */
-#define RCC_AHBENR_GPIODEN ((uint32_t)0x00100000) /*!< GPIOD clock enable */
-#define RCC_AHBENR_GPIOEEN ((uint32_t)0x00200000) /*!< GPIOE clock enable */
-#define RCC_AHBENR_GPIOFEN ((uint32_t)0x00400000) /*!< GPIOF clock enable */
-#define RCC_AHBENR_TSCEN ((uint32_t)0x01000000) /*!< TS controller clock enable */
-
-/* Old Bit definition maintained for legacy purpose */
-#define RCC_AHBENR_DMA1EN RCC_AHBENR_DMAEN /*!< DMA1 clock enable */
-#define RCC_AHBENR_TSEN RCC_AHBENR_TSCEN /*!< TS clock enable */
-
-/***************** Bit definition for RCC_APB2ENR register ******************/
-#define RCC_APB2ENR_SYSCFGCOMPEN ((uint32_t)0x00000001) /*!< SYSCFG and comparator clock enable */
-#define RCC_APB2ENR_ADCEN ((uint32_t)0x00000200) /*!< ADC1 clock enable */
-#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /*!< TIM1 clock enable */
-#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI1 clock enable */
-#define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */
-#define RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000) /*!< TIM15 clock enable */
-#define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) /*!< TIM16 clock enable */
-#define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) /*!< TIM17 clock enable */
-#define RCC_APB2ENR_DBGMCUEN ((uint32_t)0x00400000) /*!< DBGMCU clock enable */
-
-/* Old Bit definition maintained for legacy purpose */
-#define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGCOMPEN /*!< SYSCFG clock enable */
-#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADCEN /*!< ADC1 clock enable */
-
-/***************** Bit definition for RCC_APB1ENR register ******************/
-#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enable */
-#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */
-#define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */
-#define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */
-#define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) /*!< Timer 14 clock enable */
-#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */
-#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI2 clock enable */
-#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART2 clock enable */
-#define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /*!< USART3 clock enable */
-#define RCC_APB1ENR_USART4EN ((uint32_t)0x00080000) /*!< USART4 clock enable */
-#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C1 clock enable */
-#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C2 clock enable */
-#define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /*!< USB clock enable */
-#define RCC_APB1ENR_CANEN ((uint32_t)0x02000000) /*!< CAN clock enable */
-#define RCC_APB1ENR_CRSEN ((uint32_t)0x08000000) /*!< CRS clock enable */
-#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< PWR clock enable */
-#define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC clock enable */
-#define RCC_APB1ENR_CECEN ((uint32_t)0x40000000) /*!< CEC clock enable */
-
-/******************* Bit definition for RCC_BDCR register *******************/
-#define RCC_BDCR_LSEON ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */
-#define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */
-#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */
-
-#define RCC_BDCR_LSEDRV ((uint32_t)0x00000018) /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
-#define RCC_BDCR_LSEDRV_0 ((uint32_t)0x00000008) /*!< Bit 0 */
-#define RCC_BDCR_LSEDRV_1 ((uint32_t)0x00000010) /*!< Bit 1 */
-
-#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */
-#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */
-#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */
-
-/* RTC configuration */
-#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
-#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */
-#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */
-#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 32 used as RTC clock */
-
-#define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /*!< RTC clock enable */
-#define RCC_BDCR_BDRST ((uint32_t)0x00010000) /*!< Backup domain software reset */
-
-/******************* Bit definition for RCC_CSR register ********************/
-#define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */
-#define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */
-#define RCC_CSR_V18PWRRSTF ((uint32_t)0x00800000) /*!< V1.8 power domain reset flag */
-#define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */
-#define RCC_CSR_OBLRSTF ((uint32_t)0x02000000) /*!< OBL reset flag */
-#define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */
-#define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */
-#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */
-#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */
-#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */
-#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */
-
-/* Old Bit definition maintained for legacy purpose */
-#define RCC_CSR_OBL RCC_CSR_OBLRSTF /*!< OBL reset flag */
-/******************* Bit definition for RCC_AHBRSTR register ****************/
-#define RCC_AHBRSTR_GPIOARST ((uint32_t)0x00020000) /*!< GPIOA clock reset */
-#define RCC_AHBRSTR_GPIOBRST ((uint32_t)0x00040000) /*!< GPIOB clock reset */
-#define RCC_AHBRSTR_GPIOCRST ((uint32_t)0x00080000) /*!< GPIOC clock reset */
-#define RCC_AHBRSTR_GPIODRST ((uint32_t)0x00010000) /*!< GPIOD clock reset */
-#define RCC_AHBRSTR_GPIOERST ((uint32_t)0x00020000) /*!< GPIOE clock reset */
-#define RCC_AHBRSTR_GPIOFRST ((uint32_t)0x00040000) /*!< GPIOF clock reset */
-#define RCC_AHBRSTR_TSCRST ((uint32_t)0x00100000) /*!< TS clock reset */
-
-/* Old Bit definition maintained for legacy purpose */
-#define RCC_AHBRSTR_TSRST RCC_AHBRSTR_TSCRST /*!< TS clock reset */
-
-/******************* Bit definition for RCC_CFGR2 register ******************/
-/* PREDIV1 configuration */
-#define RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F) /*!< PREDIV1[3:0] bits */
-#define RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001) /*!< Bit 0 */
-#define RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004) /*!< Bit 2 */
-#define RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008) /*!< Bit 3 */
-
-#define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) /*!< PREDIV1 input clock not divided */
-#define RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001) /*!< PREDIV1 input clock divided by 2 */
-#define RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002) /*!< PREDIV1 input clock divided by 3 */
-#define RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003) /*!< PREDIV1 input clock divided by 4 */
-#define RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004) /*!< PREDIV1 input clock divided by 5 */
-#define RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005) /*!< PREDIV1 input clock divided by 6 */
-#define RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006) /*!< PREDIV1 input clock divided by 7 */
-#define RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007) /*!< PREDIV1 input clock divided by 8 */
-#define RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008) /*!< PREDIV1 input clock divided by 9 */
-#define RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009) /*!< PREDIV1 input clock divided by 10 */
-#define RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV1 input clock divided by 11 */
-#define RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV1 input clock divided by 12 */
-#define RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV1 input clock divided by 13 */
-#define RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV1 input clock divided by 14 */
-#define RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV1 input clock divided by 15 */
-#define RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV1 input clock divided by 16 */
-
-/******************* Bit definition for RCC_CFGR3 register ******************/
-#define RCC_CFGR3_USART1SW ((uint32_t)0x00000003) /*!< USART1SW[1:0] bits */
-#define RCC_CFGR3_USART1SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
-#define RCC_CFGR3_USART1SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define RCC_CFGR3_I2C1SW ((uint32_t)0x00000010) /*!< I2C1SW bits */
-#define RCC_CFGR3_CECSW ((uint32_t)0x00000040) /*!< CECSW bits */
-#define RCC_CFGR3_USBSW ((uint32_t)0x00000080) /*!< USBSW bits */
-#define RCC_CFGR3_ADCSW ((uint32_t)0x00000100) /*!< ADCSW bits */
-#define RCC_CFGR3_USART2SW ((uint32_t)0x00030000) /*!< USART2SW[1:0] bits */
-#define RCC_CFGR3_USART2SW_0 ((uint32_t)0x00010000) /*!< Bit 0 */
-#define RCC_CFGR3_USART2SW_1 ((uint32_t)0x00020000) /*!< Bit 1 */
-
-/******************* Bit definition for RCC_CR2 register ********************/
-#define RCC_CR2_HSI14ON ((uint32_t)0x00000001) /*!< Internal High Speed 14MHz clock enable */
-#define RCC_CR2_HSI14RDY ((uint32_t)0x00000002) /*!< Internal High Speed 14MHz clock ready flag */
-#define RCC_CR2_HSI14DIS ((uint32_t)0x00000004) /*!< Internal High Speed 14MHz clock disable */
-#define RCC_CR2_HSI14TRIM ((uint32_t)0x000000F8) /*!< Internal High Speed 14MHz clock trimming */
-#define RCC_CR2_HSI14CAL ((uint32_t)0x0000FF00) /*!< Internal High Speed 14MHz clock Calibration */
-#define RCC_CR2_HSI48ON ((uint32_t)0x00010000) /*!< Internal High Speed 48MHz clock enable */
-#define RCC_CR2_HSI48RDY ((uint32_t)0x00020000) /*!< Internal High Speed 48MHz clock ready flag */
-#define RCC_CR2_HSI48CAL ((uint32_t)0xFF000000) /*!< Internal High Speed 48MHz clock Calibration */
-
-/******************************************************************************/
-/* */
-/* Real-Time Clock (RTC) */
-/* */
-/******************************************************************************/
-/******************** Bits definition for RTC_TR register *******************/
-#define RTC_TR_PM ((uint32_t)0x00400000)
-#define RTC_TR_HT ((uint32_t)0x00300000)
-#define RTC_TR_HT_0 ((uint32_t)0x00100000)
-#define RTC_TR_HT_1 ((uint32_t)0x00200000)
-#define RTC_TR_HU ((uint32_t)0x000F0000)
-#define RTC_TR_HU_0 ((uint32_t)0x00010000)
-#define RTC_TR_HU_1 ((uint32_t)0x00020000)
-#define RTC_TR_HU_2 ((uint32_t)0x00040000)
-#define RTC_TR_HU_3 ((uint32_t)0x00080000)
-#define RTC_TR_MNT ((uint32_t)0x00007000)
-#define RTC_TR_MNT_0 ((uint32_t)0x00001000)
-#define RTC_TR_MNT_1 ((uint32_t)0x00002000)
-#define RTC_TR_MNT_2 ((uint32_t)0x00004000)
-#define RTC_TR_MNU ((uint32_t)0x00000F00)
-#define RTC_TR_MNU_0 ((uint32_t)0x00000100)
-#define RTC_TR_MNU_1 ((uint32_t)0x00000200)
-#define RTC_TR_MNU_2 ((uint32_t)0x00000400)
-#define RTC_TR_MNU_3 ((uint32_t)0x00000800)
-#define RTC_TR_ST ((uint32_t)0x00000070)
-#define RTC_TR_ST_0 ((uint32_t)0x00000010)
-#define RTC_TR_ST_1 ((uint32_t)0x00000020)
-#define RTC_TR_ST_2 ((uint32_t)0x00000040)
-#define RTC_TR_SU ((uint32_t)0x0000000F)
-#define RTC_TR_SU_0 ((uint32_t)0x00000001)
-#define RTC_TR_SU_1 ((uint32_t)0x00000002)
-#define RTC_TR_SU_2 ((uint32_t)0x00000004)
-#define RTC_TR_SU_3 ((uint32_t)0x00000008)
-
-/******************** Bits definition for RTC_DR register *******************/
-#define RTC_DR_YT ((uint32_t)0x00F00000)
-#define RTC_DR_YT_0 ((uint32_t)0x00100000)
-#define RTC_DR_YT_1 ((uint32_t)0x00200000)
-#define RTC_DR_YT_2 ((uint32_t)0x00400000)
-#define RTC_DR_YT_3 ((uint32_t)0x00800000)
-#define RTC_DR_YU ((uint32_t)0x000F0000)
-#define RTC_DR_YU_0 ((uint32_t)0x00010000)
-#define RTC_DR_YU_1 ((uint32_t)0x00020000)
-#define RTC_DR_YU_2 ((uint32_t)0x00040000)
-#define RTC_DR_YU_3 ((uint32_t)0x00080000)
-#define RTC_DR_WDU ((uint32_t)0x0000E000)
-#define RTC_DR_WDU_0 ((uint32_t)0x00002000)
-#define RTC_DR_WDU_1 ((uint32_t)0x00004000)
-#define RTC_DR_WDU_2 ((uint32_t)0x00008000)
-#define RTC_DR_MT ((uint32_t)0x00001000)
-#define RTC_DR_MU ((uint32_t)0x00000F00)
-#define RTC_DR_MU_0 ((uint32_t)0x00000100)
-#define RTC_DR_MU_1 ((uint32_t)0x00000200)
-#define RTC_DR_MU_2 ((uint32_t)0x00000400)
-#define RTC_DR_MU_3 ((uint32_t)0x00000800)
-#define RTC_DR_DT ((uint32_t)0x00000030)
-#define RTC_DR_DT_0 ((uint32_t)0x00000010)
-#define RTC_DR_DT_1 ((uint32_t)0x00000020)
-#define RTC_DR_DU ((uint32_t)0x0000000F)
-#define RTC_DR_DU_0 ((uint32_t)0x00000001)
-#define RTC_DR_DU_1 ((uint32_t)0x00000002)
-#define RTC_DR_DU_2 ((uint32_t)0x00000004)
-#define RTC_DR_DU_3 ((uint32_t)0x00000008)
-
-/******************** Bits definition for RTC_CR register *******************/
-#define RTC_CR_COE ((uint32_t)0x00800000)
-#define RTC_CR_OSEL ((uint32_t)0x00600000)
-#define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
-#define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
-#define RTC_CR_POL ((uint32_t)0x00100000)
-#define RTC_CR_COSEL ((uint32_t)0x00080000)
-#define RTC_CR_BKP ((uint32_t)0x00040000)
-#define RTC_CR_SUB1H ((uint32_t)0x00020000)
-#define RTC_CR_ADD1H ((uint32_t)0x00010000)
-#define RTC_CR_TSIE ((uint32_t)0x00008000)
-#define RTC_CR_WUTIE ((uint32_t)0x00004000)
-#define RTC_CR_ALRAIE ((uint32_t)0x00001000)
-#define RTC_CR_TSE ((uint32_t)0x00000800)
-#define RTC_CR_WUTE ((uint32_t)0x00000400)
-#define RTC_CR_ALRAE ((uint32_t)0x00000100)
-#define RTC_CR_FMT ((uint32_t)0x00000040)
-#define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
-#define RTC_CR_REFCKON ((uint32_t)0x00000010)
-#define RTC_CR_TSEDGE ((uint32_t)0x00000008)
-#define RTC_CR_WUCKSEL ((uint32_t)0x00000007)
-#define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)
-#define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)
-#define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)
-
-/* Old bit definition maintained for legacy purpose */
-#define RTC_CR_BCK RTC_CR_BKP
-#define RTC_CR_CALSEL RTC_CR_COSEL
-
-/******************** Bits definition for RTC_ISR register ******************/
-#define RTC_ISR_RECALPF ((uint32_t)0x00010000)
-#define RTC_ISR_TAMP3F ((uint32_t)0x00008000)
-#define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
-#define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
-#define RTC_ISR_TSOVF ((uint32_t)0x00001000)
-#define RTC_ISR_TSF ((uint32_t)0x00000800)
-#define RTC_ISR_WUTF ((uint32_t)0x00000400)
-#define RTC_ISR_ALRAF ((uint32_t)0x00000100)
-#define RTC_ISR_INIT ((uint32_t)0x00000080)
-#define RTC_ISR_INITF ((uint32_t)0x00000040)
-#define RTC_ISR_RSF ((uint32_t)0x00000020)
-#define RTC_ISR_INITS ((uint32_t)0x00000010)
-#define RTC_ISR_SHPF ((uint32_t)0x00000008)
-#define RTC_ISR_WUTWF ((uint32_t)0x00000004)
-#define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
-
-/******************** Bits definition for RTC_PRER register *****************/
-#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
-#define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
-
-/******************** Bits definition for RTC_WUTR register *****************/
-#define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
-
-/******************** Bits definition for RTC_ALRMAR register ***************/
-#define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
-#define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
-#define RTC_ALRMAR_DT ((uint32_t)0x30000000)
-#define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
-#define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
-#define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
-#define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
-#define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
-#define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
-#define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
-#define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
-#define RTC_ALRMAR_PM ((uint32_t)0x00400000)
-#define RTC_ALRMAR_HT ((uint32_t)0x00300000)
-#define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
-#define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
-#define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
-#define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
-#define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
-#define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
-#define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
-#define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
-#define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
-#define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
-#define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
-#define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
-#define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
-#define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
-#define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
-#define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
-#define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
-#define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
-#define RTC_ALRMAR_ST ((uint32_t)0x00000070)
-#define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
-#define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
-#define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
-#define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
-#define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
-#define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
-#define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
-#define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
-
-/******************** Bits definition for RTC_WPR register ******************/
-#define RTC_WPR_KEY ((uint32_t)0x000000FF)
-
-/******************** Bits definition for RTC_SSR register ******************/
-#define RTC_SSR_SS ((uint32_t)0x0003FFFF)
-
-/******************** Bits definition for RTC_SHIFTR register ***************/
-#define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
-#define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
-
-/******************** Bits definition for RTC_TSTR register *****************/
-#define RTC_TSTR_PM ((uint32_t)0x00400000)
-#define RTC_TSTR_HT ((uint32_t)0x00300000)
-#define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
-#define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
-#define RTC_TSTR_HU ((uint32_t)0x000F0000)
-#define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
-#define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
-#define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
-#define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
-#define RTC_TSTR_MNT ((uint32_t)0x00007000)
-#define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
-#define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
-#define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
-#define RTC_TSTR_MNU ((uint32_t)0x00000F00)
-#define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
-#define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
-#define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
-#define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
-#define RTC_TSTR_ST ((uint32_t)0x00000070)
-#define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
-#define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
-#define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
-#define RTC_TSTR_SU ((uint32_t)0x0000000F)
-#define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
-#define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
-#define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
-#define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
-
-/******************** Bits definition for RTC_TSDR register *****************/
-#define RTC_TSDR_WDU ((uint32_t)0x0000E000)
-#define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
-#define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
-#define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
-#define RTC_TSDR_MT ((uint32_t)0x00001000)
-#define RTC_TSDR_MU ((uint32_t)0x00000F00)
-#define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
-#define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
-#define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
-#define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
-#define RTC_TSDR_DT ((uint32_t)0x00000030)
-#define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
-#define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
-#define RTC_TSDR_DU ((uint32_t)0x0000000F)
-#define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
-#define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
-#define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
-#define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
-
-/******************** Bits definition for RTC_TSSSR register ****************/
-#define RTC_TSSSR_SS ((uint32_t)0x0003FFFF)
-
-/******************** Bits definition for RTC_CALR register ******************/
-#define RTC_CALR_CALP ((uint32_t)0x00008000)
-#define RTC_CALR_CALW8 ((uint32_t)0x00004000)
-#define RTC_CALR_CALW16 ((uint32_t)0x00002000)
-#define RTC_CALR_CALM ((uint32_t)0x000001FF)
-#define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
-#define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
-#define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
-#define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
-#define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
-#define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
-#define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
-#define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
-#define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
-
-/* Old Bits definition for RTC_CAL register maintained for legacy purpose */
-#define RTC_CAL_CALP RTC_CALR_CALP
-#define RTC_CAL_CALW8 RTC_CALR_CALW8
-#define RTC_CAL_CALW16 RTC_CALR_CALW16
-#define RTC_CAL_CALM RTC_CALR_CALM
-#define RTC_CAL_CALM_0 RTC_CALR_CALM_0
-#define RTC_CAL_CALM_1 RTC_CALR_CALM_1
-#define RTC_CAL_CALM_2 RTC_CALR_CALM_2
-#define RTC_CAL_CALM_3 RTC_CALR_CALM_3
-#define RTC_CAL_CALM_4 RTC_CALR_CALM_4
-#define RTC_CAL_CALM_5 RTC_CALR_CALM_5
-#define RTC_CAL_CALM_6 RTC_CALR_CALM_6
-#define RTC_CAL_CALM_7 RTC_CALR_CALM_7
-#define RTC_CAL_CALM_8 RTC_CALR_CALM_8
-
-/******************** Bits definition for RTC_TAFCR register ****************/
-#define RTC_TAFCR_PC15MODE ((uint32_t)0x00800000)
-#define RTC_TAFCR_PC15VALUE ((uint32_t)0x00400000)
-#define RTC_TAFCR_PC14MODE ((uint32_t)0x00200000)
-#define RTC_TAFCR_PC14VALUE ((uint32_t)0x00100000)
-#define RTC_TAFCR_PC13MODE ((uint32_t)0x00080000)
-#define RTC_TAFCR_PC13VALUE ((uint32_t)0x00040000)
-#define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
-#define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
-#define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
-#define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
-#define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
-#define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
-#define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
-#define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
-#define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
-#define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
-#define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
-#define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
-#define RTC_TAFCR_TAMP3EDGE ((uint32_t)0x00000040)
-#define RTC_TAFCR_TAMP3E ((uint32_t)0x00000020)
-#define RTC_TAFCR_TAMP2EDGE ((uint32_t)0x00000010)
-#define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008)
-#define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
-#define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
-#define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
-
-/* Old bit definition maintained for legacy purpose */
-#define RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_PC13VALUE
-
-/******************** Bits definition for RTC_ALRMASSR register *************/
-#define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
-#define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
-#define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
-#define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
-#define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
-#define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
-
-/******************** Bits definition for RTC_BKP0R register ****************/
-#define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
-
-/******************** Bits definition for RTC_BKP1R register ****************/
-#define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
-
-/******************** Bits definition for RTC_BKP2R register ****************/
-#define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
-
-/******************** Bits definition for RTC_BKP3R register ****************/
-#define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
-
-/******************** Bits definition for RTC_BKP4R register ****************/
-#define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
-
-/******************************************************************************/
-/* */
-/* Serial Peripheral Interface (SPI) */
-/* */
-/******************************************************************************/
-/******************* Bit definition for SPI_CR1 register ********************/
-#define SPI_CR1_CPHA ((uint16_t)0x0001) /*!< Clock Phase */
-#define SPI_CR1_CPOL ((uint16_t)0x0002) /*!< Clock Polarity */
-#define SPI_CR1_MSTR ((uint16_t)0x0004) /*!< Master Selection */
-#define SPI_CR1_BR ((uint16_t)0x0038) /*!< BR[2:0] bits (Baud Rate Control) */
-#define SPI_CR1_BR_0 ((uint16_t)0x0008) /*!< Bit 0 */
-#define SPI_CR1_BR_1 ((uint16_t)0x0010) /*!< Bit 1 */
-#define SPI_CR1_BR_2 ((uint16_t)0x0020) /*!< Bit 2 */
-#define SPI_CR1_SPE ((uint16_t)0x0040) /*!< SPI Enable */
-#define SPI_CR1_LSBFIRST ((uint16_t)0x0080) /*!< Frame Format */
-#define SPI_CR1_SSI ((uint16_t)0x0100) /*!< Internal slave select */
-#define SPI_CR1_SSM ((uint16_t)0x0200) /*!< Software slave management */
-#define SPI_CR1_RXONLY ((uint16_t)0x0400) /*!< Receive only */
-#define SPI_CR1_CRCL ((uint16_t)0x0800) /*!< CRC Length */
-#define SPI_CR1_CRCNEXT ((uint16_t)0x1000) /*!< Transmit CRC next */
-#define SPI_CR1_CRCEN ((uint16_t)0x2000) /*!< Hardware CRC calculation enable */
-#define SPI_CR1_BIDIOE ((uint16_t)0x4000) /*!< Output enable in bidirectional mode */
-#define SPI_CR1_BIDIMODE ((uint16_t)0x8000) /*!< Bidirectional data mode enable */
-
-/******************* Bit definition for SPI_CR2 register ********************/
-#define SPI_CR2_RXDMAEN ((uint16_t)0x0001) /*!< Rx Buffer DMA Enable */
-#define SPI_CR2_TXDMAEN ((uint16_t)0x0002) /*!< Tx Buffer DMA Enable */
-#define SPI_CR2_SSOE ((uint16_t)0x0004) /*!< SS Output Enable */
-#define SPI_CR2_NSSP ((uint16_t)0x0008) /*!< NSS pulse management Enable */
-#define SPI_CR2_FRF ((uint16_t)0x0010) /*!< Frame Format Enable */
-#define SPI_CR2_ERRIE ((uint16_t)0x0020) /*!< Error Interrupt Enable */
-#define SPI_CR2_RXNEIE ((uint16_t)0x0040) /*!< RX buffer Not Empty Interrupt Enable */
-#define SPI_CR2_TXEIE ((uint16_t)0x0080) /*!< Tx buffer Empty Interrupt Enable */
-#define SPI_CR2_DS ((uint16_t)0x0F00) /*!< DS[3:0] Data Size */
-#define SPI_CR2_DS_0 ((uint16_t)0x0100) /*!< Bit 0 */
-#define SPI_CR2_DS_1 ((uint16_t)0x0200) /*!< Bit 1 */
-#define SPI_CR2_DS_2 ((uint16_t)0x0400) /*!< Bit 2 */
-#define SPI_CR2_DS_3 ((uint16_t)0x0800) /*!< Bit 3 */
-#define SPI_CR2_FRXTH ((uint16_t)0x1000) /*!< FIFO reception Threshold */
-#define SPI_CR2_LDMARX ((uint16_t)0x2000) /*!< Last DMA transfer for reception */
-#define SPI_CR2_LDMATX ((uint16_t)0x4000) /*!< Last DMA transfer for transmission */
-
-/******************** Bit definition for SPI_SR register ********************/
-#define SPI_SR_RXNE ((uint16_t)0x0001) /*!< Receive buffer Not Empty */
-#define SPI_SR_TXE ((uint16_t)0x0002) /*!< Transmit buffer Empty */
-#define SPI_SR_CHSIDE ((uint16_t)0x0004) /*!< Channel side */
-#define SPI_SR_UDR ((uint16_t)0x0008) /*!< Underrun flag */
-#define SPI_SR_CRCERR ((uint16_t)0x0010) /*!< CRC Error flag */
-#define SPI_SR_MODF ((uint16_t)0x0020) /*!< Mode fault */
-#define SPI_SR_OVR ((uint16_t)0x0040) /*!< Overrun flag */
-#define SPI_SR_BSY ((uint16_t)0x0080) /*!< Busy flag */
-#define SPI_SR_FRE ((uint16_t)0x0100) /*!< TI frame format error */
-#define SPI_SR_FRLVL ((uint16_t)0x0600) /*!< FIFO Reception Level */
-#define SPI_SR_FRLVL_0 ((uint16_t)0x0200) /*!< Bit 0 */
-#define SPI_SR_FRLVL_1 ((uint16_t)0x0400) /*!< Bit 1 */
-#define SPI_SR_FTLVL ((uint16_t)0x1800) /*!< FIFO Transmission Level */
-#define SPI_SR_FTLVL_0 ((uint16_t)0x0800) /*!< Bit 0 */
-#define SPI_SR_FTLVL_1 ((uint16_t)0x1000) /*!< Bit 1 */
-
-/******************** Bit definition for SPI_DR register ********************/
-#define SPI_DR_DR ((uint16_t)0xFFFF) /*!< Data Register */
-
-/******************* Bit definition for SPI_CRCPR register ******************/
-#define SPI_CRCPR_CRCPOLY ((uint16_t)0xFFFF) /*!< CRC polynomial register */
-
-/****************** Bit definition for SPI_RXCRCR register ******************/
-#define SPI_RXCRCR_RXCRC ((uint16_t)0xFFFF) /*!< Rx CRC Register */
-
-/****************** Bit definition for SPI_TXCRCR register ******************/
-#define SPI_TXCRCR_TXCRC ((uint16_t)0xFFFF) /*!< Tx CRC Register */
-
-/****************** Bit definition for SPI_I2SCFGR register *****************/
-#define SPI_I2SCFGR_CHLEN ((uint16_t)0x0001) /*!<Channel length (number of bits per audio channel) */
-#define SPI_I2SCFGR_DATLEN ((uint16_t)0x0006) /*!<DATLEN[1:0] bits (Data length to be transferred) */
-#define SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002) /*!<Bit 0 */
-#define SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004) /*!<Bit 1 */
-#define SPI_I2SCFGR_CKPOL ((uint16_t)0x0008) /*!<steady state clock polarity */
-#define SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030) /*!<I2SSTD[1:0] bits (I2S standard selection) */
-#define SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010) /*!<Bit 0 */
-#define SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020) /*!<Bit 1 */
-#define SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080) /*!<PCM frame synchronization */
-#define SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
-#define SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100) /*!<Bit 0 */
-#define SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200) /*!<Bit 1 */
-#define SPI_I2SCFGR_I2SE ((uint16_t)0x0400) /*!<I2S Enable */
-#define SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800) /*!<I2S mode selection */
-
-/****************** Bit definition for SPI_I2SPR register *******************/
-#define SPI_I2SPR_I2SDIV ((uint16_t)0x00FF) /*!<I2S Linear prescaler */
-#define SPI_I2SPR_ODD ((uint16_t)0x0100) /*!<Odd factor for the prescaler */
-#define SPI_I2SPR_MCKOE ((uint16_t)0x0200) /*!<Master Clock Output Enable */
-
-/******************************************************************************/
-/* */
-/* System Configuration (SYSCFG) */
-/* */
-/******************************************************************************/
-/***************** Bit definition for SYSCFG_CFGR1 register ****************/
-#define SYSCFG_CFGR1_MEM_MODE ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */
-#define SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001) /*!< SYSCFG_Memory Remap Config Bit 0 */
-#define SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002) /*!< SYSCFG_Memory Remap Config Bit 1 */
-#define SYSCFG_CFGR1_PA11_PA12_RMP ((uint32_t)0x00000010) /*!< PA11 and PA12 remap on QFN28 and TSSOP20 packages (only for STM32F042 devices)*/
-#define SYSCFG_CFGR1_ADC_DMA_RMP ((uint32_t)0x00000100) /*!< ADC DMA remap */
-#define SYSCFG_CFGR1_USART1TX_DMA_RMP ((uint32_t)0x00000200) /*!< USART1 TX DMA remap */
-#define SYSCFG_CFGR1_USART1RX_DMA_RMP ((uint32_t)0x00000400) /*!< USART1 RX DMA remap */
-#define SYSCFG_CFGR1_TIM16_DMA_RMP ((uint32_t)0x00000800) /*!< Timer 16 DMA remap */
-#define SYSCFG_CFGR1_TIM17_DMA_RMP ((uint32_t)0x00001000) /*!< Timer 17 DMA remap */
-#define SYSCFG_CFGR1_TIM16_DMA_RMP2 ((uint32_t)0x00002000) /*!< Timer 16 DMA remap 2 (only for STM32F072) */
-#define SYSCFG_CFGR1_TIM17_DMA_RMP2 ((uint32_t)0x00004000) /*!< Timer 17 DMA remap 2 (only for STM32F072) */
-#define SYSCFG_CFGR1_I2C_FMP_PB6 ((uint32_t)0x00010000) /*!< I2C PB6 Fast mode plus */
-#define SYSCFG_CFGR1_I2C_FMP_PB7 ((uint32_t)0x00020000) /*!< I2C PB7 Fast mode plus */
-#define SYSCFG_CFGR1_I2C_FMP_PB8 ((uint32_t)0x00040000) /*!< I2C PB8 Fast mode plus */
-#define SYSCFG_CFGR1_I2C_FMP_PB9 ((uint32_t)0x00080000) /*!< I2C PB9 Fast mode plus */
-#define SYSCFG_CFGR1_I2C_FMP_I2C1 ((uint32_t)0x00100000) /*!< Enable Fast Mode Plus on PB10, PB11, PF6 and PF7(only for STM32F030, STM32F031 and STM32F072 devices) */
-#define SYSCFG_CFGR1_I2C_FMP_I2C2 ((uint32_t)0x00200000) /*!< Enable I2C2 Fast mode plus (only for STM32F072) */
-#define SYSCFG_CFGR1_I2C_FMP_PA9 ((uint32_t)0x00400000) /*!< Enable Fast Mode Plus on PA9 (only for STM32F030, STM32F031, STM32F042 and STM32F072 devices) */
-#define SYSCFG_CFGR1_I2C_FMP_PA10 ((uint32_t)0x00800000) /*!< Enable Fast Mode Plus on PA10(only for STM32F030, STM32F031, STM32F042 and STM32F072 devices) */
-#define SYSCFG_CFGR1_SPI2_DMA_RMP ((uint32_t)0x01000000) /*!< SPI2 DMA remap (only for STM32F072) */
-#define SYSCFG_CFGR1_USART2_DMA_RMP ((uint32_t)0x02000000) /*!< USART2 DMA remap (only for STM32F072) */
-#define SYSCFG_CFGR1_USART3_DMA_RMP ((uint32_t)0x04000000) /*!< USART3 DMA remap (only for STM32F072) */
-#define SYSCFG_CFGR1_I2C1_DMA_RMP ((uint32_t)0x08000000) /*!< I2C1 DMA remap (only for STM32F072) */
-#define SYSCFG_CFGR1_TIM1_DMA_RMP ((uint32_t)0x10000000) /*!< TIM1 DMA remap (only for STM32F072) */
-#define SYSCFG_CFGR1_TIM2_DMA_RMP ((uint32_t)0x20000000) /*!< TIM2 DMA remap (only for STM32F072) */
-#define SYSCFG_CFGR1_TIM3_DMA_RMP ((uint32_t)0x40000000) /*!< TIM3 DMA remap (only for STM32F072) */
-
-/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
-#define SYSCFG_EXTICR1_EXTI0 ((uint16_t)0x000F) /*!< EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1 ((uint16_t)0x00F0) /*!< EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2 ((uint16_t)0x0F00) /*!< EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3 ((uint16_t)0xF000) /*!< EXTI 3 configuration */
-
-/**
- * @brief EXTI0 configuration
- */
-#define SYSCFG_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /*!< PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /*!< PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /*!< PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /*!< PD[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /*!< PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /*!< PF[0] pin */
-
-/**
- * @brief EXTI1 configuration
- */
-#define SYSCFG_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /*!< PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /*!< PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /*!< PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /*!< PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /*!< PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /*!< PF[1] pin */
-
-/**
- * @brief EXTI2 configuration
- */
-#define SYSCFG_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /*!< PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /*!< PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /*!< PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /*!< PD[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /*!< PE[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /*!< PF[2] pin */
-
-/**
- * @brief EXTI3 configuration
- */
-#define SYSCFG_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /*!< PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /*!< PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /*!< PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /*!< PD[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /*!< PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /*!< PF[3] pin */
-
-/***************** Bit definition for SYSCFG_EXTICR2 register *****************/
-#define SYSCFG_EXTICR2_EXTI4 ((uint16_t)0x000F) /*!< EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5 ((uint16_t)0x00F0) /*!< EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6 ((uint16_t)0x0F00) /*!< EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7 ((uint16_t)0xF000) /*!< EXTI 7 configuration */
-
-/**
- * @brief EXTI4 configuration
- */
-#define SYSCFG_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /*!< PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /*!< PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /*!< PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /*!< PD[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PE ((uint16_t)0x0004) /*!< PE[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /*!< PF[4] pin */
-
-/**
- * @brief EXTI5 configuration
- */
-#define SYSCFG_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /*!< PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /*!< PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /*!< PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /*!< PD[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PE ((uint16_t)0x0040) /*!< PE[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /*!< PF[5] pin */
-
-/**
- * @brief EXTI6 configuration
- */
-#define SYSCFG_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /*!< PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /*!< PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /*!< PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /*!< PD[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PE ((uint16_t)0x0400) /*!< PE[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /*!< PF[6] pin */
-
-/**
- * @brief EXTI7 configuration
- */
-#define SYSCFG_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /*!< PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /*!< PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /*!< PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /*!< PD[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PE ((uint16_t)0x4000) /*!< PE[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /*!< PF[7] pin */
-
-/***************** Bit definition for SYSCFG_EXTICR3 register *****************/
-#define SYSCFG_EXTICR3_EXTI8 ((uint16_t)0x000F) /*!< EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9 ((uint16_t)0x00F0) /*!< EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10 ((uint16_t)0x0F00) /*!< EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11 ((uint16_t)0xF000) /*!< EXTI 11 configuration */
-
-/**
- * @brief EXTI8 configuration
- */
-#define SYSCFG_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /*!< PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /*!< PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /*!< PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /*!< PD[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /*!< PE[8] pin */
-
-/**
- * @brief EXTI9 configuration
- */
-#define SYSCFG_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /*!< PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /*!< PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /*!< PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /*!< PD[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /*!< PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /*!< PF[9] pin */
-
-/**
- * @brief EXTI10 configuration
- */
-#define SYSCFG_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /*!< PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /*!< PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /*!< PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /*!< PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /*!< PD[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /*!< PF[10] pin */
-
-/**
- * @brief EXTI11 configuration
- */
-#define SYSCFG_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /*!< PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /*!< PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /*!< PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /*!< PD[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /*!< PE[11] pin */
-
-/***************** Bit definition for SYSCFG_EXTICR4 register *****************/
-#define SYSCFG_EXTICR4_EXTI12 ((uint16_t)0x000F) /*!< EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13 ((uint16_t)0x00F0) /*!< EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14 ((uint16_t)0x0F00) /*!< EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15 ((uint16_t)0xF000) /*!< EXTI 15 configuration */
-
-/**
- * @brief EXTI12 configuration
- */
-#define SYSCFG_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /*!< PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /*!< PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /*!< PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /*!< PD[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /*!< PE[12] pin */
-
-/**
- * @brief EXTI13 configuration
- */
-#define SYSCFG_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /*!< PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /*!< PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /*!< PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /*!< PD[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /*!< PE[13] pin */
-
-/**
- * @brief EXTI14 configuration
- */
-#define SYSCFG_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /*!< PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /*!< PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /*!< PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /*!< PD[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /*!< PE[14] pin */
-
-/**
- * @brief EXTI15 configuration
- */
-#define SYSCFG_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /*!< PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /*!< PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /*!< PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /*!< PD[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /*!< PE[15] pin */
-
-/***************** Bit definition for SYSCFG_CFGR2 register ****************/
-#define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the PVD connection with Timer1 Break Input and also the PVD_EN and PVDSEL[2:0] bits of the Power Control Interface */
-#define SYSCFG_CFGR2_SRAM_PARITY_LOCK ((uint32_t)0x00000002) /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1 */
-#define SYSCFG_CFGR2_PVD_LOCK ((uint32_t)0x00000004) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIMER1 */
-#define SYSCFG_CFGR2_SRAM_PEF ((uint32_t)0x00000100) /*!< SRAM Parity error flag */
-
-/* Old Bit definition maintained for legacy purpose */
-#define SYSCFG_CFGR2_SRAM_PE SYSCFG_CFGR2_SRAM_PEF
-/******************************************************************************/
-/* */
-/* Timers (TIM) */
-/* */
-/******************************************************************************/
-/******************* Bit definition for TIM_CR1 register ********************/
-#define TIM_CR1_CEN ((uint16_t)0x0001) /*!<Counter enable */
-#define TIM_CR1_UDIS ((uint16_t)0x0002) /*!<Update disable */
-#define TIM_CR1_URS ((uint16_t)0x0004) /*!<Update request source */
-#define TIM_CR1_OPM ((uint16_t)0x0008) /*!<One pulse mode */
-#define TIM_CR1_DIR ((uint16_t)0x0010) /*!<Direction */
-
-#define TIM_CR1_CMS ((uint16_t)0x0060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define TIM_CR1_CMS_0 ((uint16_t)0x0020) /*!<Bit 0 */
-#define TIM_CR1_CMS_1 ((uint16_t)0x0040) /*!<Bit 1 */
-
-#define TIM_CR1_ARPE ((uint16_t)0x0080) /*!<Auto-reload preload enable */
-
-#define TIM_CR1_CKD ((uint16_t)0x0300) /*!<CKD[1:0] bits (clock division) */
-#define TIM_CR1_CKD_0 ((uint16_t)0x0100) /*!<Bit 0 */
-#define TIM_CR1_CKD_1 ((uint16_t)0x0200) /*!<Bit 1 */
-
-/******************* Bit definition for TIM_CR2 register ********************/
-#define TIM_CR2_CCPC ((uint16_t)0x0001) /*!<Capture/Compare Preloaded Control */
-#define TIM_CR2_CCUS ((uint16_t)0x0004) /*!<Capture/Compare Control Update Selection */
-#define TIM_CR2_CCDS ((uint16_t)0x0008) /*!<Capture/Compare DMA Selection */
-
-#define TIM_CR2_MMS ((uint16_t)0x0070) /*!<MMS[2:0] bits (Master Mode Selection) */
-#define TIM_CR2_MMS_0 ((uint16_t)0x0010) /*!<Bit 0 */
-#define TIM_CR2_MMS_1 ((uint16_t)0x0020) /*!<Bit 1 */
-#define TIM_CR2_MMS_2 ((uint16_t)0x0040) /*!<Bit 2 */
-
-#define TIM_CR2_TI1S ((uint16_t)0x0080) /*!<TI1 Selection */
-#define TIM_CR2_OIS1 ((uint16_t)0x0100) /*!<Output Idle state 1 (OC1 output) */
-#define TIM_CR2_OIS1N ((uint16_t)0x0200) /*!<Output Idle state 1 (OC1N output) */
-#define TIM_CR2_OIS2 ((uint16_t)0x0400) /*!<Output Idle state 2 (OC2 output) */
-#define TIM_CR2_OIS2N ((uint16_t)0x0800) /*!<Output Idle state 2 (OC2N output) */
-#define TIM_CR2_OIS3 ((uint16_t)0x1000) /*!<Output Idle state 3 (OC3 output) */
-#define TIM_CR2_OIS3N ((uint16_t)0x2000) /*!<Output Idle state 3 (OC3N output) */
-#define TIM_CR2_OIS4 ((uint16_t)0x4000) /*!<Output Idle state 4 (OC4 output) */
-
-/******************* Bit definition for TIM_SMCR register *******************/
-#define TIM_SMCR_SMS ((uint16_t)0x0007) /*!<SMS[2:0] bits (Slave mode selection) */
-#define TIM_SMCR_SMS_0 ((uint16_t)0x0001) /*!<Bit 0 */
-#define TIM_SMCR_SMS_1 ((uint16_t)0x0002) /*!<Bit 1 */
-#define TIM_SMCR_SMS_2 ((uint16_t)0x0004) /*!<Bit 2 */
-
-#define TIM_SMCR_OCCS ((uint16_t)0x0008) /*!< OCREF clear selection */
-
-#define TIM_SMCR_TS ((uint16_t)0x0070) /*!<TS[2:0] bits (Trigger selection) */
-#define TIM_SMCR_TS_0 ((uint16_t)0x0010) /*!<Bit 0 */
-#define TIM_SMCR_TS_1 ((uint16_t)0x0020) /*!<Bit 1 */
-#define TIM_SMCR_TS_2 ((uint16_t)0x0040) /*!<Bit 2 */
-
-#define TIM_SMCR_MSM ((uint16_t)0x0080) /*!<Master/slave mode */
-
-#define TIM_SMCR_ETF ((uint16_t)0x0F00) /*!<ETF[3:0] bits (External trigger filter) */
-#define TIM_SMCR_ETF_0 ((uint16_t)0x0100) /*!<Bit 0 */
-#define TIM_SMCR_ETF_1 ((uint16_t)0x0200) /*!<Bit 1 */
-#define TIM_SMCR_ETF_2 ((uint16_t)0x0400) /*!<Bit 2 */
-#define TIM_SMCR_ETF_3 ((uint16_t)0x0800) /*!<Bit 3 */
-
-#define TIM_SMCR_ETPS ((uint16_t)0x3000) /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define TIM_SMCR_ETPS_0 ((uint16_t)0x1000) /*!<Bit 0 */
-#define TIM_SMCR_ETPS_1 ((uint16_t)0x2000) /*!<Bit 1 */
-
-#define TIM_SMCR_ECE ((uint16_t)0x4000) /*!<External clock enable */
-#define TIM_SMCR_ETP ((uint16_t)0x8000) /*!<External trigger polarity */
-
-/******************* Bit definition for TIM_DIER register *******************/
-#define TIM_DIER_UIE ((uint16_t)0x0001) /*!<Update interrupt enable */
-#define TIM_DIER_CC1IE ((uint16_t)0x0002) /*!<Capture/Compare 1 interrupt enable */
-#define TIM_DIER_CC2IE ((uint16_t)0x0004) /*!<Capture/Compare 2 interrupt enable */
-#define TIM_DIER_CC3IE ((uint16_t)0x0008) /*!<Capture/Compare 3 interrupt enable */
-#define TIM_DIER_CC4IE ((uint16_t)0x0010) /*!<Capture/Compare 4 interrupt enable */
-#define TIM_DIER_COMIE ((uint16_t)0x0020) /*!<COM interrupt enable */
-#define TIM_DIER_TIE ((uint16_t)0x0040) /*!<Trigger interrupt enable */
-#define TIM_DIER_BIE ((uint16_t)0x0080) /*!<Break interrupt enable */
-#define TIM_DIER_UDE ((uint16_t)0x0100) /*!<Update DMA request enable */
-#define TIM_DIER_CC1DE ((uint16_t)0x0200) /*!<Capture/Compare 1 DMA request enable */
-#define TIM_DIER_CC2DE ((uint16_t)0x0400) /*!<Capture/Compare 2 DMA request enable */
-#define TIM_DIER_CC3DE ((uint16_t)0x0800) /*!<Capture/Compare 3 DMA request enable */
-#define TIM_DIER_CC4DE ((uint16_t)0x1000) /*!<Capture/Compare 4 DMA request enable */
-#define TIM_DIER_COMDE ((uint16_t)0x2000) /*!<COM DMA request enable */
-#define TIM_DIER_TDE ((uint16_t)0x4000) /*!<Trigger DMA request enable */
-
-/******************** Bit definition for TIM_SR register ********************/
-#define TIM_SR_UIF ((uint16_t)0x0001) /*!<Update interrupt Flag */
-#define TIM_SR_CC1IF ((uint16_t)0x0002) /*!<Capture/Compare 1 interrupt Flag */
-#define TIM_SR_CC2IF ((uint16_t)0x0004) /*!<Capture/Compare 2 interrupt Flag */
-#define TIM_SR_CC3IF ((uint16_t)0x0008) /*!<Capture/Compare 3 interrupt Flag */
-#define TIM_SR_CC4IF ((uint16_t)0x0010) /*!<Capture/Compare 4 interrupt Flag */
-#define TIM_SR_COMIF ((uint16_t)0x0020) /*!<COM interrupt Flag */
-#define TIM_SR_TIF ((uint16_t)0x0040) /*!<Trigger interrupt Flag */
-#define TIM_SR_BIF ((uint16_t)0x0080) /*!<Break interrupt Flag */
-#define TIM_SR_CC1OF ((uint16_t)0x0200) /*!<Capture/Compare 1 Overcapture Flag */
-#define TIM_SR_CC2OF ((uint16_t)0x0400) /*!<Capture/Compare 2 Overcapture Flag */
-#define TIM_SR_CC3OF ((uint16_t)0x0800) /*!<Capture/Compare 3 Overcapture Flag */
-#define TIM_SR_CC4OF ((uint16_t)0x1000) /*!<Capture/Compare 4 Overcapture Flag */
-
-/******************* Bit definition for TIM_EGR register ********************/
-#define TIM_EGR_UG ((uint8_t)0x01) /*!<Update Generation */
-#define TIM_EGR_CC1G ((uint8_t)0x02) /*!<Capture/Compare 1 Generation */
-#define TIM_EGR_CC2G ((uint8_t)0x04) /*!<Capture/Compare 2 Generation */
-#define TIM_EGR_CC3G ((uint8_t)0x08) /*!<Capture/Compare 3 Generation */
-#define TIM_EGR_CC4G ((uint8_t)0x10) /*!<Capture/Compare 4 Generation */
-#define TIM_EGR_COMG ((uint8_t)0x20) /*!<Capture/Compare Control Update Generation */
-#define TIM_EGR_TG ((uint8_t)0x40) /*!<Trigger Generation */
-#define TIM_EGR_BG ((uint8_t)0x80) /*!<Break Generation */
-
-/****************** Bit definition for TIM_CCMR1 register *******************/
-#define TIM_CCMR1_CC1S ((uint16_t)0x0003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define TIM_CCMR1_CC1S_0 ((uint16_t)0x0001) /*!<Bit 0 */
-#define TIM_CCMR1_CC1S_1 ((uint16_t)0x0002) /*!<Bit 1 */
-
-#define TIM_CCMR1_OC1FE ((uint16_t)0x0004) /*!<Output Compare 1 Fast enable */
-#define TIM_CCMR1_OC1PE ((uint16_t)0x0008) /*!<Output Compare 1 Preload enable */
-
-#define TIM_CCMR1_OC1M ((uint16_t)0x0070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
-#define TIM_CCMR1_OC1M_0 ((uint16_t)0x0010) /*!<Bit 0 */
-#define TIM_CCMR1_OC1M_1 ((uint16_t)0x0020) /*!<Bit 1 */
-#define TIM_CCMR1_OC1M_2 ((uint16_t)0x0040) /*!<Bit 2 */
-
-#define TIM_CCMR1_OC1CE ((uint16_t)0x0080) /*!<Output Compare 1Clear Enable */
-
-#define TIM_CCMR1_CC2S ((uint16_t)0x0300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define TIM_CCMR1_CC2S_0 ((uint16_t)0x0100) /*!<Bit 0 */
-#define TIM_CCMR1_CC2S_1 ((uint16_t)0x0200) /*!<Bit 1 */
-
-#define TIM_CCMR1_OC2FE ((uint16_t)0x0400) /*!<Output Compare 2 Fast enable */
-#define TIM_CCMR1_OC2PE ((uint16_t)0x0800) /*!<Output Compare 2 Preload enable */
-
-#define TIM_CCMR1_OC2M ((uint16_t)0x7000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
-#define TIM_CCMR1_OC2M_0 ((uint16_t)0x1000) /*!<Bit 0 */
-#define TIM_CCMR1_OC2M_1 ((uint16_t)0x2000) /*!<Bit 1 */
-#define TIM_CCMR1_OC2M_2 ((uint16_t)0x4000) /*!<Bit 2 */
-
-#define TIM_CCMR1_OC2CE ((uint16_t)0x8000) /*!<Output Compare 2 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define TIM_CCMR1_IC1PSC ((uint16_t)0x000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define TIM_CCMR1_IC1PSC_0 ((uint16_t)0x0004) /*!<Bit 0 */
-#define TIM_CCMR1_IC1PSC_1 ((uint16_t)0x0008) /*!<Bit 1 */
-
-#define TIM_CCMR1_IC1F ((uint16_t)0x00F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
-#define TIM_CCMR1_IC1F_0 ((uint16_t)0x0010) /*!<Bit 0 */
-#define TIM_CCMR1_IC1F_1 ((uint16_t)0x0020) /*!<Bit 1 */
-#define TIM_CCMR1_IC1F_2 ((uint16_t)0x0040) /*!<Bit 2 */
-#define TIM_CCMR1_IC1F_3 ((uint16_t)0x0080) /*!<Bit 3 */
-
-#define TIM_CCMR1_IC2PSC ((uint16_t)0x0C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
-#define TIM_CCMR1_IC2PSC_0 ((uint16_t)0x0400) /*!<Bit 0 */
-#define TIM_CCMR1_IC2PSC_1 ((uint16_t)0x0800) /*!<Bit 1 */
-
-#define TIM_CCMR1_IC2F ((uint16_t)0xF000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
-#define TIM_CCMR1_IC2F_0 ((uint16_t)0x1000) /*!<Bit 0 */
-#define TIM_CCMR1_IC2F_1 ((uint16_t)0x2000) /*!<Bit 1 */
-#define TIM_CCMR1_IC2F_2 ((uint16_t)0x4000) /*!<Bit 2 */
-#define TIM_CCMR1_IC2F_3 ((uint16_t)0x8000) /*!<Bit 3 */
-
-/****************** Bit definition for TIM_CCMR2 register *******************/
-#define TIM_CCMR2_CC3S ((uint16_t)0x0003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
-#define TIM_CCMR2_CC3S_0 ((uint16_t)0x0001) /*!<Bit 0 */
-#define TIM_CCMR2_CC3S_1 ((uint16_t)0x0002) /*!<Bit 1 */
-
-#define TIM_CCMR2_OC3FE ((uint16_t)0x0004) /*!<Output Compare 3 Fast enable */
-#define TIM_CCMR2_OC3PE ((uint16_t)0x0008) /*!<Output Compare 3 Preload enable */
-
-#define TIM_CCMR2_OC3M ((uint16_t)0x0070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define TIM_CCMR2_OC3M_0 ((uint16_t)0x0010) /*!<Bit 0 */
-#define TIM_CCMR2_OC3M_1 ((uint16_t)0x0020) /*!<Bit 1 */
-#define TIM_CCMR2_OC3M_2 ((uint16_t)0x0040) /*!<Bit 2 */
-
-#define TIM_CCMR2_OC3CE ((uint16_t)0x0080) /*!<Output Compare 3 Clear Enable */
-
-#define TIM_CCMR2_CC4S ((uint16_t)0x0300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define TIM_CCMR2_CC4S_0 ((uint16_t)0x0100) /*!<Bit 0 */
-#define TIM_CCMR2_CC4S_1 ((uint16_t)0x0200) /*!<Bit 1 */
-
-#define TIM_CCMR2_OC4FE ((uint16_t)0x0400) /*!<Output Compare 4 Fast enable */
-#define TIM_CCMR2_OC4PE ((uint16_t)0x0800) /*!<Output Compare 4 Preload enable */
-
-#define TIM_CCMR2_OC4M ((uint16_t)0x7000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define TIM_CCMR2_OC4M_0 ((uint16_t)0x1000) /*!<Bit 0 */
-#define TIM_CCMR2_OC4M_1 ((uint16_t)0x2000) /*!<Bit 1 */
-#define TIM_CCMR2_OC4M_2 ((uint16_t)0x4000) /*!<Bit 2 */
-
-#define TIM_CCMR2_OC4CE ((uint16_t)0x8000) /*!<Output Compare 4 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define TIM_CCMR2_IC3PSC ((uint16_t)0x000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define TIM_CCMR2_IC3PSC_0 ((uint16_t)0x0004) /*!<Bit 0 */
-#define TIM_CCMR2_IC3PSC_1 ((uint16_t)0x0008) /*!<Bit 1 */
-
-#define TIM_CCMR2_IC3F ((uint16_t)0x00F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define TIM_CCMR2_IC3F_0 ((uint16_t)0x0010) /*!<Bit 0 */
-#define TIM_CCMR2_IC3F_1 ((uint16_t)0x0020) /*!<Bit 1 */
-#define TIM_CCMR2_IC3F_2 ((uint16_t)0x0040) /*!<Bit 2 */
-#define TIM_CCMR2_IC3F_3 ((uint16_t)0x0080) /*!<Bit 3 */
-
-#define TIM_CCMR2_IC4PSC ((uint16_t)0x0C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define TIM_CCMR2_IC4PSC_0 ((uint16_t)0x0400) /*!<Bit 0 */
-#define TIM_CCMR2_IC4PSC_1 ((uint16_t)0x0800) /*!<Bit 1 */
-
-#define TIM_CCMR2_IC4F ((uint16_t)0xF000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define TIM_CCMR2_IC4F_0 ((uint16_t)0x1000) /*!<Bit 0 */
-#define TIM_CCMR2_IC4F_1 ((uint16_t)0x2000) /*!<Bit 1 */
-#define TIM_CCMR2_IC4F_2 ((uint16_t)0x4000) /*!<Bit 2 */
-#define TIM_CCMR2_IC4F_3 ((uint16_t)0x8000) /*!<Bit 3 */
-
-/******************* Bit definition for TIM_CCER register *******************/
-#define TIM_CCER_CC1E ((uint16_t)0x0001) /*!<Capture/Compare 1 output enable */
-#define TIM_CCER_CC1P ((uint16_t)0x0002) /*!<Capture/Compare 1 output Polarity */
-#define TIM_CCER_CC1NE ((uint16_t)0x0004) /*!<Capture/Compare 1 Complementary output enable */
-#define TIM_CCER_CC1NP ((uint16_t)0x0008) /*!<Capture/Compare 1 Complementary output Polarity */
-#define TIM_CCER_CC2E ((uint16_t)0x0010) /*!<Capture/Compare 2 output enable */
-#define TIM_CCER_CC2P ((uint16_t)0x0020) /*!<Capture/Compare 2 output Polarity */
-#define TIM_CCER_CC2NE ((uint16_t)0x0040) /*!<Capture/Compare 2 Complementary output enable */
-#define TIM_CCER_CC2NP ((uint16_t)0x0080) /*!<Capture/Compare 2 Complementary output Polarity */
-#define TIM_CCER_CC3E ((uint16_t)0x0100) /*!<Capture/Compare 3 output enable */
-#define TIM_CCER_CC3P ((uint16_t)0x0200) /*!<Capture/Compare 3 output Polarity */
-#define TIM_CCER_CC3NE ((uint16_t)0x0400) /*!<Capture/Compare 3 Complementary output enable */
-#define TIM_CCER_CC3NP ((uint16_t)0x0800) /*!<Capture/Compare 3 Complementary output Polarity */
-#define TIM_CCER_CC4E ((uint16_t)0x1000) /*!<Capture/Compare 4 output enable */
-#define TIM_CCER_CC4P ((uint16_t)0x2000) /*!<Capture/Compare 4 output Polarity */
-#define TIM_CCER_CC4NP ((uint16_t)0x8000) /*!<Capture/Compare 4 Complementary output Polarity */
-
-/******************* Bit definition for TIM_CNT register ********************/
-#define TIM_CNT_CNT ((uint16_t)0xFFFF) /*!<Counter Value */
-
-/******************* Bit definition for TIM_PSC register ********************/
-#define TIM_PSC_PSC ((uint16_t)0xFFFF) /*!<Prescaler Value */
-
-/******************* Bit definition for TIM_ARR register ********************/
-#define TIM_ARR_ARR ((uint16_t)0xFFFF) /*!<actual auto-reload Value */
-
-/******************* Bit definition for TIM_RCR register ********************/
-#define TIM_RCR_REP ((uint8_t)0xFF) /*!<Repetition Counter Value */
-
-/******************* Bit definition for TIM_CCR1 register *******************/
-#define TIM_CCR1_CCR1 ((uint16_t)0xFFFF) /*!<Capture/Compare 1 Value */
-
-/******************* Bit definition for TIM_CCR2 register *******************/
-#define TIM_CCR2_CCR2 ((uint16_t)0xFFFF) /*!<Capture/Compare 2 Value */
-
-/******************* Bit definition for TIM_CCR3 register *******************/
-#define TIM_CCR3_CCR3 ((uint16_t)0xFFFF) /*!<Capture/Compare 3 Value */
-
-/******************* Bit definition for TIM_CCR4 register *******************/
-#define TIM_CCR4_CCR4 ((uint16_t)0xFFFF) /*!<Capture/Compare 4 Value */
-
-/******************* Bit definition for TIM_BDTR register *******************/
-#define TIM_BDTR_DTG ((uint16_t)0x00FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
-#define TIM_BDTR_DTG_0 ((uint16_t)0x0001) /*!<Bit 0 */
-#define TIM_BDTR_DTG_1 ((uint16_t)0x0002) /*!<Bit 1 */
-#define TIM_BDTR_DTG_2 ((uint16_t)0x0004) /*!<Bit 2 */
-#define TIM_BDTR_DTG_3 ((uint16_t)0x0008) /*!<Bit 3 */
-#define TIM_BDTR_DTG_4 ((uint16_t)0x0010) /*!<Bit 4 */
-#define TIM_BDTR_DTG_5 ((uint16_t)0x0020) /*!<Bit 5 */
-#define TIM_BDTR_DTG_6 ((uint16_t)0x0040) /*!<Bit 6 */
-#define TIM_BDTR_DTG_7 ((uint16_t)0x0080) /*!<Bit 7 */
-
-#define TIM_BDTR_LOCK ((uint16_t)0x0300) /*!<LOCK[1:0] bits (Lock Configuration) */
-#define TIM_BDTR_LOCK_0 ((uint16_t)0x0100) /*!<Bit 0 */
-#define TIM_BDTR_LOCK_1 ((uint16_t)0x0200) /*!<Bit 1 */
-
-#define TIM_BDTR_OSSI ((uint16_t)0x0400) /*!<Off-State Selection for Idle mode */
-#define TIM_BDTR_OSSR ((uint16_t)0x0800) /*!<Off-State Selection for Run mode */
-#define TIM_BDTR_BKE ((uint16_t)0x1000) /*!<Break enable */
-#define TIM_BDTR_BKP ((uint16_t)0x2000) /*!<Break Polarity */
-#define TIM_BDTR_AOE ((uint16_t)0x4000) /*!<Automatic Output enable */
-#define TIM_BDTR_MOE ((uint16_t)0x8000) /*!<Main Output enable */
-
-/******************* Bit definition for TIM_DCR register ********************/
-#define TIM_DCR_DBA ((uint16_t)0x001F) /*!<DBA[4:0] bits (DMA Base Address) */
-#define TIM_DCR_DBA_0 ((uint16_t)0x0001) /*!<Bit 0 */
-#define TIM_DCR_DBA_1 ((uint16_t)0x0002) /*!<Bit 1 */
-#define TIM_DCR_DBA_2 ((uint16_t)0x0004) /*!<Bit 2 */
-#define TIM_DCR_DBA_3 ((uint16_t)0x0008) /*!<Bit 3 */
-#define TIM_DCR_DBA_4 ((uint16_t)0x0010) /*!<Bit 4 */
-
-#define TIM_DCR_DBL ((uint16_t)0x1F00) /*!<DBL[4:0] bits (DMA Burst Length) */
-#define TIM_DCR_DBL_0 ((uint16_t)0x0100) /*!<Bit 0 */
-#define TIM_DCR_DBL_1 ((uint16_t)0x0200) /*!<Bit 1 */
-#define TIM_DCR_DBL_2 ((uint16_t)0x0400) /*!<Bit 2 */
-#define TIM_DCR_DBL_3 ((uint16_t)0x0800) /*!<Bit 3 */
-#define TIM_DCR_DBL_4 ((uint16_t)0x1000) /*!<Bit 4 */
-
-/******************* Bit definition for TIM_DMAR register *******************/
-#define TIM_DMAR_DMAB ((uint16_t)0xFFFF) /*!<DMA register for burst accesses */
-
-/******************* Bit definition for TIM_OR register *********************/
-#define TIM14_OR_TI1_RMP ((uint16_t)0x0003) /*!<TI1_RMP[1:0] bits (TIM14 Input 4 remap) */
-#define TIM14_OR_TI1_RMP_0 ((uint16_t)0x0001) /*!<Bit 0 */
-#define TIM14_OR_TI1_RMP_1 ((uint16_t)0x0002) /*!<Bit 1 */
-
-
-/******************************************************************************/
-/* */
-/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
-/* */
-/******************************************************************************/
-/****************** Bit definition for USART_CR1 register *******************/
-#define USART_CR1_UE ((uint32_t)0x00000001) /*!< USART Enable */
-#define USART_CR1_UESM ((uint32_t)0x00000002) /*!< USART Enable in STOP Mode */
-#define USART_CR1_RE ((uint32_t)0x00000004) /*!< Receiver Enable */
-#define USART_CR1_TE ((uint32_t)0x00000008) /*!< Transmitter Enable */
-#define USART_CR1_IDLEIE ((uint32_t)0x00000010) /*!< IDLE Interrupt Enable */
-#define USART_CR1_RXNEIE ((uint32_t)0x00000020) /*!< RXNE Interrupt Enable */
-#define USART_CR1_TCIE ((uint32_t)0x00000040) /*!< Transmission Complete Interrupt Enable */
-#define USART_CR1_TXEIE ((uint32_t)0x00000080) /*!< TXE Interrupt Enable */
-#define USART_CR1_PEIE ((uint32_t)0x00000100) /*!< PE Interrupt Enable */
-#define USART_CR1_PS ((uint32_t)0x00000200) /*!< Parity Selection */
-#define USART_CR1_PCE ((uint32_t)0x00000400) /*!< Parity Control Enable */
-#define USART_CR1_WAKE ((uint32_t)0x00000800) /*!< Receiver Wakeup method */
-#define USART_CR1_M ((uint32_t)0x00001000) /*!< Word length */
-#define USART_CR1_MME ((uint32_t)0x00002000) /*!< Mute Mode Enable */
-#define USART_CR1_CMIE ((uint32_t)0x00004000) /*!< Character match interrupt enable */
-#define USART_CR1_OVER8 ((uint32_t)0x00008000) /*!< Oversampling by 8-bit or 16-bit mode */
-#define USART_CR1_DEDT ((uint32_t)0x001F0000) /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
-#define USART_CR1_DEDT_0 ((uint32_t)0x00010000) /*!< Bit 0 */
-#define USART_CR1_DEDT_1 ((uint32_t)0x00020000) /*!< Bit 1 */
-#define USART_CR1_DEDT_2 ((uint32_t)0x00040000) /*!< Bit 2 */
-#define USART_CR1_DEDT_3 ((uint32_t)0x00080000) /*!< Bit 3 */
-#define USART_CR1_DEDT_4 ((uint32_t)0x00100000) /*!< Bit 4 */
-#define USART_CR1_DEAT ((uint32_t)0x03E00000) /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
-#define USART_CR1_DEAT_0 ((uint32_t)0x00200000) /*!< Bit 0 */
-#define USART_CR1_DEAT_1 ((uint32_t)0x00400000) /*!< Bit 1 */
-#define USART_CR1_DEAT_2 ((uint32_t)0x00800000) /*!< Bit 2 */
-#define USART_CR1_DEAT_3 ((uint32_t)0x01000000) /*!< Bit 3 */
-#define USART_CR1_DEAT_4 ((uint32_t)0x02000000) /*!< Bit 4 */
-#define USART_CR1_RTOIE ((uint32_t)0x04000000) /*!< Receive Time Out interrupt enable */
-#define USART_CR1_EOBIE ((uint32_t)0x08000000) /*!< End of Block interrupt enable */
-
-/****************** Bit definition for USART_CR2 register *******************/
-#define USART_CR2_ADDM7 ((uint32_t)0x00000010) /*!< 7-bit or 4-bit Address Detection */
-#define USART_CR2_LBDL ((uint32_t)0x00000020) /*!< LIN Break Detection Length */
-#define USART_CR2_LBDIE ((uint32_t)0x00000040) /*!< LIN Break Detection Interrupt Enable */
-#define USART_CR2_LBCL ((uint32_t)0x00000100) /*!< Last Bit Clock pulse */
-#define USART_CR2_CPHA ((uint32_t)0x00000200) /*!< Clock Phase */
-#define USART_CR2_CPOL ((uint32_t)0x00000400) /*!< Clock Polarity */
-#define USART_CR2_CLKEN ((uint32_t)0x00000800) /*!< Clock Enable */
-#define USART_CR2_STOP ((uint32_t)0x00003000) /*!< STOP[1:0] bits (STOP bits) */
-#define USART_CR2_STOP_0 ((uint32_t)0x00001000) /*!< Bit 0 */
-#define USART_CR2_STOP_1 ((uint32_t)0x00002000) /*!< Bit 1 */
-#define USART_CR2_LINEN ((uint32_t)0x00004000) /*!< LIN mode enable */
-#define USART_CR2_SWAP ((uint32_t)0x00008000) /*!< SWAP TX/RX pins */
-#define USART_CR2_RXINV ((uint32_t)0x00010000) /*!< RX pin active level inversion */
-#define USART_CR2_TXINV ((uint32_t)0x00020000) /*!< TX pin active level inversion */
-#define USART_CR2_DATAINV ((uint32_t)0x00040000) /*!< Binary data inversion */
-#define USART_CR2_MSBFIRST ((uint32_t)0x00080000) /*!< Most Significant Bit First */
-#define USART_CR2_ABREN ((uint32_t)0x00100000) /*!< Auto Baud-Rate Enable*/
-#define USART_CR2_ABRMODE ((uint32_t)0x00600000) /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
-#define USART_CR2_ABRMODE_0 ((uint32_t)0x00200000) /*!< Bit 0 */
-#define USART_CR2_ABRMODE_1 ((uint32_t)0x00400000) /*!< Bit 1 */
-#define USART_CR2_RTOEN ((uint32_t)0x00800000) /*!< Receiver Time-Out enable */
-#define USART_CR2_ADD ((uint32_t)0xFF000000) /*!< Address of the USART node */
-
-/****************** Bit definition for USART_CR3 register *******************/
-#define USART_CR3_EIE ((uint32_t)0x00000001) /*!< Error Interrupt Enable */
-#define USART_CR3_IREN ((uint32_t)0x00000002) /*!< IrDA mode Enable */
-#define USART_CR3_IRLP ((uint32_t)0x00000004) /*!< IrDA Low-Power */
-#define USART_CR3_HDSEL ((uint32_t)0x00000008) /*!< Half-Duplex Selection */
-#define USART_CR3_NACK ((uint32_t)0x00000010) /*!< SmartCard NACK enable */
-#define USART_CR3_SCEN ((uint32_t)0x00000020) /*!< SmartCard mode enable */
-#define USART_CR3_DMAR ((uint32_t)0x00000040) /*!< DMA Enable Receiver */
-#define USART_CR3_DMAT ((uint32_t)0x00000080) /*!< DMA Enable Transmitter */
-#define USART_CR3_RTSE ((uint32_t)0x00000100) /*!< RTS Enable */
-#define USART_CR3_CTSE ((uint32_t)0x00000200) /*!< CTS Enable */
-#define USART_CR3_CTSIE ((uint32_t)0x00000400) /*!< CTS Interrupt Enable */
-#define USART_CR3_ONEBIT ((uint32_t)0x00000800) /*!< One sample bit method enable */
-#define USART_CR3_OVRDIS ((uint32_t)0x00001000) /*!< Overrun Disable */
-#define USART_CR3_DDRE ((uint32_t)0x00002000) /*!< DMA Disable on Reception Error */
-#define USART_CR3_DEM ((uint32_t)0x00004000) /*!< Driver Enable Mode */
-#define USART_CR3_DEP ((uint32_t)0x00008000) /*!< Driver Enable Polarity Selection */
-#define USART_CR3_SCARCNT ((uint32_t)0x000E0000) /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
-#define USART_CR3_SCARCNT_0 ((uint32_t)0x00020000) /*!< Bit 0 */
-#define USART_CR3_SCARCNT_1 ((uint32_t)0x00040000) /*!< Bit 1 */
-#define USART_CR3_SCARCNT_2 ((uint32_t)0x00080000) /*!< Bit 2 */
-#define USART_CR3_WUS ((uint32_t)0x00300000) /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
-#define USART_CR3_WUS_0 ((uint32_t)0x00100000) /*!< Bit 0 */
-#define USART_CR3_WUS_1 ((uint32_t)0x00200000) /*!< Bit 1 */
-#define USART_CR3_WUFIE ((uint32_t)0x00400000) /*!< Wake Up Interrupt Enable */
-
-/****************** Bit definition for USART_BRR register *******************/
-#define USART_BRR_DIV_FRACTION ((uint16_t)0x000F) /*!< Fraction of USARTDIV */
-#define USART_BRR_DIV_MANTISSA ((uint16_t)0xFFF0) /*!< Mantissa of USARTDIV */
-
-/****************** Bit definition for USART_GTPR register ******************/
-#define USART_GTPR_PSC ((uint16_t)0x00FF) /*!< PSC[7:0] bits (Prescaler value) */
-#define USART_GTPR_GT ((uint16_t)0xFF00) /*!< GT[7:0] bits (Guard time value) */
-
-
-/******************* Bit definition for USART_RTOR register *****************/
-#define USART_RTOR_RTO ((uint32_t)0x00FFFFFF) /*!< Receiver Time Out Value */
-#define USART_RTOR_BLEN ((uint32_t)0xFF000000) /*!< Block Length */
-
-/******************* Bit definition for USART_RQR register ******************/
-#define USART_RQR_ABRRQ ((uint16_t)0x0001) /*!< Auto-Baud Rate Request */
-#define USART_RQR_SBKRQ ((uint16_t)0x0002) /*!< Send Break Request */
-#define USART_RQR_MMRQ ((uint16_t)0x0004) /*!< Mute Mode Request */
-#define USART_RQR_RXFRQ ((uint16_t)0x0008) /*!< Receive Data flush Request */
-#define USART_RQR_TXFRQ ((uint16_t)0x0010) /*!< Transmit data flush Request */
-
-/******************* Bit definition for USART_ISR register ******************/
-#define USART_ISR_PE ((uint32_t)0x00000001) /*!< Parity Error */
-#define USART_ISR_FE ((uint32_t)0x00000002) /*!< Framing Error */
-#define USART_ISR_NE ((uint32_t)0x00000004) /*!< Noise detected Flag */
-#define USART_ISR_ORE ((uint32_t)0x00000008) /*!< OverRun Error */
-#define USART_ISR_IDLE ((uint32_t)0x00000010) /*!< IDLE line detected */
-#define USART_ISR_RXNE ((uint32_t)0x00000020) /*!< Read Data Register Not Empty */
-#define USART_ISR_TC ((uint32_t)0x00000040) /*!< Transmission Complete */
-#define USART_ISR_TXE ((uint32_t)0x00000080) /*!< Transmit Data Register Empty */
-#define USART_ISR_LBD ((uint32_t)0x00000100) /*!< LIN Break Detection Flag */
-#define USART_ISR_CTSIF ((uint32_t)0x00000200) /*!< CTS interrupt flag */
-#define USART_ISR_CTS ((uint32_t)0x00000400) /*!< CTS flag */
-#define USART_ISR_RTOF ((uint32_t)0x00000800) /*!< Receiver Time Out */
-#define USART_ISR_EOBF ((uint32_t)0x00001000) /*!< End Of Block Flag */
-#define USART_ISR_ABRE ((uint32_t)0x00004000) /*!< Auto-Baud Rate Error */
-#define USART_ISR_ABRF ((uint32_t)0x00008000) /*!< Auto-Baud Rate Flag */
-#define USART_ISR_BUSY ((uint32_t)0x00010000) /*!< Busy Flag */
-#define USART_ISR_CMF ((uint32_t)0x00020000) /*!< Character Match Flag */
-#define USART_ISR_SBKF ((uint32_t)0x00040000) /*!< Send Break Flag */
-#define USART_ISR_RWU ((uint32_t)0x00080000) /*!< Receive Wake Up from mute mode Flag */
-#define USART_ISR_WUF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Flag */
-#define USART_ISR_TEACK ((uint32_t)0x00200000) /*!< Transmit Enable Acknowledge Flag */
-#define USART_ISR_REACK ((uint32_t)0x00400000) /*!< Receive Enable Acknowledge Flag */
-
-/******************* Bit definition for USART_ICR register ******************/
-#define USART_ICR_PECF ((uint32_t)0x00000001) /*!< Parity Error Clear Flag */
-#define USART_ICR_FECF ((uint32_t)0x00000002) /*!< Framing Error Clear Flag */
-#define USART_ICR_NCF ((uint32_t)0x00000004) /*!< Noise detected Clear Flag */
-#define USART_ICR_ORECF ((uint32_t)0x00000008) /*!< OverRun Error Clear Flag */
-#define USART_ICR_IDLECF ((uint32_t)0x00000010) /*!< IDLE line detected Clear Flag */
-#define USART_ICR_TCCF ((uint32_t)0x00000040) /*!< Transmission Complete Clear Flag */
-#define USART_ICR_LBDCF ((uint32_t)0x00000100) /*!< LIN Break Detection Clear Flag */
-#define USART_ICR_CTSCF ((uint32_t)0x00000200) /*!< CTS Interrupt Clear Flag */
-#define USART_ICR_RTOCF ((uint32_t)0x00000800) /*!< Receiver Time Out Clear Flag */
-#define USART_ICR_EOBCF ((uint32_t)0x00001000) /*!< End Of Block Clear Flag */
-#define USART_ICR_CMCF ((uint32_t)0x00020000) /*!< Character Match Clear Flag */
-#define USART_ICR_WUCF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Clear Flag */
-
-/******************* Bit definition for USART_RDR register ******************/
-#define USART_RDR_RDR ((uint16_t)0x01FF) /*!< RDR[8:0] bits (Receive Data value) */
-
-/******************* Bit definition for USART_TDR register ******************/
-#define USART_TDR_TDR ((uint16_t)0x01FF) /*!< TDR[8:0] bits (Transmit Data value) */
-
-/******************************************************************************/
-/* */
-/* Window WATCHDOG (WWDG) */
-/* */
-/******************************************************************************/
-
-/******************* Bit definition for WWDG_CR register ********************/
-#define WWDG_CR_T ((uint8_t)0x7F) /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define WWDG_CR_T0 ((uint8_t)0x01) /*!< Bit 0 */
-#define WWDG_CR_T1 ((uint8_t)0x02) /*!< Bit 1 */
-#define WWDG_CR_T2 ((uint8_t)0x04) /*!< Bit 2 */
-#define WWDG_CR_T3 ((uint8_t)0x08) /*!< Bit 3 */
-#define WWDG_CR_T4 ((uint8_t)0x10) /*!< Bit 4 */
-#define WWDG_CR_T5 ((uint8_t)0x20) /*!< Bit 5 */
-#define WWDG_CR_T6 ((uint8_t)0x40) /*!< Bit 6 */
-
-#define WWDG_CR_WDGA ((uint8_t)0x80) /*!< Activation bit */
-
-/******************* Bit definition for WWDG_CFR register *******************/
-#define WWDG_CFR_W ((uint16_t)0x007F) /*!< W[6:0] bits (7-bit window value) */
-#define WWDG_CFR_W0 ((uint16_t)0x0001) /*!< Bit 0 */
-#define WWDG_CFR_W1 ((uint16_t)0x0002) /*!< Bit 1 */
-#define WWDG_CFR_W2 ((uint16_t)0x0004) /*!< Bit 2 */
-#define WWDG_CFR_W3 ((uint16_t)0x0008) /*!< Bit 3 */
-#define WWDG_CFR_W4 ((uint16_t)0x0010) /*!< Bit 4 */
-#define WWDG_CFR_W5 ((uint16_t)0x0020) /*!< Bit 5 */
-#define WWDG_CFR_W6 ((uint16_t)0x0040) /*!< Bit 6 */
-
-#define WWDG_CFR_WDGTB ((uint16_t)0x0180) /*!< WDGTB[1:0] bits (Timer Base) */
-#define WWDG_CFR_WDGTB0 ((uint16_t)0x0080) /*!< Bit 0 */
-#define WWDG_CFR_WDGTB1 ((uint16_t)0x0100) /*!< Bit 1 */
-
-#define WWDG_CFR_EWI ((uint16_t)0x0200) /*!< Early Wakeup Interrupt */
-
-/******************* Bit definition for WWDG_SR register ********************/
-#define WWDG_SR_EWIF ((uint8_t)0x01) /*!< Early Wakeup Interrupt Flag */
-
-/**
- * @}
- */
-
- /**
- * @}
- */
-
-#ifdef USE_STDPERIPH_DRIVER
- #include "stm32f0xx_conf.h"
-#endif
-
-/** @addtogroup Exported_macro
- * @{
- */
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F0XX_H */
-
-/**
- * @}
- */
-
- /**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h
deleted file mode 100644
index ab76a00554a84db0929414710e97c87577d96b29..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h
+++ /dev/null
@@ -1,104 +0,0 @@
-/**
- ******************************************************************************
- * @file system_stm32f0xx.h
- * @author MCD Application Team
- * @version V1.3.1
- * @date 17-January-2014
- * @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Header File.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/** @addtogroup CMSIS
- * @{
- */
-
-/** @addtogroup stm32f0xx_system
- * @{
- */
-
-/**
- * @brief Define to prevent recursive inclusion
- */
-#ifndef __SYSTEM_STM32F0XX_H
-#define __SYSTEM_STM32F0XX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/** @addtogroup STM32F0xx_System_Includes
- * @{
- */
-
-/**
- * @}
- */
-
-
-/** @addtogroup STM32F0xx_System_Exported_types
- * @{
- */
-
-extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F0xx_System_Exported_Constants
- * @{
- */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F0xx_System_Exported_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F0xx_System_Exported_Functions
- * @{
- */
-
-extern void SystemInit(void);
-extern void SystemCoreClockUpdate(void);
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__SYSTEM_STM32F0XX_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Device/ST/STM32F0xx/Release_Notes.html b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Device/ST/STM32F0xx/Release_Notes.html
deleted file mode 100644
index 47f59daea20888eac243bc68b576d453c9b2789b..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Device/ST/STM32F0xx/Release_Notes.html
+++ /dev/null
@@ -1,228 +0,0 @@
-<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
-<html xmlns:v="urn:schemas-microsoft-com:vml" xmlns:o="urn:schemas-microsoft-com:office:office" xmlns:w="urn:schemas-microsoft-com:office:word" xmlns="http://www.w3.org/TR/REC-html40"><head>
-
-
-
-
-
-
-
-
-
-<meta http-equiv="Content-Type" content="text/html; charset=ISO-8859-1">
-<link rel="File-List" href="Library_files/filelist.xml">
-<link rel="Edit-Time-Data" href="Library_files/editdata.mso"><!--[if !mso]> <style> v\:* {behavior:url(#default#VML);} o\:* {behavior:url(#default#VML);} w\:* {behavior:url(#default#VML);} .shape {behavior:url(#default#VML);} </style> <![endif]--><title>Release Notes for STM32F0xx CMSIS</title><!--[if gte mso 9]><xml> <o:DocumentProperties> <o:Author>STMicroelectronics</o:Author> <o:LastAuthor>STMicroelectronics</o:LastAuthor> <o:Revision>37</o:Revision> <o:TotalTime>136</o:TotalTime> <o:Created>2009-02-27T19:26:00Z</o:Created> <o:LastSaved>2009-03-01T17:56:00Z</o:LastSaved> <o:Pages>1</o:Pages> <o:Words>522</o:Words> <o:Characters>2977</o:Characters> <o:Company>STMicroelectronics</o:Company> <o:Lines>24</o:Lines> <o:Paragraphs>6</o:Paragraphs> <o:CharactersWithSpaces>3493</o:CharactersWithSpaces> <o:Version>11.6568</o:Version> </o:DocumentProperties> </xml><![endif]--><!--[if gte mso 9]><xml> <w:WordDocument> <w:Zoom>110</w:Zoom> <w:ValidateAgainstSchemas/> <w:SaveIfXMLInvalid>false</w:SaveIfXMLInvalid> <w:IgnoreMixedContent>false</w:IgnoreMixedContent> <w:AlwaysShowPlaceholderText>false</w:AlwaysShowPlaceholderText> <w:BrowserLevel>MicrosoftInternetExplorer4</w:BrowserLevel> </w:WordDocument> </xml><![endif]--><!--[if gte mso 9]><xml> <w:LatentStyles DefLockedState="false" LatentStyleCount="156"> </w:LatentStyles> </xml><![endif]-->
-
-
-
-<style>
-<!--
-/* Style Definitions */
-p.MsoNormal, li.MsoNormal, div.MsoNormal
-{mso-style-parent:"";
-margin:0in;
-margin-bottom:.0001pt;
-mso-pagination:widow-orphan;
-font-size:12.0pt;
-font-family:"Times New Roman";
-mso-fareast-font-family:"Times New Roman";}
-h2
-{mso-style-next:Normal;
-margin-top:12.0pt;
-margin-right:0in;
-margin-bottom:3.0pt;
-margin-left:0in;
-mso-pagination:widow-orphan;
-page-break-after:avoid;
-mso-outline-level:2;
-font-size:14.0pt;
-font-family:Arial;
-font-weight:bold;
-font-style:italic;}
-a:link, span.MsoHyperlink
-{color:blue;
-text-decoration:underline;
-text-underline:single;}
-a:visited, span.MsoHyperlinkFollowed
-{color:blue;
-text-decoration:underline;
-text-underline:single;}
-p
-{mso-margin-top-alt:auto;
-margin-right:0in;
-mso-margin-bottom-alt:auto;
-margin-left:0in;
-mso-pagination:widow-orphan;
-font-size:12.0pt;
-font-family:"Times New Roman";
-mso-fareast-font-family:"Times New Roman";}
-@page Section1
-{size:8.5in 11.0in;
-margin:1.0in 1.25in 1.0in 1.25in;
-mso-header-margin:.5in;
-mso-footer-margin:.5in;
-mso-paper-source:0;}
-div.Section1
-{page:Section1;}
--->
-</style><!--[if gte mso 10]> <style> /* Style Definitions */ table.MsoNormalTable {mso-style-name:"Table Normal"; mso-tstyle-rowband-size:0; mso-tstyle-colband-size:0; mso-style-noshow:yes; mso-style-parent:""; mso-padding-alt:0in 5.4pt 0in 5.4pt; mso-para-margin:0in; mso-para-margin-bottom:.0001pt; mso-pagination:widow-orphan; font-size:10.0pt; font-family:"Times New Roman"; mso-ansi-language:#0400; mso-fareast-language:#0400; mso-bidi-language:#0400;} </style> <![endif]--><!--[if gte mso 9]><xml> <o:shapedefaults v:ext="edit" spidmax="5122"/> </xml><![endif]--><!--[if gte mso 9]><xml> <o:shapelayout v:ext="edit"> <o:idmap v:ext="edit" data="1"/> </o:shapelayout></xml><![endif]--><meta content="MCD Application Team" name="author"></head>
-<body link="blue" vlink="blue">
-<div class="Section1">
-<p class="MsoNormal"><span style="font-family: Arial;"><o:p><br>
-</o:p></span></p>
-<div align="center">
-<table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" cellspacing="0" width="900">
-<tbody>
-<tr style="">
-<td style="padding: 0cm;" valign="top">
-<table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" cellspacing="0" width="900">
-<tbody>
- <tr>
- <td style="vertical-align: top;"><span style="font-size: 8pt; font-family: Arial; color: blue;"><a href="../../../../../Release_Notes.html">Back to Release page</a></span></td>
- </tr>
-<tr style="">
-<td style="padding: 1.5pt;">
-<h1 style="margin-bottom: 18pt; text-align: center;" align="center"><span style="font-size: 20pt; font-family: Verdana; color: rgb(51, 102, 255);">Release
-Notes for STM32F0xx CMSIS</span><span style="font-size: 20pt; font-family: Verdana;"><o:p></o:p></span></h1>
-<p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;">Copyright 2014 STMicroelectronics</span><span style="color: black;"><u1:p></u1:p><o:p></o:p></span></p>
-<p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: Arial; color: black;"><img alt="" id="_x0000_i1025" src="../../../../../_htmresc/st_logo.png" style="border: 0px solid ; width: 86px; height: 65px;"></span><span style="font-size: 10pt;"><o:p></o:p></span></p>
-</td>
-</tr>
-</tbody>
-</table>
-
-<table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" width="900">
-<tbody>
-<tr>
-<td style="padding: 0cm;" valign="top">
-
-<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><span style="font-size: 12pt; color: white;">Update History</span></h2><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.3.1 / 17-January-2014</span></h3>
-
-
- <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
-Changes<o:p></o:p></span></u></b></p>
-
-
-
- <ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">TrueSTUDIO and gcc_ride7 startup files update for STM32F042 and STM32F072 devices.</span></li></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.3.0 / 16-January-2014</span></h3>
-
-
- <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
-Changes<o:p></o:p></span></u></b></p>
-
-
-
- <ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana;"></span><span style="font-family: Verdana;"></span><small><span style="font-family: Verdana;">Add the support of the<span style="font-weight: bold;"> STM32F072 </span>and <span style="font-weight: bold;">STM32F042</span> devices.</span></small></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><small><span style="font-family: Verdana;">Update devices names definition to be in line with the new </span></small><span style="color: rgb(0, 0, 0); font-family: Verdana; font-size: 13px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; display: inline ! important; float: none;">new STM32F0xx family devices names.</span></li><ul><li class="MsoNormal" style="margin: 4.5pt 0cm; font-size: 12pt; font-family: 'Times New Roman'; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">STM32F0XX_MD</span><span class="Apple-converted-space"> </span> replaced by<span class="Apple-converted-space"> </span><span style="font-weight: bold;">STM32F051.</span></span></li><li class="MsoNormal" style="margin: 4.5pt 0cm; font-size: 12pt; font-family: 'Times New Roman'; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">STM32F0XX_LD</span><span class="Apple-converted-space"> </span> replaced by<span class="Apple-converted-space"> </span><span style="font-weight: bold;">STM32F031.</span></span></li><li class="MsoNormal" style="margin: 4.5pt 0cm; font-size: 12pt; font-family: 'Times New Roman'; color: black; font-weight: bold;"><span style="font-size: 10pt; font-family: Verdana;">STM32F030x8 </span><span style="font-size: 10pt; font-family: Verdana; font-weight: normal;">and<span class="Apple-converted-space"> </span><span style="font-weight: bold;">STM32F030x6</span><span class="Apple-converted-space"> </span>replaced by<span class="Apple-converted-space"> </span><span style="font-weight: bold;">STM32F030.</span></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f0xx.h</span></li><ul><li class="MsoNormal" style="margin: 4.5pt 0cm; font-size: 12pt; font-family: 'Times New Roman'; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Upddate to support the new STM32F0xx family devices names.</span></li><ul style="margin-bottom: 0cm;"><li class="MsoNormal" style="margin: 4.5pt 0cm; font-size: 12pt; font-family: 'Times New Roman'; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">STM32F0XX_MD</span><span class="Apple-converted-space"> </span> replaced by<span class="Apple-converted-space"> </span><span style="font-weight: bold;">STM32F051</span></span></li><li class="MsoNormal" style="margin: 4.5pt 0cm; font-size: 12pt; font-family: 'Times New Roman'; color: black;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;">STM32F0XX_LD</span><span class="Apple-converted-space"> </span> replaced by<span class="Apple-converted-space"> </span><span style="font-weight: bold;">STM32F031</span></span></li></ul></ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Update <span style="font-style: italic;">IRQn</span> enum to support the </span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">STM32F042 and STM32F072</span></span><span style="font-size: 10pt; font-family: Verdana;"> devices.</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add define for HSI48_VALUE.</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add CAN peripheral registers declaration and bits definition.</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add CRS peripheral registers declaration and bits definition.</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Update CRC_TypeDef structure definition to add POL register.</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Update DAC_TypeDef structure to add DAC Channel 2 configuration registers.</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Update OB_TypeDef structure by adding DATA0, DATA1, WRP2 and WRP3 option bytes registers.</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Rename CAL registers to CALR in the RTC_TypeDef structure.</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add the definition of the TIM7, USART3, USART4, CAN, CRS, DMA1_Channel6, DMA1_Channel7 and GPIOE.</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add bit definition for FLASH_OBR_nBOOT0, FLASH_OBR_RAM_PARITY_CHECK, FLASH_OBR_nBOOT0_SW, FLASH_OBR_DATA0 and FLASH_OBR_DATA1.</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add bit definition for OB_WRP2_WRP2, OB_WRP2_nWRP2, OB_WRP3_WRP3 and OB_WRP3_nWRP3.</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Update almost bits definition to be in line with RM0091 reference manual.<br></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">system_stm32f0xx.c</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">SystemInit()</span>: update to support <span style="font-style: italic;">STM32F042 and STM32F072</span> devices</span><span style="font-size: 10pt; font-family: Verdana;"></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new startup files for the STM32F042 and STM32F072 devices for the </span><span style="font-size: 10pt; font-family: Verdana;">supported compilers</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Replace <span style="font-style: italic;">startup_stm32f0xx_ld.s</span> and </span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">startup_stm32f0xx.s </span>by respectively <span style="font-style: italic;">startup_stm32f030.s</span> and </span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">startup_stm32f051.s </span>files.</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">startup_stm32f0xx_ld.s</span> and </span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">startup_stm32f0xx.s </span>files are maintained for legacy purpose.</span></li></ul></ul>
- <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.2.1 / 22-November-2013</span></h3>
-
-
- <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
-Changes<o:p></o:p></span></u></b></p>
-
-
-
- <ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f0xx.h</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Update STM32F030 devices definition: <br>
- </span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Remove the <span style="font-style: italic;">STM32F030X8 and STM32FO30X6</span> defines and replace them with the </span><span style="font-size: 10pt; font-family: Verdana;">S<span style="font-style: italic;">TM32F030 define</span></span></li></ul></ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Update <span style="font-style: italic;">IRQn</span> enum for </span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">STM32F030</span></span><span style="font-size: 10pt; font-family: Verdana;"> devices</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">system_stm32f0xx.c</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">SystemInit()</span>: update to support <span style="font-style: italic;">STM32F030</span> devices</span><span style="font-size: 10pt; font-family: Verdana;"></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Remove the startup files </span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">startup_stm32f030x8.s and startup_stm32f030x6.s</span> and replace them by </span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">startup_stm32f030.s</span></span><span style="font-size: 10pt; font-family: Verdana;">, for EWARM, MDK-ARM and Truestudio supported compilers</span></li></ul>
- <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.2.0 / 01-August-2013</span></h3>
-
-
- <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
-Changes<o:p></o:p></span></u></b></p>
-
-
-
- <ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add support of <span style="font-weight: bold; font-style: italic;">STM32F030 devices</span> (STM32F030x8 and STM32F030x6 microcontrollers where the Flash memory ranges between 16 and 32 Kbytes)</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f0xx.h</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Update STM32F0xx devices definition: <br>
- </span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new definition <span style="font-style: italic;">STM32F030X8 and STM32FO30X6</span> for </span><span style="font-size: 10pt; font-family: Verdana;">S<span style="font-style: italic;">TM32F030 devices</span></span></li></ul></ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Update <span style="font-style: italic;">IRQn</span> enum for </span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">STM32F030</span></span><span style="font-size: 10pt; font-family: Verdana;"> devices</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">system_stm32f0xx.c</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">SystemInit()</span>: update to support <span style="font-style: italic;">STM32F030</span> devices</span><span style="font-size: 10pt; font-family: Verdana;"></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new startup files, </span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">startup_stm32f030x8.s and startup_stm32f030x6.s</span>, for EWARM, MDK-ARM and Truestudio supported compilers</span></li></ul>
-
-
- <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.1.1 / 31-July-2013</span></h3>
-
-
- <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
-Changes<o:p></o:p></span></u></b></p>
-
-
-
- <ul style="margin-top: 0cm;" type="square">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f0xx.h</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Extend <span style="font-style: italic;">HSE_STARTUP_TIMEOUT</span> and <span style="font-style: italic;">HSI_STARTUP_TIMEOUT</span> values to 0x5000</span></li></ul>
- </ul>
-
- <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.1.0 / 10-May-2013</span></h3>
- <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
-Changes<o:p></o:p></span></u></b></p>
-
- <ul style="margin-top: 0cm;" type="square">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add support of <span style="font-weight: bold; font-style: italic;">STM32F0xx Low-density devices</span> (STM32F050xx and STM32F060xx microcontrollers where the Flash memory ranges between 16 and 32 Kbytes)</span></li>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f0xx.h</span></li>
- <ul>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Update STM32F0xx devices definition: <br>
- </span></li>
- <ul>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Define for <span style="font-style: italic;">STM32F0xx Medium-density devices</span> changed from <span style="font-style: italic;">STM32F0XX</span> to <span style="font-style: italic;">STM32F0XX_MD</span><br>
- </span></li>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new definition <span style="font-style: italic;">STM32F0XX_LD</span> for </span><span style="font-size: 10pt; font-family: Verdana;">S<span style="font-style: italic;">TM32F0xx Low-density devices</span></span></li>
- </ul>
- </ul>
- <ul>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Update <span style="font-style: italic;">IRQn</span> enum for </span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">STM32F0XX_LD</span></span><span style="font-size: 10pt; font-family: Verdana;"> devices</span></li>
- </ul>
- <ul>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new bits definition</span></li>
- <ul>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">RCC_CFGR</span></span><span style="font-size: 10pt; font-family: Verdana;"> register</span><span style="font-size: 10pt; font-family: Verdana;">: <span style="font-style: italic;">MCOPRE[0:2]</span> and <span style="font-style: italic;">PLLNODIV</span></span></li>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">SYSCFG_CFGR1</span> register: <span style="font-style: italic;">FMP_I2C1</span>, <span style="font-style: italic;">FMP_PA9</span> and <span style="font-style: italic;">FMP_PA10</span><br>
- </span></li>
- </ul>
- </ul>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">system_stm32f0xx.c</span></li>
- <ul>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">SystemInit()</span>: update to reset new bits added in </span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">RCC_CFGR</span></span><span style="font-size: 10pt; font-family: Verdana;"> register</span></li>
- </ul>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new startup files, </span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">startup_stm32f0xx_ld.s</span>, for the supported compilers</span></li>
- </ul>
-<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.2 / 13-July-2012</span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
-Changes<o:p></o:p></span></u></b></p>
-<ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f0xx.h</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Fix issue with gcc_ride7 startup file </span><span style="font-size: 10pt; font-family: Verdana;"></span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.1 / 20-April-2012</span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
-Changes<o:p></o:p></span></u></b></p>
-<ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f0xx.h</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add reference to STM32F050xx (Flash memory up to 32 Kbytes) and STM32F051xx (</span><span style="font-size: 10pt; font-family: Verdana;">Flash memory up to 64 Kbytes</span><span style="font-size: 10pt; font-family: Verdana;">) devices</span></li></ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">RTC register bits definition: remove reference to Tamper3</span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.0 / 23-March-2012</span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
-Changes<o:p></o:p></span></u></b></p>
-<ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">First official release for <span style="font-weight: bold; font-style: italic;">STM32F0xx devices</span></span><span style="font-size: 10pt; font-family: Verdana;"></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">All source files: license disclaimer text update and add link to the License file on ST Internet</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">stm32f0xx.h</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">change MCO bits value:</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">change <span style="font-style: italic;">RCC_CFGR_MCO_HSI14</span> value from 0x03000000 to 0x01000000</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add <span style="font-style: italic;">RCC_CFGR_MCO_LSI</span> having value 0x02000000</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add <span style="font-style: italic;">RCC_CFGR_MCO_LSE</span> having value 0x03000000</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add new bit <span style="font-style: italic;">RCC_CSR_V18PWRRSTF</span> having value 0x00800000</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">TIM_OR</span> bits definition values corrected</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Rename <span style="font-style: italic;">ADC_ISR_EOS</span> to <span style="font-style: italic;">ADC_ISR_EOSEQ</span></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Rename <span style="font-style: italic;">ADC_IER_EOSIE</span> to <span style="font-style: italic;">ADC_IER_EOSEQIE</span></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Rename <span style="font-style: italic;">ADC_CFGR1_AUTDLY</span> to <span style="font-style: italic;">ADC_CFGR1_WAIT</span></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Rename option bit <span style="font-style: italic;">FLASH_OBR_BOOT1</span> to <span style="font-style: italic;">FLASH_OBR_nBOOT1</span></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Rename <span style="font-style: italic;">FLASH_OBR_VDDA_ANALOG</span> to <span style="font-style: italic;">FLASH_OBR_VDDA_MONITOR</span></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Add Flash and OB keys (removed from Flash driver)</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">system_stm32f0xx.c</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">SetSysClock()</span> function: code optimized </span></li></ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Miscellaneous formatting<br></span></li></ul></ul>
- <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.0RC1 / 27-January-2012<o:p></o:p></span></h3>
- <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
-Changes<o:p></o:p></span></u></b></p>
-
- <ul style="margin-top: 0cm;" type="square">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Official version (V1.0.0) Release Candidate 1</span><span style="font-size: 10pt; font-family: Verdana;"></span></li>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;">All source
-files: update disclaimer to add reference to the new license agreement</span></li>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">Update all peripherals bits definitions<br>
-</span></li>
- </ul><span style="font-size: 10pt; font-family: Verdana;"><span style="font-weight: bold;"></span><span style="font-weight: bold; font-style: italic;"></span></span>
-
-<ul style="margin-top: 0in;" type="disc">
-</ul>
-<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="License"></a><span style="font-size: 12pt; color: white;">License<o:p></o:p></span></h2><p class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;">Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;">package</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;"> except in compliance with the License. You may obtain a copy of the License at:<br><br></span></p><div style="text-align: center;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;"> <a target="_blank" href="http://www.st.com/software_license_agreement_liberty_v2">http://www.st.com/software_license_agreement_liberty_v2</a></span><br><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;"></span></div><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;"><br>Unless
-required by applicable law or agreed to in writing, software
-distributed under the License is distributed on an "AS IS" BASIS, <br>WITHOUT
-WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See
-the License for the specific language governing permissions and
-limitations under the License.</span>
-
-<div class="MsoNormal" style="text-align: center;" align="center"><span style="color: black;">
-<hr align="center" size="2" width="100%"></span></div>
-<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt; text-align: center;" align="center"><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;">For
- complete documentation on </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">STM32<span style="color: black;">
- Microcontrollers visit </span><u><span style="color: blue;"><a href="http://www.st.com/internet/mcu/family/141.jsp" target="_blank">www.st.com/STM32</a></span></u></span><span style="font-size: 10pt; font-family: Verdana;"><u><span style="color: blue;"><a href="http://www.st.com/internet/mcu/family/141.jsp" target="_blank"></a></span></u></span><span style="color: black;"><o:p></o:p></span></p>
-</td>
-</tr>
-</tbody>
-</table>
-<p class="MsoNormal"><span style="font-size: 10pt;"><o:p></o:p></span></p>
-</td>
-</tr>
-</tbody>
-</table>
-</div>
-<p class="MsoNormal"><o:p> </o:p></p>
-</div>
-</body></html>
\ No newline at end of file
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/TrueSTUDIO/startup_stm32f030.s b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/TrueSTUDIO/startup_stm32f030.s
deleted file mode 100644
index 9bef3687a52dc5e569f908249cc1a4d65b0d6363..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/TrueSTUDIO/startup_stm32f030.s
+++ /dev/null
@@ -1,280 +0,0 @@
-/**
- ******************************************************************************
- * @file startup_stm32f030.s
- * @author MCD Application Team
- * @version V1.3.1
- * @date 17-January-2014
- * @brief STM32F030 Devices vector table for Atollic toolchain.
- * This module performs:
- * - Set the initial SP
- * - Set the initial PC == Reset_Handler,
- * - Set the vector table entries with the exceptions ISR address
- * - Configure the system clock
- * - Branches to main in the C library (which eventually
- * calls main()).
- * After Reset the Cortex-M0 processor is in Thread mode,
- * priority is Privileged, and the Stack is set to Main.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
- .syntax unified
- .cpu cortex-m0
- .fpu softvfp
- .thumb
-
-.global g_pfnVectors
-.global Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word _sidata
-/* start address for the .data section. defined in linker script */
-.word _sdata
-/* end address for the .data section. defined in linker script */
-.word _edata
-/* start address for the .bss section. defined in linker script */
-.word _sbss
-/* end address for the .bss section. defined in linker script */
-.word _ebss
-
- .section .text.Reset_Handler
- .weak Reset_Handler
- .type Reset_Handler, %function
-Reset_Handler:
- ldr r0, =_estack
- mov sp, r0 /* set stack pointer */
-
-/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
- b LoopCopyDataInit
-
-CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
-
-LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
- bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
-/* Zero fill the bss segment. */
-FillZerobss:
- movs r3, #0
- str r3, [r2]
- adds r2, r2, #4
-
-
-LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
- bcc FillZerobss
-
-/* Call the clock system intitialization function.*/
- bl SystemInit
-/* Call static constructors */
- bl __libc_init_array
-/* Call the application's entry point.*/
- bl main
-
-LoopForever:
- b LoopForever
-
-
-.size Reset_Handler, .-Reset_Handler
-
-/**
- * @brief This is the code that gets called when the processor receives an
- * unexpected interrupt. This simply enters an infinite loop, preserving
- * the system state for examination by a debugger.
- *
- * @param None
- * @retval : None
-*/
- .section .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
- b Infinite_Loop
- .size Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M0. Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
- .section .isr_vector,"a",%progbits
- .type g_pfnVectors, %object
- .size g_pfnVectors, .-g_pfnVectors
-
-g_pfnVectors:
- .word _estack
- .word Reset_Handler
-
- .word NMI_Handler
- .word HardFault_Handler
- .word 0
- .word 0
- .word 0
- .word 0
- .word 0
- .word 0
- .word 0
- .word SVC_Handler
- .word 0
- .word 0
- .word PendSV_Handler
- .word SysTick_Handler
-
-
- .word WWDG_IRQHandler
- .word 0
- .word RTC_IRQHandler
- .word FLASH_IRQHandler
- .word RCC_IRQHandler
- .word EXTI0_1_IRQHandler
- .word EXTI2_3_IRQHandler
- .word EXTI4_15_IRQHandler
- .word 0
- .word DMA1_Channel1_IRQHandler
- .word DMA1_Channel2_3_IRQHandler
- .word DMA1_Channel4_5_IRQHandler
- .word ADC1_IRQHandler
- .word TIM1_BRK_UP_TRG_COM_IRQHandler
- .word TIM1_CC_IRQHandler
- .word 0
- .word TIM3_IRQHandler
- .word 0
- .word 0
- .word TIM14_IRQHandler
- .word TIM15_IRQHandler
- .word TIM16_IRQHandler
- .word TIM17_IRQHandler
- .word I2C1_IRQHandler
- .word I2C2_IRQHandler
- .word SPI1_IRQHandler
- .word SPI2_IRQHandler
- .word USART1_IRQHandler
- .word USART2_IRQHandler
- .word 0
- .word 0
- .word 0
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
-
- .weak NMI_Handler
- .thumb_set NMI_Handler,Default_Handler
-
- .weak HardFault_Handler
- .thumb_set HardFault_Handler,Default_Handler
-
- .weak SVC_Handler
- .thumb_set SVC_Handler,Default_Handler
-
- .weak PendSV_Handler
- .thumb_set PendSV_Handler,Default_Handler
-
- .weak SysTick_Handler
- .thumb_set SysTick_Handler,Default_Handler
-
- .weak WWDG_IRQHandler
- .thumb_set WWDG_IRQHandler,Default_Handler
-
- .weak RTC_IRQHandler
- .thumb_set RTC_IRQHandler,Default_Handler
-
- .weak FLASH_IRQHandler
- .thumb_set FLASH_IRQHandler,Default_Handler
-
- .weak RCC_IRQHandler
- .thumb_set RCC_IRQHandler,Default_Handler
-
- .weak EXTI0_1_IRQHandler
- .thumb_set EXTI0_1_IRQHandler,Default_Handler
-
- .weak EXTI2_3_IRQHandler
- .thumb_set EXTI2_3_IRQHandler,Default_Handler
-
- .weak EXTI4_15_IRQHandler
- .thumb_set EXTI4_15_IRQHandler,Default_Handler
-
- .weak DMA1_Channel1_IRQHandler
- .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
- .weak DMA1_Channel2_3_IRQHandler
- .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler
-
- .weak DMA1_Channel4_5_IRQHandler
- .thumb_set DMA1_Channel4_5_IRQHandler,Default_Handler
-
- .weak ADC1_IRQHandler
- .thumb_set ADC1_IRQHandler,Default_Handler
-
- .weak TIM1_BRK_UP_TRG_COM_IRQHandler
- .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler
-
- .weak TIM1_CC_IRQHandler
- .thumb_set TIM1_CC_IRQHandler,Default_Handler
-
- .weak TIM3_IRQHandler
- .thumb_set TIM3_IRQHandler,Default_Handler
-
- .weak TIM14_IRQHandler
- .thumb_set TIM14_IRQHandler,Default_Handler
-
- .weak TIM15_IRQHandler
- .thumb_set TIM15_IRQHandler,Default_Handler
-
- .weak TIM16_IRQHandler
- .thumb_set TIM16_IRQHandler,Default_Handler
-
- .weak TIM17_IRQHandler
- .thumb_set TIM17_IRQHandler,Default_Handler
-
- .weak I2C1_IRQHandler
- .thumb_set I2C1_IRQHandler,Default_Handler
-
- .weak I2C2_IRQHandler
- .thumb_set I2C2_IRQHandler,Default_Handler
-
- .weak SPI1_IRQHandler
- .thumb_set SPI1_IRQHandler,Default_Handler
-
- .weak SPI2_IRQHandler
- .thumb_set SPI2_IRQHandler,Default_Handler
-
- .weak USART1_IRQHandler
- .thumb_set USART1_IRQHandler,Default_Handler
-
- .weak USART2_IRQHandler
- .thumb_set USART2_IRQHandler,Default_Handler
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/TrueSTUDIO/startup_stm32f031.s b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/TrueSTUDIO/startup_stm32f031.s
deleted file mode 100644
index f4454d0adb39c1931b0eb9a8f55ab1fa289fa90b..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/TrueSTUDIO/startup_stm32f031.s
+++ /dev/null
@@ -1,275 +0,0 @@
-/**
- ******************************************************************************
- * @file startup_stm32f031.s
- * @author MCD Application Team
- * @version V1.3.1
- * @date 17-January-2014
- * @brief STM32F031 Devices vector table for Atollic toolchain.
- * This module performs:
- * - Set the initial SP
- * - Set the initial PC == Reset_Handler,
- * - Set the vector table entries with the exceptions ISR address
- * - Configure the system clock
- * - Branches to main in the C library (which eventually
- * calls main()).
- * After Reset the Cortex-M0 processor is in Thread mode,
- * priority is Privileged, and the Stack is set to Main.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
- .syntax unified
- .cpu cortex-m0
- .fpu softvfp
- .thumb
-
-.global g_pfnVectors
-.global Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word _sidata
-/* start address for the .data section. defined in linker script */
-.word _sdata
-/* end address for the .data section. defined in linker script */
-.word _edata
-/* start address for the .bss section. defined in linker script */
-.word _sbss
-/* end address for the .bss section. defined in linker script */
-.word _ebss
-
- .section .text.Reset_Handler
- .weak Reset_Handler
- .type Reset_Handler, %function
-Reset_Handler:
- ldr r0, =_estack
- mov sp, r0 /* set stack pointer */
-
-/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
- b LoopCopyDataInit
-
-CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
-
-LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
- bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
-/* Zero fill the bss segment. */
-FillZerobss:
- movs r3, #0
- str r3, [r2]
- adds r2, r2, #4
-
-
-LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
- bcc FillZerobss
-
-/* Call the clock system intitialization function.*/
- bl SystemInit
-/* Call static constructors */
- bl __libc_init_array
-/* Call the application's entry point.*/
- bl main
-
-LoopForever:
- b LoopForever
-
-
-.size Reset_Handler, .-Reset_Handler
-
-/**
- * @brief This is the code that gets called when the processor receives an
- * unexpected interrupt. This simply enters an infinite loop, preserving
- * the system state for examination by a debugger.
- *
- * @param None
- * @retval : None
-*/
- .section .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
- b Infinite_Loop
- .size Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M0. Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
- .section .isr_vector,"a",%progbits
- .type g_pfnVectors, %object
- .size g_pfnVectors, .-g_pfnVectors
-
-g_pfnVectors:
- .word _estack
- .word Reset_Handler
-
- .word NMI_Handler
- .word HardFault_Handler
- .word 0
- .word 0
- .word 0
- .word 0
- .word 0
- .word 0
- .word 0
- .word SVC_Handler
- .word 0
- .word 0
- .word PendSV_Handler
- .word SysTick_Handler
-
-
- .word WWDG_IRQHandler
- .word PVD_IRQHandler
- .word RTC_IRQHandler
- .word FLASH_IRQHandler
- .word RCC_IRQHandler
- .word EXTI0_1_IRQHandler
- .word EXTI2_3_IRQHandler
- .word EXTI4_15_IRQHandler
- .word 0
- .word DMA1_Channel1_IRQHandler
- .word DMA1_Channel2_3_IRQHandler
- .word DMA1_Channel4_5_IRQHandler
- .word ADC1_IRQHandler
- .word TIM1_BRK_UP_TRG_COM_IRQHandler
- .word TIM1_CC_IRQHandler
- .word TIM2_IRQHandler
- .word TIM3_IRQHandler
- .word 0
- .word 0
- .word TIM14_IRQHandler
- .word 0
- .word TIM16_IRQHandler
- .word TIM17_IRQHandler
- .word I2C1_IRQHandler
- .word 0
- .word SPI1_IRQHandler
- .word 0
- .word USART1_IRQHandler
- .word 0
- .word 0
- .word 0
- .word 0
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
-
- .weak NMI_Handler
- .thumb_set NMI_Handler,Default_Handler
-
- .weak HardFault_Handler
- .thumb_set HardFault_Handler,Default_Handler
-
- .weak SVC_Handler
- .thumb_set SVC_Handler,Default_Handler
-
- .weak PendSV_Handler
- .thumb_set PendSV_Handler,Default_Handler
-
- .weak SysTick_Handler
- .thumb_set SysTick_Handler,Default_Handler
-
- .weak WWDG_IRQHandler
- .thumb_set WWDG_IRQHandler,Default_Handler
-
- .weak PVD_IRQHandler
- .thumb_set PVD_IRQHandler,Default_Handler
-
- .weak RTC_IRQHandler
- .thumb_set RTC_IRQHandler,Default_Handler
-
- .weak FLASH_IRQHandler
- .thumb_set FLASH_IRQHandler,Default_Handler
-
- .weak RCC_IRQHandler
- .thumb_set RCC_IRQHandler,Default_Handler
-
- .weak EXTI0_1_IRQHandler
- .thumb_set EXTI0_1_IRQHandler,Default_Handler
-
- .weak EXTI2_3_IRQHandler
- .thumb_set EXTI2_3_IRQHandler,Default_Handler
-
- .weak EXTI4_15_IRQHandler
- .thumb_set EXTI4_15_IRQHandler,Default_Handler
-
- .weak DMA1_Channel1_IRQHandler
- .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
- .weak DMA1_Channel2_3_IRQHandler
- .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler
-
- .weak DMA1_Channel4_5_IRQHandler
- .thumb_set DMA1_Channel4_5_IRQHandler,Default_Handler
-
- .weak ADC1_IRQHandler
- .thumb_set ADC1_IRQHandler,Default_Handler
-
- .weak TIM1_BRK_UP_TRG_COM_IRQHandler
- .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler
-
- .weak TIM1_CC_IRQHandler
- .thumb_set TIM1_CC_IRQHandler,Default_Handler
-
- .weak TIM2_IRQHandler
- .thumb_set TIM2_IRQHandler,Default_Handler
-
- .weak TIM3_IRQHandler
- .thumb_set TIM3_IRQHandler,Default_Handler
-
- .weak TIM14_IRQHandler
- .thumb_set TIM14_IRQHandler,Default_Handler
-
- .weak TIM16_IRQHandler
- .thumb_set TIM16_IRQHandler,Default_Handler
-
- .weak TIM17_IRQHandler
- .thumb_set TIM17_IRQHandler,Default_Handler
-
- .weak I2C1_IRQHandler
- .thumb_set I2C1_IRQHandler,Default_Handler
-
- .weak SPI1_IRQHandler
- .thumb_set SPI1_IRQHandler,Default_Handler
-
- .weak USART1_IRQHandler
- .thumb_set USART1_IRQHandler,Default_Handler
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
\ No newline at end of file
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/TrueSTUDIO/startup_stm32f042.s b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/TrueSTUDIO/startup_stm32f042.s
deleted file mode 100644
index 0255c256b589e6974922011d1163c6b671f3015a..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/TrueSTUDIO/startup_stm32f042.s
+++ /dev/null
@@ -1,289 +0,0 @@
-/**
- ******************************************************************************
- * @file startup_stm32f042.s
- * @author MCD Application Team
- * @version V1.3.1
- * @date 17-January-2014
- * @brief STM32F042 Devices vector table for Atollic toolchain.
- * This module performs:
- * - Set the initial SP
- * - Set the initial PC == Reset_Handler,
- * - Set the vector table entries with the exceptions ISR address
- * - Configure the system clock
- * - Branches to main in the C library (which eventually
- * calls main()).
- * After Reset the Cortex-M0 processor is in Thread mode,
- * priority is Privileged, and the Stack is set to Main.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
- .syntax unified
- .cpu cortex-m0
- .fpu softvfp
- .thumb
-
-.global g_pfnVectors
-.global Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word _sidata
-/* start address for the .data section. defined in linker script */
-.word _sdata
-/* end address for the .data section. defined in linker script */
-.word _edata
-/* start address for the .bss section. defined in linker script */
-.word _sbss
-/* end address for the .bss section. defined in linker script */
-.word _ebss
-
- .section .text.Reset_Handler
- .weak Reset_Handler
- .type Reset_Handler, %function
-Reset_Handler:
- ldr r0, =_estack
- mov sp, r0 /* set stack pointer */
-
-/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
- b LoopCopyDataInit
-
-CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
-
-LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
- bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
-/* Zero fill the bss segment. */
-FillZerobss:
- movs r3, #0
- str r3, [r2]
- adds r2, r2, #4
-
-
-LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
- bcc FillZerobss
-
-/* Call the clock system intitialization function.*/
- bl SystemInit
-/* Call static constructors */
- bl __libc_init_array
-/* Call the application's entry point.*/
- bl main
-
-LoopForever:
- b LoopForever
-
-
-.size Reset_Handler, .-Reset_Handler
-
-/**
- * @brief This is the code that gets called when the processor receives an
- * unexpected interrupt. This simply enters an infinite loop, preserving
- * the system state for examination by a debugger.
- *
- * @param None
- * @retval : None
-*/
- .section .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
- b Infinite_Loop
- .size Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M0. Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
- .section .isr_vector,"a",%progbits
- .type g_pfnVectors, %object
- .size g_pfnVectors, .-g_pfnVectors
-
-g_pfnVectors:
- .word _estack
- .word Reset_Handler
-
- .word NMI_Handler
- .word HardFault_Handler
- .word 0
- .word 0
- .word 0
- .word 0
- .word 0
- .word 0
- .word 0
- .word SVC_Handler
- .word 0
- .word 0
- .word PendSV_Handler
- .word SysTick_Handler
-
-
- .word WWDG_IRQHandler
- .word PVD_VDDIO2_IRQHandler
- .word RTC_IRQHandler
- .word FLASH_IRQHandler
- .word RCC_CRS_IRQHandler
- .word EXTI0_1_IRQHandler
- .word EXTI2_3_IRQHandler
- .word EXTI4_15_IRQHandler
- .word TSC_IRQHandler
- .word DMA1_Channel1_IRQHandler
- .word DMA1_Channel2_3_IRQHandler
- .word DMA1_Channel4_5_IRQHandler
- .word ADC1_IRQHandler
- .word TIM1_BRK_UP_TRG_COM_IRQHandler
- .word TIM1_CC_IRQHandler
- .word TIM2_IRQHandler
- .word TIM3_IRQHandler
- .word 0
- .word 0
- .word TIM14_IRQHandler
- .word 0
- .word TIM16_IRQHandler
- .word TIM17_IRQHandler
- .word I2C1_IRQHandler
- .word 0
- .word SPI1_IRQHandler
- .word SPI2_IRQHandler
- .word USART1_IRQHandler
- .word USART2_IRQHandler
- .word 0
- .word CEC_CAN_IRQHandler
- .word USB_IRQHandler
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
-
- .weak NMI_Handler
- .thumb_set NMI_Handler,Default_Handler
-
- .weak HardFault_Handler
- .thumb_set HardFault_Handler,Default_Handler
-
- .weak SVC_Handler
- .thumb_set SVC_Handler,Default_Handler
-
- .weak PendSV_Handler
- .thumb_set PendSV_Handler,Default_Handler
-
- .weak SysTick_Handler
- .thumb_set SysTick_Handler,Default_Handler
-
- .weak WWDG_IRQHandler
- .thumb_set WWDG_IRQHandler,Default_Handler
-
- .weak PVD_VDDIO2_IRQHandler
- .thumb_set PVD_VDDIO2_IRQHandler,Default_Handler
-
- .weak RTC_IRQHandler
- .thumb_set RTC_IRQHandler,Default_Handler
-
- .weak FLASH_IRQHandler
- .thumb_set FLASH_IRQHandler,Default_Handler
-
- .weak RCC_CRS_IRQHandler
- .thumb_set RCC_CRS_IRQHandler,Default_Handler
-
- .weak EXTI0_1_IRQHandler
- .thumb_set EXTI0_1_IRQHandler,Default_Handler
-
- .weak EXTI2_3_IRQHandler
- .thumb_set EXTI2_3_IRQHandler,Default_Handler
-
- .weak EXTI4_15_IRQHandler
- .thumb_set EXTI4_15_IRQHandler,Default_Handler
-
- .weak TSC_IRQHandler
- .thumb_set TSC_IRQHandler,Default_Handler
-
- .weak DMA1_Channel1_IRQHandler
- .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
- .weak DMA1_Channel2_3_IRQHandler
- .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler
-
- .weak DMA1_Channel4_5_IRQHandler
- .thumb_set DMA1_Channel4_5_IRQHandler,Default_Handler
-
- .weak ADC1_IRQHandler
- .thumb_set ADC1_IRQHandler,Default_Handler
-
- .weak TIM1_BRK_UP_TRG_COM_IRQHandler
- .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler
-
- .weak TIM1_CC_IRQHandler
- .thumb_set TIM1_CC_IRQHandler,Default_Handler
-
- .weak TIM2_IRQHandler
- .thumb_set TIM2_IRQHandler,Default_Handler
-
- .weak TIM3_IRQHandler
- .thumb_set TIM3_IRQHandler,Default_Handler
-
- .weak TIM14_IRQHandler
- .thumb_set TIM14_IRQHandler,Default_Handler
-
- .weak TIM16_IRQHandler
- .thumb_set TIM16_IRQHandler,Default_Handler
-
- .weak TIM17_IRQHandler
- .thumb_set TIM17_IRQHandler,Default_Handler
-
- .weak I2C1_IRQHandler
- .thumb_set I2C1_IRQHandler,Default_Handler
-
- .weak SPI1_IRQHandler
- .thumb_set SPI1_IRQHandler,Default_Handler
-
- .weak SPI2_IRQHandler
- .thumb_set SPI2_IRQHandler,Default_Handler
-
- .weak USART1_IRQHandler
- .thumb_set USART1_IRQHandler,Default_Handler
-
- .weak USART2_IRQHandler
- .thumb_set USART2_IRQHandler,Default_Handler
-
- .weak CEC_CAN_IRQHandler
- .thumb_set CEC_CAN_IRQHandler,Default_Handler
-
-
- .weak USB_IRQHandler
- .thumb_set USB_IRQHandler,Default_Handler
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/TrueSTUDIO/startup_stm32f051.s b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/TrueSTUDIO/startup_stm32f051.s
deleted file mode 100644
index d44725aa9959ec2782fd5c52d6cd627f320f23a6..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/TrueSTUDIO/startup_stm32f051.s
+++ /dev/null
@@ -1,295 +0,0 @@
-/**
- ******************************************************************************
- * @file startup_stm32f051.s
- * @author MCD Application Team
- * @version V1.3.1
- * @date 17-January-2014
- * @brief STM32F051 Devices vector table for Atollic toolchain.
- * This module performs:
- * - Set the initial SP
- * - Set the initial PC == Reset_Handler,
- * - Set the vector table entries with the exceptions ISR address
- * - Configure the system clock
- * - Branches to main in the C library (which eventually
- * calls main()).
- * After Reset the Cortex-M0 processor is in Thread mode,
- * priority is Privileged, and the Stack is set to Main.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
- .syntax unified
- .cpu cortex-m0
- .fpu softvfp
- .thumb
-
-.global g_pfnVectors
-.global Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word _sidata
-/* start address for the .data section. defined in linker script */
-.word _sdata
-/* end address for the .data section. defined in linker script */
-.word _edata
-/* start address for the .bss section. defined in linker script */
-.word _sbss
-/* end address for the .bss section. defined in linker script */
-.word _ebss
-
- .section .text.Reset_Handler
- .weak Reset_Handler
- .type Reset_Handler, %function
-Reset_Handler:
- ldr r0, =_estack
- mov sp, r0 /* set stack pointer */
-
-/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
- b LoopCopyDataInit
-
-CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
-
-LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
- bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
-/* Zero fill the bss segment. */
-FillZerobss:
- movs r3, #0
- str r3, [r2]
- adds r2, r2, #4
-
-
-LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
- bcc FillZerobss
-
-/* Call the clock system intitialization function.*/
- bl SystemInit
-/* Call static constructors */
- bl __libc_init_array
-/* Call the application's entry point.*/
- bl main
-
-LoopForever:
- b LoopForever
-
-
-.size Reset_Handler, .-Reset_Handler
-
-/**
- * @brief This is the code that gets called when the processor receives an
- * unexpected interrupt. This simply enters an infinite loop, preserving
- * the system state for examination by a debugger.
- *
- * @param None
- * @retval : None
-*/
- .section .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
- b Infinite_Loop
- .size Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M0. Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
- .section .isr_vector,"a",%progbits
- .type g_pfnVectors, %object
- .size g_pfnVectors, .-g_pfnVectors
-
-g_pfnVectors:
- .word _estack
- .word Reset_Handler
-
- .word NMI_Handler
- .word HardFault_Handler
- .word 0
- .word 0
- .word 0
- .word 0
- .word 0
- .word 0
- .word 0
- .word SVC_Handler
- .word 0
- .word 0
- .word PendSV_Handler
- .word SysTick_Handler
-
-
- .word WWDG_IRQHandler
- .word PVD_IRQHandler
- .word RTC_IRQHandler
- .word FLASH_IRQHandler
- .word RCC_IRQHandler
- .word EXTI0_1_IRQHandler
- .word EXTI2_3_IRQHandler
- .word EXTI4_15_IRQHandler
- .word TS_IRQHandler
- .word DMA1_Channel1_IRQHandler
- .word DMA1_Channel2_3_IRQHandler
- .word DMA1_Channel4_5_IRQHandler
- .word ADC1_COMP_IRQHandler
- .word TIM1_BRK_UP_TRG_COM_IRQHandler
- .word TIM1_CC_IRQHandler
- .word TIM2_IRQHandler
- .word TIM3_IRQHandler
- .word TIM6_DAC_IRQHandler
- .word 0
- .word TIM14_IRQHandler
- .word TIM15_IRQHandler
- .word TIM16_IRQHandler
- .word TIM17_IRQHandler
- .word I2C1_IRQHandler
- .word I2C2_IRQHandler
- .word SPI1_IRQHandler
- .word SPI2_IRQHandler
- .word USART1_IRQHandler
- .word USART2_IRQHandler
- .word 0
- .word CEC_IRQHandler
- .word 0
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
-
- .weak NMI_Handler
- .thumb_set NMI_Handler,Default_Handler
-
- .weak HardFault_Handler
- .thumb_set HardFault_Handler,Default_Handler
-
- .weak SVC_Handler
- .thumb_set SVC_Handler,Default_Handler
-
- .weak PendSV_Handler
- .thumb_set PendSV_Handler,Default_Handler
-
- .weak SysTick_Handler
- .thumb_set SysTick_Handler,Default_Handler
-
- .weak WWDG_IRQHandler
- .thumb_set WWDG_IRQHandler,Default_Handler
-
- .weak PVD_IRQHandler
- .thumb_set PVD_IRQHandler,Default_Handler
-
- .weak RTC_IRQHandler
- .thumb_set RTC_IRQHandler,Default_Handler
-
- .weak FLASH_IRQHandler
- .thumb_set FLASH_IRQHandler,Default_Handler
-
- .weak RCC_IRQHandler
- .thumb_set RCC_IRQHandler,Default_Handler
-
- .weak EXTI0_1_IRQHandler
- .thumb_set EXTI0_1_IRQHandler,Default_Handler
-
- .weak EXTI2_3_IRQHandler
- .thumb_set EXTI2_3_IRQHandler,Default_Handler
-
- .weak EXTI4_15_IRQHandler
- .thumb_set EXTI4_15_IRQHandler,Default_Handler
-
- .weak TS_IRQHandler
- .thumb_set TS_IRQHandler,Default_Handler
-
- .weak DMA1_Channel1_IRQHandler
- .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
- .weak DMA1_Channel2_3_IRQHandler
- .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler
-
- .weak DMA1_Channel4_5_IRQHandler
- .thumb_set DMA1_Channel4_5_IRQHandler,Default_Handler
-
- .weak ADC1_COMP_IRQHandler
- .thumb_set ADC1_COMP_IRQHandler,Default_Handler
-
- .weak TIM1_BRK_UP_TRG_COM_IRQHandler
- .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler
-
- .weak TIM1_CC_IRQHandler
- .thumb_set TIM1_CC_IRQHandler,Default_Handler
-
- .weak TIM2_IRQHandler
- .thumb_set TIM2_IRQHandler,Default_Handler
-
- .weak TIM3_IRQHandler
- .thumb_set TIM3_IRQHandler,Default_Handler
-
- .weak TIM6_DAC_IRQHandler
- .thumb_set TIM6_DAC_IRQHandler,Default_Handler
-
- .weak TIM14_IRQHandler
- .thumb_set TIM14_IRQHandler,Default_Handler
-
- .weak TIM15_IRQHandler
- .thumb_set TIM15_IRQHandler,Default_Handler
-
- .weak TIM16_IRQHandler
- .thumb_set TIM16_IRQHandler,Default_Handler
-
- .weak TIM17_IRQHandler
- .thumb_set TIM17_IRQHandler,Default_Handler
-
- .weak I2C1_IRQHandler
- .thumb_set I2C1_IRQHandler,Default_Handler
-
- .weak I2C2_IRQHandler
- .thumb_set I2C2_IRQHandler,Default_Handler
-
- .weak SPI1_IRQHandler
- .thumb_set SPI1_IRQHandler,Default_Handler
-
- .weak SPI2_IRQHandler
- .thumb_set SPI2_IRQHandler,Default_Handler
-
- .weak USART1_IRQHandler
- .thumb_set USART1_IRQHandler,Default_Handler
-
- .weak USART2_IRQHandler
- .thumb_set USART2_IRQHandler,Default_Handler
-
- .weak CEC_IRQHandler
- .thumb_set CEC_IRQHandler,Default_Handler
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/TrueSTUDIO/startup_stm32f072.s b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/TrueSTUDIO/startup_stm32f072.s
deleted file mode 100644
index 2a270e50b4ae3fd442af6175ae8e6aa12295ac92..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/TrueSTUDIO/startup_stm32f072.s
+++ /dev/null
@@ -1,304 +0,0 @@
-/**
- ******************************************************************************
- * @file startup_stm32f072.s
- * @author MCD Application Team
- * @version V1.3.1
- * @date 17-January-2014
- * @brief STM32F072 Devices vector table for Atollic toolchain.
- * This module performs:
- * - Set the initial SP
- * - Set the initial PC == Reset_Handler,
- * - Set the vector table entries with the exceptions ISR address
- * - Configure the system clock
- * - Branches to main in the C library (which eventually
- * calls main()).
- * After Reset the Cortex-M0 processor is in Thread mode,
- * priority is Privileged, and the Stack is set to Main.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
- .syntax unified
- .cpu cortex-m0
- .fpu softvfp
- .thumb
-
-.global g_pfnVectors
-.global Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word _sidata
-/* start address for the .data section. defined in linker script */
-.word _sdata
-/* end address for the .data section. defined in linker script */
-.word _edata
-/* start address for the .bss section. defined in linker script */
-.word _sbss
-/* end address for the .bss section. defined in linker script */
-.word _ebss
-
- .section .text.Reset_Handler
- .weak Reset_Handler
- .type Reset_Handler, %function
-Reset_Handler:
- ldr r0, =_estack
- mov sp, r0 /* set stack pointer */
-
-/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
- b LoopCopyDataInit
-
-CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
-
-LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
- bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
-/* Zero fill the bss segment. */
-FillZerobss:
- movs r3, #0
- str r3, [r2]
- adds r2, r2, #4
-
-
-LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
- bcc FillZerobss
-
-/* Call the clock system intitialization function.*/
- bl SystemInit
-/* Call static constructors */
- bl __libc_init_array
-/* Call the application's entry point.*/
- bl main
-
-LoopForever:
- b LoopForever
-
-
-.size Reset_Handler, .-Reset_Handler
-
-/**
- * @brief This is the code that gets called when the processor receives an
- * unexpected interrupt. This simply enters an infinite loop, preserving
- * the system state for examination by a debugger.
- *
- * @param None
- * @retval : None
-*/
- .section .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
- b Infinite_Loop
- .size Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M0. Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
- .section .isr_vector,"a",%progbits
- .type g_pfnVectors, %object
- .size g_pfnVectors, .-g_pfnVectors
-
-g_pfnVectors:
- .word _estack
- .word Reset_Handler
-
- .word NMI_Handler
- .word HardFault_Handler
- .word 0
- .word 0
- .word 0
- .word 0
- .word 0
- .word 0
- .word 0
- .word SVC_Handler
- .word 0
- .word 0
- .word PendSV_Handler
- .word SysTick_Handler
-
-
- .word WWDG_IRQHandler
- .word PVD_VDDIO2_IRQHandler
- .word RTC_IRQHandler
- .word FLASH_IRQHandler
- .word RCC_CRS_IRQHandler
- .word EXTI0_1_IRQHandler
- .word EXTI2_3_IRQHandler
- .word EXTI4_15_IRQHandler
- .word TSC_IRQHandler
- .word DMA1_Channel1_IRQHandler
- .word DMA1_Channel2_3_IRQHandler
- .word DMA1_Channel4_5_6_7_IRQHandler
- .word ADC1_COMP_IRQHandler
- .word TIM1_BRK_UP_TRG_COM_IRQHandler
- .word TIM1_CC_IRQHandler
- .word TIM2_IRQHandler
- .word TIM3_IRQHandler
- .word TIM6_DAC_IRQHandler
- .word TIM7_IRQHandler
- .word TIM14_IRQHandler
- .word TIM15_IRQHandler
- .word TIM16_IRQHandler
- .word TIM17_IRQHandler
- .word I2C1_IRQHandler
- .word I2C2_IRQHandler
- .word SPI1_IRQHandler
- .word SPI2_IRQHandler
- .word USART1_IRQHandler
- .word USART2_IRQHandler
- .word USART3_4_IRQHandler
- .word CEC_CAN_IRQHandler
- .word USB_IRQHandler
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
-
- .weak NMI_Handler
- .thumb_set NMI_Handler,Default_Handler
-
- .weak HardFault_Handler
- .thumb_set HardFault_Handler,Default_Handler
-
- .weak SVC_Handler
- .thumb_set SVC_Handler,Default_Handler
-
- .weak PendSV_Handler
- .thumb_set PendSV_Handler,Default_Handler
-
- .weak SysTick_Handler
- .thumb_set SysTick_Handler,Default_Handler
-
- .weak WWDG_IRQHandler
- .thumb_set WWDG_IRQHandler,Default_Handler
-
- .weak PVD_VDDIO2_IRQHandler
- .thumb_set PVD_VDDIO2_IRQHandler,Default_Handler
-
- .weak RTC_IRQHandler
- .thumb_set RTC_IRQHandler,Default_Handler
-
- .weak FLASH_IRQHandler
- .thumb_set FLASH_IRQHandler,Default_Handler
-
- .weak RCC_CRS_IRQHandler
- .thumb_set RCC_CRS_IRQHandler,Default_Handler
-
- .weak EXTI0_1_IRQHandler
- .thumb_set EXTI0_1_IRQHandler,Default_Handler
-
- .weak EXTI2_3_IRQHandler
- .thumb_set EXTI2_3_IRQHandler,Default_Handler
-
- .weak EXTI4_15_IRQHandler
- .thumb_set EXTI4_15_IRQHandler,Default_Handler
-
- .weak TSC_IRQHandler
- .thumb_set TSC_IRQHandler,Default_Handler
-
- .weak DMA1_Channel1_IRQHandler
- .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
- .weak DMA1_Channel2_3_IRQHandler
- .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler
-
- .weak DMA1_Channel4_5_6_7_IRQHandler
- .thumb_set DMA1_Channel4_5_6_7_IRQHandler,Default_Handler
-
- .weak ADC1_COMP_IRQHandler
- .thumb_set ADC1_COMP_IRQHandler,Default_Handler
-
- .weak TIM1_BRK_UP_TRG_COM_IRQHandler
- .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler
-
- .weak TIM1_CC_IRQHandler
- .thumb_set TIM1_CC_IRQHandler,Default_Handler
-
- .weak TIM2_IRQHandler
- .thumb_set TIM2_IRQHandler,Default_Handler
-
- .weak TIM3_IRQHandler
- .thumb_set TIM3_IRQHandler,Default_Handler
-
- .weak TIM6_DAC_IRQHandler
- .thumb_set TIM6_DAC_IRQHandler,Default_Handler
-
- .weak TIM7_IRQHandler
- .thumb_set TIM7_IRQHandler,Default_Handler
-
- .weak TIM14_IRQHandler
- .thumb_set TIM14_IRQHandler,Default_Handler
-
- .weak TIM15_IRQHandler
- .thumb_set TIM15_IRQHandler,Default_Handler
-
- .weak TIM16_IRQHandler
- .thumb_set TIM16_IRQHandler,Default_Handler
-
- .weak TIM17_IRQHandler
- .thumb_set TIM17_IRQHandler,Default_Handler
-
- .weak I2C1_IRQHandler
- .thumb_set I2C1_IRQHandler,Default_Handler
-
- .weak I2C2_IRQHandler
- .thumb_set I2C2_IRQHandler,Default_Handler
-
- .weak SPI1_IRQHandler
- .thumb_set SPI1_IRQHandler,Default_Handler
-
- .weak SPI2_IRQHandler
- .thumb_set SPI2_IRQHandler,Default_Handler
-
- .weak USART1_IRQHandler
- .thumb_set USART1_IRQHandler,Default_Handler
-
- .weak USART2_IRQHandler
- .thumb_set USART2_IRQHandler,Default_Handler
-
- .weak USART3_4_IRQHandler
- .thumb_set USART3_4_IRQHandler,Default_Handler
-
- .weak CEC_CAN_IRQHandler
- .thumb_set CEC_CAN_IRQHandler,Default_Handler
-
- .weak USB_IRQHandler
- .thumb_set USB_IRQHandler,Default_Handler
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/TrueSTUDIO/startup_stm32f0xx.s b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/TrueSTUDIO/startup_stm32f0xx.s
deleted file mode 100644
index 36b18c70e02c55769fc2f694327ed152a4ff4de4..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/TrueSTUDIO/startup_stm32f0xx.s
+++ /dev/null
@@ -1,293 +0,0 @@
-/**
- ******************************************************************************
- * @file startup_stm32f0xx.s
- * @author MCD Application Team
- * @version V1.3.1
- * @date 17-January-2014
- * @brief STM32F0xx Devices vector table for Atollic toolchain.
- * This module performs:
- * - Set the initial SP
- * - Set the initial PC == Reset_Handler,
- * - Set the vector table entries with the exceptions ISR address
- * - Configure the system clock
- * - Branches to main in the C library (which eventually
- * calls main()).
- * After Reset the Cortex-M0 processor is in Thread mode,
- * priority is Privileged, and the Stack is set to Main.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
- .syntax unified
- .cpu cortex-m0
- .fpu softvfp
- .thumb
-
-.global g_pfnVectors
-.global Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word _sidata
-/* start address for the .data section. defined in linker script */
-.word _sdata
-/* end address for the .data section. defined in linker script */
-.word _edata
-/* start address for the .bss section. defined in linker script */
-.word _sbss
-/* end address for the .bss section. defined in linker script */
-.word _ebss
-
- .section .text.Reset_Handler
- .weak Reset_Handler
- .type Reset_Handler, %function
-Reset_Handler:
- ldr r0, =_estack
- mov sp, r0 /* set stack pointer */
-
-/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
- b LoopCopyDataInit
-
-CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
-
-LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
- bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
-/* Zero fill the bss segment. */
-FillZerobss:
- movs r3, #0
- str r3, [r2]
- adds r2, r2, #4
-
-
-LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
- bcc FillZerobss
-
-/* Call the clock system intitialization function.*/
- bl SystemInit
-/* Call static constructors */
- bl __libc_init_array
-/* Call the application's entry point.*/
- bl main
-
-LoopForever:
- b LoopForever
-
-
-.size Reset_Handler, .-Reset_Handler
-
-/**
- * @brief This is the code that gets called when the processor receives an
- * unexpected interrupt. This simply enters an infinite loop, preserving
- * the system state for examination by a debugger.
- *
- * @param None
- * @retval : None
-*/
- .section .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
- b Infinite_Loop
- .size Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M0. Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
- .section .isr_vector,"a",%progbits
- .type g_pfnVectors, %object
- .size g_pfnVectors, .-g_pfnVectors
-
-
-g_pfnVectors:
- .word _estack
- .word Reset_Handler
- .word NMI_Handler
- .word HardFault_Handler
- .word 0
- .word 0
- .word 0
- .word 0
- .word 0
- .word 0
- .word 0
- .word SVC_Handler
- .word 0
- .word 0
- .word PendSV_Handler
- .word SysTick_Handler
- .word WWDG_IRQHandler
- .word PVD_IRQHandler
- .word RTC_IRQHandler
- .word FLASH_IRQHandler
- .word RCC_IRQHandler
- .word EXTI0_1_IRQHandler
- .word EXTI2_3_IRQHandler
- .word EXTI4_15_IRQHandler
- .word TS_IRQHandler
- .word DMA1_Channel1_IRQHandler
- .word DMA1_Channel2_3_IRQHandler
- .word DMA1_Channel4_5_IRQHandler
- .word ADC1_COMP_IRQHandler
- .word TIM1_BRK_UP_TRG_COM_IRQHandler
- .word TIM1_CC_IRQHandler
- .word TIM2_IRQHandler
- .word TIM3_IRQHandler
- .word TIM6_DAC_IRQHandler
- .word 0
- .word TIM14_IRQHandler
- .word TIM15_IRQHandler
- .word TIM16_IRQHandler
- .word TIM17_IRQHandler
- .word I2C1_IRQHandler
- .word I2C2_IRQHandler
- .word SPI1_IRQHandler
- .word SPI2_IRQHandler
- .word USART1_IRQHandler
- .word USART2_IRQHandler
- .word 0
- .word CEC_IRQHandler
- .word 0
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
-
- .weak NMI_Handler
- .thumb_set NMI_Handler,Default_Handler
-
- .weak HardFault_Handler
- .thumb_set HardFault_Handler,Default_Handler
-
- .weak SVC_Handler
- .thumb_set SVC_Handler,Default_Handler
-
- .weak PendSV_Handler
- .thumb_set PendSV_Handler,Default_Handler
-
- .weak SysTick_Handler
- .thumb_set SysTick_Handler,Default_Handler
-
- .weak WWDG_IRQHandler
- .thumb_set WWDG_IRQHandler,Default_Handler
-
- .weak PVD_IRQHandler
- .thumb_set PVD_IRQHandler,Default_Handler
-
- .weak RTC_IRQHandler
- .thumb_set RTC_IRQHandler,Default_Handler
-
- .weak FLASH_IRQHandler
- .thumb_set FLASH_IRQHandler,Default_Handler
-
- .weak RCC_IRQHandler
- .thumb_set RCC_IRQHandler,Default_Handler
-
- .weak EXTI0_1_IRQHandler
- .thumb_set EXTI0_1_IRQHandler,Default_Handler
-
- .weak EXTI2_3_IRQHandler
- .thumb_set EXTI2_3_IRQHandler,Default_Handler
-
- .weak EXTI4_15_IRQHandler
- .thumb_set EXTI4_15_IRQHandler,Default_Handler
-
- .weak TS_IRQHandler
- .thumb_set TS_IRQHandler,Default_Handler
-
- .weak DMA1_Channel1_IRQHandler
- .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
- .weak DMA1_Channel2_3_IRQHandler
- .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler
-
- .weak DMA1_Channel4_5_IRQHandler
- .thumb_set DMA1_Channel4_5_IRQHandler,Default_Handler
-
- .weak ADC1_COMP_IRQHandler
- .thumb_set ADC1_COMP_IRQHandler,Default_Handler
-
- .weak TIM1_BRK_UP_TRG_COM_IRQHandler
- .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler
-
- .weak TIM1_CC_IRQHandler
- .thumb_set TIM1_CC_IRQHandler,Default_Handler
-
- .weak TIM2_IRQHandler
- .thumb_set TIM2_IRQHandler,Default_Handler
-
- .weak TIM3_IRQHandler
- .thumb_set TIM3_IRQHandler,Default_Handler
-
- .weak TIM6_DAC_IRQHandler
- .thumb_set TIM6_DAC_IRQHandler,Default_Handler
-
- .weak TIM14_IRQHandler
- .thumb_set TIM14_IRQHandler,Default_Handler
-
- .weak TIM15_IRQHandler
- .thumb_set TIM15_IRQHandler,Default_Handler
-
- .weak TIM16_IRQHandler
- .thumb_set TIM16_IRQHandler,Default_Handler
-
- .weak TIM17_IRQHandler
- .thumb_set TIM17_IRQHandler,Default_Handler
-
- .weak I2C1_IRQHandler
- .thumb_set I2C1_IRQHandler,Default_Handler
-
- .weak I2C2_IRQHandler
- .thumb_set I2C2_IRQHandler,Default_Handler
-
- .weak SPI1_IRQHandler
- .thumb_set SPI1_IRQHandler,Default_Handler
-
- .weak SPI2_IRQHandler
- .thumb_set SPI2_IRQHandler,Default_Handler
-
- .weak USART1_IRQHandler
- .thumb_set USART1_IRQHandler,Default_Handler
-
- .weak USART2_IRQHandler
- .thumb_set USART2_IRQHandler,Default_Handler
-
- .weak CEC_IRQHandler
- .thumb_set CEC_IRQHandler,Default_Handler
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/TrueSTUDIO/startup_stm32f0xx_ld.s b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/TrueSTUDIO/startup_stm32f0xx_ld.s
deleted file mode 100644
index aa59dabc1b8975e3bea1541064f0b51837c87fd7..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/TrueSTUDIO/startup_stm32f0xx_ld.s
+++ /dev/null
@@ -1,273 +0,0 @@
-/**
- ******************************************************************************
- * @file startup_stm32f0xx_ld.s
- * @author MCD Application Team
- * @version V1.3.1
- * @date 17-January-2014
- * @brief STM32F031 devices vector table for Atollic toolchain.
- * This module performs:
- * - Set the initial SP
- * - Set the initial PC == Reset_Handler,
- * - Set the vector table entries with the exceptions ISR address
- * - Configure the system clock
- * - Branches to main in the C library (which eventually
- * calls main()).
- * After Reset the Cortex-M0 processor is in Thread mode,
- * priority is Privileged, and the Stack is set to Main.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
- .syntax unified
- .cpu cortex-m0
- .fpu softvfp
- .thumb
-
-.global g_pfnVectors
-.global Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word _sidata
-/* start address for the .data section. defined in linker script */
-.word _sdata
-/* end address for the .data section. defined in linker script */
-.word _edata
-/* start address for the .bss section. defined in linker script */
-.word _sbss
-/* end address for the .bss section. defined in linker script */
-.word _ebss
-
- .section .text.Reset_Handler
- .weak Reset_Handler
- .type Reset_Handler, %function
-Reset_Handler:
- ldr r0, =_estack
- mov sp, r0 /* set stack pointer */
-
-/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
- b LoopCopyDataInit
-
-CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
-
-LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
- bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
-/* Zero fill the bss segment. */
-FillZerobss:
- movs r3, #0
- str r3, [r2]
- adds r2, r2, #4
-
-
-LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
- bcc FillZerobss
-
-/* Call the clock system intitialization function.*/
- bl SystemInit
-/* Call static constructors */
- bl __libc_init_array
-/* Call the application's entry point.*/
- bl main
-
-LoopForever:
- b LoopForever
-
-
-.size Reset_Handler, .-Reset_Handler
-
-/**
- * @brief This is the code that gets called when the processor receives an
- * unexpected interrupt. This simply enters an infinite loop, preserving
- * the system state for examination by a debugger.
- *
- * @param None
- * @retval : None
-*/
- .section .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
- b Infinite_Loop
- .size Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M0. Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
- .section .isr_vector,"a",%progbits
- .type g_pfnVectors, %object
- .size g_pfnVectors, .-g_pfnVectors
-
-
-g_pfnVectors:
- .word _estack
- .word Reset_Handler
- .word NMI_Handler
- .word HardFault_Handler
- .word 0
- .word 0
- .word 0
- .word 0
- .word 0
- .word 0
- .word 0
- .word SVC_Handler
- .word 0
- .word 0
- .word PendSV_Handler
- .word SysTick_Handler
- .word WWDG_IRQHandler
- .word PVD_IRQHandler
- .word RTC_IRQHandler
- .word FLASH_IRQHandler
- .word RCC_IRQHandler
- .word EXTI0_1_IRQHandler
- .word EXTI2_3_IRQHandler
- .word EXTI4_15_IRQHandler
- .word 0
- .word DMA1_Channel1_IRQHandler
- .word DMA1_Channel2_3_IRQHandler
- .word DMA1_Channel4_5_IRQHandler
- .word ADC1_IRQHandler
- .word TIM1_BRK_UP_TRG_COM_IRQHandler
- .word TIM1_CC_IRQHandler
- .word TIM2_IRQHandler
- .word TIM3_IRQHandler
- .word 0
- .word 0
- .word TIM14_IRQHandler
- .word 0
- .word TIM16_IRQHandler
- .word TIM17_IRQHandler
- .word I2C1_IRQHandler
- .word 0
- .word SPI1_IRQHandler
- .word 0
- .word USART1_IRQHandler
- .word 0
- .word 0
- .word 0
- .word 0
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
-
- .weak NMI_Handler
- .thumb_set NMI_Handler,Default_Handler
-
- .weak HardFault_Handler
- .thumb_set HardFault_Handler,Default_Handler
-
- .weak SVC_Handler
- .thumb_set SVC_Handler,Default_Handler
-
- .weak PendSV_Handler
- .thumb_set PendSV_Handler,Default_Handler
-
- .weak SysTick_Handler
- .thumb_set SysTick_Handler,Default_Handler
-
- .weak WWDG_IRQHandler
- .thumb_set WWDG_IRQHandler,Default_Handler
-
- .weak PVD_IRQHandler
- .thumb_set PVD_IRQHandler,Default_Handler
-
- .weak RTC_IRQHandler
- .thumb_set RTC_IRQHandler,Default_Handler
-
- .weak FLASH_IRQHandler
- .thumb_set FLASH_IRQHandler,Default_Handler
-
- .weak RCC_IRQHandler
- .thumb_set RCC_IRQHandler,Default_Handler
-
- .weak EXTI0_1_IRQHandler
- .thumb_set EXTI0_1_IRQHandler,Default_Handler
-
- .weak EXTI2_3_IRQHandler
- .thumb_set EXTI2_3_IRQHandler,Default_Handler
-
- .weak EXTI4_15_IRQHandler
- .thumb_set EXTI4_15_IRQHandler,Default_Handler
-
- .weak DMA1_Channel1_IRQHandler
- .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
- .weak DMA1_Channel2_3_IRQHandler
- .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler
-
- .weak DMA1_Channel4_5_IRQHandler
- .thumb_set DMA1_Channel4_5_IRQHandler,Default_Handler
-
- .weak ADC1_IRQHandler
- .thumb_set ADC1_IRQHandler,Default_Handler
-
- .weak TIM1_BRK_UP_TRG_COM_IRQHandler
- .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler
-
- .weak TIM1_CC_IRQHandler
- .thumb_set TIM1_CC_IRQHandler,Default_Handler
-
- .weak TIM2_IRQHandler
- .thumb_set TIM2_IRQHandler,Default_Handler
-
- .weak TIM3_IRQHandler
- .thumb_set TIM3_IRQHandler,Default_Handler
-
- .weak TIM14_IRQHandler
- .thumb_set TIM14_IRQHandler,Default_Handler
-
- .weak TIM16_IRQHandler
- .thumb_set TIM16_IRQHandler,Default_Handler
-
- .weak TIM17_IRQHandler
- .thumb_set TIM17_IRQHandler,Default_Handler
-
- .weak I2C1_IRQHandler
- .thumb_set I2C1_IRQHandler,Default_Handler
-
- .weak SPI1_IRQHandler
- .thumb_set SPI1_IRQHandler,Default_Handler
-
- .weak USART1_IRQHandler
- .thumb_set USART1_IRQHandler,Default_Handler
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/arm/startup_stm32f030.s b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/arm/startup_stm32f030.s
deleted file mode 100644
index 187f5d774266ca25df940e8a2fb808fabfa71a0c..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/arm/startup_stm32f030.s
+++ /dev/null
@@ -1,244 +0,0 @@
-;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
-;* File Name : startup_stm32f030.s
-;* Author : MCD Application Team
-;* Version : V1.3.1
-;* Date : 17-January-2014
-;* Description : STM32F030 devices vector table for MDK-ARM toolchain.
-;* This module performs:
-;* - Set the initial SP
-;* - Set the initial PC == Reset_Handler
-;* - Set the vector table entries with the exceptions ISR address
-;* - Configure the system clock
-;* - Branches to __main in the C library (which eventually
-;* calls main()).
-;* After Reset the CortexM0 processor is in Thread mode,
-;* priority is Privileged, and the Stack is set to Main.
-;* <<< Use Configuration Wizard in Context Menu >>>
-;*******************************************************************************
-; @attention
-;
-; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-; You may not use this file except in compliance with the License.
-; You may obtain a copy of the License at:
-;
-; http://www.st.com/software_license_agreement_liberty_v2
-;
-; Unless required by applicable law or agreed to in writing, software
-; distributed under the License is distributed on an "AS IS" BASIS,
-; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-; See the License for the specific language governing permissions and
-; limitations under the License.
-;
-;*******************************************************************************
-;
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size EQU 0x00000400
-
- AREA STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem SPACE Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size EQU 0x00000200
-
- AREA HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem SPACE Heap_Size
-__heap_limit
-
- PRESERVE8
- THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
- AREA RESET, DATA, READONLY
- EXPORT __Vectors
- EXPORT __Vectors_End
- EXPORT __Vectors_Size
-
-__Vectors DCD __initial_sp ; Top of Stack
- DCD Reset_Handler ; Reset Handler
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
-
- ; External Interrupts
- DCD WWDG_IRQHandler ; Window Watchdog
- DCD 0 ; Reserved
- DCD RTC_IRQHandler ; RTC through EXTI Line
- DCD FLASH_IRQHandler ; FLASH
- DCD RCC_IRQHandler ; RCC
- DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1
- DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3
- DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15
- DCD 0 ; Reserved
- DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
- DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3
- DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5
- DCD ADC1_IRQHandler ; ADC1
- DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
- DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
- DCD 0 ; Reserved
- DCD TIM3_IRQHandler ; TIM3
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD TIM14_IRQHandler ; TIM14
- DCD TIM15_IRQHandler ; TIM15
- DCD TIM16_IRQHandler ; TIM16
- DCD TIM17_IRQHandler ; TIM17
- DCD I2C1_IRQHandler ; I2C1
- DCD I2C2_IRQHandler ; I2C2
- DCD SPI1_IRQHandler ; SPI1
- DCD SPI2_IRQHandler ; SPI2
- DCD USART1_IRQHandler ; USART1
- DCD USART2_IRQHandler ; USART2
-
-__Vectors_End
-
-__Vectors_Size EQU __Vectors_End - __Vectors
-
- AREA |.text|, CODE, READONLY
-
-; Reset handler routine
-Reset_Handler PROC
- EXPORT Reset_Handler [WEAK]
- IMPORT __main
- IMPORT SystemInit
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__main
- BX R0
- ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler PROC
- EXPORT NMI_Handler [WEAK]
- B .
- ENDP
-HardFault_Handler\
- PROC
- EXPORT HardFault_Handler [WEAK]
- B .
- ENDP
-SVC_Handler PROC
- EXPORT SVC_Handler [WEAK]
- B .
- ENDP
-PendSV_Handler PROC
- EXPORT PendSV_Handler [WEAK]
- B .
- ENDP
-SysTick_Handler PROC
- EXPORT SysTick_Handler [WEAK]
- B .
- ENDP
-
-Default_Handler PROC
-
- EXPORT WWDG_IRQHandler [WEAK]
- EXPORT RTC_IRQHandler [WEAK]
- EXPORT FLASH_IRQHandler [WEAK]
- EXPORT RCC_IRQHandler [WEAK]
- EXPORT EXTI0_1_IRQHandler [WEAK]
- EXPORT EXTI2_3_IRQHandler [WEAK]
- EXPORT EXTI4_15_IRQHandler [WEAK]
- EXPORT DMA1_Channel1_IRQHandler [WEAK]
- EXPORT DMA1_Channel2_3_IRQHandler [WEAK]
- EXPORT DMA1_Channel4_5_IRQHandler [WEAK]
- EXPORT ADC1_IRQHandler [WEAK]
- EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK]
- EXPORT TIM1_CC_IRQHandler [WEAK]
- EXPORT TIM3_IRQHandler [WEAK]
- EXPORT TIM14_IRQHandler [WEAK]
- EXPORT TIM15_IRQHandler [WEAK]
- EXPORT TIM16_IRQHandler [WEAK]
- EXPORT TIM17_IRQHandler [WEAK]
- EXPORT I2C1_IRQHandler [WEAK]
- EXPORT I2C2_IRQHandler [WEAK]
- EXPORT SPI1_IRQHandler [WEAK]
- EXPORT SPI2_IRQHandler [WEAK]
- EXPORT USART1_IRQHandler [WEAK]
- EXPORT USART2_IRQHandler [WEAK]
-
-
-WWDG_IRQHandler
-RTC_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_1_IRQHandler
-EXTI2_3_IRQHandler
-EXTI4_15_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_3_IRQHandler
-DMA1_Channel4_5_IRQHandler
-ADC1_IRQHandler
-TIM1_BRK_UP_TRG_COM_IRQHandler
-TIM1_CC_IRQHandler
-TIM3_IRQHandler
-TIM14_IRQHandler
-TIM15_IRQHandler
-TIM16_IRQHandler
-TIM17_IRQHandler
-I2C1_IRQHandler
-I2C2_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-
- B .
-
- ENDP
-
- ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
- IF :DEF:__MICROLIB
-
- EXPORT __initial_sp
- EXPORT __heap_base
- EXPORT __heap_limit
-
- ELSE
-
- IMPORT __use_two_region_memory
- EXPORT __user_initial_stackheap
-
-__user_initial_stackheap
-
- LDR R0, = Heap_Mem
- LDR R1, =(Stack_Mem + Stack_Size)
- LDR R2, = (Heap_Mem + Heap_Size)
- LDR R3, = Stack_Mem
- BX LR
-
- ALIGN
-
- ENDIF
-
- END
-
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/arm/startup_stm32f031.s b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/arm/startup_stm32f031.s
deleted file mode 100644
index d6b1e6ca116b299edd8a788dc9d986a314fa1aff..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/arm/startup_stm32f031.s
+++ /dev/null
@@ -1,239 +0,0 @@
-;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
-;* File Name : startup_stm32f031.s
-;* Author : MCD Application Team
-;* Version : V1.3.1
-;* Date : 17-January-2014
-;* Description : STM32F031 devices vector table for MDK-ARM toolchain.
-;* This module performs:
-;* - Set the initial SP
-;* - Set the initial PC == Reset_Handler
-;* - Set the vector table entries with the exceptions ISR address
-;* - Configure the system clock
-;* - Branches to __main in the C library (which eventually
-;* calls main()).
-;* After Reset the CortexM0 processor is in Thread mode,
-;* priority is Privileged, and the Stack is set to Main.
-;* <<< Use Configuration Wizard in Context Menu >>>
-;*******************************************************************************
-; @attention
-;
-; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-; You may not use this file except in compliance with the License.
-; You may obtain a copy of the License at:
-;
-; http://www.st.com/software_license_agreement_liberty_v2
-;
-; Unless required by applicable law or agreed to in writing, software
-; distributed under the License is distributed on an "AS IS" BASIS,
-; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-; See the License for the specific language governing permissions and
-; limitations under the License.
-;
-;*******************************************************************************
-;
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size EQU 0x00000400
-
- AREA STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem SPACE Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size EQU 0x00000200
-
- AREA HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem SPACE Heap_Size
-__heap_limit
-
- PRESERVE8
- THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
- AREA RESET, DATA, READONLY
- EXPORT __Vectors
- EXPORT __Vectors_End
- EXPORT __Vectors_Size
-
-__Vectors DCD __initial_sp ; Top of Stack
- DCD Reset_Handler ; Reset Handler
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
-
- ; External Interrupts
- DCD WWDG_IRQHandler ; Window Watchdog
- DCD PVD_IRQHandler ; PVD through EXTI Line detect
- DCD RTC_IRQHandler ; RTC through EXTI Line
- DCD FLASH_IRQHandler ; FLASH
- DCD RCC_IRQHandler ; RCC
- DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1
- DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3
- DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15
- DCD 0 ; Reserved
- DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
- DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3
- DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5
- DCD ADC1_IRQHandler ; ADC1
- DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
- DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
- DCD TIM2_IRQHandler ; TIM2
- DCD TIM3_IRQHandler ; TIM3
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD TIM14_IRQHandler ; TIM14
- DCD 0 ; Reserved
- DCD TIM16_IRQHandler ; TIM16
- DCD TIM17_IRQHandler ; TIM17
- DCD I2C1_IRQHandler ; I2C1
- DCD 0 ; Reserved
- DCD SPI1_IRQHandler ; SPI1
- DCD 0 ; Reserved
- DCD USART1_IRQHandler ; USART1
-
-__Vectors_End
-
-__Vectors_Size EQU __Vectors_End - __Vectors
-
- AREA |.text|, CODE, READONLY
-
-; Reset handler routine
-Reset_Handler PROC
- EXPORT Reset_Handler [WEAK]
- IMPORT __main
- IMPORT SystemInit
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__main
- BX R0
- ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler PROC
- EXPORT NMI_Handler [WEAK]
- B .
- ENDP
-HardFault_Handler\
- PROC
- EXPORT HardFault_Handler [WEAK]
- B .
- ENDP
-SVC_Handler PROC
- EXPORT SVC_Handler [WEAK]
- B .
- ENDP
-PendSV_Handler PROC
- EXPORT PendSV_Handler [WEAK]
- B .
- ENDP
-SysTick_Handler PROC
- EXPORT SysTick_Handler [WEAK]
- B .
- ENDP
-
-Default_Handler PROC
-
- EXPORT WWDG_IRQHandler [WEAK]
- EXPORT PVD_IRQHandler [WEAK]
- EXPORT RTC_IRQHandler [WEAK]
- EXPORT FLASH_IRQHandler [WEAK]
- EXPORT RCC_IRQHandler [WEAK]
- EXPORT EXTI0_1_IRQHandler [WEAK]
- EXPORT EXTI2_3_IRQHandler [WEAK]
- EXPORT EXTI4_15_IRQHandler [WEAK]
- EXPORT DMA1_Channel1_IRQHandler [WEAK]
- EXPORT DMA1_Channel2_3_IRQHandler [WEAK]
- EXPORT DMA1_Channel4_5_IRQHandler [WEAK]
- EXPORT ADC1_IRQHandler [WEAK]
- EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK]
- EXPORT TIM1_CC_IRQHandler [WEAK]
- EXPORT TIM2_IRQHandler [WEAK]
- EXPORT TIM3_IRQHandler [WEAK]
- EXPORT TIM14_IRQHandler [WEAK]
- EXPORT TIM16_IRQHandler [WEAK]
- EXPORT TIM17_IRQHandler [WEAK]
- EXPORT I2C1_IRQHandler [WEAK]
- EXPORT SPI1_IRQHandler [WEAK]
- EXPORT USART1_IRQHandler [WEAK]
-
-
-WWDG_IRQHandler
-PVD_IRQHandler
-RTC_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_1_IRQHandler
-EXTI2_3_IRQHandler
-EXTI4_15_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_3_IRQHandler
-DMA1_Channel4_5_IRQHandler
-ADC1_IRQHandler
-TIM1_BRK_UP_TRG_COM_IRQHandler
-TIM1_CC_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-TIM14_IRQHandler
-TIM16_IRQHandler
-TIM17_IRQHandler
-I2C1_IRQHandler
-SPI1_IRQHandler
-USART1_IRQHandler
-
- B .
-
- ENDP
-
- ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
- IF :DEF:__MICROLIB
-
- EXPORT __initial_sp
- EXPORT __heap_base
- EXPORT __heap_limit
-
- ELSE
-
- IMPORT __use_two_region_memory
- EXPORT __user_initial_stackheap
-
-__user_initial_stackheap
-
- LDR R0, = Heap_Mem
- LDR R1, =(Stack_Mem + Stack_Size)
- LDR R2, = (Heap_Mem + Heap_Size)
- LDR R3, = Stack_Mem
- BX LR
-
- ALIGN
-
- ENDIF
-
- END
-
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/arm/startup_stm32f042.s b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/arm/startup_stm32f042.s
deleted file mode 100644
index ebf6eefef7bad4fe985e9fedf577a16a247a2fe2..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/arm/startup_stm32f042.s
+++ /dev/null
@@ -1,254 +0,0 @@
-;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
-;* File Name : startup_stm32f042.s
-;* Author : MCD Application Team
-;* Version : V1.3.1
-;* Date : 17-January-2014
-;* Description : STM32F042 Devices vector table for
-;* for MDK-ARM toolchain.
-;* This module performs:
-;* - Set the initial SP
-;* - Set the initial PC == Reset_Handler
-;* - Set the vector table entries with the exceptions ISR address
-;* - Configure the system clock
-;* - Branches to __main in the C library (which eventually
-;* calls main()).
-;* After Reset the CortexM0 processor is in Thread mode,
-;* priority is Privileged, and the Stack is set to Main.
-;* <<< Use Configuration Wizard in Context Menu >>>
-;*******************************************************************************
-; @attention
-;
-; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-; You may not use this file except in compliance with the License.
-; You may obtain a copy of the License at:
-;
-; http://www.st.com/software_license_agreement_liberty_v2
-;
-; Unless required by applicable law or agreed to in writing, software
-; distributed under the License is distributed on an "AS IS" BASIS,
-; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-; See the License for the specific language governing permissions and
-; limitations under the License.
-;
-;*******************************************************************************
-;
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size EQU 0x00000400
-
- AREA STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem SPACE Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size EQU 0x00000200
-
- AREA HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem SPACE Heap_Size
-__heap_limit
-
- PRESERVE8
- THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
- AREA RESET, DATA, READONLY
- EXPORT __Vectors
- EXPORT __Vectors_End
- EXPORT __Vectors_Size
-
-__Vectors DCD __initial_sp ; Top of Stack
- DCD Reset_Handler ; Reset Handler
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
-
- ; External Interrupts
- DCD WWDG_IRQHandler ; Window Watchdog
- DCD PVD_VDDIO2_IRQHandler ; PVD and VDDIO2 through EXTI Line detect
- DCD RTC_IRQHandler ; RTC through EXTI Line
- DCD FLASH_IRQHandler ; FLASH
- DCD RCC_CRS_IRQHandler ; RCC and CRS
- DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1
- DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3
- DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15
- DCD TSC_IRQHandler ; TS
- DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
- DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3
- DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4, Channel 5
- DCD ADC1_IRQHandler ; ADC1
- DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
- DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
- DCD TIM2_IRQHandler ; TIM2
- DCD TIM3_IRQHandler ; TIM3
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD TIM14_IRQHandler ; TIM14
- DCD 0 ; Reserved
- DCD TIM16_IRQHandler ; TIM16
- DCD TIM17_IRQHandler ; TIM17
- DCD I2C1_IRQHandler ; I2C1
- DCD 0 ; Reserved
- DCD SPI1_IRQHandler ; SPI1
- DCD SPI2_IRQHandler ; SPI2
- DCD USART1_IRQHandler ; USART1
- DCD USART2_IRQHandler ; USART2
- DCD 0 ; Reserved
- DCD CEC_CAN_IRQHandler ; CEC and CAN
- DCD USB_IRQHandler ; USB
-
-__Vectors_End
-
-__Vectors_Size EQU __Vectors_End - __Vectors
-
- AREA |.text|, CODE, READONLY
-
-; Reset handler routine
-Reset_Handler PROC
- EXPORT Reset_Handler [WEAK]
- IMPORT __main
- IMPORT SystemInit
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__main
- BX R0
- ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler PROC
- EXPORT NMI_Handler [WEAK]
- B .
- ENDP
-HardFault_Handler\
- PROC
- EXPORT HardFault_Handler [WEAK]
- B .
- ENDP
-SVC_Handler PROC
- EXPORT SVC_Handler [WEAK]
- B .
- ENDP
-PendSV_Handler PROC
- EXPORT PendSV_Handler [WEAK]
- B .
- ENDP
-SysTick_Handler PROC
- EXPORT SysTick_Handler [WEAK]
- B .
- ENDP
-
-Default_Handler PROC
-
- EXPORT WWDG_IRQHandler [WEAK]
- EXPORT PVD_VDDIO2_IRQHandler [WEAK]
- EXPORT RTC_IRQHandler [WEAK]
- EXPORT FLASH_IRQHandler [WEAK]
- EXPORT RCC_CRS_IRQHandler [WEAK]
- EXPORT EXTI0_1_IRQHandler [WEAK]
- EXPORT EXTI2_3_IRQHandler [WEAK]
- EXPORT EXTI4_15_IRQHandler [WEAK]
- EXPORT TSC_IRQHandler [WEAK]
- EXPORT DMA1_Channel1_IRQHandler [WEAK]
- EXPORT DMA1_Channel2_3_IRQHandler [WEAK]
- EXPORT DMA1_Channel4_5_IRQHandler [WEAK]
- EXPORT ADC1_IRQHandler [WEAK]
- EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK]
- EXPORT TIM1_CC_IRQHandler [WEAK]
- EXPORT TIM2_IRQHandler [WEAK]
- EXPORT TIM3_IRQHandler [WEAK]
- EXPORT TIM14_IRQHandler [WEAK]
- EXPORT TIM16_IRQHandler [WEAK]
- EXPORT TIM17_IRQHandler [WEAK]
- EXPORT I2C1_IRQHandler [WEAK]
- EXPORT SPI1_IRQHandler [WEAK]
- EXPORT SPI2_IRQHandler [WEAK]
- EXPORT USART1_IRQHandler [WEAK]
- EXPORT USART2_IRQHandler [WEAK]
- EXPORT CEC_CAN_IRQHandler [WEAK]
- EXPORT USB_IRQHandler [WEAK]
-
-
-WWDG_IRQHandler
-PVD_VDDIO2_IRQHandler
-RTC_IRQHandler
-FLASH_IRQHandler
-RCC_CRS_IRQHandler
-EXTI0_1_IRQHandler
-EXTI2_3_IRQHandler
-EXTI4_15_IRQHandler
-TSC_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_3_IRQHandler
-DMA1_Channel4_5_IRQHandler
-ADC1_IRQHandler
-TIM1_BRK_UP_TRG_COM_IRQHandler
-TIM1_CC_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-TIM14_IRQHandler
-TIM16_IRQHandler
-TIM17_IRQHandler
-I2C1_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-CEC_CAN_IRQHandler
-USB_IRQHandler
-
- B .
-
- ENDP
-
- ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
- IF :DEF:__MICROLIB
-
- EXPORT __initial_sp
- EXPORT __heap_base
- EXPORT __heap_limit
-
- ELSE
-
- IMPORT __use_two_region_memory
- EXPORT __user_initial_stackheap
-
-__user_initial_stackheap
-
- LDR R0, = Heap_Mem
- LDR R1, =(Stack_Mem + Stack_Size)
- LDR R2, = (Heap_Mem + Heap_Size)
- LDR R3, = Stack_Mem
- BX LR
-
- ALIGN
-
- ENDIF
-
- END
-
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/arm/startup_stm32f051.s b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/arm/startup_stm32f051.s
deleted file mode 100644
index 1e194f5d211448ae6c61b72c73ad0f9677380c24..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/arm/startup_stm32f051.s
+++ /dev/null
@@ -1,257 +0,0 @@
-;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
-;* File Name : startup_stm32f051.s
-;* Author : MCD Application Team
-;* Version : V1.3.1
-;* Date : 17-January-2014
-;* Description : STM32F051 devices vector table for MDK-ARM toolchain.
-;* This module performs:
-;* - Set the initial SP
-;* - Set the initial PC == Reset_Handler
-;* - Set the vector table entries with the exceptions ISR address
-;* - Configure the system clock
-;* - Branches to __main in the C library (which eventually
-;* calls main()).
-;* After Reset the CortexM0 processor is in Thread mode,
-;* priority is Privileged, and the Stack is set to Main.
-;* <<< Use Configuration Wizard in Context Menu >>>
-;*******************************************************************************
-; @attention
-;
-; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-; You may not use this file except in compliance with the License.
-; You may obtain a copy of the License at:
-;
-; http://www.st.com/software_license_agreement_liberty_v2
-;
-; Unless required by applicable law or agreed to in writing, software
-; distributed under the License is distributed on an "AS IS" BASIS,
-; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-; See the License for the specific language governing permissions and
-; limitations under the License.
-;
-;*******************************************************************************
-;
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size EQU 0x00000400
-
- AREA STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem SPACE Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size EQU 0x00000200
-
- AREA HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem SPACE Heap_Size
-__heap_limit
-
- PRESERVE8
- THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
- AREA RESET, DATA, READONLY
- EXPORT __Vectors
- EXPORT __Vectors_End
- EXPORT __Vectors_Size
-
-__Vectors DCD __initial_sp ; Top of Stack
- DCD Reset_Handler ; Reset Handler
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
-
- ; External Interrupts
- DCD WWDG_IRQHandler ; Window Watchdog
- DCD PVD_IRQHandler ; PVD through EXTI Line detect
- DCD RTC_IRQHandler ; RTC through EXTI Line
- DCD FLASH_IRQHandler ; FLASH
- DCD RCC_IRQHandler ; RCC
- DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1
- DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3
- DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15
- DCD TS_IRQHandler ; TS
- DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
- DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3
- DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5
- DCD ADC1_COMP_IRQHandler ; ADC1, COMP1 and COMP2
- DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
- DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
- DCD TIM2_IRQHandler ; TIM2
- DCD TIM3_IRQHandler ; TIM3
- DCD TIM6_DAC_IRQHandler ; TIM6 and DAC
- DCD 0 ; Reserved
- DCD TIM14_IRQHandler ; TIM14
- DCD TIM15_IRQHandler ; TIM15
- DCD TIM16_IRQHandler ; TIM16
- DCD TIM17_IRQHandler ; TIM17
- DCD I2C1_IRQHandler ; I2C1
- DCD I2C2_IRQHandler ; I2C2
- DCD SPI1_IRQHandler ; SPI1
- DCD SPI2_IRQHandler ; SPI2
- DCD USART1_IRQHandler ; USART1
- DCD USART2_IRQHandler ; USART2
- DCD 0 ; Reserved
- DCD CEC_IRQHandler ; CEC
- DCD 0 ; Reserved
-
-__Vectors_End
-
-__Vectors_Size EQU __Vectors_End - __Vectors
-
- AREA |.text|, CODE, READONLY
-
-; Reset handler routine
-Reset_Handler PROC
- EXPORT Reset_Handler [WEAK]
- IMPORT __main
- IMPORT SystemInit
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__main
- BX R0
- ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler PROC
- EXPORT NMI_Handler [WEAK]
- B .
- ENDP
-HardFault_Handler\
- PROC
- EXPORT HardFault_Handler [WEAK]
- B .
- ENDP
-SVC_Handler PROC
- EXPORT SVC_Handler [WEAK]
- B .
- ENDP
-PendSV_Handler PROC
- EXPORT PendSV_Handler [WEAK]
- B .
- ENDP
-SysTick_Handler PROC
- EXPORT SysTick_Handler [WEAK]
- B .
- ENDP
-
-Default_Handler PROC
-
- EXPORT WWDG_IRQHandler [WEAK]
- EXPORT PVD_IRQHandler [WEAK]
- EXPORT RTC_IRQHandler [WEAK]
- EXPORT FLASH_IRQHandler [WEAK]
- EXPORT RCC_IRQHandler [WEAK]
- EXPORT EXTI0_1_IRQHandler [WEAK]
- EXPORT EXTI2_3_IRQHandler [WEAK]
- EXPORT EXTI4_15_IRQHandler [WEAK]
- EXPORT TS_IRQHandler [WEAK]
- EXPORT DMA1_Channel1_IRQHandler [WEAK]
- EXPORT DMA1_Channel2_3_IRQHandler [WEAK]
- EXPORT DMA1_Channel4_5_IRQHandler [WEAK]
- EXPORT ADC1_COMP_IRQHandler [WEAK]
- EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK]
- EXPORT TIM1_CC_IRQHandler [WEAK]
- EXPORT TIM2_IRQHandler [WEAK]
- EXPORT TIM3_IRQHandler [WEAK]
- EXPORT TIM6_DAC_IRQHandler [WEAK]
- EXPORT TIM14_IRQHandler [WEAK]
- EXPORT TIM15_IRQHandler [WEAK]
- EXPORT TIM16_IRQHandler [WEAK]
- EXPORT TIM17_IRQHandler [WEAK]
- EXPORT I2C1_IRQHandler [WEAK]
- EXPORT I2C2_IRQHandler [WEAK]
- EXPORT SPI1_IRQHandler [WEAK]
- EXPORT SPI2_IRQHandler [WEAK]
- EXPORT USART1_IRQHandler [WEAK]
- EXPORT USART2_IRQHandler [WEAK]
- EXPORT CEC_IRQHandler [WEAK]
-
-
-WWDG_IRQHandler
-PVD_IRQHandler
-RTC_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_1_IRQHandler
-EXTI2_3_IRQHandler
-EXTI4_15_IRQHandler
-TS_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_3_IRQHandler
-DMA1_Channel4_5_IRQHandler
-ADC1_COMP_IRQHandler
-TIM1_BRK_UP_TRG_COM_IRQHandler
-TIM1_CC_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-TIM6_DAC_IRQHandler
-TIM14_IRQHandler
-TIM15_IRQHandler
-TIM16_IRQHandler
-TIM17_IRQHandler
-I2C1_IRQHandler
-I2C2_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-CEC_IRQHandler
-
- B .
-
- ENDP
-
- ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
- IF :DEF:__MICROLIB
-
- EXPORT __initial_sp
- EXPORT __heap_base
- EXPORT __heap_limit
-
- ELSE
-
- IMPORT __use_two_region_memory
- EXPORT __user_initial_stackheap
-
-__user_initial_stackheap
-
- LDR R0, = Heap_Mem
- LDR R1, =(Stack_Mem + Stack_Size)
- LDR R2, = (Heap_Mem + Heap_Size)
- LDR R3, = Stack_Mem
- BX LR
-
- ALIGN
-
- ENDIF
-
- END
-
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/arm/startup_stm32f072.s b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/arm/startup_stm32f072.s
deleted file mode 100644
index f1a85a3b83ccacf9b5aefd409e7f5f76af0bdac5..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/arm/startup_stm32f072.s
+++ /dev/null
@@ -1,264 +0,0 @@
-;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
-;* File Name : startup_stm32f072.s
-;* Author : MCD Application Team
-;* Version : V1.3.1
-;* Date : 17-January-2014
-;* Description : STM32F072 Devices vector table for
-;* for MDK-ARM toolchain.
-;* This module performs:
-;* - Set the initial SP
-;* - Set the initial PC == Reset_Handler
-;* - Set the vector table entries with the exceptions ISR address
-;* - Configure the system clock
-;* - Branches to __main in the C library (which eventually
-;* calls main()).
-;* After Reset the CortexM0 processor is in Thread mode,
-;* priority is Privileged, and the Stack is set to Main.
-;* <<< Use Configuration Wizard in Context Menu >>>
-;*******************************************************************************
-; @attention
-;
-; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-; You may not use this file except in compliance with the License.
-; You may obtain a copy of the License at:
-;
-; http://www.st.com/software_license_agreement_liberty_v2
-;
-; Unless required by applicable law or agreed to in writing, software
-; distributed under the License is distributed on an "AS IS" BASIS,
-; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-; See the License for the specific language governing permissions and
-; limitations under the License.
-;
-;*******************************************************************************
-;
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size EQU 0x00000400
-
- AREA STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem SPACE Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size EQU 0x00000200
-
- AREA HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem SPACE Heap_Size
-__heap_limit
-
- PRESERVE8
- THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
- AREA RESET, DATA, READONLY
- EXPORT __Vectors
- EXPORT __Vectors_End
- EXPORT __Vectors_Size
-
-__Vectors DCD __initial_sp ; Top of Stack
- DCD Reset_Handler ; Reset Handler
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
-
- ; External Interrupts
- DCD WWDG_IRQHandler ; Window Watchdog
- DCD PVD_VDDIO2_IRQHandler ; PVD and VDDIO2 through EXTI Line detect
- DCD RTC_IRQHandler ; RTC through EXTI Line
- DCD FLASH_IRQHandler ; FLASH
- DCD RCC_CRS_IRQHandler ; RCC and CRS
- DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1
- DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3
- DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15
- DCD TSC_IRQHandler ; TS
- DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
- DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3
- DCD DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channel 4, Channel 5, Channel 6 and Channel 7
- DCD ADC1_COMP_IRQHandler ; ADC1, COMP1 and COMP2
- DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
- DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
- DCD TIM2_IRQHandler ; TIM2
- DCD TIM3_IRQHandler ; TIM3
- DCD TIM6_DAC_IRQHandler ; TIM6 and DAC
- DCD TIM7_IRQHandler ; TIM7
- DCD TIM14_IRQHandler ; TIM14
- DCD TIM15_IRQHandler ; TIM15
- DCD TIM16_IRQHandler ; TIM16
- DCD TIM17_IRQHandler ; TIM17
- DCD I2C1_IRQHandler ; I2C1
- DCD I2C2_IRQHandler ; I2C2
- DCD SPI1_IRQHandler ; SPI1
- DCD SPI2_IRQHandler ; SPI2
- DCD USART1_IRQHandler ; USART1
- DCD USART2_IRQHandler ; USART2
- DCD USART3_4_IRQHandler ; USART3 and USART4
- DCD CEC_CAN_IRQHandler ; CEC and CAN
- DCD USB_IRQHandler ; USB
-
-__Vectors_End
-
-__Vectors_Size EQU __Vectors_End - __Vectors
-
- AREA |.text|, CODE, READONLY
-
-; Reset handler routine
-Reset_Handler PROC
- EXPORT Reset_Handler [WEAK]
- IMPORT __main
- IMPORT SystemInit
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__main
- BX R0
- ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler PROC
- EXPORT NMI_Handler [WEAK]
- B .
- ENDP
-HardFault_Handler\
- PROC
- EXPORT HardFault_Handler [WEAK]
- B .
- ENDP
-SVC_Handler PROC
- EXPORT SVC_Handler [WEAK]
- B .
- ENDP
-PendSV_Handler PROC
- EXPORT PendSV_Handler [WEAK]
- B .
- ENDP
-SysTick_Handler PROC
- EXPORT SysTick_Handler [WEAK]
- B .
- ENDP
-
-Default_Handler PROC
-
- EXPORT WWDG_IRQHandler [WEAK]
- EXPORT PVD_VDDIO2_IRQHandler [WEAK]
- EXPORT RTC_IRQHandler [WEAK]
- EXPORT FLASH_IRQHandler [WEAK]
- EXPORT RCC_CRS_IRQHandler [WEAK]
- EXPORT EXTI0_1_IRQHandler [WEAK]
- EXPORT EXTI2_3_IRQHandler [WEAK]
- EXPORT EXTI4_15_IRQHandler [WEAK]
- EXPORT TSC_IRQHandler [WEAK]
- EXPORT DMA1_Channel1_IRQHandler [WEAK]
- EXPORT DMA1_Channel2_3_IRQHandler [WEAK]
- EXPORT DMA1_Channel4_5_6_7_IRQHandler [WEAK]
- EXPORT ADC1_COMP_IRQHandler [WEAK]
- EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK]
- EXPORT TIM1_CC_IRQHandler [WEAK]
- EXPORT TIM2_IRQHandler [WEAK]
- EXPORT TIM3_IRQHandler [WEAK]
- EXPORT TIM6_DAC_IRQHandler [WEAK]
- EXPORT TIM7_IRQHandler [WEAK]
- EXPORT TIM14_IRQHandler [WEAK]
- EXPORT TIM15_IRQHandler [WEAK]
- EXPORT TIM16_IRQHandler [WEAK]
- EXPORT TIM17_IRQHandler [WEAK]
- EXPORT I2C1_IRQHandler [WEAK]
- EXPORT I2C2_IRQHandler [WEAK]
- EXPORT SPI1_IRQHandler [WEAK]
- EXPORT SPI2_IRQHandler [WEAK]
- EXPORT USART1_IRQHandler [WEAK]
- EXPORT USART2_IRQHandler [WEAK]
- EXPORT USART3_4_IRQHandler [WEAK]
- EXPORT CEC_CAN_IRQHandler [WEAK]
- EXPORT USB_IRQHandler [WEAK]
-
-
-WWDG_IRQHandler
-PVD_VDDIO2_IRQHandler
-RTC_IRQHandler
-FLASH_IRQHandler
-RCC_CRS_IRQHandler
-EXTI0_1_IRQHandler
-EXTI2_3_IRQHandler
-EXTI4_15_IRQHandler
-TSC_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_3_IRQHandler
-DMA1_Channel4_5_6_7_IRQHandler
-ADC1_COMP_IRQHandler
-TIM1_BRK_UP_TRG_COM_IRQHandler
-TIM1_CC_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-TIM6_DAC_IRQHandler
-TIM7_IRQHandler
-TIM14_IRQHandler
-TIM15_IRQHandler
-TIM16_IRQHandler
-TIM17_IRQHandler
-I2C1_IRQHandler
-I2C2_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-USART3_4_IRQHandler
-CEC_CAN_IRQHandler
-USB_IRQHandler
-
- B .
-
- ENDP
-
- ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
- IF :DEF:__MICROLIB
-
- EXPORT __initial_sp
- EXPORT __heap_base
- EXPORT __heap_limit
-
- ELSE
-
- IMPORT __use_two_region_memory
- EXPORT __user_initial_stackheap
-
-__user_initial_stackheap
-
- LDR R0, = Heap_Mem
- LDR R1, =(Stack_Mem + Stack_Size)
- LDR R2, = (Heap_Mem + Heap_Size)
- LDR R3, = Stack_Mem
- BX LR
-
- ALIGN
-
- ENDIF
-
- END
-
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/arm/startup_stm32f0xx.s b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/arm/startup_stm32f0xx.s
deleted file mode 100644
index 7e2bb2b11359decdc0a7cfcb41d23b4487ef11af..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/arm/startup_stm32f0xx.s
+++ /dev/null
@@ -1,257 +0,0 @@
-;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
-;* File Name : startup_stm32f0xx.s
-;* Author : MCD Application Team
-;* Version : V1.3.1
-;* Date : 17-January-2014
-;* Description : STM32F051 devices vector table for MDK-ARM toolchain.
-;* This module performs:
-;* - Set the initial SP
-;* - Set the initial PC == Reset_Handler
-;* - Set the vector table entries with the exceptions ISR address
-;* - Configure the system clock
-;* - Branches to __main in the C library (which eventually
-;* calls main()).
-;* After Reset the CortexM0 processor is in Thread mode,
-;* priority is Privileged, and the Stack is set to Main.
-;* <<< Use Configuration Wizard in Context Menu >>>
-;*******************************************************************************
-; @attention
-;
-; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-; You may not use this file except in compliance with the License.
-; You may obtain a copy of the License at:
-;
-; http://www.st.com/software_license_agreement_liberty_v2
-;
-; Unless required by applicable law or agreed to in writing, software
-; distributed under the License is distributed on an "AS IS" BASIS,
-; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-; See the License for the specific language governing permissions and
-; limitations under the License.
-;
-;*******************************************************************************
-;
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size EQU 0x00000400
-
- AREA STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem SPACE Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size EQU 0x00000200
-
- AREA HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem SPACE Heap_Size
-__heap_limit
-
- PRESERVE8
- THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
- AREA RESET, DATA, READONLY
- EXPORT __Vectors
- EXPORT __Vectors_End
- EXPORT __Vectors_Size
-
-__Vectors DCD __initial_sp ; Top of Stack
- DCD Reset_Handler ; Reset Handler
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
-
- ; External Interrupts
- DCD WWDG_IRQHandler ; Window Watchdog
- DCD PVD_IRQHandler ; PVD through EXTI Line detect
- DCD RTC_IRQHandler ; RTC through EXTI Line
- DCD FLASH_IRQHandler ; FLASH
- DCD RCC_IRQHandler ; RCC
- DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1
- DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3
- DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15
- DCD TS_IRQHandler ; TS
- DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
- DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3
- DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5
- DCD ADC1_COMP_IRQHandler ; ADC1, COMP1 and COMP2
- DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
- DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
- DCD TIM2_IRQHandler ; TIM2
- DCD TIM3_IRQHandler ; TIM3
- DCD TIM6_DAC_IRQHandler ; TIM6 and DAC
- DCD 0 ; Reserved
- DCD TIM14_IRQHandler ; TIM14
- DCD TIM15_IRQHandler ; TIM15
- DCD TIM16_IRQHandler ; TIM16
- DCD TIM17_IRQHandler ; TIM17
- DCD I2C1_IRQHandler ; I2C1
- DCD I2C2_IRQHandler ; I2C2
- DCD SPI1_IRQHandler ; SPI1
- DCD SPI2_IRQHandler ; SPI2
- DCD USART1_IRQHandler ; USART1
- DCD USART2_IRQHandler ; USART2
- DCD 0 ; Reserved
- DCD CEC_IRQHandler ; CEC
- DCD 0 ; Reserved
-
-__Vectors_End
-
-__Vectors_Size EQU __Vectors_End - __Vectors
-
- AREA |.text|, CODE, READONLY
-
-; Reset handler routine
-Reset_Handler PROC
- EXPORT Reset_Handler [WEAK]
- IMPORT __main
- IMPORT SystemInit
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__main
- BX R0
- ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler PROC
- EXPORT NMI_Handler [WEAK]
- B .
- ENDP
-HardFault_Handler\
- PROC
- EXPORT HardFault_Handler [WEAK]
- B .
- ENDP
-SVC_Handler PROC
- EXPORT SVC_Handler [WEAK]
- B .
- ENDP
-PendSV_Handler PROC
- EXPORT PendSV_Handler [WEAK]
- B .
- ENDP
-SysTick_Handler PROC
- EXPORT SysTick_Handler [WEAK]
- B .
- ENDP
-
-Default_Handler PROC
-
- EXPORT WWDG_IRQHandler [WEAK]
- EXPORT PVD_IRQHandler [WEAK]
- EXPORT RTC_IRQHandler [WEAK]
- EXPORT FLASH_IRQHandler [WEAK]
- EXPORT RCC_IRQHandler [WEAK]
- EXPORT EXTI0_1_IRQHandler [WEAK]
- EXPORT EXTI2_3_IRQHandler [WEAK]
- EXPORT EXTI4_15_IRQHandler [WEAK]
- EXPORT TS_IRQHandler [WEAK]
- EXPORT DMA1_Channel1_IRQHandler [WEAK]
- EXPORT DMA1_Channel2_3_IRQHandler [WEAK]
- EXPORT DMA1_Channel4_5_IRQHandler [WEAK]
- EXPORT ADC1_COMP_IRQHandler [WEAK]
- EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK]
- EXPORT TIM1_CC_IRQHandler [WEAK]
- EXPORT TIM2_IRQHandler [WEAK]
- EXPORT TIM3_IRQHandler [WEAK]
- EXPORT TIM6_DAC_IRQHandler [WEAK]
- EXPORT TIM14_IRQHandler [WEAK]
- EXPORT TIM15_IRQHandler [WEAK]
- EXPORT TIM16_IRQHandler [WEAK]
- EXPORT TIM17_IRQHandler [WEAK]
- EXPORT I2C1_IRQHandler [WEAK]
- EXPORT I2C2_IRQHandler [WEAK]
- EXPORT SPI1_IRQHandler [WEAK]
- EXPORT SPI2_IRQHandler [WEAK]
- EXPORT USART1_IRQHandler [WEAK]
- EXPORT USART2_IRQHandler [WEAK]
- EXPORT CEC_IRQHandler [WEAK]
-
-
-WWDG_IRQHandler
-PVD_IRQHandler
-RTC_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_1_IRQHandler
-EXTI2_3_IRQHandler
-EXTI4_15_IRQHandler
-TS_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_3_IRQHandler
-DMA1_Channel4_5_IRQHandler
-ADC1_COMP_IRQHandler
-TIM1_BRK_UP_TRG_COM_IRQHandler
-TIM1_CC_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-TIM6_DAC_IRQHandler
-TIM14_IRQHandler
-TIM15_IRQHandler
-TIM16_IRQHandler
-TIM17_IRQHandler
-I2C1_IRQHandler
-I2C2_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-CEC_IRQHandler
-
- B .
-
- ENDP
-
- ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
- IF :DEF:__MICROLIB
-
- EXPORT __initial_sp
- EXPORT __heap_base
- EXPORT __heap_limit
-
- ELSE
-
- IMPORT __use_two_region_memory
- EXPORT __user_initial_stackheap
-
-__user_initial_stackheap
-
- LDR R0, = Heap_Mem
- LDR R1, =(Stack_Mem + Stack_Size)
- LDR R2, = (Heap_Mem + Heap_Size)
- LDR R3, = Stack_Mem
- BX LR
-
- ALIGN
-
- ENDIF
-
- END
-
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/arm/startup_stm32f0xx_ld.s b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/arm/startup_stm32f0xx_ld.s
deleted file mode 100644
index 22a98073a3ae753ccb01754d4284d8c451e14327..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/arm/startup_stm32f0xx_ld.s
+++ /dev/null
@@ -1,239 +0,0 @@
-;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
-;* File Name : startup_stm32f0xx_ld.s
-;* Author : MCD Application Team
-;* Version : V1.3.1
-;* Date : 17-January-2014
-;* Description : STM32F0031 devices vector table for MDK-ARM toolchain.
-;* This module performs:
-;* - Set the initial SP
-;* - Set the initial PC == Reset_Handler
-;* - Set the vector table entries with the exceptions ISR address
-;* - Configure the system clock
-;* - Branches to __main in the C library (which eventually
-;* calls main()).
-;* After Reset the CortexM0 processor is in Thread mode,
-;* priority is Privileged, and the Stack is set to Main.
-;* <<< Use Configuration Wizard in Context Menu >>>
-;*******************************************************************************
-; @attention
-;
-; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-; You may not use this file except in compliance with the License.
-; You may obtain a copy of the License at:
-;
-; http://www.st.com/software_license_agreement_liberty_v2
-;
-; Unless required by applicable law or agreed to in writing, software
-; distributed under the License is distributed on an "AS IS" BASIS,
-; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-; See the License for the specific language governing permissions and
-; limitations under the License.
-;
-;*******************************************************************************
-;
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size EQU 0x00000400
-
- AREA STACK, NOINIT, READWRITE, ALIGN=3
-Stack_Mem SPACE Stack_Size
-__initial_sp
-
-
-; <h> Heap Configuration
-; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size EQU 0x00000200
-
- AREA HEAP, NOINIT, READWRITE, ALIGN=3
-__heap_base
-Heap_Mem SPACE Heap_Size
-__heap_limit
-
- PRESERVE8
- THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
- AREA RESET, DATA, READONLY
- EXPORT __Vectors
- EXPORT __Vectors_End
- EXPORT __Vectors_Size
-
-__Vectors DCD __initial_sp ; Top of Stack
- DCD Reset_Handler ; Reset Handler
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
-
- ; External Interrupts
- DCD WWDG_IRQHandler ; Window Watchdog
- DCD PVD_IRQHandler ; PVD through EXTI Line detect
- DCD RTC_IRQHandler ; RTC through EXTI Line
- DCD FLASH_IRQHandler ; FLASH
- DCD RCC_IRQHandler ; RCC
- DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1
- DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3
- DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15
- DCD 0 ; Reserved
- DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
- DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3
- DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5
- DCD ADC1_IRQHandler ; ADC1
- DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
- DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
- DCD TIM2_IRQHandler ; TIM2
- DCD TIM3_IRQHandler ; TIM3
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD TIM14_IRQHandler ; TIM14
- DCD 0 ; Reserved
- DCD TIM16_IRQHandler ; TIM16
- DCD TIM17_IRQHandler ; TIM17
- DCD I2C1_IRQHandler ; I2C1
- DCD 0 ; Reserved
- DCD SPI1_IRQHandler ; SPI1
- DCD 0 ; Reserved
- DCD USART1_IRQHandler ; USART1
-
-__Vectors_End
-
-__Vectors_Size EQU __Vectors_End - __Vectors
-
- AREA |.text|, CODE, READONLY
-
-; Reset handler routine
-Reset_Handler PROC
- EXPORT Reset_Handler [WEAK]
- IMPORT __main
- IMPORT SystemInit
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__main
- BX R0
- ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler PROC
- EXPORT NMI_Handler [WEAK]
- B .
- ENDP
-HardFault_Handler\
- PROC
- EXPORT HardFault_Handler [WEAK]
- B .
- ENDP
-SVC_Handler PROC
- EXPORT SVC_Handler [WEAK]
- B .
- ENDP
-PendSV_Handler PROC
- EXPORT PendSV_Handler [WEAK]
- B .
- ENDP
-SysTick_Handler PROC
- EXPORT SysTick_Handler [WEAK]
- B .
- ENDP
-
-Default_Handler PROC
-
- EXPORT WWDG_IRQHandler [WEAK]
- EXPORT PVD_IRQHandler [WEAK]
- EXPORT RTC_IRQHandler [WEAK]
- EXPORT FLASH_IRQHandler [WEAK]
- EXPORT RCC_IRQHandler [WEAK]
- EXPORT EXTI0_1_IRQHandler [WEAK]
- EXPORT EXTI2_3_IRQHandler [WEAK]
- EXPORT EXTI4_15_IRQHandler [WEAK]
- EXPORT DMA1_Channel1_IRQHandler [WEAK]
- EXPORT DMA1_Channel2_3_IRQHandler [WEAK]
- EXPORT DMA1_Channel4_5_IRQHandler [WEAK]
- EXPORT ADC1_IRQHandler [WEAK]
- EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK]
- EXPORT TIM1_CC_IRQHandler [WEAK]
- EXPORT TIM2_IRQHandler [WEAK]
- EXPORT TIM3_IRQHandler [WEAK]
- EXPORT TIM14_IRQHandler [WEAK]
- EXPORT TIM16_IRQHandler [WEAK]
- EXPORT TIM17_IRQHandler [WEAK]
- EXPORT I2C1_IRQHandler [WEAK]
- EXPORT SPI1_IRQHandler [WEAK]
- EXPORT USART1_IRQHandler [WEAK]
-
-
-WWDG_IRQHandler
-PVD_IRQHandler
-RTC_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_1_IRQHandler
-EXTI2_3_IRQHandler
-EXTI4_15_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_3_IRQHandler
-DMA1_Channel4_5_IRQHandler
-ADC1_IRQHandler
-TIM1_BRK_UP_TRG_COM_IRQHandler
-TIM1_CC_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-TIM14_IRQHandler
-TIM16_IRQHandler
-TIM17_IRQHandler
-I2C1_IRQHandler
-SPI1_IRQHandler
-USART1_IRQHandler
-
- B .
-
- ENDP
-
- ALIGN
-
-;*******************************************************************************
-; User Stack and Heap initialization
-;*******************************************************************************
- IF :DEF:__MICROLIB
-
- EXPORT __initial_sp
- EXPORT __heap_base
- EXPORT __heap_limit
-
- ELSE
-
- IMPORT __use_two_region_memory
- EXPORT __user_initial_stackheap
-
-__user_initial_stackheap
-
- LDR R0, = Heap_Mem
- LDR R1, =(Stack_Mem + Stack_Size)
- LDR R2, = (Heap_Mem + Heap_Size)
- LDR R3, = Stack_Mem
- BX LR
-
- ALIGN
-
- ENDIF
-
- END
-
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc_ride7/startup_stm32f030.s b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc_ride7/startup_stm32f030.s
deleted file mode 100644
index f15783405d54c60d94826827f8660f43cf142684..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc_ride7/startup_stm32f030.s
+++ /dev/null
@@ -1,294 +0,0 @@
-/**
- ******************************************************************************
- * @file startup_stm32f0xx.s
- * @author MCD Application Team
- * @version V1.3.1
- * @date 17-January-2014
- * @brief STM32F030 Devices vector table for RIDE7 toolchain.
- * This module performs:
- * - Set the initial SP
- * - Set the initial PC == Reset_Handler,
- * - Set the vector table entries with the exceptions ISR address
- * - Configure the system clock
- * - Branches to main in the C library (which eventually
- * calls main()).
- * After Reset the Cortex-M0 processor is in Thread mode,
- * priority is Privileged, and the Stack is set to Main.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
- .syntax unified
- .cpu cortex-m0
- .fpu softvfp
- .thumb
-
-.global g_pfnVectors
-.global Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word _sidata
-/* start address for the .data section. defined in linker script */
-.word _sdata
-/* end address for the .data section. defined in linker script */
-.word _edata
-/* start address for the .bss section. defined in linker script */
-.word _sbss
-/* end address for the .bss section. defined in linker script */
-.word _ebss
-
-.equ BootRAM, 0xF108F85F
-/**
- * @brief This is the code that gets called when the processor first
- * starts execution following a reset event. Only the absolutely
- * necessary set is performed, after which the application
- * supplied main() routine is called.
- * @param None
- * @retval : None
-*/
-
- .section .text.Reset_Handler
- .weak Reset_Handler
- .type Reset_Handler, %function
-Reset_Handler:
- ldr r0, =_estack
- mov sp, r0 /* set stack pointer */
-
-/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
- b LoopCopyDataInit
-
-CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
-
-LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
- bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
-/* Zero fill the bss segment. */
-FillZerobss:
- movs r3, #0
- str r3, [r2]
- adds r2, r2, #4
-
-
-LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
- bcc FillZerobss
-
-/* Call the clock system intitialization function.*/
- bl SystemInit
-
-/* Call the application's entry point.*/
- bl main
-
-LoopForever:
- b LoopForever
-
-
-.size Reset_Handler, .-Reset_Handler
-
-/**
- * @brief This is the code that gets called when the processor receives an
- * unexpected interrupt. This simply enters an infinite loop, preserving
- * the system state for examination by a debugger.
- *
- * @param None
- * @retval : None
-*/
- .section .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
- b Infinite_Loop
- .size Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M0. Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
- .section .isr_vector,"a",%progbits
- .type g_pfnVectors, %object
- .size g_pfnVectors, .-g_pfnVectors
-
-
-g_pfnVectors:
- .word _estack
- .word Reset_Handler
-
- .word NMI_Handler
- .word HardFault_Handler
- .word 0
- .word 0
- .word 0
- .word 0
- .word 0
- .word 0
- .word 0
- .word SVC_Handler
- .word 0
- .word 0
- .word PendSV_Handler
- .word SysTick_Handler
-
-
- .word WWDG_IRQHandler
- .word 0
- .word RTC_IRQHandler
- .word FLASH_IRQHandler
- .word RCC_IRQHandler
- .word EXTI0_1_IRQHandler
- .word EXTI2_3_IRQHandler
- .word EXTI4_15_IRQHandler
- .word 0
- .word DMA1_Channel1_IRQHandler
- .word DMA1_Channel2_3_IRQHandler
- .word DMA1_Channel4_5_IRQHandler
- .word ADC1_IRQHandler
- .word TIM1_BRK_UP_TRG_COM_IRQHandler
- .word TIM1_CC_IRQHandler
- .word 0
- .word TIM3_IRQHandler
- .word 0
- .word 0
- .word TIM14_IRQHandler
- .word TIM15_IRQHandler
- .word TIM16_IRQHandler
- .word TIM17_IRQHandler
- .word I2C1_IRQHandler
- .word I2C2_IRQHandler
- .word SPI1_IRQHandler
- .word SPI2_IRQHandler
- .word USART1_IRQHandler
- .word USART2_IRQHandler
- .word 0
- .word 0
- .word 0
- .word BootRAM /* @0x108. This is for boot in RAM mode for
- STM32F0xx devices. */
-
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
-
- .weak NMI_Handler
- .thumb_set NMI_Handler,Default_Handler
-
- .weak HardFault_Handler
- .thumb_set HardFault_Handler,Default_Handler
-
- .weak SVC_Handler
- .thumb_set SVC_Handler,Default_Handler
-
- .weak PendSV_Handler
- .thumb_set PendSV_Handler,Default_Handler
-
- .weak SysTick_Handler
- .thumb_set SysTick_Handler,Default_Handler
-
- .weak WWDG_IRQHandler
- .thumb_set WWDG_IRQHandler,Default_Handler
-
- .weak RTC_IRQHandler
- .thumb_set RTC_IRQHandler,Default_Handler
-
- .weak FLASH_IRQHandler
- .thumb_set FLASH_IRQHandler,Default_Handler
-
- .weak RCC_IRQHandler
- .thumb_set RCC_IRQHandler,Default_Handler
-
- .weak EXTI0_1_IRQHandler
- .thumb_set EXTI0_1_IRQHandler,Default_Handler
-
- .weak EXTI2_3_IRQHandler
- .thumb_set EXTI2_3_IRQHandler,Default_Handler
-
- .weak EXTI4_15_IRQHandler
- .thumb_set EXTI4_15_IRQHandler,Default_Handler
-
- .weak DMA1_Channel1_IRQHandler
- .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
- .weak DMA1_Channel2_3_IRQHandler
- .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler
-
- .weak DMA1_Channel4_5_IRQHandler
- .thumb_set DMA1_Channel4_5_IRQHandler,Default_Handler
-
- .weak ADC1_IRQHandler
- .thumb_set ADC1_IRQHandler,Default_Handler
-
- .weak TIM1_BRK_UP_TRG_COM_IRQHandler
- .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler
-
- .weak TIM1_CC_IRQHandler
- .thumb_set TIM1_CC_IRQHandler,Default_Handler
-
- .weak TIM3_IRQHandler
- .thumb_set TIM3_IRQHandler,Default_Handler
-
- .weak TIM14_IRQHandler
- .thumb_set TIM14_IRQHandler,Default_Handler
-
- .weak TIM15_IRQHandler
- .thumb_set TIM15_IRQHandler,Default_Handler
-
- .weak TIM16_IRQHandler
- .thumb_set TIM16_IRQHandler,Default_Handler
-
- .weak TIM17_IRQHandler
- .thumb_set TIM17_IRQHandler,Default_Handler
-
- .weak I2C1_IRQHandler
- .thumb_set I2C1_IRQHandler,Default_Handler
-
- .weak I2C2_IRQHandler
- .thumb_set I2C2_IRQHandler,Default_Handler
-
- .weak SPI1_IRQHandler
- .thumb_set SPI1_IRQHandler,Default_Handler
-
- .weak SPI2_IRQHandler
- .thumb_set SPI2_IRQHandler,Default_Handler
-
- .weak USART1_IRQHandler
- .thumb_set USART1_IRQHandler,Default_Handler
-
- .weak USART2_IRQHandler
- .thumb_set USART2_IRQHandler,Default_Handler
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc_ride7/startup_stm32f031.s b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc_ride7/startup_stm32f031.s
deleted file mode 100644
index 7cca76391223d9b7fbc5ec7c0478ab4619999673..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc_ride7/startup_stm32f031.s
+++ /dev/null
@@ -1,287 +0,0 @@
-/**
- ******************************************************************************
- * @file startup_stm32f0xx.s
- * @author MCD Application Team
- * @version V1.3.1
- * @date 17-January-2014
- * @brief STM32F031 Devices vector table for RIDE7 toolchain.
- * This module performs:
- * - Set the initial SP
- * - Set the initial PC == Reset_Handler,
- * - Set the vector table entries with the exceptions ISR address
- * - Configure the system clock
- * - Branches to main in the C library (which eventually
- * calls main()).
- * After Reset the Cortex-M0 processor is in Thread mode,
- * priority is Privileged, and the Stack is set to Main.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
- .syntax unified
- .cpu cortex-m0
- .fpu softvfp
- .thumb
-
-.global g_pfnVectors
-.global Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word _sidata
-/* start address for the .data section. defined in linker script */
-.word _sdata
-/* end address for the .data section. defined in linker script */
-.word _edata
-/* start address for the .bss section. defined in linker script */
-.word _sbss
-/* end address for the .bss section. defined in linker script */
-.word _ebss
-
-.equ BootRAM, 0xF108F85F
-/**
- * @brief This is the code that gets called when the processor first
- * starts execution following a reset event. Only the absolutely
- * necessary set is performed, after which the application
- * supplied main() routine is called.
- * @param None
- * @retval : None
-*/
-
- .section .text.Reset_Handler
- .weak Reset_Handler
- .type Reset_Handler, %function
-Reset_Handler:
- ldr r0, =_estack
- mov sp, r0 /* set stack pointer */
-
-/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
- b LoopCopyDataInit
-
-CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
-
-LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
- bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
-/* Zero fill the bss segment. */
-FillZerobss:
- movs r3, #0
- str r3, [r2]
- adds r2, r2, #4
-
-
-LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
- bcc FillZerobss
-
-/* Call the clock system intitialization function.*/
- bl SystemInit
-
-/* Call the application's entry point.*/
- bl main
-
-LoopForever:
- b LoopForever
-
-
-.size Reset_Handler, .-Reset_Handler
-
-/**
- * @brief This is the code that gets called when the processor receives an
- * unexpected interrupt. This simply enters an infinite loop, preserving
- * the system state for examination by a debugger.
- *
- * @param None
- * @retval : None
-*/
- .section .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
- b Infinite_Loop
- .size Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M0. Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
- .section .isr_vector,"a",%progbits
- .type g_pfnVectors, %object
- .size g_pfnVectors, .-g_pfnVectors
-
-
-
-g_pfnVectors:
- .word _estack
- .word Reset_Handler
-
- .word NMI_Handler
- .word HardFault_Handler
- .word 0
- .word 0
- .word 0
- .word 0
- .word 0
- .word 0
- .word 0
- .word SVC_Handler
- .word 0
- .word 0
- .word PendSV_Handler
- .word SysTick_Handler
-
-
- .word WWDG_IRQHandler
- .word PVD_IRQHandler
- .word RTC_IRQHandler
- .word FLASH_IRQHandler
- .word RCC_IRQHandler
- .word EXTI0_1_IRQHandler
- .word EXTI2_3_IRQHandler
- .word EXTI4_15_IRQHandler
- .word 0
- .word DMA1_Channel1_IRQHandler
- .word DMA1_Channel2_3_IRQHandler
- .word DMA1_Channel4_5_IRQHandler
- .word ADC1_IRQHandler
- .word TIM1_BRK_UP_TRG_COM_IRQHandler
- .word TIM1_CC_IRQHandler
- .word TIM2_IRQHandler
- .word TIM3_IRQHandler
- .word 0
- .word 0
- .word TIM14_IRQHandler
- .word 0
- .word TIM16_IRQHandler
- .word TIM17_IRQHandler
- .word I2C1_IRQHandler
- .word 0
- .word SPI1_IRQHandler
- .word 0
- .word USART1_IRQHandler
- .word 0
- .word 0
- .word 0
- .word 0
- .word BootRAM /* @0x108. This is for boot in RAM mode for
- STM32F0xx devices. */
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
-
- .weak NMI_Handler
- .thumb_set NMI_Handler,Default_Handler
-
- .weak HardFault_Handler
- .thumb_set HardFault_Handler,Default_Handler
-
- .weak SVC_Handler
- .thumb_set SVC_Handler,Default_Handler
-
- .weak PendSV_Handler
- .thumb_set PendSV_Handler,Default_Handler
-
- .weak SysTick_Handler
- .thumb_set SysTick_Handler,Default_Handler
-
- .weak WWDG_IRQHandler
- .thumb_set WWDG_IRQHandler,Default_Handler
-
- .weak PVD_IRQHandler
- .thumb_set PVD_IRQHandler,Default_Handler
-
- .weak RTC_IRQHandler
- .thumb_set RTC_IRQHandler,Default_Handler
-
- .weak FLASH_IRQHandler
- .thumb_set FLASH_IRQHandler,Default_Handler
-
- .weak RCC_IRQHandler
- .thumb_set RCC_IRQHandler,Default_Handler
-
- .weak EXTI0_1_IRQHandler
- .thumb_set EXTI0_1_IRQHandler,Default_Handler
-
- .weak EXTI2_3_IRQHandler
- .thumb_set EXTI2_3_IRQHandler,Default_Handler
-
- .weak EXTI4_15_IRQHandler
- .thumb_set EXTI4_15_IRQHandler,Default_Handler
-
- .weak DMA1_Channel1_IRQHandler
- .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
- .weak DMA1_Channel2_3_IRQHandler
- .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler
-
- .weak DMA1_Channel4_5_IRQHandler
- .thumb_set DMA1_Channel4_5_IRQHandler,Default_Handler
-
- .weak ADC1_IRQHandler
- .thumb_set ADC1_IRQHandler,Default_Handler
-
- .weak TIM1_BRK_UP_TRG_COM_IRQHandler
- .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler
-
- .weak TIM1_CC_IRQHandler
- .thumb_set TIM1_CC_IRQHandler,Default_Handler
-
- .weak TIM2_IRQHandler
- .thumb_set TIM2_IRQHandler,Default_Handler
-
- .weak TIM3_IRQHandler
- .thumb_set TIM3_IRQHandler,Default_Handler
-
- .weak TIM14_IRQHandler
- .thumb_set TIM14_IRQHandler,Default_Handler
-
- .weak TIM16_IRQHandler
- .thumb_set TIM16_IRQHandler,Default_Handler
-
- .weak TIM17_IRQHandler
- .thumb_set TIM17_IRQHandler,Default_Handler
-
- .weak I2C1_IRQHandler
- .thumb_set I2C1_IRQHandler,Default_Handler
-
- .weak SPI1_IRQHandler
- .thumb_set SPI1_IRQHandler,Default_Handler
-
- .weak USART1_IRQHandler
- .thumb_set USART1_IRQHandler,Default_Handler
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc_ride7/startup_stm32f042.s b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc_ride7/startup_stm32f042.s
deleted file mode 100644
index 598290c51d86df02d100c1e1ace526cf36363bec..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc_ride7/startup_stm32f042.s
+++ /dev/null
@@ -1,302 +0,0 @@
-/**
- ******************************************************************************
- * @file startup_stm32f042.s
- * @author MCD Application Team
- * @version V1.3.1
- * @date 17-January-2014
- * @brief STM32F042 Devices vector table for Atollic toolchain.
- * This module performs:
- * - Set the initial SP
- * - Set the initial PC == Reset_Handler,
- * - Set the vector table entries with the exceptions ISR address
- * - Configure the system clock
- * - Branches to main in the C library (which eventually
- * calls main()).
- * After Reset the Cortex-M0 processor is in Thread mode,
- * priority is Privileged, and the Stack is set to Main.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
- .syntax unified
- .cpu cortex-m0
- .fpu softvfp
- .thumb
-
-.global g_pfnVectors
-.global Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word _sidata
-/* start address for the .data section. defined in linker script */
-.word _sdata
-/* end address for the .data section. defined in linker script */
-.word _edata
-/* start address for the .bss section. defined in linker script */
-.word _sbss
-/* end address for the .bss section. defined in linker script */
-.word _ebss
-
-.equ BootRAM, 0xF108F85F
-/**
- * @brief This is the code that gets called when the processor first
- * starts execution following a reset event. Only the absolutely
- * necessary set is performed, after which the application
- * supplied main() routine is called.
- * @param None
- * @retval : None
-*/
-
- .section .text.Reset_Handler
- .weak Reset_Handler
- .type Reset_Handler, %function
-Reset_Handler:
- ldr r0, =_estack
- mov sp, r0 /* set stack pointer */
-
-/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
- b LoopCopyDataInit
-
-CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
-
-LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
- bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
-/* Zero fill the bss segment. */
-FillZerobss:
- movs r3, #0
- str r3, [r2]
- adds r2, r2, #4
-
-
-LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
- bcc FillZerobss
-
-/* Call the clock system intitialization function.*/
- bl SystemInit
-/* Call static constructors */
- bl __libc_init_array
-/* Call the application's entry point.*/
- bl main
-
-LoopForever:
- b LoopForever
-
-
-.size Reset_Handler, .-Reset_Handler
-
-/**
- * @brief This is the code that gets called when the processor receives an
- * unexpected interrupt. This simply enters an infinite loop, preserving
- * the system state for examination by a debugger.
- *
- * @param None
- * @retval : None
-*/
- .section .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
- b Infinite_Loop
- .size Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M0. Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
- .section .isr_vector,"a",%progbits
- .type g_pfnVectors, %object
- .size g_pfnVectors, .-g_pfnVectors
-
-g_pfnVectors:
- .word _estack
- .word Reset_Handler
-
- .word NMI_Handler
- .word HardFault_Handler
- .word 0
- .word 0
- .word 0
- .word 0
- .word 0
- .word 0
- .word 0
- .word SVC_Handler
- .word 0
- .word 0
- .word PendSV_Handler
- .word SysTick_Handler
-
-
- .word WWDG_IRQHandler
- .word PVD_VDDIO2_IRQHandler
- .word RTC_IRQHandler
- .word FLASH_IRQHandler
- .word RCC_CRS_IRQHandler
- .word EXTI0_1_IRQHandler
- .word EXTI2_3_IRQHandler
- .word EXTI4_15_IRQHandler
- .word TSC_IRQHandler
- .word DMA1_Channel1_IRQHandler
- .word DMA1_Channel2_3_IRQHandler
- .word DMA1_Channel4_5_IRQHandler
- .word ADC1_IRQHandler
- .word TIM1_BRK_UP_TRG_COM_IRQHandler
- .word TIM1_CC_IRQHandler
- .word TIM2_IRQHandler
- .word TIM3_IRQHandler
- .word 0
- .word 0
- .word TIM14_IRQHandler
- .word 0
- .word TIM16_IRQHandler
- .word TIM17_IRQHandler
- .word I2C1_IRQHandler
- .word 0
- .word SPI1_IRQHandler
- .word SPI2_IRQHandler
- .word USART1_IRQHandler
- .word USART2_IRQHandler
- .word 0
- .word CEC_CAN_IRQHandler
- .word USB_IRQHandler
- .word BootRAM /* @0x108. This is for boot in RAM mode for
- STM32F0xx devices. */
-
-
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
-
- .weak NMI_Handler
- .thumb_set NMI_Handler,Default_Handler
-
- .weak HardFault_Handler
- .thumb_set HardFault_Handler,Default_Handler
-
- .weak SVC_Handler
- .thumb_set SVC_Handler,Default_Handler
-
- .weak PendSV_Handler
- .thumb_set PendSV_Handler,Default_Handler
-
- .weak SysTick_Handler
- .thumb_set SysTick_Handler,Default_Handler
-
- .weak WWDG_IRQHandler
- .thumb_set WWDG_IRQHandler,Default_Handler
-
- .weak PVD_VDDIO2_IRQHandler
- .thumb_set PVD_VDDIO2_IRQHandler,Default_Handler
-
- .weak RTC_IRQHandler
- .thumb_set RTC_IRQHandler,Default_Handler
-
- .weak FLASH_IRQHandler
- .thumb_set FLASH_IRQHandler,Default_Handler
-
- .weak RCC_CRS_IRQHandler
- .thumb_set RCC_CRS_IRQHandler,Default_Handler
-
- .weak EXTI0_1_IRQHandler
- .thumb_set EXTI0_1_IRQHandler,Default_Handler
-
- .weak EXTI2_3_IRQHandler
- .thumb_set EXTI2_3_IRQHandler,Default_Handler
-
- .weak EXTI4_15_IRQHandler
- .thumb_set EXTI4_15_IRQHandler,Default_Handler
-
- .weak TSC_IRQHandler
- .thumb_set TSC_IRQHandler,Default_Handler
-
- .weak DMA1_Channel1_IRQHandler
- .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
- .weak DMA1_Channel2_3_IRQHandler
- .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler
-
- .weak DMA1_Channel4_5_IRQHandler
- .thumb_set DMA1_Channel4_5_IRQHandler,Default_Handler
-
- .weak ADC1_IRQHandler
- .thumb_set ADC1_IRQHandler,Default_Handler
-
- .weak TIM1_BRK_UP_TRG_COM_IRQHandler
- .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler
-
- .weak TIM1_CC_IRQHandler
- .thumb_set TIM1_CC_IRQHandler,Default_Handler
-
- .weak TIM2_IRQHandler
- .thumb_set TIM2_IRQHandler,Default_Handler
-
- .weak TIM3_IRQHandler
- .thumb_set TIM3_IRQHandler,Default_Handler
-
- .weak TIM14_IRQHandler
- .thumb_set TIM14_IRQHandler,Default_Handler
-
- .weak TIM16_IRQHandler
- .thumb_set TIM16_IRQHandler,Default_Handler
-
- .weak TIM17_IRQHandler
- .thumb_set TIM17_IRQHandler,Default_Handler
-
- .weak I2C1_IRQHandler
- .thumb_set I2C1_IRQHandler,Default_Handler
-
- .weak SPI1_IRQHandler
- .thumb_set SPI1_IRQHandler,Default_Handler
-
- .weak SPI2_IRQHandler
- .thumb_set SPI2_IRQHandler,Default_Handler
-
- .weak USART1_IRQHandler
- .thumb_set USART1_IRQHandler,Default_Handler
-
- .weak USART2_IRQHandler
- .thumb_set USART2_IRQHandler,Default_Handler
-
- .weak CEC_CAN_IRQHandler
- .thumb_set CEC_CAN_IRQHandler,Default_Handler
-
-
- .weak USB_IRQHandler
- .thumb_set USB_IRQHandler,Default_Handler
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc_ride7/startup_stm32f051.s b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc_ride7/startup_stm32f051.s
deleted file mode 100644
index b0bb312cd4a2e5ebe7188c662765ee2e09c94861..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc_ride7/startup_stm32f051.s
+++ /dev/null
@@ -1,307 +0,0 @@
-/**
- ******************************************************************************
- * @file startup_stm32f0xx.s
- * @author MCD Application Team
- * @version V1.3.1
- * @date 17-January-2014
- * @brief STM32F051 Devices vector table for RIDE7 toolchain.
- * This module performs:
- * - Set the initial SP
- * - Set the initial PC == Reset_Handler,
- * - Set the vector table entries with the exceptions ISR address
- * - Configure the system clock
- * - Branches to main in the C library (which eventually
- * calls main()).
- * After Reset the Cortex-M0 processor is in Thread mode,
- * priority is Privileged, and the Stack is set to Main.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
- .syntax unified
- .cpu cortex-m0
- .fpu softvfp
- .thumb
-
-.global g_pfnVectors
-.global Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word _sidata
-/* start address for the .data section. defined in linker script */
-.word _sdata
-/* end address for the .data section. defined in linker script */
-.word _edata
-/* start address for the .bss section. defined in linker script */
-.word _sbss
-/* end address for the .bss section. defined in linker script */
-.word _ebss
-
-.equ BootRAM, 0xF108F85F
-/**
- * @brief This is the code that gets called when the processor first
- * starts execution following a reset event. Only the absolutely
- * necessary set is performed, after which the application
- * supplied main() routine is called.
- * @param None
- * @retval : None
-*/
-
- .section .text.Reset_Handler
- .weak Reset_Handler
- .type Reset_Handler, %function
-Reset_Handler:
- ldr r0, =_estack
- mov sp, r0 /* set stack pointer */
-
-/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
- b LoopCopyDataInit
-
-CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
-
-LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
- bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
-/* Zero fill the bss segment. */
-FillZerobss:
- movs r3, #0
- str r3, [r2]
- adds r2, r2, #4
-
-
-LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
- bcc FillZerobss
-
-/* Call the clock system intitialization function.*/
- bl SystemInit
-
-/* Call the application's entry point.*/
- bl main
-
-LoopForever:
- b LoopForever
-
-
-.size Reset_Handler, .-Reset_Handler
-
-/**
- * @brief This is the code that gets called when the processor receives an
- * unexpected interrupt. This simply enters an infinite loop, preserving
- * the system state for examination by a debugger.
- *
- * @param None
- * @retval : None
-*/
- .section .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
- b Infinite_Loop
- .size Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M0. Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
- .section .isr_vector,"a",%progbits
- .type g_pfnVectors, %object
- .size g_pfnVectors, .-g_pfnVectors
-
-
-g_pfnVectors:
- .word _estack
- .word Reset_Handler
-
- .word NMI_Handler
- .word HardFault_Handler
- .word 0
- .word 0
- .word 0
- .word 0
- .word 0
- .word 0
- .word 0
- .word SVC_Handler
- .word 0
- .word 0
- .word PendSV_Handler
- .word SysTick_Handler
-
-
- .word WWDG_IRQHandler
- .word PVD_IRQHandler
- .word RTC_IRQHandler
- .word FLASH_IRQHandler
- .word RCC_IRQHandler
- .word EXTI0_1_IRQHandler
- .word EXTI2_3_IRQHandler
- .word EXTI4_15_IRQHandler
- .word TS_IRQHandler
- .word DMA1_Channel1_IRQHandler
- .word DMA1_Channel2_3_IRQHandler
- .word DMA1_Channel4_5_IRQHandler
- .word ADC1_COMP_IRQHandler
- .word TIM1_BRK_UP_TRG_COM_IRQHandler
- .word TIM1_CC_IRQHandler
- .word TIM2_IRQHandler
- .word TIM3_IRQHandler
- .word TIM6_DAC_IRQHandler
- .word 0
- .word TIM14_IRQHandler
- .word TIM15_IRQHandler
- .word TIM16_IRQHandler
- .word TIM17_IRQHandler
- .word I2C1_IRQHandler
- .word I2C2_IRQHandler
- .word SPI1_IRQHandler
- .word SPI2_IRQHandler
- .word USART1_IRQHandler
- .word USART2_IRQHandler
- .word 0
- .word CEC_IRQHandler
- .word 0
- .word BootRAM /* @0x108. This is for boot in RAM mode for
- STM32F0xx devices. */
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
-
- .weak NMI_Handler
- .thumb_set NMI_Handler,Default_Handler
-
- .weak HardFault_Handler
- .thumb_set HardFault_Handler,Default_Handler
-
- .weak SVC_Handler
- .thumb_set SVC_Handler,Default_Handler
-
- .weak PendSV_Handler
- .thumb_set PendSV_Handler,Default_Handler
-
- .weak SysTick_Handler
- .thumb_set SysTick_Handler,Default_Handler
-
- .weak WWDG_IRQHandler
- .thumb_set WWDG_IRQHandler,Default_Handler
-
- .weak PVD_IRQHandler
- .thumb_set PVD_IRQHandler,Default_Handler
-
- .weak RTC_IRQHandler
- .thumb_set RTC_IRQHandler,Default_Handler
-
- .weak FLASH_IRQHandler
- .thumb_set FLASH_IRQHandler,Default_Handler
-
- .weak RCC_IRQHandler
- .thumb_set RCC_IRQHandler,Default_Handler
-
- .weak EXTI0_1_IRQHandler
- .thumb_set EXTI0_1_IRQHandler,Default_Handler
-
- .weak EXTI2_3_IRQHandler
- .thumb_set EXTI2_3_IRQHandler,Default_Handler
-
- .weak EXTI4_15_IRQHandler
- .thumb_set EXTI4_15_IRQHandler,Default_Handler
-
- .weak TS_IRQHandler
- .thumb_set TS_IRQHandler,Default_Handler
-
- .weak DMA1_Channel1_IRQHandler
- .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
- .weak DMA1_Channel2_3_IRQHandler
- .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler
-
- .weak DMA1_Channel4_5_IRQHandler
- .thumb_set DMA1_Channel4_5_IRQHandler,Default_Handler
-
- .weak ADC1_COMP_IRQHandler
- .thumb_set ADC1_COMP_IRQHandler,Default_Handler
-
- .weak TIM1_BRK_UP_TRG_COM_IRQHandler
- .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler
-
- .weak TIM1_CC_IRQHandler
- .thumb_set TIM1_CC_IRQHandler,Default_Handler
-
- .weak TIM2_IRQHandler
- .thumb_set TIM2_IRQHandler,Default_Handler
-
- .weak TIM3_IRQHandler
- .thumb_set TIM3_IRQHandler,Default_Handler
-
- .weak TIM6_DAC_IRQHandler
- .thumb_set TIM6_DAC_IRQHandler,Default_Handler
-
- .weak TIM14_IRQHandler
- .thumb_set TIM14_IRQHandler,Default_Handler
-
- .weak TIM15_IRQHandler
- .thumb_set TIM15_IRQHandler,Default_Handler
-
- .weak TIM16_IRQHandler
- .thumb_set TIM16_IRQHandler,Default_Handler
-
- .weak TIM17_IRQHandler
- .thumb_set TIM17_IRQHandler,Default_Handler
-
- .weak I2C1_IRQHandler
- .thumb_set I2C1_IRQHandler,Default_Handler
-
- .weak I2C2_IRQHandler
- .thumb_set I2C2_IRQHandler,Default_Handler
-
- .weak SPI1_IRQHandler
- .thumb_set SPI1_IRQHandler,Default_Handler
-
- .weak SPI2_IRQHandler
- .thumb_set SPI2_IRQHandler,Default_Handler
-
- .weak USART1_IRQHandler
- .thumb_set USART1_IRQHandler,Default_Handler
-
- .weak USART2_IRQHandler
- .thumb_set USART2_IRQHandler,Default_Handler
-
- .weak CEC_IRQHandler
- .thumb_set CEC_IRQHandler,Default_Handler
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc_ride7/startup_stm32f072.s b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc_ride7/startup_stm32f072.s
deleted file mode 100644
index 21bb90cba9594148e6fad9c8c6cfceae62b8eb3e..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc_ride7/startup_stm32f072.s
+++ /dev/null
@@ -1,316 +0,0 @@
-/**
- ******************************************************************************
- * @file startup_stm32f0xx.s
- * @author MCD Application Team
- * @version V1.3.1
- * @date 17-January-2014
- * @brief STM32F072 Devices vector table for RIDE7 toolchain.
- * This module performs:
- * - Set the initial SP
- * - Set the initial PC == Reset_Handler,
- * - Set the vector table entries with the exceptions ISR address
- * - Configure the system clock
- * - Branches to main in the C library (which eventually
- * calls main()).
- * After Reset the Cortex-M0 processor is in Thread mode,
- * priority is Privileged, and the Stack is set to Main.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
- .syntax unified
- .cpu cortex-m0
- .fpu softvfp
- .thumb
-
-.global g_pfnVectors
-.global Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word _sidata
-/* start address for the .data section. defined in linker script */
-.word _sdata
-/* end address for the .data section. defined in linker script */
-.word _edata
-/* start address for the .bss section. defined in linker script */
-.word _sbss
-/* end address for the .bss section. defined in linker script */
-.word _ebss
-
-.equ BootRAM, 0xF108F85F
-/**
- * @brief This is the code that gets called when the processor first
- * starts execution following a reset event. Only the absolutely
- * necessary set is performed, after which the application
- * supplied main() routine is called.
- * @param None
- * @retval : None
-*/
-
- .section .text.Reset_Handler
- .weak Reset_Handler
- .type Reset_Handler, %function
-Reset_Handler:
- ldr r0, =_estack
- mov sp, r0 /* set stack pointer */
-
-/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
- b LoopCopyDataInit
-
-CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
-
-LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
- bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
-/* Zero fill the bss segment. */
-FillZerobss:
- movs r3, #0
- str r3, [r2]
- adds r2, r2, #4
-
-
-LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
- bcc FillZerobss
-
-/* Call the clock system intitialization function.*/
- bl SystemInit
-
-/* Call the application's entry point.*/
- bl main
-
-LoopForever:
- b LoopForever
-
-
-.size Reset_Handler, .-Reset_Handler
-
-/**
- * @brief This is the code that gets called when the processor receives an
- * unexpected interrupt. This simply enters an infinite loop, preserving
- * the system state for examination by a debugger.
- *
- * @param None
- * @retval : None
-*/
- .section .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
- b Infinite_Loop
- .size Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M0. Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
- .section .isr_vector,"a",%progbits
- .type g_pfnVectors, %object
- .size g_pfnVectors, .-g_pfnVectors
-
-
-g_pfnVectors:
- .word _estack
- .word Reset_Handler
-
- .word NMI_Handler
- .word HardFault_Handler
- .word 0
- .word 0
- .word 0
- .word 0
- .word 0
- .word 0
- .word 0
- .word SVC_Handler
- .word 0
- .word 0
- .word PendSV_Handler
- .word SysTick_Handler
-
-
- .word WWDG_IRQHandler
- .word PVD_VDDIO2_IRQHandler
- .word RTC_IRQHandler
- .word FLASH_IRQHandler
- .word RCC_CRS_IRQHandler
- .word EXTI0_1_IRQHandler
- .word EXTI2_3_IRQHandler
- .word EXTI4_15_IRQHandler
- .word TSC_IRQHandler
- .word DMA1_Channel1_IRQHandler
- .word DMA1_Channel2_3_IRQHandler
- .word DMA1_Channel4_5_6_7_IRQHandler
- .word ADC1_COMP_IRQHandler
- .word TIM1_BRK_UP_TRG_COM_IRQHandler
- .word TIM1_CC_IRQHandler
- .word TIM2_IRQHandler
- .word TIM3_IRQHandler
- .word TIM6_DAC_IRQHandler
- .word TIM7_IRQHandler
- .word TIM14_IRQHandler
- .word TIM15_IRQHandler
- .word TIM16_IRQHandler
- .word TIM17_IRQHandler
- .word I2C1_IRQHandler
- .word I2C2_IRQHandler
- .word SPI1_IRQHandler
- .word SPI2_IRQHandler
- .word USART1_IRQHandler
- .word USART2_IRQHandler
- .word USART3_4_IRQHandler
- .word CEC_CAN_IRQHandler
- .word USB_IRQHandler
- .word BootRAM /* @0x108. This is for boot in RAM mode for
- STM32F0xx devices. */
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
-
- .weak NMI_Handler
- .thumb_set NMI_Handler,Default_Handler
-
- .weak HardFault_Handler
- .thumb_set HardFault_Handler,Default_Handler
-
- .weak SVC_Handler
- .thumb_set SVC_Handler,Default_Handler
-
- .weak PendSV_Handler
- .thumb_set PendSV_Handler,Default_Handler
-
- .weak SysTick_Handler
- .thumb_set SysTick_Handler,Default_Handler
-
- .weak WWDG_IRQHandler
- .thumb_set WWDG_IRQHandler,Default_Handler
-
- .weak PVD_VDDIO2_IRQHandler
- .thumb_set PVD_VDDIO2_IRQHandler,Default_Handler
-
- .weak RTC_IRQHandler
- .thumb_set RTC_IRQHandler,Default_Handler
-
- .weak FLASH_IRQHandler
- .thumb_set FLASH_IRQHandler,Default_Handler
-
- .weak RCC_CRS_IRQHandler
- .thumb_set RCC_CRS_IRQHandler,Default_Handler
-
- .weak EXTI0_1_IRQHandler
- .thumb_set EXTI0_1_IRQHandler,Default_Handler
-
- .weak EXTI2_3_IRQHandler
- .thumb_set EXTI2_3_IRQHandler,Default_Handler
-
- .weak EXTI4_15_IRQHandler
- .thumb_set EXTI4_15_IRQHandler,Default_Handler
-
- .weak TSC_IRQHandler
- .thumb_set TSC_IRQHandler,Default_Handler
-
- .weak DMA1_Channel1_IRQHandler
- .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
- .weak DMA1_Channel2_3_IRQHandler
- .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler
-
- .weak DMA1_Channel4_5_6_7_IRQHandler
- .thumb_set DMA1_Channel4_5_6_7_IRQHandler,Default_Handler
-
- .weak ADC1_COMP_IRQHandler
- .thumb_set ADC1_COMP_IRQHandler,Default_Handler
-
- .weak TIM1_BRK_UP_TRG_COM_IRQHandler
- .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler
-
- .weak TIM1_CC_IRQHandler
- .thumb_set TIM1_CC_IRQHandler,Default_Handler
-
- .weak TIM2_IRQHandler
- .thumb_set TIM2_IRQHandler,Default_Handler
-
- .weak TIM3_IRQHandler
- .thumb_set TIM3_IRQHandler,Default_Handler
-
- .weak TIM6_DAC_IRQHandler
- .thumb_set TIM6_DAC_IRQHandler,Default_Handler
-
- .weak TIM7_IRQHandler
- .thumb_set TIM7_IRQHandler,Default_Handler
-
- .weak TIM14_IRQHandler
- .thumb_set TIM14_IRQHandler,Default_Handler
-
- .weak TIM15_IRQHandler
- .thumb_set TIM15_IRQHandler,Default_Handler
-
- .weak TIM16_IRQHandler
- .thumb_set TIM16_IRQHandler,Default_Handler
-
- .weak TIM17_IRQHandler
- .thumb_set TIM17_IRQHandler,Default_Handler
-
- .weak I2C1_IRQHandler
- .thumb_set I2C1_IRQHandler,Default_Handler
-
- .weak I2C2_IRQHandler
- .thumb_set I2C2_IRQHandler,Default_Handler
-
- .weak SPI1_IRQHandler
- .thumb_set SPI1_IRQHandler,Default_Handler
-
- .weak SPI2_IRQHandler
- .thumb_set SPI2_IRQHandler,Default_Handler
-
- .weak USART1_IRQHandler
- .thumb_set USART1_IRQHandler,Default_Handler
-
- .weak USART2_IRQHandler
- .thumb_set USART2_IRQHandler,Default_Handler
-
- .weak USART3_4_IRQHandler
- .thumb_set USART3_4_IRQHandler,Default_Handler
-
- .weak CEC_CAN_IRQHandler
- .thumb_set CEC_CAN_IRQHandler,Default_Handler
-
- .weak USB_IRQHandler
- .thumb_set USB_IRQHandler,Default_Handler
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc_ride7/startup_stm32f0xx.s b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc_ride7/startup_stm32f0xx.s
deleted file mode 100644
index 3ed8d9d4c00ad7e86d4117845580311e9a7557d5..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/gcc_ride7/startup_stm32f0xx.s
+++ /dev/null
@@ -1,304 +0,0 @@
-/**
- ******************************************************************************
- * @file startup_stm32f0xx.s
- * @author MCD Application Team
- * @version V1.3.1
- * @date 17-January-2014
- * @brief STM32F0xx Devices vector table for RIDE7 toolchain.
- * This module performs:
- * - Set the initial SP
- * - Set the initial PC == Reset_Handler,
- * - Set the vector table entries with the exceptions ISR address
- * - Configure the system clock
- * - Branches to main in the C library (which eventually
- * calls main()).
- * After Reset the Cortex-M0 processor is in Thread mode,
- * priority is Privileged, and the Stack is set to Main.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
- .syntax unified
- .cpu cortex-m0
- .fpu softvfp
- .thumb
-
-.global g_pfnVectors
-.global Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word _sidata
-/* start address for the .data section. defined in linker script */
-.word _sdata
-/* end address for the .data section. defined in linker script */
-.word _edata
-/* start address for the .bss section. defined in linker script */
-.word _sbss
-/* end address for the .bss section. defined in linker script */
-.word _ebss
-
-.equ BootRAM, 0xF108F85F
-/**
- * @brief This is the code that gets called when the processor first
- * starts execution following a reset event. Only the absolutely
- * necessary set is performed, after which the application
- * supplied main() routine is called.
- * @param None
- * @retval : None
-*/
-
- .section .text.Reset_Handler
- .weak Reset_Handler
- .type Reset_Handler, %function
-Reset_Handler:
- ldr r0, =_estack
- mov sp, r0 /* set stack pointer */
-
-/* Copy the data segment initializers from flash to SRAM */
- movs r1, #0
- b LoopCopyDataInit
-
-CopyDataInit:
- ldr r3, =_sidata
- ldr r3, [r3, r1]
- str r3, [r0, r1]
- adds r1, r1, #4
-
-LoopCopyDataInit:
- ldr r0, =_sdata
- ldr r3, =_edata
- adds r2, r0, r1
- cmp r2, r3
- bcc CopyDataInit
- ldr r2, =_sbss
- b LoopFillZerobss
-/* Zero fill the bss segment. */
-FillZerobss:
- movs r3, #0
- str r3, [r2]
- adds r2, r2, #4
-
-
-LoopFillZerobss:
- ldr r3, = _ebss
- cmp r2, r3
- bcc FillZerobss
-
-/* Call the clock system intitialization function.*/
- bl SystemInit
-
-/* Call the application's entry point.*/
- bl main
-
-LoopForever:
- b LoopForever
-
-
-.size Reset_Handler, .-Reset_Handler
-
-/**
- * @brief This is the code that gets called when the processor receives an
- * unexpected interrupt. This simply enters an infinite loop, preserving
- * the system state for examination by a debugger.
- *
- * @param None
- * @retval : None
-*/
- .section .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
- b Infinite_Loop
- .size Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M0. Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
- .section .isr_vector,"a",%progbits
- .type g_pfnVectors, %object
- .size g_pfnVectors, .-g_pfnVectors
-
-
-g_pfnVectors:
- .word _estack
- .word Reset_Handler
- .word NMI_Handler
- .word HardFault_Handler
- .word 0
- .word 0
- .word 0
- .word 0
- .word 0
- .word 0
- .word 0
- .word SVC_Handler
- .word 0
- .word 0
- .word PendSV_Handler
- .word SysTick_Handler
- .word WWDG_IRQHandler
- .word PVD_IRQHandler
- .word RTC_IRQHandler
- .word FLASH_IRQHandler
- .word RCC_IRQHandler
- .word EXTI0_1_IRQHandler
- .word EXTI2_3_IRQHandler
- .word EXTI4_15_IRQHandler
- .word TS_IRQHandler
- .word DMA1_Channel1_IRQHandler
- .word DMA1_Channel2_3_IRQHandler
- .word DMA1_Channel4_5_IRQHandler
- .word ADC1_COMP_IRQHandler
- .word TIM1_BRK_UP_TRG_COM_IRQHandler
- .word TIM1_CC_IRQHandler
- .word TIM2_IRQHandler
- .word TIM3_IRQHandler
- .word TIM6_DAC_IRQHandler
- .word 0
- .word TIM14_IRQHandler
- .word TIM15_IRQHandler
- .word TIM16_IRQHandler
- .word TIM17_IRQHandler
- .word I2C1_IRQHandler
- .word I2C2_IRQHandler
- .word SPI1_IRQHandler
- .word SPI2_IRQHandler
- .word USART1_IRQHandler
- .word USART2_IRQHandler
- .word 0
- .word CEC_IRQHandler
- .word 0
- .word BootRAM /* @0x108. This is for boot in RAM mode for
- STM32F0xx devices. */
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
-
- .weak NMI_Handler
- .thumb_set NMI_Handler,Default_Handler
-
- .weak HardFault_Handler
- .thumb_set HardFault_Handler,Default_Handler
-
- .weak SVC_Handler
- .thumb_set SVC_Handler,Default_Handler
-
- .weak PendSV_Handler
- .thumb_set PendSV_Handler,Default_Handler
-
- .weak SysTick_Handler
- .thumb_set SysTick_Handler,Default_Handler
-
- .weak WWDG_IRQHandler
- .thumb_set WWDG_IRQHandler,Default_Handler
-
- .weak PVD_IRQHandler
- .thumb_set PVD_IRQHandler,Default_Handler
-
- .weak RTC_IRQHandler
- .thumb_set RTC_IRQHandler,Default_Handler
-
- .weak FLASH_IRQHandler
- .thumb_set FLASH_IRQHandler,Default_Handler
-
- .weak RCC_IRQHandler
- .thumb_set RCC_IRQHandler,Default_Handler
-
- .weak EXTI0_1_IRQHandler
- .thumb_set EXTI0_1_IRQHandler,Default_Handler
-
- .weak EXTI2_3_IRQHandler
- .thumb_set EXTI2_3_IRQHandler,Default_Handler
-
- .weak EXTI4_15_IRQHandler
- .thumb_set EXTI4_15_IRQHandler,Default_Handler
-
- .weak TS_IRQHandler
- .thumb_set TS_IRQHandler,Default_Handler
-
- .weak DMA1_Channel1_IRQHandler
- .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
- .weak DMA1_Channel2_3_IRQHandler
- .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler
-
- .weak DMA1_Channel4_5_IRQHandler
- .thumb_set DMA1_Channel4_5_IRQHandler,Default_Handler
-
- .weak ADC1_COMP_IRQHandler
- .thumb_set ADC1_COMP_IRQHandler,Default_Handler
-
- .weak TIM1_BRK_UP_TRG_COM_IRQHandler
- .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler
-
- .weak TIM1_CC_IRQHandler
- .thumb_set TIM1_CC_IRQHandler,Default_Handler
-
- .weak TIM2_IRQHandler
- .thumb_set TIM2_IRQHandler,Default_Handler
-
- .weak TIM3_IRQHandler
- .thumb_set TIM3_IRQHandler,Default_Handler
-
- .weak TIM6_DAC_IRQHandler
- .thumb_set TIM6_DAC_IRQHandler,Default_Handler
-
- .weak TIM14_IRQHandler
- .thumb_set TIM14_IRQHandler,Default_Handler
-
- .weak TIM15_IRQHandler
- .thumb_set TIM15_IRQHandler,Default_Handler
-
- .weak TIM16_IRQHandler
- .thumb_set TIM16_IRQHandler,Default_Handler
-
- .weak TIM17_IRQHandler
- .thumb_set TIM17_IRQHandler,Default_Handler
-
- .weak I2C1_IRQHandler
- .thumb_set I2C1_IRQHandler,Default_Handler
-
- .weak I2C2_IRQHandler
- .thumb_set I2C2_IRQHandler,Default_Handler
-
- .weak SPI1_IRQHandler
- .thumb_set SPI1_IRQHandler,Default_Handler
-
- .weak SPI2_IRQHandler
- .thumb_set SPI2_IRQHandler,Default_Handler
-
- .weak USART1_IRQHandler
- .thumb_set USART1_IRQHandler,Default_Handler
-
- .weak USART2_IRQHandler
- .thumb_set USART2_IRQHandler,Default_Handler
-
- .weak CEC_IRQHandler
- .thumb_set CEC_IRQHandler,Default_Handler
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/iar/startup_stm32f030.s b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/iar/startup_stm32f030.s
deleted file mode 100644
index f2e56032d18830b3254c3345abff39aac39e7be7..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/iar/startup_stm32f030.s
+++ /dev/null
@@ -1,300 +0,0 @@
-;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
-;* File Name : startup_stm32f030.s
-;* Author : MCD Application Team
-;* Version : V1.3.1
-;* Date : 17-January-2014
-;* Description : STM32F030 devices vector table for EWARM toolchain.
-;* This module performs:
-;* - Set the initial SP
-;* - Set the initial PC == iar_program_start,
-;* - Set the vector table entries with the exceptions ISR
-;* address
-;* - Configure the system clock
-;* - Branches to main in the C library (which eventually
-;* calls main()).
-;* After Reset the Cortex-M0 processor is in Thread mode,
-;* priority is Privileged, and the Stack is set to Main.
-;*******************************************************************************
-; @attention
-;
-; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-; You may not use this file except in compliance with the License.
-; You may obtain a copy of the License at:
-;
-; http://www.st.com/software_license_agreement_liberty_v2
-;
-; Unless required by applicable law or agreed to in writing, software
-; distributed under the License is distributed on an "AS IS" BASIS,
-; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-; See the License for the specific language governing permissions and
-; limitations under the License.
-;
-;*******************************************************************************
-;
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
- MODULE ?cstartup
-
- ;; Forward declaration of sections.
- SECTION CSTACK:DATA:NOROOT(3)
-
- SECTION .intvec:CODE:NOROOT(2)
-
- EXTERN __iar_program_start
- EXTERN SystemInit
- PUBLIC __vector_table
-
- DATA
-__vector_table
- DCD sfe(CSTACK)
- DCD Reset_Handler ; Reset Handler
-
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
-
- ; External Interrupts
- DCD WWDG_IRQHandler ; Window Watchdog
- DCD 0 ; Reserved
- DCD RTC_IRQHandler ; RTC through EXTI Line
- DCD FLASH_IRQHandler ; FLASH
- DCD RCC_IRQHandler ; RCC
- DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1
- DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3
- DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15
- DCD 0 ; Reserved
- DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
- DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3
- DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5
- DCD ADC1_IRQHandler ; ADC1
- DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
- DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
- DCD 0 ; Reserved
- DCD TIM3_IRQHandler ; TIM3
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD TIM14_IRQHandler ; TIM14
- DCD TIM15_IRQHandler ; TIM15
- DCD TIM16_IRQHandler ; TIM16
- DCD TIM17_IRQHandler ; TIM17
- DCD I2C1_IRQHandler ; I2C1
- DCD I2C2_IRQHandler ; I2C2
- DCD SPI1_IRQHandler ; SPI1
- DCD SPI2_IRQHandler ; SPI2
- DCD USART1_IRQHandler ; USART1
- DCD USART2_IRQHandler ; USART2
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
- THUMB
-
- PUBWEAK Reset_Handler
- SECTION .text:CODE:REORDER(2)
-Reset_Handler
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__iar_program_start
- BX R0
-
- PUBWEAK NMI_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-NMI_Handler
- B NMI_Handler
-
-
- PUBWEAK HardFault_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-HardFault_Handler
- B HardFault_Handler
-
-
- PUBWEAK SVC_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SVC_Handler
- B SVC_Handler
-
-
- PUBWEAK PendSV_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-PendSV_Handler
- B PendSV_Handler
-
-
- PUBWEAK SysTick_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SysTick_Handler
- B SysTick_Handler
-
-
- PUBWEAK WWDG_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-WWDG_IRQHandler
- B WWDG_IRQHandler
-
-
- PUBWEAK RTC_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-RTC_IRQHandler
- B RTC_IRQHandler
-
-
- PUBWEAK FLASH_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-FLASH_IRQHandler
- B FLASH_IRQHandler
-
-
- PUBWEAK RCC_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-RCC_IRQHandler
- B RCC_IRQHandler
-
-
- PUBWEAK EXTI0_1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI0_1_IRQHandler
- B EXTI0_1_IRQHandler
-
-
- PUBWEAK EXTI2_3_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI2_3_IRQHandler
- B EXTI2_3_IRQHandler
-
-
- PUBWEAK EXTI4_15_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI4_15_IRQHandler
- B EXTI4_15_IRQHandler
-
-
- PUBWEAK DMA1_Channel1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel1_IRQHandler
- B DMA1_Channel1_IRQHandler
-
-
- PUBWEAK DMA1_Channel2_3_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel2_3_IRQHandler
- B DMA1_Channel2_3_IRQHandler
-
-
- PUBWEAK DMA1_Channel4_5_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel4_5_IRQHandler
- B DMA1_Channel4_5_IRQHandler
-
-
- PUBWEAK ADC1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-ADC1_IRQHandler
- B ADC1_IRQHandler
-
-
- PUBWEAK TIM1_BRK_UP_TRG_COM_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM1_BRK_UP_TRG_COM_IRQHandler
- B TIM1_BRK_UP_TRG_COM_IRQHandler
-
-
- PUBWEAK TIM1_CC_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM1_CC_IRQHandler
- B TIM1_CC_IRQHandler
-
-
- PUBWEAK TIM3_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM3_IRQHandler
- B TIM3_IRQHandler
-
-
- PUBWEAK TIM14_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM14_IRQHandler
- B TIM14_IRQHandler
-
-
- PUBWEAK TIM15_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM15_IRQHandler
- B TIM15_IRQHandler
-
-
- PUBWEAK TIM16_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM16_IRQHandler
- B TIM16_IRQHandler
-
-
- PUBWEAK TIM17_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM17_IRQHandler
- B TIM17_IRQHandler
-
-
- PUBWEAK I2C1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-I2C1_IRQHandler
- B I2C1_IRQHandler
-
-
- PUBWEAK I2C2_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-I2C2_IRQHandler
- B I2C2_IRQHandler
-
-
- PUBWEAK SPI1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SPI1_IRQHandler
- B SPI1_IRQHandler
-
-
- PUBWEAK SPI2_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SPI2_IRQHandler
- B SPI2_IRQHandler
-
-
- PUBWEAK USART1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-USART1_IRQHandler
- B USART1_IRQHandler
-
-
- PUBWEAK USART2_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-USART2_IRQHandler
- B USART2_IRQHandler
-
- END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/iar/startup_stm32f031.s b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/iar/startup_stm32f031.s
deleted file mode 100644
index a8718ca6dd17bb0d5d475ebc7a34fc57b83d2c67..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/iar/startup_stm32f031.s
+++ /dev/null
@@ -1,288 +0,0 @@
-;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
-;* File Name : startup_stm32f031.s
-;* Author : MCD Application Team
-;* Version : V1.3.1
-;* Date : 17-January-2014
-;* Description : STM32F031 devices vector table for EWARM toolchain.
-;* This module performs:
-;* - Set the initial SP
-;* - Set the initial PC == iar_program_start,
-;* - Set the vector table entries with the exceptions ISR
-;* address
-;* - Configure the system clock
-;* - Branches to main in the C library (which eventually
-;* calls main()).
-;* After Reset the Cortex-M0 processor is in Thread mode,
-;* priority is Privileged, and the Stack is set to Main.
-;*******************************************************************************
-; @attention
-;
-; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-; You may not use this file except in compliance with the License.
-; You may obtain a copy of the License at:
-;
-; http://www.st.com/software_license_agreement_liberty_v2
-;
-; Unless required by applicable law or agreed to in writing, software
-; distributed under the License is distributed on an "AS IS" BASIS,
-; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-; See the License for the specific language governing permissions and
-; limitations under the License.
-;
-;*******************************************************************************
-;
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
- MODULE ?cstartup
-
- ;; Forward declaration of sections.
- SECTION CSTACK:DATA:NOROOT(3)
-
- SECTION .intvec:CODE:NOROOT(2)
-
- EXTERN __iar_program_start
- EXTERN SystemInit
- PUBLIC __vector_table
-
- DATA
-__vector_table
- DCD sfe(CSTACK)
- DCD Reset_Handler ; Reset Handler
-
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
-
- ; External Interrupts
- DCD WWDG_IRQHandler ; Window Watchdog
- DCD PVD_IRQHandler ; PVD through EXTI Line detect
- DCD RTC_IRQHandler ; RTC through EXTI Line
- DCD FLASH_IRQHandler ; FLASH
- DCD RCC_IRQHandler ; RCC
- DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1
- DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3
- DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15
- DCD 0 ; Reserved
- DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
- DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3
- DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5
- DCD ADC1_IRQHandler ; ADC1
- DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
- DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
- DCD TIM2_IRQHandler ; TIM2
- DCD TIM3_IRQHandler ; TIM3
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD TIM14_IRQHandler ; TIM14
- DCD 0 ; Reserved
- DCD TIM16_IRQHandler ; TIM16
- DCD TIM17_IRQHandler ; TIM17
- DCD I2C1_IRQHandler ; I2C1
- DCD 0 ; Reserved
- DCD SPI1_IRQHandler ; SPI1
- DCD 0 ; Reserved
- DCD USART1_IRQHandler ; USART1
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
- THUMB
-
- PUBWEAK Reset_Handler
- SECTION .text:CODE:REORDER(2)
-Reset_Handler
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__iar_program_start
- BX R0
-
- PUBWEAK NMI_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-NMI_Handler
- B NMI_Handler
-
-
- PUBWEAK HardFault_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-HardFault_Handler
- B HardFault_Handler
-
-
- PUBWEAK SVC_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SVC_Handler
- B SVC_Handler
-
-
- PUBWEAK PendSV_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-PendSV_Handler
- B PendSV_Handler
-
-
- PUBWEAK SysTick_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SysTick_Handler
- B SysTick_Handler
-
-
- PUBWEAK WWDG_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-WWDG_IRQHandler
- B WWDG_IRQHandler
-
-
- PUBWEAK PVD_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-PVD_IRQHandler
- B PVD_IRQHandler
-
-
- PUBWEAK RTC_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-RTC_IRQHandler
- B RTC_IRQHandler
-
-
- PUBWEAK FLASH_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-FLASH_IRQHandler
- B FLASH_IRQHandler
-
-
- PUBWEAK RCC_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-RCC_IRQHandler
- B RCC_IRQHandler
-
-
- PUBWEAK EXTI0_1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI0_1_IRQHandler
- B EXTI0_1_IRQHandler
-
-
- PUBWEAK EXTI2_3_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI2_3_IRQHandler
- B EXTI2_3_IRQHandler
-
-
- PUBWEAK EXTI4_15_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI4_15_IRQHandler
- B EXTI4_15_IRQHandler
-
-
- PUBWEAK DMA1_Channel1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel1_IRQHandler
- B DMA1_Channel1_IRQHandler
-
-
- PUBWEAK DMA1_Channel2_3_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel2_3_IRQHandler
- B DMA1_Channel2_3_IRQHandler
-
-
- PUBWEAK DMA1_Channel4_5_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel4_5_IRQHandler
- B DMA1_Channel4_5_IRQHandler
-
-
- PUBWEAK ADC1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-ADC1_IRQHandler
- B ADC1_IRQHandler
-
-
- PUBWEAK TIM1_BRK_UP_TRG_COM_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM1_BRK_UP_TRG_COM_IRQHandler
- B TIM1_BRK_UP_TRG_COM_IRQHandler
-
-
- PUBWEAK TIM1_CC_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM1_CC_IRQHandler
- B TIM1_CC_IRQHandler
-
-
- PUBWEAK TIM2_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM2_IRQHandler
- B TIM2_IRQHandler
-
-
- PUBWEAK TIM3_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM3_IRQHandler
- B TIM3_IRQHandler
-
-
- PUBWEAK TIM14_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM14_IRQHandler
- B TIM14_IRQHandler
-
-
- PUBWEAK TIM16_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM16_IRQHandler
- B TIM16_IRQHandler
-
-
- PUBWEAK TIM17_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM17_IRQHandler
- B TIM17_IRQHandler
-
-
- PUBWEAK I2C1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-I2C1_IRQHandler
- B I2C1_IRQHandler
-
-
- PUBWEAK SPI1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SPI1_IRQHandler
- B SPI1_IRQHandler
-
-
- PUBWEAK USART1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-USART1_IRQHandler
- B USART1_IRQHandler
-
-
- END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/iar/startup_stm32f042.s b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/iar/startup_stm32f042.s
deleted file mode 100644
index 1ebe0466a50c8979b238d7bf64bf9aef81c74ba5..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/iar/startup_stm32f042.s
+++ /dev/null
@@ -1,318 +0,0 @@
-;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
-;* File Name : startup_stm32f042.s
-;* Author : MCD Appl&ication Team
-;* Version : V1.3.1
-;* Date : 17-January-2014
-;* Description : STM32F042 Devices Devices vector table for
-;* EWARM toolchain.
-;* This module performs:
-;* - Set the initial SP
-;* - Set the initial PC == iar_program_start,
-;* - Set the vector table entries with the exceptions ISR
-;* address.
-;* After Reset the Cortex-M0 processor is in Thread mode,
-;* priority is Privileged, and the Stack is set to Main.
-;*******************************************************************************
-; @attention
-;
-; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-; You may not use this file except in compliance with the License.
-; You may obtain a copy of the License at:
-;
-; http://www.st.com/software_license_agreement_liberty_v2
-;
-; Unless required by applicable law or agreed to in writing, software
-; distributed under the License is distributed on an "AS IS" BASIS,
-; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-; See the License for the specific language governing permissions and
-; limitations under the License.
-;
-;*******************************************************************************
-;
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
- MODULE ?cstartup
-
- ;; Forward declaration of sections.
- SECTION CSTACK:DATA:NOROOT(3)
-
- SECTION .intvec:CODE:NOROOT(2)
-
- EXTERN __iar_program_start
- EXTERN SystemInit
- PUBLIC __vector_table
-
- DATA
-__vector_table
- DCD sfe(CSTACK)
- DCD Reset_Handler ; Reset Handler
-
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
-
- ; External Interrupts
- DCD WWDG_IRQHandler ; Window Watchdog
- DCD PVD_VDDIO2_IRQHandler ; PVD and VDDIO2 through EXTI Line detect
- DCD RTC_IRQHandler ; RTC through EXTI Line
- DCD FLASH_IRQHandler ; FLASH
- DCD RCC_CRS_IRQHandler ; RCC and CRS
- DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1
- DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3
- DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15
- DCD TSC_IRQHandler ; TS
- DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
- DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3
- DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4, Channel 5, Channel 6 and Channel 7
- DCD ADC1_IRQHandler ; ADC1
- DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
- DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
- DCD TIM2_IRQHandler ; TIM2
- DCD TIM3_IRQHandler ; TIM3
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD TIM14_IRQHandler ; TIM14
- DCD 0 ; Reserved
- DCD TIM16_IRQHandler ; TIM16
- DCD TIM17_IRQHandler ; TIM17
- DCD I2C1_IRQHandler ; I2C1
- DCD 0 ; Reserved
- DCD SPI1_IRQHandler ; SPI1
- DCD SPI2_IRQHandler ; SPI2
- DCD USART1_IRQHandler ; USART1
- DCD USART2_IRQHandler ; USART2
- DCD 0 ; Reserved
- DCD CEC_CAN_IRQHandler ; CEC and CAN
- DCD USB_IRQHandler ; USB
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
- THUMB
-
- PUBWEAK Reset_Handler
- SECTION .text:CODE:REORDER(2)
-Reset_Handler
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__iar_program_start
- BX R0
-
- PUBWEAK NMI_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-NMI_Handler
- B NMI_Handler
-
-
- PUBWEAK HardFault_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-HardFault_Handler
- B HardFault_Handler
-
-
- PUBWEAK SVC_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SVC_Handler
- B SVC_Handler
-
-
- PUBWEAK PendSV_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-PendSV_Handler
- B PendSV_Handler
-
-
- PUBWEAK SysTick_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SysTick_Handler
- B SysTick_Handler
-
-
- PUBWEAK WWDG_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-WWDG_IRQHandler
- B WWDG_IRQHandler
-
-
- PUBWEAK PVD_VDDIO2_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-PVD_VDDIO2_IRQHandler
- B PVD_VDDIO2_IRQHandler
-
-
- PUBWEAK RTC_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-RTC_IRQHandler
- B RTC_IRQHandler
-
-
- PUBWEAK FLASH_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-FLASH_IRQHandler
- B FLASH_IRQHandler
-
-
- PUBWEAK RCC_CRS_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-RCC_CRS_IRQHandler
- B RCC_CRS_IRQHandler
-
-
- PUBWEAK EXTI0_1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI0_1_IRQHandler
- B EXTI0_1_IRQHandler
-
-
- PUBWEAK EXTI2_3_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI2_3_IRQHandler
- B EXTI2_3_IRQHandler
-
-
- PUBWEAK EXTI4_15_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI4_15_IRQHandler
- B EXTI4_15_IRQHandler
-
-
- PUBWEAK TSC_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TSC_IRQHandler
- B TSC_IRQHandler
-
-
- PUBWEAK DMA1_Channel1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel1_IRQHandler
- B DMA1_Channel1_IRQHandler
-
-
- PUBWEAK DMA1_Channel2_3_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel2_3_IRQHandler
- B DMA1_Channel2_3_IRQHandler
-
-
- PUBWEAK DMA1_Channel4_5_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel4_5_IRQHandler
- B DMA1_Channel4_5_IRQHandler
-
-
- PUBWEAK ADC1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-ADC1_IRQHandler
- B ADC1_IRQHandler
-
-
- PUBWEAK TIM1_BRK_UP_TRG_COM_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM1_BRK_UP_TRG_COM_IRQHandler
- B TIM1_BRK_UP_TRG_COM_IRQHandler
-
-
- PUBWEAK TIM1_CC_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM1_CC_IRQHandler
- B TIM1_CC_IRQHandler
-
-
- PUBWEAK TIM2_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM2_IRQHandler
- B TIM2_IRQHandler
-
-
- PUBWEAK TIM3_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM3_IRQHandler
- B TIM3_IRQHandler
-
-
- PUBWEAK TIM14_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM14_IRQHandler
- B TIM14_IRQHandler
-
-
- PUBWEAK TIM16_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM16_IRQHandler
- B TIM16_IRQHandler
-
-
- PUBWEAK TIM17_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM17_IRQHandler
- B TIM17_IRQHandler
-
-
- PUBWEAK I2C1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-I2C1_IRQHandler
- B I2C1_IRQHandler
-
-
- PUBWEAK SPI1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SPI1_IRQHandler
- B SPI1_IRQHandler
-
-
- PUBWEAK SPI2_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SPI2_IRQHandler
- B SPI2_IRQHandler
-
-
- PUBWEAK USART1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-USART1_IRQHandler
- B USART1_IRQHandler
-
-
- PUBWEAK USART2_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-USART2_IRQHandler
- B USART2_IRQHandler
-
-
- PUBWEAK CEC_CAN_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-CEC_CAN_IRQHandler
- B CEC_CAN_IRQHandler
-
- PUBWEAK USB_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-USB_IRQHandler
- B USB_IRQHandler
-
- END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/iar/startup_stm32f051.s b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/iar/startup_stm32f051.s
deleted file mode 100644
index 29c1e7ae4442ed2c0c9743ea03039fc4ed6de965..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/iar/startup_stm32f051.s
+++ /dev/null
@@ -1,333 +0,0 @@
-;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
-;* File Name : startup_stm32f051.s
-;* Author : MCD Application Team
-;* Version : V1.3.1
-;* Date : 17-January-2014
-;* Description : STM32F051 devices vector table for EWARM toolchain.
-;* This module performs:
-;* - Set the initial SP
-;* - Set the initial PC == iar_program_start,
-;* - Set the vector table entries with the exceptions ISR
-;* address
-;* - Configure the system clock
-;* - Branches to main in the C library (which eventually
-;* calls main()).
-;* After Reset the Cortex-M0 processor is in Thread mode,
-;* priority is Privileged, and the Stack is set to Main.
-;*******************************************************************************
-; @attention
-;
-; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-; You may not use this file except in compliance with the License.
-; You may obtain a copy of the License at:
-;
-; http://www.st.com/software_license_agreement_liberty_v2
-;
-; Unless required by applicable law or agreed to in writing, software
-; distributed under the License is distributed on an "AS IS" BASIS,
-; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-; See the License for the specific language governing permissions and
-; limitations under the License.
-;
-;*******************************************************************************
-;
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
- MODULE ?cstartup
-
- ;; Forward declaration of sections.
- SECTION CSTACK:DATA:NOROOT(3)
-
- SECTION .intvec:CODE:NOROOT(2)
-
- EXTERN __iar_program_start
- EXTERN SystemInit
- PUBLIC __vector_table
-
- DATA
-__vector_table
- DCD sfe(CSTACK)
- DCD Reset_Handler ; Reset Handler
-
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
-
- ; External Interrupts
- DCD WWDG_IRQHandler ; Window Watchdog
- DCD PVD_IRQHandler ; PVD through EXTI Line detect
- DCD RTC_IRQHandler ; RTC through EXTI Line
- DCD FLASH_IRQHandler ; FLASH
- DCD RCC_IRQHandler ; RCC
- DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1
- DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3
- DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15
- DCD TS_IRQHandler ; TS
- DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
- DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3
- DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5
- DCD ADC1_COMP_IRQHandler ; ADC1, COMP1 and COMP2
- DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
- DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
- DCD TIM2_IRQHandler ; TIM2
- DCD TIM3_IRQHandler ; TIM3
- DCD TIM6_DAC_IRQHandler ; TIM6 and DAC
- DCD 0 ; Reserved
- DCD TIM14_IRQHandler ; TIM14
- DCD TIM15_IRQHandler ; TIM15
- DCD TIM16_IRQHandler ; TIM16
- DCD TIM17_IRQHandler ; TIM17
- DCD I2C1_IRQHandler ; I2C1
- DCD I2C2_IRQHandler ; I2C2
- DCD SPI1_IRQHandler ; SPI1
- DCD SPI2_IRQHandler ; SPI2
- DCD USART1_IRQHandler ; USART1
- DCD USART2_IRQHandler ; USART2
- DCD 0 ; Reserved
- DCD CEC_IRQHandler ; CEC
- DCD 0 ; Reserved
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
- THUMB
-
- PUBWEAK Reset_Handler
- SECTION .text:CODE:REORDER(2)
-Reset_Handler
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__iar_program_start
- BX R0
-
- PUBWEAK NMI_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-NMI_Handler
- B NMI_Handler
-
-
- PUBWEAK HardFault_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-HardFault_Handler
- B HardFault_Handler
-
-
- PUBWEAK SVC_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SVC_Handler
- B SVC_Handler
-
-
- PUBWEAK PendSV_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-PendSV_Handler
- B PendSV_Handler
-
-
- PUBWEAK SysTick_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SysTick_Handler
- B SysTick_Handler
-
-
- PUBWEAK WWDG_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-WWDG_IRQHandler
- B WWDG_IRQHandler
-
-
- PUBWEAK PVD_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-PVD_IRQHandler
- B PVD_IRQHandler
-
-
- PUBWEAK RTC_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-RTC_IRQHandler
- B RTC_IRQHandler
-
-
- PUBWEAK FLASH_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-FLASH_IRQHandler
- B FLASH_IRQHandler
-
-
- PUBWEAK RCC_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-RCC_IRQHandler
- B RCC_IRQHandler
-
-
- PUBWEAK EXTI0_1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI0_1_IRQHandler
- B EXTI0_1_IRQHandler
-
-
- PUBWEAK EXTI2_3_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI2_3_IRQHandler
- B EXTI2_3_IRQHandler
-
-
- PUBWEAK EXTI4_15_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI4_15_IRQHandler
- B EXTI4_15_IRQHandler
-
-
- PUBWEAK TS_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TS_IRQHandler
- B TS_IRQHandler
-
-
- PUBWEAK DMA1_Channel1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel1_IRQHandler
- B DMA1_Channel1_IRQHandler
-
-
- PUBWEAK DMA1_Channel2_3_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel2_3_IRQHandler
- B DMA1_Channel2_3_IRQHandler
-
-
- PUBWEAK DMA1_Channel4_5_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel4_5_IRQHandler
- B DMA1_Channel4_5_IRQHandler
-
-
- PUBWEAK ADC1_COMP_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-ADC1_COMP_IRQHandler
- B ADC1_COMP_IRQHandler
-
-
- PUBWEAK TIM1_BRK_UP_TRG_COM_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM1_BRK_UP_TRG_COM_IRQHandler
- B TIM1_BRK_UP_TRG_COM_IRQHandler
-
-
- PUBWEAK TIM1_CC_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM1_CC_IRQHandler
- B TIM1_CC_IRQHandler
-
-
- PUBWEAK TIM2_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM2_IRQHandler
- B TIM2_IRQHandler
-
-
- PUBWEAK TIM3_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM3_IRQHandler
- B TIM3_IRQHandler
-
-
- PUBWEAK TIM6_DAC_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM6_DAC_IRQHandler
- B TIM6_DAC_IRQHandler
-
-
- PUBWEAK TIM14_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM14_IRQHandler
- B TIM14_IRQHandler
-
-
- PUBWEAK TIM15_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM15_IRQHandler
- B TIM15_IRQHandler
-
-
- PUBWEAK TIM16_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM16_IRQHandler
- B TIM16_IRQHandler
-
-
- PUBWEAK TIM17_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM17_IRQHandler
- B TIM17_IRQHandler
-
-
- PUBWEAK I2C1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-I2C1_IRQHandler
- B I2C1_IRQHandler
-
-
- PUBWEAK I2C2_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-I2C2_IRQHandler
- B I2C2_IRQHandler
-
-
- PUBWEAK SPI1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SPI1_IRQHandler
- B SPI1_IRQHandler
-
-
- PUBWEAK SPI2_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SPI2_IRQHandler
- B SPI2_IRQHandler
-
-
- PUBWEAK USART1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-USART1_IRQHandler
- B USART1_IRQHandler
-
-
- PUBWEAK USART2_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-USART2_IRQHandler
- B USART2_IRQHandler
-
-
- PUBWEAK CEC_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-CEC_IRQHandler
- B CEC_IRQHandler
-
- END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/iar/startup_stm32f072.s b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/iar/startup_stm32f072.s
deleted file mode 100644
index c01281d93c043f9fc873a58a832b2ada95ed8384..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/iar/startup_stm32f072.s
+++ /dev/null
@@ -1,346 +0,0 @@
-;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
-;* File Name : startup_stm32f072.s
-;* Author : MCD Appl&ication Team
-;* Version : V1.3.1
-;* Date : 17-January-2014
-;* Description : STM32F072 Devices Devices vector table for
-;* EWARM toolchain.
-;* This module performs:
-;* - Set the initial SP
-;* - Set the initial PC == iar_program_start,
-;* - Set the vector table entries with the exceptions ISR
-;* address.
-;* After Reset the Cortex-M0 processor is in Thread mode,
-;* priority is Privileged, and the Stack is set to Main.
-;*******************************************************************************
-; @attention
-;
-; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-; You may not use this file except in compliance with the License.
-; You may obtain a copy of the License at:
-;
-; http://www.st.com/software_license_agreement_liberty_v2
-;
-; Unless required by applicable law or agreed to in writing, software
-; distributed under the License is distributed on an "AS IS" BASIS,
-; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-; See the License for the specific language governing permissions and
-; limitations under the License.
-;
-;*******************************************************************************
-;
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
- MODULE ?cstartup
-
- ;; Forward declaration of sections.
- SECTION CSTACK:DATA:NOROOT(3)
-
- SECTION .intvec:CODE:NOROOT(2)
-
- EXTERN __iar_program_start
- EXTERN SystemInit
- PUBLIC __vector_table
-
- DATA
-__vector_table
- DCD sfe(CSTACK)
- DCD Reset_Handler ; Reset Handler
-
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
-
- ; External Interrupts
- DCD WWDG_IRQHandler ; Window Watchdog
- DCD PVD_VDDIO2_IRQHandler ; PVD and VDDIO2 through EXTI Line detect
- DCD RTC_IRQHandler ; RTC through EXTI Line
- DCD FLASH_IRQHandler ; FLASH
- DCD RCC_CRS_IRQHandler ; RCC and CRS
- DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1
- DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3
- DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15
- DCD TSC_IRQHandler ; TS
- DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
- DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3
- DCD DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channel 4, Channel 5, Channel 6 and Channel 7
- DCD ADC1_COMP_IRQHandler ; ADC1, COMP1 and COMP2
- DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
- DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
- DCD TIM2_IRQHandler ; TIM2
- DCD TIM3_IRQHandler ; TIM3
- DCD TIM6_DAC_IRQHandler ; TIM6 and DAC
- DCD TIM7_IRQHandler ; TIM7
- DCD TIM14_IRQHandler ; TIM14
- DCD TIM15_IRQHandler ; TIM15
- DCD TIM16_IRQHandler ; TIM16
- DCD TIM17_IRQHandler ; TIM17
- DCD I2C1_IRQHandler ; I2C1
- DCD I2C2_IRQHandler ; I2C2
- DCD SPI1_IRQHandler ; SPI1
- DCD SPI2_IRQHandler ; SPI2
- DCD USART1_IRQHandler ; USART1
- DCD USART2_IRQHandler ; USART2
- DCD USART3_4_IRQHandler ; USART3 and USART4
- DCD CEC_CAN_IRQHandler ; CEC and CAN
- DCD USB_IRQHandler ; USB
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
- THUMB
-
- PUBWEAK Reset_Handler
- SECTION .text:CODE:REORDER(2)
-Reset_Handler
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__iar_program_start
- BX R0
-
- PUBWEAK NMI_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-NMI_Handler
- B NMI_Handler
-
-
- PUBWEAK HardFault_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-HardFault_Handler
- B HardFault_Handler
-
-
- PUBWEAK SVC_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SVC_Handler
- B SVC_Handler
-
-
- PUBWEAK PendSV_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-PendSV_Handler
- B PendSV_Handler
-
-
- PUBWEAK SysTick_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SysTick_Handler
- B SysTick_Handler
-
-
- PUBWEAK WWDG_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-WWDG_IRQHandler
- B WWDG_IRQHandler
-
-
- PUBWEAK PVD_VDDIO2_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-PVD_VDDIO2_IRQHandler
- B PVD_VDDIO2_IRQHandler
-
-
- PUBWEAK RTC_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-RTC_IRQHandler
- B RTC_IRQHandler
-
-
- PUBWEAK FLASH_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-FLASH_IRQHandler
- B FLASH_IRQHandler
-
-
- PUBWEAK RCC_CRS_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-RCC_CRS_IRQHandler
- B RCC_CRS_IRQHandler
-
-
- PUBWEAK EXTI0_1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI0_1_IRQHandler
- B EXTI0_1_IRQHandler
-
-
- PUBWEAK EXTI2_3_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI2_3_IRQHandler
- B EXTI2_3_IRQHandler
-
-
- PUBWEAK EXTI4_15_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI4_15_IRQHandler
- B EXTI4_15_IRQHandler
-
-
- PUBWEAK TSC_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TSC_IRQHandler
- B TSC_IRQHandler
-
-
- PUBWEAK DMA1_Channel1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel1_IRQHandler
- B DMA1_Channel1_IRQHandler
-
-
- PUBWEAK DMA1_Channel2_3_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel2_3_IRQHandler
- B DMA1_Channel2_3_IRQHandler
-
-
- PUBWEAK DMA1_Channel4_5_6_7_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel4_5_6_7_IRQHandler
- B DMA1_Channel4_5_6_7_IRQHandler
-
-
- PUBWEAK ADC1_COMP_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-ADC1_COMP_IRQHandler
- B ADC1_COMP_IRQHandler
-
-
- PUBWEAK TIM1_BRK_UP_TRG_COM_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM1_BRK_UP_TRG_COM_IRQHandler
- B TIM1_BRK_UP_TRG_COM_IRQHandler
-
-
- PUBWEAK TIM1_CC_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM1_CC_IRQHandler
- B TIM1_CC_IRQHandler
-
-
- PUBWEAK TIM2_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM2_IRQHandler
- B TIM2_IRQHandler
-
-
- PUBWEAK TIM3_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM3_IRQHandler
- B TIM3_IRQHandler
-
-
- PUBWEAK TIM6_DAC_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM6_DAC_IRQHandler
- B TIM6_DAC_IRQHandler
-
- PUBWEAK TIM7_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM7_IRQHandler
- B TIM7_IRQHandler
-
- PUBWEAK TIM14_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM14_IRQHandler
- B TIM14_IRQHandler
-
-
- PUBWEAK TIM15_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM15_IRQHandler
- B TIM15_IRQHandler
-
-
- PUBWEAK TIM16_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM16_IRQHandler
- B TIM16_IRQHandler
-
-
- PUBWEAK TIM17_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM17_IRQHandler
- B TIM17_IRQHandler
-
-
- PUBWEAK I2C1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-I2C1_IRQHandler
- B I2C1_IRQHandler
-
-
- PUBWEAK I2C2_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-I2C2_IRQHandler
- B I2C2_IRQHandler
-
-
- PUBWEAK SPI1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SPI1_IRQHandler
- B SPI1_IRQHandler
-
-
- PUBWEAK SPI2_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SPI2_IRQHandler
- B SPI2_IRQHandler
-
-
- PUBWEAK USART1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-USART1_IRQHandler
- B USART1_IRQHandler
-
-
- PUBWEAK USART2_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-USART2_IRQHandler
- B USART2_IRQHandler
-
-
- PUBWEAK USART3_4_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-USART3_4_IRQHandler
- B USART3_4_IRQHandler
-
-
- PUBWEAK CEC_CAN_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-CEC_CAN_IRQHandler
- B CEC_CAN_IRQHandler
-
- PUBWEAK USB_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-USB_IRQHandler
- B USB_IRQHandler
-
- END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/iar/startup_stm32f0xx.s b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/iar/startup_stm32f0xx.s
deleted file mode 100644
index 27d799f028a2079baf0d7ff4106de5a44f12c72f..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/iar/startup_stm32f0xx.s
+++ /dev/null
@@ -1,333 +0,0 @@
-;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
-;* File Name : startup_stm32f0xx.s
-;* Author : MCD Application Team
-;* Version : V1.3.1
-;* Date : 17-January-2014
-;* Description : STM32F051 devices vector table for EWARM toolchain.
-;* This module performs:
-;* - Set the initial SP
-;* - Set the initial PC == iar_program_start,
-;* - Set the vector table entries with the exceptions ISR
-;* address
-;* - Configure the system clock
-;* - Branches to main in the C library (which eventually
-;* calls main()).
-;* After Reset the Cortex-M0 processor is in Thread mode,
-;* priority is Privileged, and the Stack is set to Main.
-;*******************************************************************************
-; @attention
-;
-; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-; You may not use this file except in compliance with the License.
-; You may obtain a copy of the License at:
-;
-; http://www.st.com/software_license_agreement_liberty_v2
-;
-; Unless required by applicable law or agreed to in writing, software
-; distributed under the License is distributed on an "AS IS" BASIS,
-; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-; See the License for the specific language governing permissions and
-; limitations under the License.
-;
-;*******************************************************************************
-;
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
- MODULE ?cstartup
-
- ;; Forward declaration of sections.
- SECTION CSTACK:DATA:NOROOT(3)
-
- SECTION .intvec:CODE:NOROOT(2)
-
- EXTERN __iar_program_start
- EXTERN SystemInit
- PUBLIC __vector_table
-
- DATA
-__vector_table
- DCD sfe(CSTACK)
- DCD Reset_Handler ; Reset Handler
-
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
-
- ; External Interrupts
- DCD WWDG_IRQHandler ; Window Watchdog
- DCD PVD_IRQHandler ; PVD through EXTI Line detect
- DCD RTC_IRQHandler ; RTC through EXTI Line
- DCD FLASH_IRQHandler ; FLASH
- DCD RCC_IRQHandler ; RCC
- DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1
- DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3
- DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15
- DCD TS_IRQHandler ; TS
- DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
- DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3
- DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5
- DCD ADC1_COMP_IRQHandler ; ADC1, COMP1 and COMP2
- DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
- DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
- DCD TIM2_IRQHandler ; TIM2
- DCD TIM3_IRQHandler ; TIM3
- DCD TIM6_DAC_IRQHandler ; TIM6 and DAC
- DCD 0 ; Reserved
- DCD TIM14_IRQHandler ; TIM14
- DCD TIM15_IRQHandler ; TIM15
- DCD TIM16_IRQHandler ; TIM16
- DCD TIM17_IRQHandler ; TIM17
- DCD I2C1_IRQHandler ; I2C1
- DCD I2C2_IRQHandler ; I2C2
- DCD SPI1_IRQHandler ; SPI1
- DCD SPI2_IRQHandler ; SPI2
- DCD USART1_IRQHandler ; USART1
- DCD USART2_IRQHandler ; USART2
- DCD 0 ; Reserved
- DCD CEC_IRQHandler ; CEC
- DCD 0 ; Reserved
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
- THUMB
-
- PUBWEAK Reset_Handler
- SECTION .text:CODE:REORDER(2)
-Reset_Handler
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__iar_program_start
- BX R0
-
- PUBWEAK NMI_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-NMI_Handler
- B NMI_Handler
-
-
- PUBWEAK HardFault_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-HardFault_Handler
- B HardFault_Handler
-
-
- PUBWEAK SVC_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SVC_Handler
- B SVC_Handler
-
-
- PUBWEAK PendSV_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-PendSV_Handler
- B PendSV_Handler
-
-
- PUBWEAK SysTick_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SysTick_Handler
- B SysTick_Handler
-
-
- PUBWEAK WWDG_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-WWDG_IRQHandler
- B WWDG_IRQHandler
-
-
- PUBWEAK PVD_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-PVD_IRQHandler
- B PVD_IRQHandler
-
-
- PUBWEAK RTC_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-RTC_IRQHandler
- B RTC_IRQHandler
-
-
- PUBWEAK FLASH_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-FLASH_IRQHandler
- B FLASH_IRQHandler
-
-
- PUBWEAK RCC_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-RCC_IRQHandler
- B RCC_IRQHandler
-
-
- PUBWEAK EXTI0_1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI0_1_IRQHandler
- B EXTI0_1_IRQHandler
-
-
- PUBWEAK EXTI2_3_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI2_3_IRQHandler
- B EXTI2_3_IRQHandler
-
-
- PUBWEAK EXTI4_15_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI4_15_IRQHandler
- B EXTI4_15_IRQHandler
-
-
- PUBWEAK TS_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TS_IRQHandler
- B TS_IRQHandler
-
-
- PUBWEAK DMA1_Channel1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel1_IRQHandler
- B DMA1_Channel1_IRQHandler
-
-
- PUBWEAK DMA1_Channel2_3_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel2_3_IRQHandler
- B DMA1_Channel2_3_IRQHandler
-
-
- PUBWEAK DMA1_Channel4_5_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel4_5_IRQHandler
- B DMA1_Channel4_5_IRQHandler
-
-
- PUBWEAK ADC1_COMP_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-ADC1_COMP_IRQHandler
- B ADC1_COMP_IRQHandler
-
-
- PUBWEAK TIM1_BRK_UP_TRG_COM_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM1_BRK_UP_TRG_COM_IRQHandler
- B TIM1_BRK_UP_TRG_COM_IRQHandler
-
-
- PUBWEAK TIM1_CC_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM1_CC_IRQHandler
- B TIM1_CC_IRQHandler
-
-
- PUBWEAK TIM2_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM2_IRQHandler
- B TIM2_IRQHandler
-
-
- PUBWEAK TIM3_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM3_IRQHandler
- B TIM3_IRQHandler
-
-
- PUBWEAK TIM6_DAC_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM6_DAC_IRQHandler
- B TIM6_DAC_IRQHandler
-
-
- PUBWEAK TIM14_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM14_IRQHandler
- B TIM14_IRQHandler
-
-
- PUBWEAK TIM15_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM15_IRQHandler
- B TIM15_IRQHandler
-
-
- PUBWEAK TIM16_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM16_IRQHandler
- B TIM16_IRQHandler
-
-
- PUBWEAK TIM17_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM17_IRQHandler
- B TIM17_IRQHandler
-
-
- PUBWEAK I2C1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-I2C1_IRQHandler
- B I2C1_IRQHandler
-
-
- PUBWEAK I2C2_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-I2C2_IRQHandler
- B I2C2_IRQHandler
-
-
- PUBWEAK SPI1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SPI1_IRQHandler
- B SPI1_IRQHandler
-
-
- PUBWEAK SPI2_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SPI2_IRQHandler
- B SPI2_IRQHandler
-
-
- PUBWEAK USART1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-USART1_IRQHandler
- B USART1_IRQHandler
-
-
- PUBWEAK USART2_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-USART2_IRQHandler
- B USART2_IRQHandler
-
-
- PUBWEAK CEC_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-CEC_IRQHandler
- B CEC_IRQHandler
-
- END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/iar/startup_stm32f0xx_ld.s b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/iar/startup_stm32f0xx_ld.s
deleted file mode 100644
index 595fa8df14326138292be81b487132f9bcf376b4..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/iar/startup_stm32f0xx_ld.s
+++ /dev/null
@@ -1,288 +0,0 @@
-;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
-;* File Name : startup_stm32f0xx_ld.s
-;* Author : MCD Application Team
-;* Version : V1.3.1
-;* Date : 17-January-2014
-;* Description : STM32F031 devices vector table for EWARM toolchain.
-;* This module performs:
-;* - Set the initial SP
-;* - Set the initial PC == iar_program_start,
-;* - Set the vector table entries with the exceptions ISR
-;* address
-;* - Configure the system clock
-;* - Branches to main in the C library (which eventually
-;* calls main()).
-;* After Reset the Cortex-M0 processor is in Thread mode,
-;* priority is Privileged, and the Stack is set to Main.
-;*******************************************************************************
-; @attention
-;
-; Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
-; You may not use this file except in compliance with the License.
-; You may obtain a copy of the License at:
-;
-; http://www.st.com/software_license_agreement_liberty_v2
-;
-; Unless required by applicable law or agreed to in writing, software
-; distributed under the License is distributed on an "AS IS" BASIS,
-; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-; See the License for the specific language governing permissions and
-; limitations under the License.
-;
-;*******************************************************************************
-;
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
- MODULE ?cstartup
-
- ;; Forward declaration of sections.
- SECTION CSTACK:DATA:NOROOT(3)
-
- SECTION .intvec:CODE:NOROOT(2)
-
- EXTERN __iar_program_start
- EXTERN SystemInit
- PUBLIC __vector_table
-
- DATA
-__vector_table
- DCD sfe(CSTACK)
- DCD Reset_Handler ; Reset Handler
-
- DCD NMI_Handler ; NMI Handler
- DCD HardFault_Handler ; Hard Fault Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SVC_Handler ; SVCall Handler
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD PendSV_Handler ; PendSV Handler
- DCD SysTick_Handler ; SysTick Handler
-
- ; External Interrupts
- DCD WWDG_IRQHandler ; Window Watchdog
- DCD PVD_IRQHandler ; PVD through EXTI Line detect
- DCD RTC_IRQHandler ; RTC through EXTI Line
- DCD FLASH_IRQHandler ; FLASH
- DCD RCC_IRQHandler ; RCC
- DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1
- DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3
- DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15
- DCD 0 ; Reserved
- DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
- DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3
- DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5
- DCD ADC1_IRQHandler ; ADC1
- DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
- DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
- DCD TIM2_IRQHandler ; TIM2
- DCD TIM3_IRQHandler ; TIM3
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD TIM14_IRQHandler ; TIM14
- DCD 0 ; Reserved
- DCD TIM16_IRQHandler ; TIM16
- DCD TIM17_IRQHandler ; TIM17
- DCD I2C1_IRQHandler ; I2C1
- DCD 0 ; Reserved
- DCD SPI1_IRQHandler ; SPI1
- DCD 0 ; Reserved
- DCD USART1_IRQHandler ; USART1
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
- THUMB
-
- PUBWEAK Reset_Handler
- SECTION .text:CODE:REORDER(2)
-Reset_Handler
- LDR R0, =SystemInit
- BLX R0
- LDR R0, =__iar_program_start
- BX R0
-
- PUBWEAK NMI_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-NMI_Handler
- B NMI_Handler
-
-
- PUBWEAK HardFault_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-HardFault_Handler
- B HardFault_Handler
-
-
- PUBWEAK SVC_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SVC_Handler
- B SVC_Handler
-
-
- PUBWEAK PendSV_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-PendSV_Handler
- B PendSV_Handler
-
-
- PUBWEAK SysTick_Handler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SysTick_Handler
- B SysTick_Handler
-
-
- PUBWEAK WWDG_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-WWDG_IRQHandler
- B WWDG_IRQHandler
-
-
- PUBWEAK PVD_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-PVD_IRQHandler
- B PVD_IRQHandler
-
-
- PUBWEAK RTC_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-RTC_IRQHandler
- B RTC_IRQHandler
-
-
- PUBWEAK FLASH_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-FLASH_IRQHandler
- B FLASH_IRQHandler
-
-
- PUBWEAK RCC_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-RCC_IRQHandler
- B RCC_IRQHandler
-
-
- PUBWEAK EXTI0_1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI0_1_IRQHandler
- B EXTI0_1_IRQHandler
-
-
- PUBWEAK EXTI2_3_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI2_3_IRQHandler
- B EXTI2_3_IRQHandler
-
-
- PUBWEAK EXTI4_15_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI4_15_IRQHandler
- B EXTI4_15_IRQHandler
-
-
- PUBWEAK DMA1_Channel1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel1_IRQHandler
- B DMA1_Channel1_IRQHandler
-
-
- PUBWEAK DMA1_Channel2_3_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel2_3_IRQHandler
- B DMA1_Channel2_3_IRQHandler
-
-
- PUBWEAK DMA1_Channel4_5_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel4_5_IRQHandler
- B DMA1_Channel4_5_IRQHandler
-
-
- PUBWEAK ADC1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-ADC1_IRQHandler
- B ADC1_IRQHandler
-
-
- PUBWEAK TIM1_BRK_UP_TRG_COM_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM1_BRK_UP_TRG_COM_IRQHandler
- B TIM1_BRK_UP_TRG_COM_IRQHandler
-
-
- PUBWEAK TIM1_CC_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM1_CC_IRQHandler
- B TIM1_CC_IRQHandler
-
-
- PUBWEAK TIM2_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM2_IRQHandler
- B TIM2_IRQHandler
-
-
- PUBWEAK TIM3_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM3_IRQHandler
- B TIM3_IRQHandler
-
-
- PUBWEAK TIM14_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM14_IRQHandler
- B TIM14_IRQHandler
-
-
- PUBWEAK TIM16_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM16_IRQHandler
- B TIM16_IRQHandler
-
-
- PUBWEAK TIM17_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-TIM17_IRQHandler
- B TIM17_IRQHandler
-
-
- PUBWEAK I2C1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-I2C1_IRQHandler
- B I2C1_IRQHandler
-
-
- PUBWEAK SPI1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-SPI1_IRQHandler
- B SPI1_IRQHandler
-
-
- PUBWEAK USART1_IRQHandler
- SECTION .text:CODE:NOROOT:REORDER(1)
-USART1_IRQHandler
- B USART1_IRQHandler
-
-
- END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/system_stm32f0xx.c b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/system_stm32f0xx.c
deleted file mode 100644
index e05ebe27552302880e1f44f1c8f4825a63f35470..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Device/ST/STM32F0xx/Source/Templates/system_stm32f0xx.c
+++ /dev/null
@@ -1,358 +0,0 @@
-/**
- ******************************************************************************
- * @file system_stm32f0xx.c
- * @author MCD Application Team
- * @version V1.3.1
- * @date 17-January-2014
- * @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File.
- * This file contains the system clock configuration for STM32F0xx devices,
- * and is generated by the clock configuration tool
- * STM32F0xx_Clock_Configuration_V1.0.0.xls
- *
- * 1. This file provides two functions and one global variable to be called from
- * user application:
- * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
- * and Divider factors, AHB/APBx prescalers and Flash settings),
- * depending on the configuration made in the clock xls tool.
- * This function is called at startup just after reset and
- * before branch to main program. This call is made inside
- * the "startup_stm32f0xx.s" file.
- *
- * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
- * by the user application to setup the SysTick
- * timer or configure other parameters.
- *
- * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
- * be called whenever the core clock is changed
- * during program execution.
- *
- * 2. After each device reset the HSI (8 MHz Range) is used as system clock source.
- * Then SystemInit() function is called, in "startup_stm32f0xx.s" file, to
- * configure the system clock before to branch to main program.
- *
- * 3. If the system clock source selected by user fails to startup, the SystemInit()
- * function will do nothing and HSI still used as system clock source. User can
- * add some code to deal with this issue inside the SetSysClock() function.
- *
- * 4. The default value of HSE crystal is set to 8MHz, refer to "HSE_VALUE" define
- * in "stm32f0xx.h" file. When HSE is used as system clock source, directly or
- * through PLL, and you are using different crystal you have to adapt the HSE
- * value to your own configuration.
- *
- * 5. This file configures the system clock as follows:
- *=============================================================================
- * System Clock Configuration
- *=============================================================================
- * System Clock source | PLL(HSE)
- *-----------------------------------------------------------------------------
- * SYSCLK | 48000000 Hz
- *-----------------------------------------------------------------------------
- * HCLK | 48000000 Hz
- *-----------------------------------------------------------------------------
- * AHB Prescaler | 1
- *-----------------------------------------------------------------------------
- * APB1 Prescaler | 1
- *-----------------------------------------------------------------------------
- * APB2 Prescaler | 1
- *-----------------------------------------------------------------------------
- * HSE Frequency | 8000000 Hz
- *-----------------------------------------------------------------------------
- * PLL MUL | 6
- *-----------------------------------------------------------------------------
- * VDD | 3.3 V
- *-----------------------------------------------------------------------------
- * Flash Latency | 1 WS
- *-----------------------------------------------------------------------------
- *=============================================================================
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/** @addtogroup CMSIS
- * @{
- */
-
-/** @addtogroup stm32f0xx_system
- * @{
- */
-
-/** @addtogroup STM32F0xx_System_Private_Includes
- * @{
- */
-
-#include "stm32f0xx.h"
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F0xx_System_Private_TypesDefinitions
- * @{
- */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F0xx_System_Private_Defines
- * @{
- */
-/**
- * @}
- */
-
-/** @addtogroup STM32F0xx_System_Private_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F0xx_System_Private_Variables
- * @{
- */
-uint32_t SystemCoreClock = 48000000;
-__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F0xx_System_Private_FunctionPrototypes
- * @{
- */
-
-static void SetSysClock(void);
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F0xx_System_Private_Functions
- * @{
- */
-
-/**
- * @brief Setup the microcontroller system.
- * Initialize the Embedded Flash Interface, the PLL and update the
- * SystemCoreClock variable.
- * @param None
- * @retval None
- */
-void SystemInit (void)
-{
- /* Set HSION bit */
- RCC->CR |= (uint32_t)0x00000001;
-
-#if defined (STM32F031) || defined (STM32F072) || defined (STM32F042)
- /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */
- RCC->CFGR &= (uint32_t)0xF8FFB80C;
-#else
- /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, MCOSEL[2:0], MCOPRE[2:0] and PLLNODIV bits */
- RCC->CFGR &= (uint32_t)0x08FFB80C;
-#endif /* STM32F031*/
-
- /* Reset HSEON, CSSON and PLLON bits */
- RCC->CR &= (uint32_t)0xFEF6FFFF;
-
- /* Reset HSEBYP bit */
- RCC->CR &= (uint32_t)0xFFFBFFFF;
-
- /* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
- RCC->CFGR &= (uint32_t)0xFFC0FFFF;
-
- /* Reset PREDIV1[3:0] bits */
- RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
-
- /* Reset USARTSW[1:0], I2CSW, CECSW and ADCSW bits */
- RCC->CFGR3 &= (uint32_t)0xFFFFFEAC;
-
- /* Reset HSI14 bit */
- RCC->CR2 &= (uint32_t)0xFFFFFFFE;
-
- /* Disable all interrupts */
- RCC->CIR = 0x00000000;
-
- /* Configure the System clock frequency, AHB/APBx prescalers and Flash settings */
- SetSysClock();
-}
-
-/**
- * @brief Update SystemCoreClock according to Clock Register Values
- * The SystemCoreClock variable contains the core clock (HCLK), it can
- * be used by the user application to setup the SysTick timer or configure
- * other parameters.
- *
- * @note Each time the core clock (HCLK) changes, this function must be called
- * to update SystemCoreClock variable value. Otherwise, any configuration
- * based on this variable will be incorrect.
- *
- * @note - The system frequency computed by this function is not the real
- * frequency in the chip. It is calculated based on the predefined
- * constant and the selected clock source:
- *
- * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
- *
- * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
- *
- * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
- * or HSI_VALUE(*) multiplied/divided by the PLL factors.
- *
- * (*) HSI_VALUE is a constant defined in stm32f0xx.h file (default value
- * 8 MHz) but the real value may vary depending on the variations
- * in voltage and temperature.
- *
- * (**) HSE_VALUE is a constant defined in stm32f0xx.h file (default value
- * 8 MHz), user has to ensure that HSE_VALUE is same as the real
- * frequency of the crystal used. Otherwise, this function may
- * have wrong result.
- *
- * - The result of this function could be not correct when using fractional
- * value for HSE crystal.
- * @param None
- * @retval None
- */
-void SystemCoreClockUpdate (void)
-{
- uint32_t tmp = 0, pllmull = 0, pllsource = 0, prediv1factor = 0;
-
- /* Get SYSCLK source -------------------------------------------------------*/
- tmp = RCC->CFGR & RCC_CFGR_SWS;
-
- switch (tmp)
- {
- case 0x00: /* HSI used as system clock */
- SystemCoreClock = HSI_VALUE;
- break;
- case 0x04: /* HSE used as system clock */
- SystemCoreClock = HSE_VALUE;
- break;
- case 0x08: /* PLL used as system clock */
- /* Get PLL clock source and multiplication factor ----------------------*/
- pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
- pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
- pllmull = ( pllmull >> 18) + 2;
-
- if (pllsource == 0x00)
- {
- /* HSI oscillator clock divided by 2 selected as PLL clock entry */
- SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
- }
- else
- {
- prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
- /* HSE oscillator clock selected as PREDIV1 clock entry */
- SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
- }
- break;
- default: /* HSI used as system clock */
- SystemCoreClock = HSI_VALUE;
- break;
- }
- /* Compute HCLK clock frequency ----------------*/
- /* Get HCLK prescaler */
- tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
- /* HCLK clock frequency */
- SystemCoreClock >>= tmp;
-}
-
-/**
- * @brief Configures the System clock frequency, AHB/APBx prescalers and Flash
- * settings.
- * @note This function should be called only once the RCC clock configuration
- * is reset to the default reset state (done in SystemInit() function).
- * @param None
- * @retval None
- */
-static void SetSysClock(void)
-{
- __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
-
- /* SYSCLK, HCLK, PCLK configuration ----------------------------------------*/
- /* Enable HSE */
- RCC->CR |= ((uint32_t)RCC_CR_HSEON);
-
- /* Wait till HSE is ready and if Time out is reached exit */
- do
- {
- HSEStatus = RCC->CR & RCC_CR_HSERDY;
- StartUpCounter++;
- } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
- if ((RCC->CR & RCC_CR_HSERDY) != RESET)
- {
- HSEStatus = (uint32_t)0x01;
- }
- else
- {
- HSEStatus = (uint32_t)0x00;
- }
-
- if (HSEStatus == (uint32_t)0x01)
- {
- /* Enable Prefetch Buffer and set Flash Latency */
- FLASH->ACR = FLASH_ACR_PRFTBE | FLASH_ACR_LATENCY;
-
- /* HCLK = SYSCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-
- /* PCLK = HCLK */
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE_DIV1;
-
- /* PLL configuration = HSE * 6 = 48 MHz */
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
- RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL6);
-
- /* Enable PLL */
- RCC->CR |= RCC_CR_PLLON;
-
- /* Wait till PLL is ready */
- while((RCC->CR & RCC_CR_PLLRDY) == 0)
- {
- }
-
- /* Select PLL as system clock source */
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
- RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
-
- /* Wait till PLL is used as system clock source */
- while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)
- {
- }
- }
- else
- { /* If HSE fails to start-up, the application will have wrong clock
- configuration. User can add here some code to deal with this error */
- }
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Include/arm_common_tables.h b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Include/arm_common_tables.h
deleted file mode 100644
index 7a59b5923e9edcfc684691f70cb06360d20ddfff..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Include/arm_common_tables.h
+++ /dev/null
@@ -1,93 +0,0 @@
-/* ----------------------------------------------------------------------
-* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
-*
-* $Date: 17. January 2013
-* $Revision: V1.4.1
-*
-* Project: CMSIS DSP Library
-* Title: arm_common_tables.h
-*
-* Description: This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
-*
-* Target Processor: Cortex-M4/Cortex-M3
-*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions
-* are met:
-* - Redistributions of source code must retain the above copyright
-* notice, this list of conditions and the following disclaimer.
-* - Redistributions in binary form must reproduce the above copyright
-* notice, this list of conditions and the following disclaimer in
-* the documentation and/or other materials provided with the
-* distribution.
-* - Neither the name of ARM LIMITED nor the names of its contributors
-* may be used to endorse or promote products derived from this
-* software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.
-* -------------------------------------------------------------------- */
-
-#ifndef _ARM_COMMON_TABLES_H
-#define _ARM_COMMON_TABLES_H
-
-#include "arm_math.h"
-
-extern const uint16_t armBitRevTable[1024];
-extern const q15_t armRecipTableQ15[64];
-extern const q31_t armRecipTableQ31[64];
-extern const q31_t realCoefAQ31[1024];
-extern const q31_t realCoefBQ31[1024];
-extern const float32_t twiddleCoef_16[32];
-extern const float32_t twiddleCoef_32[64];
-extern const float32_t twiddleCoef_64[128];
-extern const float32_t twiddleCoef_128[256];
-extern const float32_t twiddleCoef_256[512];
-extern const float32_t twiddleCoef_512[1024];
-extern const float32_t twiddleCoef_1024[2048];
-extern const float32_t twiddleCoef_2048[4096];
-extern const float32_t twiddleCoef_4096[8192];
-#define twiddleCoef twiddleCoef_4096
-extern const q31_t twiddleCoefQ31[6144];
-extern const q15_t twiddleCoefQ15[6144];
-extern const float32_t twiddleCoef_rfft_32[32];
-extern const float32_t twiddleCoef_rfft_64[64];
-extern const float32_t twiddleCoef_rfft_128[128];
-extern const float32_t twiddleCoef_rfft_256[256];
-extern const float32_t twiddleCoef_rfft_512[512];
-extern const float32_t twiddleCoef_rfft_1024[1024];
-extern const float32_t twiddleCoef_rfft_2048[2048];
-extern const float32_t twiddleCoef_rfft_4096[4096];
-
-
-#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 )
-#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 )
-#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 )
-#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 )
-#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 )
-#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 )
-#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)
-#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)
-#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)
-
-extern const uint16_t armBitRevIndexTable16[ARMBITREVINDEXTABLE__16_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable32[ARMBITREVINDEXTABLE__32_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable64[ARMBITREVINDEXTABLE__64_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable128[ARMBITREVINDEXTABLE_128_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable256[ARMBITREVINDEXTABLE_256_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable512[ARMBITREVINDEXTABLE_512_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable1024[ARMBITREVINDEXTABLE1024_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable2048[ARMBITREVINDEXTABLE2048_TABLE_LENGTH];
-extern const uint16_t armBitRevIndexTable4096[ARMBITREVINDEXTABLE4096_TABLE_LENGTH];
-
-#endif /* ARM_COMMON_TABLES_H */
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Include/arm_const_structs.h b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Include/arm_const_structs.h
deleted file mode 100644
index 8d7fac0f04e7b971161600376203961b9f9395b7..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Include/arm_const_structs.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/* ----------------------------------------------------------------------
-* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
-*
-* $Date: 17. January 2013
-* $Revision: V1.4.1
-*
-* Project: CMSIS DSP Library
-* Title: arm_const_structs.h
-*
-* Description: This file has constant structs that are initialized for
-* user convenience. For example, some can be given as
-* arguments to the arm_cfft_f32() function.
-*
-* Target Processor: Cortex-M4/Cortex-M3
-*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions
-* are met:
-* - Redistributions of source code must retain the above copyright
-* notice, this list of conditions and the following disclaimer.
-* - Redistributions in binary form must reproduce the above copyright
-* notice, this list of conditions and the following disclaimer in
-* the documentation and/or other materials provided with the
-* distribution.
-* - Neither the name of ARM LIMITED nor the names of its contributors
-* may be used to endorse or promote products derived from this
-* software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.
-* -------------------------------------------------------------------- */
-
-#ifndef _ARM_CONST_STRUCTS_H
-#define _ARM_CONST_STRUCTS_H
-
-#include "arm_math.h"
-#include "arm_common_tables.h"
-
- const arm_cfft_instance_f32 arm_cfft_sR_f32_len16 = {
- 16, twiddleCoef_16, armBitRevIndexTable16, ARMBITREVINDEXTABLE__16_TABLE_LENGTH
- };
-
- const arm_cfft_instance_f32 arm_cfft_sR_f32_len32 = {
- 32, twiddleCoef_32, armBitRevIndexTable32, ARMBITREVINDEXTABLE__32_TABLE_LENGTH
- };
-
- const arm_cfft_instance_f32 arm_cfft_sR_f32_len64 = {
- 64, twiddleCoef_64, armBitRevIndexTable64, ARMBITREVINDEXTABLE__64_TABLE_LENGTH
- };
-
- const arm_cfft_instance_f32 arm_cfft_sR_f32_len128 = {
- 128, twiddleCoef_128, armBitRevIndexTable128, ARMBITREVINDEXTABLE_128_TABLE_LENGTH
- };
-
- const arm_cfft_instance_f32 arm_cfft_sR_f32_len256 = {
- 256, twiddleCoef_256, armBitRevIndexTable256, ARMBITREVINDEXTABLE_256_TABLE_LENGTH
- };
-
- const arm_cfft_instance_f32 arm_cfft_sR_f32_len512 = {
- 512, twiddleCoef_512, armBitRevIndexTable512, ARMBITREVINDEXTABLE_512_TABLE_LENGTH
- };
-
- const arm_cfft_instance_f32 arm_cfft_sR_f32_len1024 = {
- 1024, twiddleCoef_1024, armBitRevIndexTable1024, ARMBITREVINDEXTABLE1024_TABLE_LENGTH
- };
-
- const arm_cfft_instance_f32 arm_cfft_sR_f32_len2048 = {
- 2048, twiddleCoef_2048, armBitRevIndexTable2048, ARMBITREVINDEXTABLE2048_TABLE_LENGTH
- };
-
- const arm_cfft_instance_f32 arm_cfft_sR_f32_len4096 = {
- 4096, twiddleCoef_4096, armBitRevIndexTable4096, ARMBITREVINDEXTABLE4096_TABLE_LENGTH
- };
-
-#endif
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Include/arm_math.h b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Include/arm_math.h
deleted file mode 100644
index 65304c127d6c5ad0a49cab6b0c30be220035a16a..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Include/arm_math.h
+++ /dev/null
@@ -1,7306 +0,0 @@
-/* ----------------------------------------------------------------------
-* Copyright (C) 2010-2013 ARM Limited. All rights reserved.
-*
-* $Date: 17. January 2013
-* $Revision: V1.4.1
-*
-* Project: CMSIS DSP Library
-* Title: arm_math.h
-*
-* Description: Public header file for CMSIS DSP Library
-*
-* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
-*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions
-* are met:
-* - Redistributions of source code must retain the above copyright
-* notice, this list of conditions and the following disclaimer.
-* - Redistributions in binary form must reproduce the above copyright
-* notice, this list of conditions and the following disclaimer in
-* the documentation and/or other materials provided with the
-* distribution.
-* - Neither the name of ARM LIMITED nor the names of its contributors
-* may be used to endorse or promote products derived from this
-* software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-* POSSIBILITY OF SUCH DAMAGE.
- * -------------------------------------------------------------------- */
-
-/**
- \mainpage CMSIS DSP Software Library
- *
- * <b>Introduction</b>
- *
- * This user manual describes the CMSIS DSP software library,
- * a suite of common signal processing functions for use on Cortex-M processor based devices.
- *
- * The library is divided into a number of functions each covering a specific category:
- * - Basic math functions
- * - Fast math functions
- * - Complex math functions
- * - Filters
- * - Matrix functions
- * - Transforms
- * - Motor control functions
- * - Statistical functions
- * - Support functions
- * - Interpolation functions
- *
- * The library has separate functions for operating on 8-bit integers, 16-bit integers,
- * 32-bit integer and 32-bit floating-point values.
- *
- * <b>Using the Library</b>
- *
- * The library installer contains prebuilt versions of the libraries in the <code>Lib</code> folder.
- * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4)
- * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4)
- * - arm_cortexM4l_math.lib (Little endian on Cortex-M4)
- * - arm_cortexM4b_math.lib (Big endian on Cortex-M4)
- * - arm_cortexM3l_math.lib (Little endian on Cortex-M3)
- * - arm_cortexM3b_math.lib (Big endian on Cortex-M3)
- * - arm_cortexM0l_math.lib (Little endian on Cortex-M0)
- * - arm_cortexM0b_math.lib (Big endian on Cortex-M3)
- *
- * The library functions are declared in the public file <code>arm_math.h</code> which is placed in the <code>Include</code> folder.
- * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single
- * public header file <code> arm_math.h</code> for Cortex-M4/M3/M0 with little endian and big endian. Same header file will be used for floating point unit(FPU) variants.
- * Define the appropriate pre processor MACRO ARM_MATH_CM4 or ARM_MATH_CM3 or
- * ARM_MATH_CM0 or ARM_MATH_CM0PLUS depending on the target processor in the application.
- *
- * <b>Examples</b>
- *
- * The library ships with a number of examples which demonstrate how to use the library functions.
- *
- * <b>Toolchain Support</b>
- *
- * The library has been developed and tested with MDK-ARM version 4.60.
- * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.
- *
- * <b>Building the Library</b>
- *
- * The library installer contains project files to re build libraries on MDK Tool chain in the <code>CMSIS\\DSP_Lib\\Source\\ARM</code> folder.
- * - arm_cortexM0b_math.uvproj
- * - arm_cortexM0l_math.uvproj
- * - arm_cortexM3b_math.uvproj
- * - arm_cortexM3l_math.uvproj
- * - arm_cortexM4b_math.uvproj
- * - arm_cortexM4l_math.uvproj
- * - arm_cortexM4bf_math.uvproj
- * - arm_cortexM4lf_math.uvproj
- *
- *
- * The project can be built by opening the appropriate project in MDK-ARM 4.60 chain and defining the optional pre processor MACROs detailed above.
- *
- * <b>Pre-processor Macros</b>
- *
- * Each library project have differant pre-processor macros.
- *
- * - UNALIGNED_SUPPORT_DISABLE:
- *
- * Define macro UNALIGNED_SUPPORT_DISABLE, If the silicon does not support unaligned memory access
- *
- * - ARM_MATH_BIG_ENDIAN:
- *
- * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.
- *
- * - ARM_MATH_MATRIX_CHECK:
- *
- * Define macro ARM_MATH_MATRIX_CHECK for checking on the input and output sizes of matrices
- *
- * - ARM_MATH_ROUNDING:
- *
- * Define macro ARM_MATH_ROUNDING for rounding on support functions
- *
- * - ARM_MATH_CMx:
- *
- * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target
- * and ARM_MATH_CM0 for building library on cortex-M0 target, ARM_MATH_CM0PLUS for building library on cortex-M0+ target.
- *
- * - __FPU_PRESENT:
- *
- * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries
- *
- * <b>Copyright Notice</b>
- *
- * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
- */
-
-
-/**
- * @defgroup groupMath Basic Math Functions
- */
-
-/**
- * @defgroup groupFastMath Fast Math Functions
- * This set of functions provides a fast approximation to sine, cosine, and square root.
- * As compared to most of the other functions in the CMSIS math library, the fast math functions
- * operate on individual values and not arrays.
- * There are separate functions for Q15, Q31, and floating-point data.
- *
- */
-
-/**
- * @defgroup groupCmplxMath Complex Math Functions
- * This set of functions operates on complex data vectors.
- * The data in the complex arrays is stored in an interleaved fashion
- * (real, imag, real, imag, ...).
- * In the API functions, the number of samples in a complex array refers
- * to the number of complex values; the array contains twice this number of
- * real values.
- */
-
-/**
- * @defgroup groupFilters Filtering Functions
- */
-
-/**
- * @defgroup groupMatrix Matrix Functions
- *
- * This set of functions provides basic matrix math operations.
- * The functions operate on matrix data structures. For example,
- * the type
- * definition for the floating-point matrix structure is shown
- * below:
- * <pre>
- * typedef struct
- * {
- * uint16_t numRows; // number of rows of the matrix.
- * uint16_t numCols; // number of columns of the matrix.
- * float32_t *pData; // points to the data of the matrix.
- * } arm_matrix_instance_f32;
- * </pre>
- * There are similar definitions for Q15 and Q31 data types.
- *
- * The structure specifies the size of the matrix and then points to
- * an array of data. The array is of size <code>numRows X numCols</code>
- * and the values are arranged in row order. That is, the
- * matrix element (i, j) is stored at:
- * <pre>
- * pData[i*numCols + j]
- * </pre>
- *
- * \par Init Functions
- * There is an associated initialization function for each type of matrix
- * data structure.
- * The initialization function sets the values of the internal structure fields.
- * Refer to the function <code>arm_mat_init_f32()</code>, <code>arm_mat_init_q31()</code>
- * and <code>arm_mat_init_q15()</code> for floating-point, Q31 and Q15 types, respectively.
- *
- * \par
- * Use of the initialization function is optional. However, if initialization function is used
- * then the instance structure cannot be placed into a const data section.
- * To place the instance structure in a const data
- * section, manually initialize the data structure. For example:
- * <pre>
- * <code>arm_matrix_instance_f32 S = {nRows, nColumns, pData};</code>
- * <code>arm_matrix_instance_q31 S = {nRows, nColumns, pData};</code>
- * <code>arm_matrix_instance_q15 S = {nRows, nColumns, pData};</code>
- * </pre>
- * where <code>nRows</code> specifies the number of rows, <code>nColumns</code>
- * specifies the number of columns, and <code>pData</code> points to the
- * data array.
- *
- * \par Size Checking
- * By default all of the matrix functions perform size checking on the input and
- * output matrices. For example, the matrix addition function verifies that the
- * two input matrices and the output matrix all have the same number of rows and
- * columns. If the size check fails the functions return:
- * <pre>
- * ARM_MATH_SIZE_MISMATCH
- * </pre>
- * Otherwise the functions return
- * <pre>
- * ARM_MATH_SUCCESS
- * </pre>
- * There is some overhead associated with this matrix size checking.
- * The matrix size checking is enabled via the \#define
- * <pre>
- * ARM_MATH_MATRIX_CHECK
- * </pre>
- * within the library project settings. By default this macro is defined
- * and size checking is enabled. By changing the project settings and
- * undefining this macro size checking is eliminated and the functions
- * run a bit faster. With size checking disabled the functions always
- * return <code>ARM_MATH_SUCCESS</code>.
- */
-
-/**
- * @defgroup groupTransforms Transform Functions
- */
-
-/**
- * @defgroup groupController Controller Functions
- */
-
-/**
- * @defgroup groupStats Statistics Functions
- */
-/**
- * @defgroup groupSupport Support Functions
- */
-
-/**
- * @defgroup groupInterpolation Interpolation Functions
- * These functions perform 1- and 2-dimensional interpolation of data.
- * Linear interpolation is used for 1-dimensional data and
- * bilinear interpolation is used for 2-dimensional data.
- */
-
-/**
- * @defgroup groupExamples Examples
- */
-#ifndef _ARM_MATH_H
-#define _ARM_MATH_H
-
-#define __CMSIS_GENERIC /* disable NVIC and Systick functions */
-
-#if defined (ARM_MATH_CM4)
-#include "core_cm4.h"
-#elif defined (ARM_MATH_CM3)
-#include "core_cm3.h"
-#elif defined (ARM_MATH_CM0)
-#include "core_cm0.h"
-#define ARM_MATH_CM0_FAMILY
-#elif defined (ARM_MATH_CM0PLUS)
-#include "core_cm0plus.h"
-#define ARM_MATH_CM0_FAMILY
-#else
-#include "ARMCM4.h"
-#warning "Define either ARM_MATH_CM4 OR ARM_MATH_CM3...By Default building on ARM_MATH_CM4....."
-#endif
-
-#undef __CMSIS_GENERIC /* enable NVIC and Systick functions */
-#include "string.h"
-#include "math.h"
-#ifdef __cplusplus
-extern "C"
-{
-#endif
-
-
- /**
- * @brief Macros required for reciprocal calculation in Normalized LMS
- */
-
-#define DELTA_Q31 (0x100)
-#define DELTA_Q15 0x5
-#define INDEX_MASK 0x0000003F
-#ifndef PI
-#define PI 3.14159265358979f
-#endif
-
- /**
- * @brief Macros required for SINE and COSINE Fast math approximations
- */
-
-#define TABLE_SIZE 256
-#define TABLE_SPACING_Q31 0x800000
-#define TABLE_SPACING_Q15 0x80
-
- /**
- * @brief Macros required for SINE and COSINE Controller functions
- */
- /* 1.31(q31) Fixed value of 2/360 */
- /* -1 to +1 is divided into 360 values so total spacing is (2/360) */
-#define INPUT_SPACING 0xB60B61
-
- /**
- * @brief Macro for Unaligned Support
- */
-#ifndef UNALIGNED_SUPPORT_DISABLE
- #define ALIGN4
-#else
- #if defined (__GNUC__)
- #define ALIGN4 __attribute__((aligned(4)))
- #else
- #define ALIGN4 __align(4)
- #endif
-#endif /* #ifndef UNALIGNED_SUPPORT_DISABLE */
-
- /**
- * @brief Error status returned by some functions in the library.
- */
-
- typedef enum
- {
- ARM_MATH_SUCCESS = 0, /**< No error */
- ARM_MATH_ARGUMENT_ERROR = -1, /**< One or more arguments are incorrect */
- ARM_MATH_LENGTH_ERROR = -2, /**< Length of data buffer is incorrect */
- ARM_MATH_SIZE_MISMATCH = -3, /**< Size of matrices is not compatible with the operation. */
- ARM_MATH_NANINF = -4, /**< Not-a-number (NaN) or infinity is generated */
- ARM_MATH_SINGULAR = -5, /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */
- ARM_MATH_TEST_FAILURE = -6 /**< Test Failed */
- } arm_status;
-
- /**
- * @brief 8-bit fractional data type in 1.7 format.
- */
- typedef int8_t q7_t;
-
- /**
- * @brief 16-bit fractional data type in 1.15 format.
- */
- typedef int16_t q15_t;
-
- /**
- * @brief 32-bit fractional data type in 1.31 format.
- */
- typedef int32_t q31_t;
-
- /**
- * @brief 64-bit fractional data type in 1.63 format.
- */
- typedef int64_t q63_t;
-
- /**
- * @brief 32-bit floating-point type definition.
- */
- typedef float float32_t;
-
- /**
- * @brief 64-bit floating-point type definition.
- */
- typedef double float64_t;
-
- /**
- * @brief definition to read/write two 16 bit values.
- */
-#if defined __CC_ARM
-#define __SIMD32_TYPE int32_t __packed
-#define CMSIS_UNUSED __attribute__((unused))
-#elif defined __ICCARM__
-#define CMSIS_UNUSED
-#define __SIMD32_TYPE int32_t __packed
-#elif defined __GNUC__
-#define __SIMD32_TYPE int32_t
-#define CMSIS_UNUSED __attribute__((unused))
-#else
-#error Unknown compiler
-#endif
-
-#define __SIMD32(addr) (*(__SIMD32_TYPE **) & (addr))
-#define __SIMD32_CONST(addr) ((__SIMD32_TYPE *)(addr))
-
-#define _SIMD32_OFFSET(addr) (*(__SIMD32_TYPE *) (addr))
-
-#define __SIMD64(addr) (*(int64_t **) & (addr))
-
-#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY)
- /**
- * @brief definition to pack two 16 bit values.
- */
-#define __PKHBT(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0x0000FFFF) | \
- (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000) )
-#define __PKHTB(ARG1, ARG2, ARG3) ( (((int32_t)(ARG1) << 0) & (int32_t)0xFFFF0000) | \
- (((int32_t)(ARG2) >> ARG3) & (int32_t)0x0000FFFF) )
-
-#endif
-
-
- /**
- * @brief definition to pack four 8 bit values.
- */
-#ifndef ARM_MATH_BIG_ENDIAN
-
-#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) << 0) & (int32_t)0x000000FF) | \
- (((int32_t)(v1) << 8) & (int32_t)0x0000FF00) | \
- (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \
- (((int32_t)(v3) << 24) & (int32_t)0xFF000000) )
-#else
-
-#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) << 0) & (int32_t)0x000000FF) | \
- (((int32_t)(v2) << 8) & (int32_t)0x0000FF00) | \
- (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) | \
- (((int32_t)(v0) << 24) & (int32_t)0xFF000000) )
-
-#endif
-
-
- /**
- * @brief Clips Q63 to Q31 values.
- */
- static __INLINE q31_t clip_q63_to_q31(
- q63_t x)
- {
- return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
- ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;
- }
-
- /**
- * @brief Clips Q63 to Q15 values.
- */
- static __INLINE q15_t clip_q63_to_q15(
- q63_t x)
- {
- return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
- ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);
- }
-
- /**
- * @brief Clips Q31 to Q7 values.
- */
- static __INLINE q7_t clip_q31_to_q7(
- q31_t x)
- {
- return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?
- ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;
- }
-
- /**
- * @brief Clips Q31 to Q15 values.
- */
- static __INLINE q15_t clip_q31_to_q15(
- q31_t x)
- {
- return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?
- ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;
- }
-
- /**
- * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.
- */
-
- static __INLINE q63_t mult32x64(
- q63_t x,
- q31_t y)
- {
- return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +
- (((q63_t) (x >> 32) * y)));
- }
-
-
-#if defined (ARM_MATH_CM0_FAMILY) && defined ( __CC_ARM )
-#define __CLZ __clz
-#endif
-
-#if defined (ARM_MATH_CM0_FAMILY) && ((defined (__ICCARM__)) ||(defined (__GNUC__)) || defined (__TASKING__) )
-
- static __INLINE uint32_t __CLZ(
- q31_t data);
-
-
- static __INLINE uint32_t __CLZ(
- q31_t data)
- {
- uint32_t count = 0;
- uint32_t mask = 0x80000000;
-
- while((data & mask) == 0)
- {
- count += 1u;
- mask = mask >> 1u;
- }
-
- return (count);
-
- }
-
-#endif
-
- /**
- * @brief Function to Calculates 1/in (reciprocal) value of Q31 Data type.
- */
-
- static __INLINE uint32_t arm_recip_q31(
- q31_t in,
- q31_t * dst,
- q31_t * pRecipTable)
- {
-
- uint32_t out, tempVal;
- uint32_t index, i;
- uint32_t signBits;
-
- if(in > 0)
- {
- signBits = __CLZ(in) - 1;
- }
- else
- {
- signBits = __CLZ(-in) - 1;
- }
-
- /* Convert input sample to 1.31 format */
- in = in << signBits;
-
- /* calculation of index for initial approximated Val */
- index = (uint32_t) (in >> 24u);
- index = (index & INDEX_MASK);
-
- /* 1.31 with exp 1 */
- out = pRecipTable[index];
-
- /* calculation of reciprocal value */
- /* running approximation for two iterations */
- for (i = 0u; i < 2u; i++)
- {
- tempVal = (q31_t) (((q63_t) in * out) >> 31u);
- tempVal = 0x7FFFFFFF - tempVal;
- /* 1.31 with exp 1 */
- //out = (q31_t) (((q63_t) out * tempVal) >> 30u);
- out = (q31_t) clip_q63_to_q31(((q63_t) out * tempVal) >> 30u);
- }
-
- /* write output */
- *dst = out;
-
- /* return num of signbits of out = 1/in value */
- return (signBits + 1u);
-
- }
-
- /**
- * @brief Function to Calculates 1/in (reciprocal) value of Q15 Data type.
- */
- static __INLINE uint32_t arm_recip_q15(
- q15_t in,
- q15_t * dst,
- q15_t * pRecipTable)
- {
-
- uint32_t out = 0, tempVal = 0;
- uint32_t index = 0, i = 0;
- uint32_t signBits = 0;
-
- if(in > 0)
- {
- signBits = __CLZ(in) - 17;
- }
- else
- {
- signBits = __CLZ(-in) - 17;
- }
-
- /* Convert input sample to 1.15 format */
- in = in << signBits;
-
- /* calculation of index for initial approximated Val */
- index = in >> 8;
- index = (index & INDEX_MASK);
-
- /* 1.15 with exp 1 */
- out = pRecipTable[index];
-
- /* calculation of reciprocal value */
- /* running approximation for two iterations */
- for (i = 0; i < 2; i++)
- {
- tempVal = (q15_t) (((q31_t) in * out) >> 15);
- tempVal = 0x7FFF - tempVal;
- /* 1.15 with exp 1 */
- out = (q15_t) (((q31_t) out * tempVal) >> 14);
- }
-
- /* write output */
- *dst = out;
-
- /* return num of signbits of out = 1/in value */
- return (signBits + 1);
-
- }
-
-
- /*
- * @brief C custom defined intrinisic function for only M0 processors
- */
-#if defined(ARM_MATH_CM0_FAMILY)
-
- static __INLINE q31_t __SSAT(
- q31_t x,
- uint32_t y)
- {
- int32_t posMax, negMin;
- uint32_t i;
-
- posMax = 1;
- for (i = 0; i < (y - 1); i++)
- {
- posMax = posMax * 2;
- }
-
- if(x > 0)
- {
- posMax = (posMax - 1);
-
- if(x > posMax)
- {
- x = posMax;
- }
- }
- else
- {
- negMin = -posMax;
-
- if(x < negMin)
- {
- x = negMin;
- }
- }
- return (x);
-
-
- }
-
-#endif /* end of ARM_MATH_CM0_FAMILY */
-
-
-
- /*
- * @brief C custom defined intrinsic function for M3 and M0 processors
- */
-#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY)
-
- /*
- * @brief C custom defined QADD8 for M3 and M0 processors
- */
- static __INLINE q31_t __QADD8(
- q31_t x,
- q31_t y)
- {
-
- q31_t sum;
- q7_t r, s, t, u;
-
- r = (q7_t) x;
- s = (q7_t) y;
-
- r = __SSAT((q31_t) (r + s), 8);
- s = __SSAT(((q31_t) (((x << 16) >> 24) + ((y << 16) >> 24))), 8);
- t = __SSAT(((q31_t) (((x << 8) >> 24) + ((y << 8) >> 24))), 8);
- u = __SSAT(((q31_t) ((x >> 24) + (y >> 24))), 8);
-
- sum =
- (((q31_t) u << 24) & 0xFF000000) | (((q31_t) t << 16) & 0x00FF0000) |
- (((q31_t) s << 8) & 0x0000FF00) | (r & 0x000000FF);
-
- return sum;
-
- }
-
- /*
- * @brief C custom defined QSUB8 for M3 and M0 processors
- */
- static __INLINE q31_t __QSUB8(
- q31_t x,
- q31_t y)
- {
-
- q31_t sum;
- q31_t r, s, t, u;
-
- r = (q7_t) x;
- s = (q7_t) y;
-
- r = __SSAT((r - s), 8);
- s = __SSAT(((q31_t) (((x << 16) >> 24) - ((y << 16) >> 24))), 8) << 8;
- t = __SSAT(((q31_t) (((x << 8) >> 24) - ((y << 8) >> 24))), 8) << 16;
- u = __SSAT(((q31_t) ((x >> 24) - (y >> 24))), 8) << 24;
-
- sum =
- (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r &
- 0x000000FF);
-
- return sum;
- }
-
- /*
- * @brief C custom defined QADD16 for M3 and M0 processors
- */
-
- /*
- * @brief C custom defined QADD16 for M3 and M0 processors
- */
- static __INLINE q31_t __QADD16(
- q31_t x,
- q31_t y)
- {
-
- q31_t sum;
- q31_t r, s;
-
- r = (short) x;
- s = (short) y;
-
- r = __SSAT(r + s, 16);
- s = __SSAT(((q31_t) ((x >> 16) + (y >> 16))), 16) << 16;
-
- sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
-
- return sum;
-
- }
-
- /*
- * @brief C custom defined SHADD16 for M3 and M0 processors
- */
- static __INLINE q31_t __SHADD16(
- q31_t x,
- q31_t y)
- {
-
- q31_t sum;
- q31_t r, s;
-
- r = (short) x;
- s = (short) y;
-
- r = ((r >> 1) + (s >> 1));
- s = ((q31_t) ((x >> 17) + (y >> 17))) << 16;
-
- sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
-
- return sum;
-
- }
-
- /*
- * @brief C custom defined QSUB16 for M3 and M0 processors
- */
- static __INLINE q31_t __QSUB16(
- q31_t x,
- q31_t y)
- {
-
- q31_t sum;
- q31_t r, s;
-
- r = (short) x;
- s = (short) y;
-
- r = __SSAT(r - s, 16);
- s = __SSAT(((q31_t) ((x >> 16) - (y >> 16))), 16) << 16;
-
- sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
-
- return sum;
- }
-
- /*
- * @brief C custom defined SHSUB16 for M3 and M0 processors
- */
- static __INLINE q31_t __SHSUB16(
- q31_t x,
- q31_t y)
- {
-
- q31_t diff;
- q31_t r, s;
-
- r = (short) x;
- s = (short) y;
-
- r = ((r >> 1) - (s >> 1));
- s = (((x >> 17) - (y >> 17)) << 16);
-
- diff = (s & 0xFFFF0000) | (r & 0x0000FFFF);
-
- return diff;
- }
-
- /*
- * @brief C custom defined QASX for M3 and M0 processors
- */
- static __INLINE q31_t __QASX(
- q31_t x,
- q31_t y)
- {
-
- q31_t sum = 0;
-
- sum =
- ((sum +
- clip_q31_to_q15((q31_t) ((short) (x >> 16) + (short) y))) << 16) +
- clip_q31_to_q15((q31_t) ((short) x - (short) (y >> 16)));
-
- return sum;
- }
-
- /*
- * @brief C custom defined SHASX for M3 and M0 processors
- */
- static __INLINE q31_t __SHASX(
- q31_t x,
- q31_t y)
- {
-
- q31_t sum;
- q31_t r, s;
-
- r = (short) x;
- s = (short) y;
-
- r = ((r >> 1) - (y >> 17));
- s = (((x >> 17) + (s >> 1)) << 16);
-
- sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
-
- return sum;
- }
-
-
- /*
- * @brief C custom defined QSAX for M3 and M0 processors
- */
- static __INLINE q31_t __QSAX(
- q31_t x,
- q31_t y)
- {
-
- q31_t sum = 0;
-
- sum =
- ((sum +
- clip_q31_to_q15((q31_t) ((short) (x >> 16) - (short) y))) << 16) +
- clip_q31_to_q15((q31_t) ((short) x + (short) (y >> 16)));
-
- return sum;
- }
-
- /*
- * @brief C custom defined SHSAX for M3 and M0 processors
- */
- static __INLINE q31_t __SHSAX(
- q31_t x,
- q31_t y)
- {
-
- q31_t sum;
- q31_t r, s;
-
- r = (short) x;
- s = (short) y;
-
- r = ((r >> 1) + (y >> 17));
- s = (((x >> 17) - (s >> 1)) << 16);
-
- sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
-
- return sum;
- }
-
- /*
- * @brief C custom defined SMUSDX for M3 and M0 processors
- */
- static __INLINE q31_t __SMUSDX(
- q31_t x,
- q31_t y)
- {
-
- return ((q31_t) (((short) x * (short) (y >> 16)) -
- ((short) (x >> 16) * (short) y)));
- }
-
- /*
- * @brief C custom defined SMUADX for M3 and M0 processors
- */
- static __INLINE q31_t __SMUADX(
- q31_t x,
- q31_t y)
- {
-
- return ((q31_t) (((short) x * (short) (y >> 16)) +
- ((short) (x >> 16) * (short) y)));
- }
-
- /*
- * @brief C custom defined QADD for M3 and M0 processors
- */
- static __INLINE q31_t __QADD(
- q31_t x,
- q31_t y)
- {
- return clip_q63_to_q31((q63_t) x + y);
- }
-
- /*
- * @brief C custom defined QSUB for M3 and M0 processors
- */
- static __INLINE q31_t __QSUB(
- q31_t x,
- q31_t y)
- {
- return clip_q63_to_q31((q63_t) x - y);
- }
-
- /*
- * @brief C custom defined SMLAD for M3 and M0 processors
- */
- static __INLINE q31_t __SMLAD(
- q31_t x,
- q31_t y,
- q31_t sum)
- {
-
- return (sum + ((short) (x >> 16) * (short) (y >> 16)) +
- ((short) x * (short) y));
- }
-
- /*
- * @brief C custom defined SMLADX for M3 and M0 processors
- */
- static __INLINE q31_t __SMLADX(
- q31_t x,
- q31_t y,
- q31_t sum)
- {
-
- return (sum + ((short) (x >> 16) * (short) (y)) +
- ((short) x * (short) (y >> 16)));
- }
-
- /*
- * @brief C custom defined SMLSDX for M3 and M0 processors
- */
- static __INLINE q31_t __SMLSDX(
- q31_t x,
- q31_t y,
- q31_t sum)
- {
-
- return (sum - ((short) (x >> 16) * (short) (y)) +
- ((short) x * (short) (y >> 16)));
- }
-
- /*
- * @brief C custom defined SMLALD for M3 and M0 processors
- */
- static __INLINE q63_t __SMLALD(
- q31_t x,
- q31_t y,
- q63_t sum)
- {
-
- return (sum + ((short) (x >> 16) * (short) (y >> 16)) +
- ((short) x * (short) y));
- }
-
- /*
- * @brief C custom defined SMLALDX for M3 and M0 processors
- */
- static __INLINE q63_t __SMLALDX(
- q31_t x,
- q31_t y,
- q63_t sum)
- {
-
- return (sum + ((short) (x >> 16) * (short) y)) +
- ((short) x * (short) (y >> 16));
- }
-
- /*
- * @brief C custom defined SMUAD for M3 and M0 processors
- */
- static __INLINE q31_t __SMUAD(
- q31_t x,
- q31_t y)
- {
-
- return (((x >> 16) * (y >> 16)) +
- (((x << 16) >> 16) * ((y << 16) >> 16)));
- }
-
- /*
- * @brief C custom defined SMUSD for M3 and M0 processors
- */
- static __INLINE q31_t __SMUSD(
- q31_t x,
- q31_t y)
- {
-
- return (-((x >> 16) * (y >> 16)) +
- (((x << 16) >> 16) * ((y << 16) >> 16)));
- }
-
-
- /*
- * @brief C custom defined SXTB16 for M3 and M0 processors
- */
- static __INLINE q31_t __SXTB16(
- q31_t x)
- {
-
- return ((((x << 24) >> 24) & 0x0000FFFF) |
- (((x << 8) >> 8) & 0xFFFF0000));
- }
-
-
-#endif /* defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0_FAMILY) */
-
-
- /**
- * @brief Instance structure for the Q7 FIR filter.
- */
- typedef struct
- {
- uint16_t numTaps; /**< number of filter coefficients in the filter. */
- q7_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
- q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
- } arm_fir_instance_q7;
-
- /**
- * @brief Instance structure for the Q15 FIR filter.
- */
- typedef struct
- {
- uint16_t numTaps; /**< number of filter coefficients in the filter. */
- q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
- q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
- } arm_fir_instance_q15;
-
- /**
- * @brief Instance structure for the Q31 FIR filter.
- */
- typedef struct
- {
- uint16_t numTaps; /**< number of filter coefficients in the filter. */
- q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
- q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
- } arm_fir_instance_q31;
-
- /**
- * @brief Instance structure for the floating-point FIR filter.
- */
- typedef struct
- {
- uint16_t numTaps; /**< number of filter coefficients in the filter. */
- float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
- float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
- } arm_fir_instance_f32;
-
-
- /**
- * @brief Processing function for the Q7 FIR filter.
- * @param[in] *S points to an instance of the Q7 FIR filter structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- * @return none.
- */
- void arm_fir_q7(
- const arm_fir_instance_q7 * S,
- q7_t * pSrc,
- q7_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for the Q7 FIR filter.
- * @param[in,out] *S points to an instance of the Q7 FIR structure.
- * @param[in] numTaps Number of filter coefficients in the filter.
- * @param[in] *pCoeffs points to the filter coefficients.
- * @param[in] *pState points to the state buffer.
- * @param[in] blockSize number of samples that are processed.
- * @return none
- */
- void arm_fir_init_q7(
- arm_fir_instance_q7 * S,
- uint16_t numTaps,
- q7_t * pCoeffs,
- q7_t * pState,
- uint32_t blockSize);
-
-
- /**
- * @brief Processing function for the Q15 FIR filter.
- * @param[in] *S points to an instance of the Q15 FIR structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- * @return none.
- */
- void arm_fir_q15(
- const arm_fir_instance_q15 * S,
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4.
- * @param[in] *S points to an instance of the Q15 FIR filter structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- * @return none.
- */
- void arm_fir_fast_q15(
- const arm_fir_instance_q15 * S,
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Initialization function for the Q15 FIR filter.
- * @param[in,out] *S points to an instance of the Q15 FIR filter structure.
- * @param[in] numTaps Number of filter coefficients in the filter. Must be even and greater than or equal to 4.
- * @param[in] *pCoeffs points to the filter coefficients.
- * @param[in] *pState points to the state buffer.
- * @param[in] blockSize number of samples that are processed at a time.
- * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if
- * <code>numTaps</code> is not a supported value.
- */
-
- arm_status arm_fir_init_q15(
- arm_fir_instance_q15 * S,
- uint16_t numTaps,
- q15_t * pCoeffs,
- q15_t * pState,
- uint32_t blockSize);
-
- /**
- * @brief Processing function for the Q31 FIR filter.
- * @param[in] *S points to an instance of the Q31 FIR filter structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- * @return none.
- */
- void arm_fir_q31(
- const arm_fir_instance_q31 * S,
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4.
- * @param[in] *S points to an instance of the Q31 FIR structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- * @return none.
- */
- void arm_fir_fast_q31(
- const arm_fir_instance_q31 * S,
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Initialization function for the Q31 FIR filter.
- * @param[in,out] *S points to an instance of the Q31 FIR structure.
- * @param[in] numTaps Number of filter coefficients in the filter.
- * @param[in] *pCoeffs points to the filter coefficients.
- * @param[in] *pState points to the state buffer.
- * @param[in] blockSize number of samples that are processed at a time.
- * @return none.
- */
- void arm_fir_init_q31(
- arm_fir_instance_q31 * S,
- uint16_t numTaps,
- q31_t * pCoeffs,
- q31_t * pState,
- uint32_t blockSize);
-
- /**
- * @brief Processing function for the floating-point FIR filter.
- * @param[in] *S points to an instance of the floating-point FIR structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- * @return none.
- */
- void arm_fir_f32(
- const arm_fir_instance_f32 * S,
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Initialization function for the floating-point FIR filter.
- * @param[in,out] *S points to an instance of the floating-point FIR filter structure.
- * @param[in] numTaps Number of filter coefficients in the filter.
- * @param[in] *pCoeffs points to the filter coefficients.
- * @param[in] *pState points to the state buffer.
- * @param[in] blockSize number of samples that are processed at a time.
- * @return none.
- */
- void arm_fir_init_f32(
- arm_fir_instance_f32 * S,
- uint16_t numTaps,
- float32_t * pCoeffs,
- float32_t * pState,
- uint32_t blockSize);
-
-
- /**
- * @brief Instance structure for the Q15 Biquad cascade filter.
- */
- typedef struct
- {
- int8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
- q15_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
- q15_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
- int8_t postShift; /**< Additional shift, in bits, applied to each output sample. */
-
- } arm_biquad_casd_df1_inst_q15;
-
-
- /**
- * @brief Instance structure for the Q31 Biquad cascade filter.
- */
- typedef struct
- {
- uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
- q31_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
- q31_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
- uint8_t postShift; /**< Additional shift, in bits, applied to each output sample. */
-
- } arm_biquad_casd_df1_inst_q31;
-
- /**
- * @brief Instance structure for the floating-point Biquad cascade filter.
- */
- typedef struct
- {
- uint32_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
- float32_t *pState; /**< Points to the array of state coefficients. The array is of length 4*numStages. */
- float32_t *pCoeffs; /**< Points to the array of coefficients. The array is of length 5*numStages. */
-
-
- } arm_biquad_casd_df1_inst_f32;
-
-
-
- /**
- * @brief Processing function for the Q15 Biquad cascade filter.
- * @param[in] *S points to an instance of the Q15 Biquad cascade structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- * @return none.
- */
-
- void arm_biquad_cascade_df1_q15(
- const arm_biquad_casd_df1_inst_q15 * S,
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Initialization function for the Q15 Biquad cascade filter.
- * @param[in,out] *S points to an instance of the Q15 Biquad cascade structure.
- * @param[in] numStages number of 2nd order stages in the filter.
- * @param[in] *pCoeffs points to the filter coefficients.
- * @param[in] *pState points to the state buffer.
- * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format
- * @return none
- */
-
- void arm_biquad_cascade_df1_init_q15(
- arm_biquad_casd_df1_inst_q15 * S,
- uint8_t numStages,
- q15_t * pCoeffs,
- q15_t * pState,
- int8_t postShift);
-
-
- /**
- * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.
- * @param[in] *S points to an instance of the Q15 Biquad cascade structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- * @return none.
- */
-
- void arm_biquad_cascade_df1_fast_q15(
- const arm_biquad_casd_df1_inst_q15 * S,
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Processing function for the Q31 Biquad cascade filter
- * @param[in] *S points to an instance of the Q31 Biquad cascade structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- * @return none.
- */
-
- void arm_biquad_cascade_df1_q31(
- const arm_biquad_casd_df1_inst_q31 * S,
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.
- * @param[in] *S points to an instance of the Q31 Biquad cascade structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- * @return none.
- */
-
- void arm_biquad_cascade_df1_fast_q31(
- const arm_biquad_casd_df1_inst_q31 * S,
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Initialization function for the Q31 Biquad cascade filter.
- * @param[in,out] *S points to an instance of the Q31 Biquad cascade structure.
- * @param[in] numStages number of 2nd order stages in the filter.
- * @param[in] *pCoeffs points to the filter coefficients.
- * @param[in] *pState points to the state buffer.
- * @param[in] postShift Shift to be applied to the output. Varies according to the coefficients format
- * @return none
- */
-
- void arm_biquad_cascade_df1_init_q31(
- arm_biquad_casd_df1_inst_q31 * S,
- uint8_t numStages,
- q31_t * pCoeffs,
- q31_t * pState,
- int8_t postShift);
-
- /**
- * @brief Processing function for the floating-point Biquad cascade filter.
- * @param[in] *S points to an instance of the floating-point Biquad cascade structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- * @return none.
- */
-
- void arm_biquad_cascade_df1_f32(
- const arm_biquad_casd_df1_inst_f32 * S,
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Initialization function for the floating-point Biquad cascade filter.
- * @param[in,out] *S points to an instance of the floating-point Biquad cascade structure.
- * @param[in] numStages number of 2nd order stages in the filter.
- * @param[in] *pCoeffs points to the filter coefficients.
- * @param[in] *pState points to the state buffer.
- * @return none
- */
-
- void arm_biquad_cascade_df1_init_f32(
- arm_biquad_casd_df1_inst_f32 * S,
- uint8_t numStages,
- float32_t * pCoeffs,
- float32_t * pState);
-
-
- /**
- * @brief Instance structure for the floating-point matrix structure.
- */
-
- typedef struct
- {
- uint16_t numRows; /**< number of rows of the matrix. */
- uint16_t numCols; /**< number of columns of the matrix. */
- float32_t *pData; /**< points to the data of the matrix. */
- } arm_matrix_instance_f32;
-
- /**
- * @brief Instance structure for the Q15 matrix structure.
- */
-
- typedef struct
- {
- uint16_t numRows; /**< number of rows of the matrix. */
- uint16_t numCols; /**< number of columns of the matrix. */
- q15_t *pData; /**< points to the data of the matrix. */
-
- } arm_matrix_instance_q15;
-
- /**
- * @brief Instance structure for the Q31 matrix structure.
- */
-
- typedef struct
- {
- uint16_t numRows; /**< number of rows of the matrix. */
- uint16_t numCols; /**< number of columns of the matrix. */
- q31_t *pData; /**< points to the data of the matrix. */
-
- } arm_matrix_instance_q31;
-
-
-
- /**
- * @brief Floating-point matrix addition.
- * @param[in] *pSrcA points to the first input matrix structure
- * @param[in] *pSrcB points to the second input matrix structure
- * @param[out] *pDst points to output matrix structure
- * @return The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
-
- arm_status arm_mat_add_f32(
- const arm_matrix_instance_f32 * pSrcA,
- const arm_matrix_instance_f32 * pSrcB,
- arm_matrix_instance_f32 * pDst);
-
- /**
- * @brief Q15 matrix addition.
- * @param[in] *pSrcA points to the first input matrix structure
- * @param[in] *pSrcB points to the second input matrix structure
- * @param[out] *pDst points to output matrix structure
- * @return The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
-
- arm_status arm_mat_add_q15(
- const arm_matrix_instance_q15 * pSrcA,
- const arm_matrix_instance_q15 * pSrcB,
- arm_matrix_instance_q15 * pDst);
-
- /**
- * @brief Q31 matrix addition.
- * @param[in] *pSrcA points to the first input matrix structure
- * @param[in] *pSrcB points to the second input matrix structure
- * @param[out] *pDst points to output matrix structure
- * @return The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
-
- arm_status arm_mat_add_q31(
- const arm_matrix_instance_q31 * pSrcA,
- const arm_matrix_instance_q31 * pSrcB,
- arm_matrix_instance_q31 * pDst);
-
-
- /**
- * @brief Floating-point matrix transpose.
- * @param[in] *pSrc points to the input matrix
- * @param[out] *pDst points to the output matrix
- * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>
- * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
-
- arm_status arm_mat_trans_f32(
- const arm_matrix_instance_f32 * pSrc,
- arm_matrix_instance_f32 * pDst);
-
-
- /**
- * @brief Q15 matrix transpose.
- * @param[in] *pSrc points to the input matrix
- * @param[out] *pDst points to the output matrix
- * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>
- * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
-
- arm_status arm_mat_trans_q15(
- const arm_matrix_instance_q15 * pSrc,
- arm_matrix_instance_q15 * pDst);
-
- /**
- * @brief Q31 matrix transpose.
- * @param[in] *pSrc points to the input matrix
- * @param[out] *pDst points to the output matrix
- * @return The function returns either <code>ARM_MATH_SIZE_MISMATCH</code>
- * or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
-
- arm_status arm_mat_trans_q31(
- const arm_matrix_instance_q31 * pSrc,
- arm_matrix_instance_q31 * pDst);
-
-
- /**
- * @brief Floating-point matrix multiplication
- * @param[in] *pSrcA points to the first input matrix structure
- * @param[in] *pSrcB points to the second input matrix structure
- * @param[out] *pDst points to output matrix structure
- * @return The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
-
- arm_status arm_mat_mult_f32(
- const arm_matrix_instance_f32 * pSrcA,
- const arm_matrix_instance_f32 * pSrcB,
- arm_matrix_instance_f32 * pDst);
-
- /**
- * @brief Q15 matrix multiplication
- * @param[in] *pSrcA points to the first input matrix structure
- * @param[in] *pSrcB points to the second input matrix structure
- * @param[out] *pDst points to output matrix structure
- * @param[in] *pState points to the array for storing intermediate results
- * @return The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
-
- arm_status arm_mat_mult_q15(
- const arm_matrix_instance_q15 * pSrcA,
- const arm_matrix_instance_q15 * pSrcB,
- arm_matrix_instance_q15 * pDst,
- q15_t * pState);
-
- /**
- * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
- * @param[in] *pSrcA points to the first input matrix structure
- * @param[in] *pSrcB points to the second input matrix structure
- * @param[out] *pDst points to output matrix structure
- * @param[in] *pState points to the array for storing intermediate results
- * @return The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
-
- arm_status arm_mat_mult_fast_q15(
- const arm_matrix_instance_q15 * pSrcA,
- const arm_matrix_instance_q15 * pSrcB,
- arm_matrix_instance_q15 * pDst,
- q15_t * pState);
-
- /**
- * @brief Q31 matrix multiplication
- * @param[in] *pSrcA points to the first input matrix structure
- * @param[in] *pSrcB points to the second input matrix structure
- * @param[out] *pDst points to output matrix structure
- * @return The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
-
- arm_status arm_mat_mult_q31(
- const arm_matrix_instance_q31 * pSrcA,
- const arm_matrix_instance_q31 * pSrcB,
- arm_matrix_instance_q31 * pDst);
-
- /**
- * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
- * @param[in] *pSrcA points to the first input matrix structure
- * @param[in] *pSrcB points to the second input matrix structure
- * @param[out] *pDst points to output matrix structure
- * @return The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
-
- arm_status arm_mat_mult_fast_q31(
- const arm_matrix_instance_q31 * pSrcA,
- const arm_matrix_instance_q31 * pSrcB,
- arm_matrix_instance_q31 * pDst);
-
-
- /**
- * @brief Floating-point matrix subtraction
- * @param[in] *pSrcA points to the first input matrix structure
- * @param[in] *pSrcB points to the second input matrix structure
- * @param[out] *pDst points to output matrix structure
- * @return The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
-
- arm_status arm_mat_sub_f32(
- const arm_matrix_instance_f32 * pSrcA,
- const arm_matrix_instance_f32 * pSrcB,
- arm_matrix_instance_f32 * pDst);
-
- /**
- * @brief Q15 matrix subtraction
- * @param[in] *pSrcA points to the first input matrix structure
- * @param[in] *pSrcB points to the second input matrix structure
- * @param[out] *pDst points to output matrix structure
- * @return The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
-
- arm_status arm_mat_sub_q15(
- const arm_matrix_instance_q15 * pSrcA,
- const arm_matrix_instance_q15 * pSrcB,
- arm_matrix_instance_q15 * pDst);
-
- /**
- * @brief Q31 matrix subtraction
- * @param[in] *pSrcA points to the first input matrix structure
- * @param[in] *pSrcB points to the second input matrix structure
- * @param[out] *pDst points to output matrix structure
- * @return The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
-
- arm_status arm_mat_sub_q31(
- const arm_matrix_instance_q31 * pSrcA,
- const arm_matrix_instance_q31 * pSrcB,
- arm_matrix_instance_q31 * pDst);
-
- /**
- * @brief Floating-point matrix scaling.
- * @param[in] *pSrc points to the input matrix
- * @param[in] scale scale factor
- * @param[out] *pDst points to the output matrix
- * @return The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
-
- arm_status arm_mat_scale_f32(
- const arm_matrix_instance_f32 * pSrc,
- float32_t scale,
- arm_matrix_instance_f32 * pDst);
-
- /**
- * @brief Q15 matrix scaling.
- * @param[in] *pSrc points to input matrix
- * @param[in] scaleFract fractional portion of the scale factor
- * @param[in] shift number of bits to shift the result by
- * @param[out] *pDst points to output matrix
- * @return The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
-
- arm_status arm_mat_scale_q15(
- const arm_matrix_instance_q15 * pSrc,
- q15_t scaleFract,
- int32_t shift,
- arm_matrix_instance_q15 * pDst);
-
- /**
- * @brief Q31 matrix scaling.
- * @param[in] *pSrc points to input matrix
- * @param[in] scaleFract fractional portion of the scale factor
- * @param[in] shift number of bits to shift the result by
- * @param[out] *pDst points to output matrix structure
- * @return The function returns either
- * <code>ARM_MATH_SIZE_MISMATCH</code> or <code>ARM_MATH_SUCCESS</code> based on the outcome of size checking.
- */
-
- arm_status arm_mat_scale_q31(
- const arm_matrix_instance_q31 * pSrc,
- q31_t scaleFract,
- int32_t shift,
- arm_matrix_instance_q31 * pDst);
-
-
- /**
- * @brief Q31 matrix initialization.
- * @param[in,out] *S points to an instance of the floating-point matrix structure.
- * @param[in] nRows number of rows in the matrix.
- * @param[in] nColumns number of columns in the matrix.
- * @param[in] *pData points to the matrix data array.
- * @return none
- */
-
- void arm_mat_init_q31(
- arm_matrix_instance_q31 * S,
- uint16_t nRows,
- uint16_t nColumns,
- q31_t * pData);
-
- /**
- * @brief Q15 matrix initialization.
- * @param[in,out] *S points to an instance of the floating-point matrix structure.
- * @param[in] nRows number of rows in the matrix.
- * @param[in] nColumns number of columns in the matrix.
- * @param[in] *pData points to the matrix data array.
- * @return none
- */
-
- void arm_mat_init_q15(
- arm_matrix_instance_q15 * S,
- uint16_t nRows,
- uint16_t nColumns,
- q15_t * pData);
-
- /**
- * @brief Floating-point matrix initialization.
- * @param[in,out] *S points to an instance of the floating-point matrix structure.
- * @param[in] nRows number of rows in the matrix.
- * @param[in] nColumns number of columns in the matrix.
- * @param[in] *pData points to the matrix data array.
- * @return none
- */
-
- void arm_mat_init_f32(
- arm_matrix_instance_f32 * S,
- uint16_t nRows,
- uint16_t nColumns,
- float32_t * pData);
-
-
-
- /**
- * @brief Instance structure for the Q15 PID Control.
- */
- typedef struct
- {
- q15_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
-#ifdef ARM_MATH_CM0_FAMILY
- q15_t A1;
- q15_t A2;
-#else
- q31_t A1; /**< The derived gain A1 = -Kp - 2Kd | Kd.*/
-#endif
- q15_t state[3]; /**< The state array of length 3. */
- q15_t Kp; /**< The proportional gain. */
- q15_t Ki; /**< The integral gain. */
- q15_t Kd; /**< The derivative gain. */
- } arm_pid_instance_q15;
-
- /**
- * @brief Instance structure for the Q31 PID Control.
- */
- typedef struct
- {
- q31_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
- q31_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */
- q31_t A2; /**< The derived gain, A2 = Kd . */
- q31_t state[3]; /**< The state array of length 3. */
- q31_t Kp; /**< The proportional gain. */
- q31_t Ki; /**< The integral gain. */
- q31_t Kd; /**< The derivative gain. */
-
- } arm_pid_instance_q31;
-
- /**
- * @brief Instance structure for the floating-point PID Control.
- */
- typedef struct
- {
- float32_t A0; /**< The derived gain, A0 = Kp + Ki + Kd . */
- float32_t A1; /**< The derived gain, A1 = -Kp - 2Kd. */
- float32_t A2; /**< The derived gain, A2 = Kd . */
- float32_t state[3]; /**< The state array of length 3. */
- float32_t Kp; /**< The proportional gain. */
- float32_t Ki; /**< The integral gain. */
- float32_t Kd; /**< The derivative gain. */
- } arm_pid_instance_f32;
-
-
-
- /**
- * @brief Initialization function for the floating-point PID Control.
- * @param[in,out] *S points to an instance of the PID structure.
- * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
- * @return none.
- */
- void arm_pid_init_f32(
- arm_pid_instance_f32 * S,
- int32_t resetStateFlag);
-
- /**
- * @brief Reset function for the floating-point PID Control.
- * @param[in,out] *S is an instance of the floating-point PID Control structure
- * @return none
- */
- void arm_pid_reset_f32(
- arm_pid_instance_f32 * S);
-
-
- /**
- * @brief Initialization function for the Q31 PID Control.
- * @param[in,out] *S points to an instance of the Q15 PID structure.
- * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
- * @return none.
- */
- void arm_pid_init_q31(
- arm_pid_instance_q31 * S,
- int32_t resetStateFlag);
-
-
- /**
- * @brief Reset function for the Q31 PID Control.
- * @param[in,out] *S points to an instance of the Q31 PID Control structure
- * @return none
- */
-
- void arm_pid_reset_q31(
- arm_pid_instance_q31 * S);
-
- /**
- * @brief Initialization function for the Q15 PID Control.
- * @param[in,out] *S points to an instance of the Q15 PID structure.
- * @param[in] resetStateFlag flag to reset the state. 0 = no change in state 1 = reset the state.
- * @return none.
- */
- void arm_pid_init_q15(
- arm_pid_instance_q15 * S,
- int32_t resetStateFlag);
-
- /**
- * @brief Reset function for the Q15 PID Control.
- * @param[in,out] *S points to an instance of the q15 PID Control structure
- * @return none
- */
- void arm_pid_reset_q15(
- arm_pid_instance_q15 * S);
-
-
- /**
- * @brief Instance structure for the floating-point Linear Interpolate function.
- */
- typedef struct
- {
- uint32_t nValues; /**< nValues */
- float32_t x1; /**< x1 */
- float32_t xSpacing; /**< xSpacing */
- float32_t *pYData; /**< pointer to the table of Y values */
- } arm_linear_interp_instance_f32;
-
- /**
- * @brief Instance structure for the floating-point bilinear interpolation function.
- */
-
- typedef struct
- {
- uint16_t numRows; /**< number of rows in the data table. */
- uint16_t numCols; /**< number of columns in the data table. */
- float32_t *pData; /**< points to the data table. */
- } arm_bilinear_interp_instance_f32;
-
- /**
- * @brief Instance structure for the Q31 bilinear interpolation function.
- */
-
- typedef struct
- {
- uint16_t numRows; /**< number of rows in the data table. */
- uint16_t numCols; /**< number of columns in the data table. */
- q31_t *pData; /**< points to the data table. */
- } arm_bilinear_interp_instance_q31;
-
- /**
- * @brief Instance structure for the Q15 bilinear interpolation function.
- */
-
- typedef struct
- {
- uint16_t numRows; /**< number of rows in the data table. */
- uint16_t numCols; /**< number of columns in the data table. */
- q15_t *pData; /**< points to the data table. */
- } arm_bilinear_interp_instance_q15;
-
- /**
- * @brief Instance structure for the Q15 bilinear interpolation function.
- */
-
- typedef struct
- {
- uint16_t numRows; /**< number of rows in the data table. */
- uint16_t numCols; /**< number of columns in the data table. */
- q7_t *pData; /**< points to the data table. */
- } arm_bilinear_interp_instance_q7;
-
-
- /**
- * @brief Q7 vector multiplication.
- * @param[in] *pSrcA points to the first input vector
- * @param[in] *pSrcB points to the second input vector
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in each vector
- * @return none.
- */
-
- void arm_mult_q7(
- q7_t * pSrcA,
- q7_t * pSrcB,
- q7_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Q15 vector multiplication.
- * @param[in] *pSrcA points to the first input vector
- * @param[in] *pSrcB points to the second input vector
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in each vector
- * @return none.
- */
-
- void arm_mult_q15(
- q15_t * pSrcA,
- q15_t * pSrcB,
- q15_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Q31 vector multiplication.
- * @param[in] *pSrcA points to the first input vector
- * @param[in] *pSrcB points to the second input vector
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in each vector
- * @return none.
- */
-
- void arm_mult_q31(
- q31_t * pSrcA,
- q31_t * pSrcB,
- q31_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Floating-point vector multiplication.
- * @param[in] *pSrcA points to the first input vector
- * @param[in] *pSrcB points to the second input vector
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in each vector
- * @return none.
- */
-
- void arm_mult_f32(
- float32_t * pSrcA,
- float32_t * pSrcB,
- float32_t * pDst,
- uint32_t blockSize);
-
-
-
-
-
-
- /**
- * @brief Instance structure for the Q15 CFFT/CIFFT function.
- */
-
- typedef struct
- {
- uint16_t fftLen; /**< length of the FFT. */
- uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
- uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
- q15_t *pTwiddle; /**< points to the Sin twiddle factor table. */
- uint16_t *pBitRevTable; /**< points to the bit reversal table. */
- uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
- uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
- } arm_cfft_radix2_instance_q15;
-
- arm_status arm_cfft_radix2_init_q15(
- arm_cfft_radix2_instance_q15 * S,
- uint16_t fftLen,
- uint8_t ifftFlag,
- uint8_t bitReverseFlag);
-
- void arm_cfft_radix2_q15(
- const arm_cfft_radix2_instance_q15 * S,
- q15_t * pSrc);
-
-
-
- /**
- * @brief Instance structure for the Q15 CFFT/CIFFT function.
- */
-
- typedef struct
- {
- uint16_t fftLen; /**< length of the FFT. */
- uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
- uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
- q15_t *pTwiddle; /**< points to the twiddle factor table. */
- uint16_t *pBitRevTable; /**< points to the bit reversal table. */
- uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
- uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
- } arm_cfft_radix4_instance_q15;
-
- arm_status arm_cfft_radix4_init_q15(
- arm_cfft_radix4_instance_q15 * S,
- uint16_t fftLen,
- uint8_t ifftFlag,
- uint8_t bitReverseFlag);
-
- void arm_cfft_radix4_q15(
- const arm_cfft_radix4_instance_q15 * S,
- q15_t * pSrc);
-
- /**
- * @brief Instance structure for the Radix-2 Q31 CFFT/CIFFT function.
- */
-
- typedef struct
- {
- uint16_t fftLen; /**< length of the FFT. */
- uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
- uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
- q31_t *pTwiddle; /**< points to the Twiddle factor table. */
- uint16_t *pBitRevTable; /**< points to the bit reversal table. */
- uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
- uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
- } arm_cfft_radix2_instance_q31;
-
- arm_status arm_cfft_radix2_init_q31(
- arm_cfft_radix2_instance_q31 * S,
- uint16_t fftLen,
- uint8_t ifftFlag,
- uint8_t bitReverseFlag);
-
- void arm_cfft_radix2_q31(
- const arm_cfft_radix2_instance_q31 * S,
- q31_t * pSrc);
-
- /**
- * @brief Instance structure for the Q31 CFFT/CIFFT function.
- */
-
- typedef struct
- {
- uint16_t fftLen; /**< length of the FFT. */
- uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
- uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
- q31_t *pTwiddle; /**< points to the twiddle factor table. */
- uint16_t *pBitRevTable; /**< points to the bit reversal table. */
- uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
- uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
- } arm_cfft_radix4_instance_q31;
-
-
- void arm_cfft_radix4_q31(
- const arm_cfft_radix4_instance_q31 * S,
- q31_t * pSrc);
-
- arm_status arm_cfft_radix4_init_q31(
- arm_cfft_radix4_instance_q31 * S,
- uint16_t fftLen,
- uint8_t ifftFlag,
- uint8_t bitReverseFlag);
-
- /**
- * @brief Instance structure for the floating-point CFFT/CIFFT function.
- */
-
- typedef struct
- {
- uint16_t fftLen; /**< length of the FFT. */
- uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
- uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
- float32_t *pTwiddle; /**< points to the Twiddle factor table. */
- uint16_t *pBitRevTable; /**< points to the bit reversal table. */
- uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
- uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
- float32_t onebyfftLen; /**< value of 1/fftLen. */
- } arm_cfft_radix2_instance_f32;
-
-/* Deprecated */
- arm_status arm_cfft_radix2_init_f32(
- arm_cfft_radix2_instance_f32 * S,
- uint16_t fftLen,
- uint8_t ifftFlag,
- uint8_t bitReverseFlag);
-
-/* Deprecated */
- void arm_cfft_radix2_f32(
- const arm_cfft_radix2_instance_f32 * S,
- float32_t * pSrc);
-
- /**
- * @brief Instance structure for the floating-point CFFT/CIFFT function.
- */
-
- typedef struct
- {
- uint16_t fftLen; /**< length of the FFT. */
- uint8_t ifftFlag; /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
- uint8_t bitReverseFlag; /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
- float32_t *pTwiddle; /**< points to the Twiddle factor table. */
- uint16_t *pBitRevTable; /**< points to the bit reversal table. */
- uint16_t twidCoefModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
- uint16_t bitRevFactor; /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
- float32_t onebyfftLen; /**< value of 1/fftLen. */
- } arm_cfft_radix4_instance_f32;
-
-/* Deprecated */
- arm_status arm_cfft_radix4_init_f32(
- arm_cfft_radix4_instance_f32 * S,
- uint16_t fftLen,
- uint8_t ifftFlag,
- uint8_t bitReverseFlag);
-
-/* Deprecated */
- void arm_cfft_radix4_f32(
- const arm_cfft_radix4_instance_f32 * S,
- float32_t * pSrc);
-
- /**
- * @brief Instance structure for the floating-point CFFT/CIFFT function.
- */
-
- typedef struct
- {
- uint16_t fftLen; /**< length of the FFT. */
- const float32_t *pTwiddle; /**< points to the Twiddle factor table. */
- const uint16_t *pBitRevTable; /**< points to the bit reversal table. */
- uint16_t bitRevLength; /**< bit reversal table length. */
- } arm_cfft_instance_f32;
-
- void arm_cfft_f32(
- const arm_cfft_instance_f32 * S,
- float32_t * p1,
- uint8_t ifftFlag,
- uint8_t bitReverseFlag);
-
- /**
- * @brief Instance structure for the Q15 RFFT/RIFFT function.
- */
-
- typedef struct
- {
- uint32_t fftLenReal; /**< length of the real FFT. */
- uint32_t fftLenBy2; /**< length of the complex FFT. */
- uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
- uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
- uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
- q15_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
- q15_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
- arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */
- } arm_rfft_instance_q15;
-
- arm_status arm_rfft_init_q15(
- arm_rfft_instance_q15 * S,
- arm_cfft_radix4_instance_q15 * S_CFFT,
- uint32_t fftLenReal,
- uint32_t ifftFlagR,
- uint32_t bitReverseFlag);
-
- void arm_rfft_q15(
- const arm_rfft_instance_q15 * S,
- q15_t * pSrc,
- q15_t * pDst);
-
- /**
- * @brief Instance structure for the Q31 RFFT/RIFFT function.
- */
-
- typedef struct
- {
- uint32_t fftLenReal; /**< length of the real FFT. */
- uint32_t fftLenBy2; /**< length of the complex FFT. */
- uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
- uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
- uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
- q31_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
- q31_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
- arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */
- } arm_rfft_instance_q31;
-
- arm_status arm_rfft_init_q31(
- arm_rfft_instance_q31 * S,
- arm_cfft_radix4_instance_q31 * S_CFFT,
- uint32_t fftLenReal,
- uint32_t ifftFlagR,
- uint32_t bitReverseFlag);
-
- void arm_rfft_q31(
- const arm_rfft_instance_q31 * S,
- q31_t * pSrc,
- q31_t * pDst);
-
- /**
- * @brief Instance structure for the floating-point RFFT/RIFFT function.
- */
-
- typedef struct
- {
- uint32_t fftLenReal; /**< length of the real FFT. */
- uint16_t fftLenBy2; /**< length of the complex FFT. */
- uint8_t ifftFlagR; /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
- uint8_t bitReverseFlagR; /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
- uint32_t twidCoefRModifier; /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
- float32_t *pTwiddleAReal; /**< points to the real twiddle factor table. */
- float32_t *pTwiddleBReal; /**< points to the imag twiddle factor table. */
- arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
- } arm_rfft_instance_f32;
-
- arm_status arm_rfft_init_f32(
- arm_rfft_instance_f32 * S,
- arm_cfft_radix4_instance_f32 * S_CFFT,
- uint32_t fftLenReal,
- uint32_t ifftFlagR,
- uint32_t bitReverseFlag);
-
- void arm_rfft_f32(
- const arm_rfft_instance_f32 * S,
- float32_t * pSrc,
- float32_t * pDst);
-
- /**
- * @brief Instance structure for the floating-point RFFT/RIFFT function.
- */
-
-typedef struct
- {
- arm_cfft_instance_f32 Sint; /**< Internal CFFT structure. */
- uint16_t fftLenRFFT; /**< length of the real sequence */
- float32_t * pTwiddleRFFT; /**< Twiddle factors real stage */
- } arm_rfft_fast_instance_f32 ;
-
-arm_status arm_rfft_fast_init_f32 (
- arm_rfft_fast_instance_f32 * S,
- uint16_t fftLen);
-
-void arm_rfft_fast_f32(
- arm_rfft_fast_instance_f32 * S,
- float32_t * p, float32_t * pOut,
- uint8_t ifftFlag);
-
- /**
- * @brief Instance structure for the floating-point DCT4/IDCT4 function.
- */
-
- typedef struct
- {
- uint16_t N; /**< length of the DCT4. */
- uint16_t Nby2; /**< half of the length of the DCT4. */
- float32_t normalize; /**< normalizing factor. */
- float32_t *pTwiddle; /**< points to the twiddle factor table. */
- float32_t *pCosFactor; /**< points to the cosFactor table. */
- arm_rfft_instance_f32 *pRfft; /**< points to the real FFT instance. */
- arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
- } arm_dct4_instance_f32;
-
- /**
- * @brief Initialization function for the floating-point DCT4/IDCT4.
- * @param[in,out] *S points to an instance of floating-point DCT4/IDCT4 structure.
- * @param[in] *S_RFFT points to an instance of floating-point RFFT/RIFFT structure.
- * @param[in] *S_CFFT points to an instance of floating-point CFFT/CIFFT structure.
- * @param[in] N length of the DCT4.
- * @param[in] Nby2 half of the length of the DCT4.
- * @param[in] normalize normalizing factor.
- * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>fftLenReal</code> is not a supported transform length.
- */
-
- arm_status arm_dct4_init_f32(
- arm_dct4_instance_f32 * S,
- arm_rfft_instance_f32 * S_RFFT,
- arm_cfft_radix4_instance_f32 * S_CFFT,
- uint16_t N,
- uint16_t Nby2,
- float32_t normalize);
-
- /**
- * @brief Processing function for the floating-point DCT4/IDCT4.
- * @param[in] *S points to an instance of the floating-point DCT4/IDCT4 structure.
- * @param[in] *pState points to state buffer.
- * @param[in,out] *pInlineBuffer points to the in-place input and output buffer.
- * @return none.
- */
-
- void arm_dct4_f32(
- const arm_dct4_instance_f32 * S,
- float32_t * pState,
- float32_t * pInlineBuffer);
-
- /**
- * @brief Instance structure for the Q31 DCT4/IDCT4 function.
- */
-
- typedef struct
- {
- uint16_t N; /**< length of the DCT4. */
- uint16_t Nby2; /**< half of the length of the DCT4. */
- q31_t normalize; /**< normalizing factor. */
- q31_t *pTwiddle; /**< points to the twiddle factor table. */
- q31_t *pCosFactor; /**< points to the cosFactor table. */
- arm_rfft_instance_q31 *pRfft; /**< points to the real FFT instance. */
- arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */
- } arm_dct4_instance_q31;
-
- /**
- * @brief Initialization function for the Q31 DCT4/IDCT4.
- * @param[in,out] *S points to an instance of Q31 DCT4/IDCT4 structure.
- * @param[in] *S_RFFT points to an instance of Q31 RFFT/RIFFT structure
- * @param[in] *S_CFFT points to an instance of Q31 CFFT/CIFFT structure
- * @param[in] N length of the DCT4.
- * @param[in] Nby2 half of the length of the DCT4.
- * @param[in] normalize normalizing factor.
- * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
- */
-
- arm_status arm_dct4_init_q31(
- arm_dct4_instance_q31 * S,
- arm_rfft_instance_q31 * S_RFFT,
- arm_cfft_radix4_instance_q31 * S_CFFT,
- uint16_t N,
- uint16_t Nby2,
- q31_t normalize);
-
- /**
- * @brief Processing function for the Q31 DCT4/IDCT4.
- * @param[in] *S points to an instance of the Q31 DCT4 structure.
- * @param[in] *pState points to state buffer.
- * @param[in,out] *pInlineBuffer points to the in-place input and output buffer.
- * @return none.
- */
-
- void arm_dct4_q31(
- const arm_dct4_instance_q31 * S,
- q31_t * pState,
- q31_t * pInlineBuffer);
-
- /**
- * @brief Instance structure for the Q15 DCT4/IDCT4 function.
- */
-
- typedef struct
- {
- uint16_t N; /**< length of the DCT4. */
- uint16_t Nby2; /**< half of the length of the DCT4. */
- q15_t normalize; /**< normalizing factor. */
- q15_t *pTwiddle; /**< points to the twiddle factor table. */
- q15_t *pCosFactor; /**< points to the cosFactor table. */
- arm_rfft_instance_q15 *pRfft; /**< points to the real FFT instance. */
- arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */
- } arm_dct4_instance_q15;
-
- /**
- * @brief Initialization function for the Q15 DCT4/IDCT4.
- * @param[in,out] *S points to an instance of Q15 DCT4/IDCT4 structure.
- * @param[in] *S_RFFT points to an instance of Q15 RFFT/RIFFT structure.
- * @param[in] *S_CFFT points to an instance of Q15 CFFT/CIFFT structure.
- * @param[in] N length of the DCT4.
- * @param[in] Nby2 half of the length of the DCT4.
- * @param[in] normalize normalizing factor.
- * @return arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if <code>N</code> is not a supported transform length.
- */
-
- arm_status arm_dct4_init_q15(
- arm_dct4_instance_q15 * S,
- arm_rfft_instance_q15 * S_RFFT,
- arm_cfft_radix4_instance_q15 * S_CFFT,
- uint16_t N,
- uint16_t Nby2,
- q15_t normalize);
-
- /**
- * @brief Processing function for the Q15 DCT4/IDCT4.
- * @param[in] *S points to an instance of the Q15 DCT4 structure.
- * @param[in] *pState points to state buffer.
- * @param[in,out] *pInlineBuffer points to the in-place input and output buffer.
- * @return none.
- */
-
- void arm_dct4_q15(
- const arm_dct4_instance_q15 * S,
- q15_t * pState,
- q15_t * pInlineBuffer);
-
- /**
- * @brief Floating-point vector addition.
- * @param[in] *pSrcA points to the first input vector
- * @param[in] *pSrcB points to the second input vector
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in each vector
- * @return none.
- */
-
- void arm_add_f32(
- float32_t * pSrcA,
- float32_t * pSrcB,
- float32_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Q7 vector addition.
- * @param[in] *pSrcA points to the first input vector
- * @param[in] *pSrcB points to the second input vector
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in each vector
- * @return none.
- */
-
- void arm_add_q7(
- q7_t * pSrcA,
- q7_t * pSrcB,
- q7_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Q15 vector addition.
- * @param[in] *pSrcA points to the first input vector
- * @param[in] *pSrcB points to the second input vector
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in each vector
- * @return none.
- */
-
- void arm_add_q15(
- q15_t * pSrcA,
- q15_t * pSrcB,
- q15_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Q31 vector addition.
- * @param[in] *pSrcA points to the first input vector
- * @param[in] *pSrcB points to the second input vector
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in each vector
- * @return none.
- */
-
- void arm_add_q31(
- q31_t * pSrcA,
- q31_t * pSrcB,
- q31_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Floating-point vector subtraction.
- * @param[in] *pSrcA points to the first input vector
- * @param[in] *pSrcB points to the second input vector
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in each vector
- * @return none.
- */
-
- void arm_sub_f32(
- float32_t * pSrcA,
- float32_t * pSrcB,
- float32_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Q7 vector subtraction.
- * @param[in] *pSrcA points to the first input vector
- * @param[in] *pSrcB points to the second input vector
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in each vector
- * @return none.
- */
-
- void arm_sub_q7(
- q7_t * pSrcA,
- q7_t * pSrcB,
- q7_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Q15 vector subtraction.
- * @param[in] *pSrcA points to the first input vector
- * @param[in] *pSrcB points to the second input vector
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in each vector
- * @return none.
- */
-
- void arm_sub_q15(
- q15_t * pSrcA,
- q15_t * pSrcB,
- q15_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Q31 vector subtraction.
- * @param[in] *pSrcA points to the first input vector
- * @param[in] *pSrcB points to the second input vector
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in each vector
- * @return none.
- */
-
- void arm_sub_q31(
- q31_t * pSrcA,
- q31_t * pSrcB,
- q31_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Multiplies a floating-point vector by a scalar.
- * @param[in] *pSrc points to the input vector
- * @param[in] scale scale factor to be applied
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- * @return none.
- */
-
- void arm_scale_f32(
- float32_t * pSrc,
- float32_t scale,
- float32_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Multiplies a Q7 vector by a scalar.
- * @param[in] *pSrc points to the input vector
- * @param[in] scaleFract fractional portion of the scale value
- * @param[in] shift number of bits to shift the result by
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- * @return none.
- */
-
- void arm_scale_q7(
- q7_t * pSrc,
- q7_t scaleFract,
- int8_t shift,
- q7_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Multiplies a Q15 vector by a scalar.
- * @param[in] *pSrc points to the input vector
- * @param[in] scaleFract fractional portion of the scale value
- * @param[in] shift number of bits to shift the result by
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- * @return none.
- */
-
- void arm_scale_q15(
- q15_t * pSrc,
- q15_t scaleFract,
- int8_t shift,
- q15_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Multiplies a Q31 vector by a scalar.
- * @param[in] *pSrc points to the input vector
- * @param[in] scaleFract fractional portion of the scale value
- * @param[in] shift number of bits to shift the result by
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- * @return none.
- */
-
- void arm_scale_q31(
- q31_t * pSrc,
- q31_t scaleFract,
- int8_t shift,
- q31_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Q7 vector absolute value.
- * @param[in] *pSrc points to the input buffer
- * @param[out] *pDst points to the output buffer
- * @param[in] blockSize number of samples in each vector
- * @return none.
- */
-
- void arm_abs_q7(
- q7_t * pSrc,
- q7_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Floating-point vector absolute value.
- * @param[in] *pSrc points to the input buffer
- * @param[out] *pDst points to the output buffer
- * @param[in] blockSize number of samples in each vector
- * @return none.
- */
-
- void arm_abs_f32(
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Q15 vector absolute value.
- * @param[in] *pSrc points to the input buffer
- * @param[out] *pDst points to the output buffer
- * @param[in] blockSize number of samples in each vector
- * @return none.
- */
-
- void arm_abs_q15(
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Q31 vector absolute value.
- * @param[in] *pSrc points to the input buffer
- * @param[out] *pDst points to the output buffer
- * @param[in] blockSize number of samples in each vector
- * @return none.
- */
-
- void arm_abs_q31(
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Dot product of floating-point vectors.
- * @param[in] *pSrcA points to the first input vector
- * @param[in] *pSrcB points to the second input vector
- * @param[in] blockSize number of samples in each vector
- * @param[out] *result output result returned here
- * @return none.
- */
-
- void arm_dot_prod_f32(
- float32_t * pSrcA,
- float32_t * pSrcB,
- uint32_t blockSize,
- float32_t * result);
-
- /**
- * @brief Dot product of Q7 vectors.
- * @param[in] *pSrcA points to the first input vector
- * @param[in] *pSrcB points to the second input vector
- * @param[in] blockSize number of samples in each vector
- * @param[out] *result output result returned here
- * @return none.
- */
-
- void arm_dot_prod_q7(
- q7_t * pSrcA,
- q7_t * pSrcB,
- uint32_t blockSize,
- q31_t * result);
-
- /**
- * @brief Dot product of Q15 vectors.
- * @param[in] *pSrcA points to the first input vector
- * @param[in] *pSrcB points to the second input vector
- * @param[in] blockSize number of samples in each vector
- * @param[out] *result output result returned here
- * @return none.
- */
-
- void arm_dot_prod_q15(
- q15_t * pSrcA,
- q15_t * pSrcB,
- uint32_t blockSize,
- q63_t * result);
-
- /**
- * @brief Dot product of Q31 vectors.
- * @param[in] *pSrcA points to the first input vector
- * @param[in] *pSrcB points to the second input vector
- * @param[in] blockSize number of samples in each vector
- * @param[out] *result output result returned here
- * @return none.
- */
-
- void arm_dot_prod_q31(
- q31_t * pSrcA,
- q31_t * pSrcB,
- uint32_t blockSize,
- q63_t * result);
-
- /**
- * @brief Shifts the elements of a Q7 vector a specified number of bits.
- * @param[in] *pSrc points to the input vector
- * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- * @return none.
- */
-
- void arm_shift_q7(
- q7_t * pSrc,
- int8_t shiftBits,
- q7_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Shifts the elements of a Q15 vector a specified number of bits.
- * @param[in] *pSrc points to the input vector
- * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- * @return none.
- */
-
- void arm_shift_q15(
- q15_t * pSrc,
- int8_t shiftBits,
- q15_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Shifts the elements of a Q31 vector a specified number of bits.
- * @param[in] *pSrc points to the input vector
- * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right.
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- * @return none.
- */
-
- void arm_shift_q31(
- q31_t * pSrc,
- int8_t shiftBits,
- q31_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Adds a constant offset to a floating-point vector.
- * @param[in] *pSrc points to the input vector
- * @param[in] offset is the offset to be added
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- * @return none.
- */
-
- void arm_offset_f32(
- float32_t * pSrc,
- float32_t offset,
- float32_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Adds a constant offset to a Q7 vector.
- * @param[in] *pSrc points to the input vector
- * @param[in] offset is the offset to be added
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- * @return none.
- */
-
- void arm_offset_q7(
- q7_t * pSrc,
- q7_t offset,
- q7_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Adds a constant offset to a Q15 vector.
- * @param[in] *pSrc points to the input vector
- * @param[in] offset is the offset to be added
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- * @return none.
- */
-
- void arm_offset_q15(
- q15_t * pSrc,
- q15_t offset,
- q15_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Adds a constant offset to a Q31 vector.
- * @param[in] *pSrc points to the input vector
- * @param[in] offset is the offset to be added
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- * @return none.
- */
-
- void arm_offset_q31(
- q31_t * pSrc,
- q31_t offset,
- q31_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Negates the elements of a floating-point vector.
- * @param[in] *pSrc points to the input vector
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- * @return none.
- */
-
- void arm_negate_f32(
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Negates the elements of a Q7 vector.
- * @param[in] *pSrc points to the input vector
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- * @return none.
- */
-
- void arm_negate_q7(
- q7_t * pSrc,
- q7_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Negates the elements of a Q15 vector.
- * @param[in] *pSrc points to the input vector
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- * @return none.
- */
-
- void arm_negate_q15(
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Negates the elements of a Q31 vector.
- * @param[in] *pSrc points to the input vector
- * @param[out] *pDst points to the output vector
- * @param[in] blockSize number of samples in the vector
- * @return none.
- */
-
- void arm_negate_q31(
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
- /**
- * @brief Copies the elements of a floating-point vector.
- * @param[in] *pSrc input pointer
- * @param[out] *pDst output pointer
- * @param[in] blockSize number of samples to process
- * @return none.
- */
- void arm_copy_f32(
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Copies the elements of a Q7 vector.
- * @param[in] *pSrc input pointer
- * @param[out] *pDst output pointer
- * @param[in] blockSize number of samples to process
- * @return none.
- */
- void arm_copy_q7(
- q7_t * pSrc,
- q7_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Copies the elements of a Q15 vector.
- * @param[in] *pSrc input pointer
- * @param[out] *pDst output pointer
- * @param[in] blockSize number of samples to process
- * @return none.
- */
- void arm_copy_q15(
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Copies the elements of a Q31 vector.
- * @param[in] *pSrc input pointer
- * @param[out] *pDst output pointer
- * @param[in] blockSize number of samples to process
- * @return none.
- */
- void arm_copy_q31(
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
- /**
- * @brief Fills a constant value into a floating-point vector.
- * @param[in] value input value to be filled
- * @param[out] *pDst output pointer
- * @param[in] blockSize number of samples to process
- * @return none.
- */
- void arm_fill_f32(
- float32_t value,
- float32_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Fills a constant value into a Q7 vector.
- * @param[in] value input value to be filled
- * @param[out] *pDst output pointer
- * @param[in] blockSize number of samples to process
- * @return none.
- */
- void arm_fill_q7(
- q7_t value,
- q7_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Fills a constant value into a Q15 vector.
- * @param[in] value input value to be filled
- * @param[out] *pDst output pointer
- * @param[in] blockSize number of samples to process
- * @return none.
- */
- void arm_fill_q15(
- q15_t value,
- q15_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Fills a constant value into a Q31 vector.
- * @param[in] value input value to be filled
- * @param[out] *pDst output pointer
- * @param[in] blockSize number of samples to process
- * @return none.
- */
- void arm_fill_q31(
- q31_t value,
- q31_t * pDst,
- uint32_t blockSize);
-
-/**
- * @brief Convolution of floating-point sequences.
- * @param[in] *pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] *pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
- * @return none.
- */
-
- void arm_conv_f32(
- float32_t * pSrcA,
- uint32_t srcALen,
- float32_t * pSrcB,
- uint32_t srcBLen,
- float32_t * pDst);
-
-
- /**
- * @brief Convolution of Q15 sequences.
- * @param[in] *pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] *pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.
- * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
- * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
- * @return none.
- */
-
-
- void arm_conv_opt_q15(
- q15_t * pSrcA,
- uint32_t srcALen,
- q15_t * pSrcB,
- uint32_t srcBLen,
- q15_t * pDst,
- q15_t * pScratch1,
- q15_t * pScratch2);
-
-
-/**
- * @brief Convolution of Q15 sequences.
- * @param[in] *pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] *pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] *pDst points to the location where the output result is written. Length srcALen+srcBLen-1.
- * @return none.
- */
-
- void arm_conv_q15(
- q15_t * pSrcA,
- uint32_t srcALen,
- q15_t * pSrcB,
- uint32_t srcBLen,
- q15_t * pDst);
-
- /**
- * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
- * @param[in] *pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] *pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.
- * @return none.
- */
-
- void arm_conv_fast_q15(
- q15_t * pSrcA,
- uint32_t srcALen,
- q15_t * pSrcB,
- uint32_t srcBLen,
- q15_t * pDst);
-
- /**
- * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
- * @param[in] *pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] *pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.
- * @param[in] *pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
- * @param[in] *pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
- * @return none.
- */
-
- void arm_conv_fast_opt_q15(
- q15_t * pSrcA,
- uint32_t srcALen,
- q15_t * pSrcB,
- uint32_t srcBLen,
- q15_t * pDst,
- q15_t * pScratch1,
- q15_t * pScratch2);
-
-
-
- /**
- * @brief Convolution of Q31 sequences.
- * @param[in] *pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] *pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.
- * @return none.
- */
-
- void arm_conv_q31(
- q31_t * pSrcA,
- uint32_t srcALen,
- q31_t * pSrcB,
- uint32_t srcBLen,
- q31_t * pDst);
-
- /**
- * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
- * @param[in] *pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] *pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.
- * @return none.
- */
-
- void arm_conv_fast_q31(
- q31_t * pSrcA,
- uint32_t srcALen,
- q31_t * pSrcB,
- uint32_t srcBLen,
- q31_t * pDst);
-
-
- /**
- * @brief Convolution of Q7 sequences.
- * @param[in] *pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] *pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.
- * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
- * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
- * @return none.
- */
-
- void arm_conv_opt_q7(
- q7_t * pSrcA,
- uint32_t srcALen,
- q7_t * pSrcB,
- uint32_t srcBLen,
- q7_t * pDst,
- q15_t * pScratch1,
- q15_t * pScratch2);
-
-
-
- /**
- * @brief Convolution of Q7 sequences.
- * @param[in] *pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] *pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] *pDst points to the block of output data Length srcALen+srcBLen-1.
- * @return none.
- */
-
- void arm_conv_q7(
- q7_t * pSrcA,
- uint32_t srcALen,
- q7_t * pSrcB,
- uint32_t srcBLen,
- q7_t * pDst);
-
-
- /**
- * @brief Partial convolution of floating-point sequences.
- * @param[in] *pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] *pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] *pDst points to the block of output data
- * @param[in] firstIndex is the first output sample to start with.
- * @param[in] numPoints is the number of output points to be computed.
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
- */
-
- arm_status arm_conv_partial_f32(
- float32_t * pSrcA,
- uint32_t srcALen,
- float32_t * pSrcB,
- uint32_t srcBLen,
- float32_t * pDst,
- uint32_t firstIndex,
- uint32_t numPoints);
-
- /**
- * @brief Partial convolution of Q15 sequences.
- * @param[in] *pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] *pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] *pDst points to the block of output data
- * @param[in] firstIndex is the first output sample to start with.
- * @param[in] numPoints is the number of output points to be computed.
- * @param[in] * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
- * @param[in] * pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
- */
-
- arm_status arm_conv_partial_opt_q15(
- q15_t * pSrcA,
- uint32_t srcALen,
- q15_t * pSrcB,
- uint32_t srcBLen,
- q15_t * pDst,
- uint32_t firstIndex,
- uint32_t numPoints,
- q15_t * pScratch1,
- q15_t * pScratch2);
-
-
-/**
- * @brief Partial convolution of Q15 sequences.
- * @param[in] *pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] *pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] *pDst points to the block of output data
- * @param[in] firstIndex is the first output sample to start with.
- * @param[in] numPoints is the number of output points to be computed.
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
- */
-
- arm_status arm_conv_partial_q15(
- q15_t * pSrcA,
- uint32_t srcALen,
- q15_t * pSrcB,
- uint32_t srcBLen,
- q15_t * pDst,
- uint32_t firstIndex,
- uint32_t numPoints);
-
- /**
- * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
- * @param[in] *pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] *pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] *pDst points to the block of output data
- * @param[in] firstIndex is the first output sample to start with.
- * @param[in] numPoints is the number of output points to be computed.
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
- */
-
- arm_status arm_conv_partial_fast_q15(
- q15_t * pSrcA,
- uint32_t srcALen,
- q15_t * pSrcB,
- uint32_t srcBLen,
- q15_t * pDst,
- uint32_t firstIndex,
- uint32_t numPoints);
-
-
- /**
- * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
- * @param[in] *pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] *pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] *pDst points to the block of output data
- * @param[in] firstIndex is the first output sample to start with.
- * @param[in] numPoints is the number of output points to be computed.
- * @param[in] * pScratch1 points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
- * @param[in] * pScratch2 points to scratch buffer of size min(srcALen, srcBLen).
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
- */
-
- arm_status arm_conv_partial_fast_opt_q15(
- q15_t * pSrcA,
- uint32_t srcALen,
- q15_t * pSrcB,
- uint32_t srcBLen,
- q15_t * pDst,
- uint32_t firstIndex,
- uint32_t numPoints,
- q15_t * pScratch1,
- q15_t * pScratch2);
-
-
- /**
- * @brief Partial convolution of Q31 sequences.
- * @param[in] *pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] *pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] *pDst points to the block of output data
- * @param[in] firstIndex is the first output sample to start with.
- * @param[in] numPoints is the number of output points to be computed.
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
- */
-
- arm_status arm_conv_partial_q31(
- q31_t * pSrcA,
- uint32_t srcALen,
- q31_t * pSrcB,
- uint32_t srcBLen,
- q31_t * pDst,
- uint32_t firstIndex,
- uint32_t numPoints);
-
-
- /**
- * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
- * @param[in] *pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] *pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] *pDst points to the block of output data
- * @param[in] firstIndex is the first output sample to start with.
- * @param[in] numPoints is the number of output points to be computed.
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
- */
-
- arm_status arm_conv_partial_fast_q31(
- q31_t * pSrcA,
- uint32_t srcALen,
- q31_t * pSrcB,
- uint32_t srcBLen,
- q31_t * pDst,
- uint32_t firstIndex,
- uint32_t numPoints);
-
-
- /**
- * @brief Partial convolution of Q7 sequences
- * @param[in] *pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] *pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] *pDst points to the block of output data
- * @param[in] firstIndex is the first output sample to start with.
- * @param[in] numPoints is the number of output points to be computed.
- * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
- * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
- */
-
- arm_status arm_conv_partial_opt_q7(
- q7_t * pSrcA,
- uint32_t srcALen,
- q7_t * pSrcB,
- uint32_t srcBLen,
- q7_t * pDst,
- uint32_t firstIndex,
- uint32_t numPoints,
- q15_t * pScratch1,
- q15_t * pScratch2);
-
-
-/**
- * @brief Partial convolution of Q7 sequences.
- * @param[in] *pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] *pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] *pDst points to the block of output data
- * @param[in] firstIndex is the first output sample to start with.
- * @param[in] numPoints is the number of output points to be computed.
- * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
- */
-
- arm_status arm_conv_partial_q7(
- q7_t * pSrcA,
- uint32_t srcALen,
- q7_t * pSrcB,
- uint32_t srcBLen,
- q7_t * pDst,
- uint32_t firstIndex,
- uint32_t numPoints);
-
-
-
- /**
- * @brief Instance structure for the Q15 FIR decimator.
- */
-
- typedef struct
- {
- uint8_t M; /**< decimation factor. */
- uint16_t numTaps; /**< number of coefficients in the filter. */
- q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
- q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
- } arm_fir_decimate_instance_q15;
-
- /**
- * @brief Instance structure for the Q31 FIR decimator.
- */
-
- typedef struct
- {
- uint8_t M; /**< decimation factor. */
- uint16_t numTaps; /**< number of coefficients in the filter. */
- q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
- q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-
- } arm_fir_decimate_instance_q31;
-
- /**
- * @brief Instance structure for the floating-point FIR decimator.
- */
-
- typedef struct
- {
- uint8_t M; /**< decimation factor. */
- uint16_t numTaps; /**< number of coefficients in the filter. */
- float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
- float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
-
- } arm_fir_decimate_instance_f32;
-
-
-
- /**
- * @brief Processing function for the floating-point FIR decimator.
- * @param[in] *S points to an instance of the floating-point FIR decimator structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data
- * @param[in] blockSize number of input samples to process per call.
- * @return none
- */
-
- void arm_fir_decimate_f32(
- const arm_fir_decimate_instance_f32 * S,
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for the floating-point FIR decimator.
- * @param[in,out] *S points to an instance of the floating-point FIR decimator structure.
- * @param[in] numTaps number of coefficients in the filter.
- * @param[in] M decimation factor.
- * @param[in] *pCoeffs points to the filter coefficients.
- * @param[in] *pState points to the state buffer.
- * @param[in] blockSize number of input samples to process per call.
- * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
- * <code>blockSize</code> is not a multiple of <code>M</code>.
- */
-
- arm_status arm_fir_decimate_init_f32(
- arm_fir_decimate_instance_f32 * S,
- uint16_t numTaps,
- uint8_t M,
- float32_t * pCoeffs,
- float32_t * pState,
- uint32_t blockSize);
-
- /**
- * @brief Processing function for the Q15 FIR decimator.
- * @param[in] *S points to an instance of the Q15 FIR decimator structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data
- * @param[in] blockSize number of input samples to process per call.
- * @return none
- */
-
- void arm_fir_decimate_q15(
- const arm_fir_decimate_instance_q15 * S,
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
- * @param[in] *S points to an instance of the Q15 FIR decimator structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data
- * @param[in] blockSize number of input samples to process per call.
- * @return none
- */
-
- void arm_fir_decimate_fast_q15(
- const arm_fir_decimate_instance_q15 * S,
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
-
-
-
- /**
- * @brief Initialization function for the Q15 FIR decimator.
- * @param[in,out] *S points to an instance of the Q15 FIR decimator structure.
- * @param[in] numTaps number of coefficients in the filter.
- * @param[in] M decimation factor.
- * @param[in] *pCoeffs points to the filter coefficients.
- * @param[in] *pState points to the state buffer.
- * @param[in] blockSize number of input samples to process per call.
- * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
- * <code>blockSize</code> is not a multiple of <code>M</code>.
- */
-
- arm_status arm_fir_decimate_init_q15(
- arm_fir_decimate_instance_q15 * S,
- uint16_t numTaps,
- uint8_t M,
- q15_t * pCoeffs,
- q15_t * pState,
- uint32_t blockSize);
-
- /**
- * @brief Processing function for the Q31 FIR decimator.
- * @param[in] *S points to an instance of the Q31 FIR decimator structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data
- * @param[in] blockSize number of input samples to process per call.
- * @return none
- */
-
- void arm_fir_decimate_q31(
- const arm_fir_decimate_instance_q31 * S,
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
- * @param[in] *S points to an instance of the Q31 FIR decimator structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data
- * @param[in] blockSize number of input samples to process per call.
- * @return none
- */
-
- void arm_fir_decimate_fast_q31(
- arm_fir_decimate_instance_q31 * S,
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for the Q31 FIR decimator.
- * @param[in,out] *S points to an instance of the Q31 FIR decimator structure.
- * @param[in] numTaps number of coefficients in the filter.
- * @param[in] M decimation factor.
- * @param[in] *pCoeffs points to the filter coefficients.
- * @param[in] *pState points to the state buffer.
- * @param[in] blockSize number of input samples to process per call.
- * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
- * <code>blockSize</code> is not a multiple of <code>M</code>.
- */
-
- arm_status arm_fir_decimate_init_q31(
- arm_fir_decimate_instance_q31 * S,
- uint16_t numTaps,
- uint8_t M,
- q31_t * pCoeffs,
- q31_t * pState,
- uint32_t blockSize);
-
-
-
- /**
- * @brief Instance structure for the Q15 FIR interpolator.
- */
-
- typedef struct
- {
- uint8_t L; /**< upsample factor. */
- uint16_t phaseLength; /**< length of each polyphase filter component. */
- q15_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
- q15_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
- } arm_fir_interpolate_instance_q15;
-
- /**
- * @brief Instance structure for the Q31 FIR interpolator.
- */
-
- typedef struct
- {
- uint8_t L; /**< upsample factor. */
- uint16_t phaseLength; /**< length of each polyphase filter component. */
- q31_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
- q31_t *pState; /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
- } arm_fir_interpolate_instance_q31;
-
- /**
- * @brief Instance structure for the floating-point FIR interpolator.
- */
-
- typedef struct
- {
- uint8_t L; /**< upsample factor. */
- uint16_t phaseLength; /**< length of each polyphase filter component. */
- float32_t *pCoeffs; /**< points to the coefficient array. The array is of length L*phaseLength. */
- float32_t *pState; /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */
- } arm_fir_interpolate_instance_f32;
-
-
- /**
- * @brief Processing function for the Q15 FIR interpolator.
- * @param[in] *S points to an instance of the Q15 FIR interpolator structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data.
- * @param[in] blockSize number of input samples to process per call.
- * @return none.
- */
-
- void arm_fir_interpolate_q15(
- const arm_fir_interpolate_instance_q15 * S,
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for the Q15 FIR interpolator.
- * @param[in,out] *S points to an instance of the Q15 FIR interpolator structure.
- * @param[in] L upsample factor.
- * @param[in] numTaps number of filter coefficients in the filter.
- * @param[in] *pCoeffs points to the filter coefficient buffer.
- * @param[in] *pState points to the state buffer.
- * @param[in] blockSize number of input samples to process per call.
- * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
- * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
- */
-
- arm_status arm_fir_interpolate_init_q15(
- arm_fir_interpolate_instance_q15 * S,
- uint8_t L,
- uint16_t numTaps,
- q15_t * pCoeffs,
- q15_t * pState,
- uint32_t blockSize);
-
- /**
- * @brief Processing function for the Q31 FIR interpolator.
- * @param[in] *S points to an instance of the Q15 FIR interpolator structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data.
- * @param[in] blockSize number of input samples to process per call.
- * @return none.
- */
-
- void arm_fir_interpolate_q31(
- const arm_fir_interpolate_instance_q31 * S,
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Initialization function for the Q31 FIR interpolator.
- * @param[in,out] *S points to an instance of the Q31 FIR interpolator structure.
- * @param[in] L upsample factor.
- * @param[in] numTaps number of filter coefficients in the filter.
- * @param[in] *pCoeffs points to the filter coefficient buffer.
- * @param[in] *pState points to the state buffer.
- * @param[in] blockSize number of input samples to process per call.
- * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
- * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
- */
-
- arm_status arm_fir_interpolate_init_q31(
- arm_fir_interpolate_instance_q31 * S,
- uint8_t L,
- uint16_t numTaps,
- q31_t * pCoeffs,
- q31_t * pState,
- uint32_t blockSize);
-
-
- /**
- * @brief Processing function for the floating-point FIR interpolator.
- * @param[in] *S points to an instance of the floating-point FIR interpolator structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data.
- * @param[in] blockSize number of input samples to process per call.
- * @return none.
- */
-
- void arm_fir_interpolate_f32(
- const arm_fir_interpolate_instance_f32 * S,
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Initialization function for the floating-point FIR interpolator.
- * @param[in,out] *S points to an instance of the floating-point FIR interpolator structure.
- * @param[in] L upsample factor.
- * @param[in] numTaps number of filter coefficients in the filter.
- * @param[in] *pCoeffs points to the filter coefficient buffer.
- * @param[in] *pState points to the state buffer.
- * @param[in] blockSize number of input samples to process per call.
- * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
- * the filter length <code>numTaps</code> is not a multiple of the interpolation factor <code>L</code>.
- */
-
- arm_status arm_fir_interpolate_init_f32(
- arm_fir_interpolate_instance_f32 * S,
- uint8_t L,
- uint16_t numTaps,
- float32_t * pCoeffs,
- float32_t * pState,
- uint32_t blockSize);
-
- /**
- * @brief Instance structure for the high precision Q31 Biquad cascade filter.
- */
-
- typedef struct
- {
- uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
- q63_t *pState; /**< points to the array of state coefficients. The array is of length 4*numStages. */
- q31_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
- uint8_t postShift; /**< additional shift, in bits, applied to each output sample. */
-
- } arm_biquad_cas_df1_32x64_ins_q31;
-
-
- /**
- * @param[in] *S points to an instance of the high precision Q31 Biquad cascade filter structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data
- * @param[in] blockSize number of samples to process.
- * @return none.
- */
-
- void arm_biquad_cas_df1_32x64_q31(
- const arm_biquad_cas_df1_32x64_ins_q31 * S,
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @param[in,out] *S points to an instance of the high precision Q31 Biquad cascade filter structure.
- * @param[in] numStages number of 2nd order stages in the filter.
- * @param[in] *pCoeffs points to the filter coefficients.
- * @param[in] *pState points to the state buffer.
- * @param[in] postShift shift to be applied to the output. Varies according to the coefficients format
- * @return none
- */
-
- void arm_biquad_cas_df1_32x64_init_q31(
- arm_biquad_cas_df1_32x64_ins_q31 * S,
- uint8_t numStages,
- q31_t * pCoeffs,
- q63_t * pState,
- uint8_t postShift);
-
-
-
- /**
- * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
- */
-
- typedef struct
- {
- uint8_t numStages; /**< number of 2nd order stages in the filter. Overall order is 2*numStages. */
- float32_t *pState; /**< points to the array of state coefficients. The array is of length 2*numStages. */
- float32_t *pCoeffs; /**< points to the array of coefficients. The array is of length 5*numStages. */
- } arm_biquad_cascade_df2T_instance_f32;
-
-
- /**
- * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
- * @param[in] *S points to an instance of the filter data structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data
- * @param[in] blockSize number of samples to process.
- * @return none.
- */
-
- void arm_biquad_cascade_df2T_f32(
- const arm_biquad_cascade_df2T_instance_f32 * S,
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for the floating-point transposed direct form II Biquad cascade filter.
- * @param[in,out] *S points to an instance of the filter data structure.
- * @param[in] numStages number of 2nd order stages in the filter.
- * @param[in] *pCoeffs points to the filter coefficients.
- * @param[in] *pState points to the state buffer.
- * @return none
- */
-
- void arm_biquad_cascade_df2T_init_f32(
- arm_biquad_cascade_df2T_instance_f32 * S,
- uint8_t numStages,
- float32_t * pCoeffs,
- float32_t * pState);
-
-
-
- /**
- * @brief Instance structure for the Q15 FIR lattice filter.
- */
-
- typedef struct
- {
- uint16_t numStages; /**< number of filter stages. */
- q15_t *pState; /**< points to the state variable array. The array is of length numStages. */
- q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
- } arm_fir_lattice_instance_q15;
-
- /**
- * @brief Instance structure for the Q31 FIR lattice filter.
- */
-
- typedef struct
- {
- uint16_t numStages; /**< number of filter stages. */
- q31_t *pState; /**< points to the state variable array. The array is of length numStages. */
- q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
- } arm_fir_lattice_instance_q31;
-
- /**
- * @brief Instance structure for the floating-point FIR lattice filter.
- */
-
- typedef struct
- {
- uint16_t numStages; /**< number of filter stages. */
- float32_t *pState; /**< points to the state variable array. The array is of length numStages. */
- float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numStages. */
- } arm_fir_lattice_instance_f32;
-
- /**
- * @brief Initialization function for the Q15 FIR lattice filter.
- * @param[in] *S points to an instance of the Q15 FIR lattice structure.
- * @param[in] numStages number of filter stages.
- * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages.
- * @param[in] *pState points to the state buffer. The array is of length numStages.
- * @return none.
- */
-
- void arm_fir_lattice_init_q15(
- arm_fir_lattice_instance_q15 * S,
- uint16_t numStages,
- q15_t * pCoeffs,
- q15_t * pState);
-
-
- /**
- * @brief Processing function for the Q15 FIR lattice filter.
- * @param[in] *S points to an instance of the Q15 FIR lattice structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- * @return none.
- */
- void arm_fir_lattice_q15(
- const arm_fir_lattice_instance_q15 * S,
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Initialization function for the Q31 FIR lattice filter.
- * @param[in] *S points to an instance of the Q31 FIR lattice structure.
- * @param[in] numStages number of filter stages.
- * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages.
- * @param[in] *pState points to the state buffer. The array is of length numStages.
- * @return none.
- */
-
- void arm_fir_lattice_init_q31(
- arm_fir_lattice_instance_q31 * S,
- uint16_t numStages,
- q31_t * pCoeffs,
- q31_t * pState);
-
-
- /**
- * @brief Processing function for the Q31 FIR lattice filter.
- * @param[in] *S points to an instance of the Q31 FIR lattice structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data
- * @param[in] blockSize number of samples to process.
- * @return none.
- */
-
- void arm_fir_lattice_q31(
- const arm_fir_lattice_instance_q31 * S,
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
-
-/**
- * @brief Initialization function for the floating-point FIR lattice filter.
- * @param[in] *S points to an instance of the floating-point FIR lattice structure.
- * @param[in] numStages number of filter stages.
- * @param[in] *pCoeffs points to the coefficient buffer. The array is of length numStages.
- * @param[in] *pState points to the state buffer. The array is of length numStages.
- * @return none.
- */
-
- void arm_fir_lattice_init_f32(
- arm_fir_lattice_instance_f32 * S,
- uint16_t numStages,
- float32_t * pCoeffs,
- float32_t * pState);
-
- /**
- * @brief Processing function for the floating-point FIR lattice filter.
- * @param[in] *S points to an instance of the floating-point FIR lattice structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data
- * @param[in] blockSize number of samples to process.
- * @return none.
- */
-
- void arm_fir_lattice_f32(
- const arm_fir_lattice_instance_f32 * S,
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Instance structure for the Q15 IIR lattice filter.
- */
- typedef struct
- {
- uint16_t numStages; /**< number of stages in the filter. */
- q15_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
- q15_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
- q15_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
- } arm_iir_lattice_instance_q15;
-
- /**
- * @brief Instance structure for the Q31 IIR lattice filter.
- */
- typedef struct
- {
- uint16_t numStages; /**< number of stages in the filter. */
- q31_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
- q31_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
- q31_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
- } arm_iir_lattice_instance_q31;
-
- /**
- * @brief Instance structure for the floating-point IIR lattice filter.
- */
- typedef struct
- {
- uint16_t numStages; /**< number of stages in the filter. */
- float32_t *pState; /**< points to the state variable array. The array is of length numStages+blockSize. */
- float32_t *pkCoeffs; /**< points to the reflection coefficient array. The array is of length numStages. */
- float32_t *pvCoeffs; /**< points to the ladder coefficient array. The array is of length numStages+1. */
- } arm_iir_lattice_instance_f32;
-
- /**
- * @brief Processing function for the floating-point IIR lattice filter.
- * @param[in] *S points to an instance of the floating-point IIR lattice structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- * @return none.
- */
-
- void arm_iir_lattice_f32(
- const arm_iir_lattice_instance_f32 * S,
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Initialization function for the floating-point IIR lattice filter.
- * @param[in] *S points to an instance of the floating-point IIR lattice structure.
- * @param[in] numStages number of stages in the filter.
- * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.
- * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.
- * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize-1.
- * @param[in] blockSize number of samples to process.
- * @return none.
- */
-
- void arm_iir_lattice_init_f32(
- arm_iir_lattice_instance_f32 * S,
- uint16_t numStages,
- float32_t * pkCoeffs,
- float32_t * pvCoeffs,
- float32_t * pState,
- uint32_t blockSize);
-
-
- /**
- * @brief Processing function for the Q31 IIR lattice filter.
- * @param[in] *S points to an instance of the Q31 IIR lattice structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- * @return none.
- */
-
- void arm_iir_lattice_q31(
- const arm_iir_lattice_instance_q31 * S,
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for the Q31 IIR lattice filter.
- * @param[in] *S points to an instance of the Q31 IIR lattice structure.
- * @param[in] numStages number of stages in the filter.
- * @param[in] *pkCoeffs points to the reflection coefficient buffer. The array is of length numStages.
- * @param[in] *pvCoeffs points to the ladder coefficient buffer. The array is of length numStages+1.
- * @param[in] *pState points to the state buffer. The array is of length numStages+blockSize.
- * @param[in] blockSize number of samples to process.
- * @return none.
- */
-
- void arm_iir_lattice_init_q31(
- arm_iir_lattice_instance_q31 * S,
- uint16_t numStages,
- q31_t * pkCoeffs,
- q31_t * pvCoeffs,
- q31_t * pState,
- uint32_t blockSize);
-
-
- /**
- * @brief Processing function for the Q15 IIR lattice filter.
- * @param[in] *S points to an instance of the Q15 IIR lattice structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data.
- * @param[in] blockSize number of samples to process.
- * @return none.
- */
-
- void arm_iir_lattice_q15(
- const arm_iir_lattice_instance_q15 * S,
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
-
-
-/**
- * @brief Initialization function for the Q15 IIR lattice filter.
- * @param[in] *S points to an instance of the fixed-point Q15 IIR lattice structure.
- * @param[in] numStages number of stages in the filter.
- * @param[in] *pkCoeffs points to reflection coefficient buffer. The array is of length numStages.
- * @param[in] *pvCoeffs points to ladder coefficient buffer. The array is of length numStages+1.
- * @param[in] *pState points to state buffer. The array is of length numStages+blockSize.
- * @param[in] blockSize number of samples to process per call.
- * @return none.
- */
-
- void arm_iir_lattice_init_q15(
- arm_iir_lattice_instance_q15 * S,
- uint16_t numStages,
- q15_t * pkCoeffs,
- q15_t * pvCoeffs,
- q15_t * pState,
- uint32_t blockSize);
-
- /**
- * @brief Instance structure for the floating-point LMS filter.
- */
-
- typedef struct
- {
- uint16_t numTaps; /**< number of coefficients in the filter. */
- float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
- float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
- float32_t mu; /**< step size that controls filter coefficient updates. */
- } arm_lms_instance_f32;
-
- /**
- * @brief Processing function for floating-point LMS filter.
- * @param[in] *S points to an instance of the floating-point LMS filter structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[in] *pRef points to the block of reference data.
- * @param[out] *pOut points to the block of output data.
- * @param[out] *pErr points to the block of error data.
- * @param[in] blockSize number of samples to process.
- * @return none.
- */
-
- void arm_lms_f32(
- const arm_lms_instance_f32 * S,
- float32_t * pSrc,
- float32_t * pRef,
- float32_t * pOut,
- float32_t * pErr,
- uint32_t blockSize);
-
- /**
- * @brief Initialization function for floating-point LMS filter.
- * @param[in] *S points to an instance of the floating-point LMS filter structure.
- * @param[in] numTaps number of filter coefficients.
- * @param[in] *pCoeffs points to the coefficient buffer.
- * @param[in] *pState points to state buffer.
- * @param[in] mu step size that controls filter coefficient updates.
- * @param[in] blockSize number of samples to process.
- * @return none.
- */
-
- void arm_lms_init_f32(
- arm_lms_instance_f32 * S,
- uint16_t numTaps,
- float32_t * pCoeffs,
- float32_t * pState,
- float32_t mu,
- uint32_t blockSize);
-
- /**
- * @brief Instance structure for the Q15 LMS filter.
- */
-
- typedef struct
- {
- uint16_t numTaps; /**< number of coefficients in the filter. */
- q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
- q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
- q15_t mu; /**< step size that controls filter coefficient updates. */
- uint32_t postShift; /**< bit shift applied to coefficients. */
- } arm_lms_instance_q15;
-
-
- /**
- * @brief Initialization function for the Q15 LMS filter.
- * @param[in] *S points to an instance of the Q15 LMS filter structure.
- * @param[in] numTaps number of filter coefficients.
- * @param[in] *pCoeffs points to the coefficient buffer.
- * @param[in] *pState points to the state buffer.
- * @param[in] mu step size that controls filter coefficient updates.
- * @param[in] blockSize number of samples to process.
- * @param[in] postShift bit shift applied to coefficients.
- * @return none.
- */
-
- void arm_lms_init_q15(
- arm_lms_instance_q15 * S,
- uint16_t numTaps,
- q15_t * pCoeffs,
- q15_t * pState,
- q15_t mu,
- uint32_t blockSize,
- uint32_t postShift);
-
- /**
- * @brief Processing function for Q15 LMS filter.
- * @param[in] *S points to an instance of the Q15 LMS filter structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[in] *pRef points to the block of reference data.
- * @param[out] *pOut points to the block of output data.
- * @param[out] *pErr points to the block of error data.
- * @param[in] blockSize number of samples to process.
- * @return none.
- */
-
- void arm_lms_q15(
- const arm_lms_instance_q15 * S,
- q15_t * pSrc,
- q15_t * pRef,
- q15_t * pOut,
- q15_t * pErr,
- uint32_t blockSize);
-
-
- /**
- * @brief Instance structure for the Q31 LMS filter.
- */
-
- typedef struct
- {
- uint16_t numTaps; /**< number of coefficients in the filter. */
- q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
- q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
- q31_t mu; /**< step size that controls filter coefficient updates. */
- uint32_t postShift; /**< bit shift applied to coefficients. */
-
- } arm_lms_instance_q31;
-
- /**
- * @brief Processing function for Q31 LMS filter.
- * @param[in] *S points to an instance of the Q15 LMS filter structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[in] *pRef points to the block of reference data.
- * @param[out] *pOut points to the block of output data.
- * @param[out] *pErr points to the block of error data.
- * @param[in] blockSize number of samples to process.
- * @return none.
- */
-
- void arm_lms_q31(
- const arm_lms_instance_q31 * S,
- q31_t * pSrc,
- q31_t * pRef,
- q31_t * pOut,
- q31_t * pErr,
- uint32_t blockSize);
-
- /**
- * @brief Initialization function for Q31 LMS filter.
- * @param[in] *S points to an instance of the Q31 LMS filter structure.
- * @param[in] numTaps number of filter coefficients.
- * @param[in] *pCoeffs points to coefficient buffer.
- * @param[in] *pState points to state buffer.
- * @param[in] mu step size that controls filter coefficient updates.
- * @param[in] blockSize number of samples to process.
- * @param[in] postShift bit shift applied to coefficients.
- * @return none.
- */
-
- void arm_lms_init_q31(
- arm_lms_instance_q31 * S,
- uint16_t numTaps,
- q31_t * pCoeffs,
- q31_t * pState,
- q31_t mu,
- uint32_t blockSize,
- uint32_t postShift);
-
- /**
- * @brief Instance structure for the floating-point normalized LMS filter.
- */
-
- typedef struct
- {
- uint16_t numTaps; /**< number of coefficients in the filter. */
- float32_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
- float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
- float32_t mu; /**< step size that control filter coefficient updates. */
- float32_t energy; /**< saves previous frame energy. */
- float32_t x0; /**< saves previous input sample. */
- } arm_lms_norm_instance_f32;
-
- /**
- * @brief Processing function for floating-point normalized LMS filter.
- * @param[in] *S points to an instance of the floating-point normalized LMS filter structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[in] *pRef points to the block of reference data.
- * @param[out] *pOut points to the block of output data.
- * @param[out] *pErr points to the block of error data.
- * @param[in] blockSize number of samples to process.
- * @return none.
- */
-
- void arm_lms_norm_f32(
- arm_lms_norm_instance_f32 * S,
- float32_t * pSrc,
- float32_t * pRef,
- float32_t * pOut,
- float32_t * pErr,
- uint32_t blockSize);
-
- /**
- * @brief Initialization function for floating-point normalized LMS filter.
- * @param[in] *S points to an instance of the floating-point LMS filter structure.
- * @param[in] numTaps number of filter coefficients.
- * @param[in] *pCoeffs points to coefficient buffer.
- * @param[in] *pState points to state buffer.
- * @param[in] mu step size that controls filter coefficient updates.
- * @param[in] blockSize number of samples to process.
- * @return none.
- */
-
- void arm_lms_norm_init_f32(
- arm_lms_norm_instance_f32 * S,
- uint16_t numTaps,
- float32_t * pCoeffs,
- float32_t * pState,
- float32_t mu,
- uint32_t blockSize);
-
-
- /**
- * @brief Instance structure for the Q31 normalized LMS filter.
- */
- typedef struct
- {
- uint16_t numTaps; /**< number of coefficients in the filter. */
- q31_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
- q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
- q31_t mu; /**< step size that controls filter coefficient updates. */
- uint8_t postShift; /**< bit shift applied to coefficients. */
- q31_t *recipTable; /**< points to the reciprocal initial value table. */
- q31_t energy; /**< saves previous frame energy. */
- q31_t x0; /**< saves previous input sample. */
- } arm_lms_norm_instance_q31;
-
- /**
- * @brief Processing function for Q31 normalized LMS filter.
- * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[in] *pRef points to the block of reference data.
- * @param[out] *pOut points to the block of output data.
- * @param[out] *pErr points to the block of error data.
- * @param[in] blockSize number of samples to process.
- * @return none.
- */
-
- void arm_lms_norm_q31(
- arm_lms_norm_instance_q31 * S,
- q31_t * pSrc,
- q31_t * pRef,
- q31_t * pOut,
- q31_t * pErr,
- uint32_t blockSize);
-
- /**
- * @brief Initialization function for Q31 normalized LMS filter.
- * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.
- * @param[in] numTaps number of filter coefficients.
- * @param[in] *pCoeffs points to coefficient buffer.
- * @param[in] *pState points to state buffer.
- * @param[in] mu step size that controls filter coefficient updates.
- * @param[in] blockSize number of samples to process.
- * @param[in] postShift bit shift applied to coefficients.
- * @return none.
- */
-
- void arm_lms_norm_init_q31(
- arm_lms_norm_instance_q31 * S,
- uint16_t numTaps,
- q31_t * pCoeffs,
- q31_t * pState,
- q31_t mu,
- uint32_t blockSize,
- uint8_t postShift);
-
- /**
- * @brief Instance structure for the Q15 normalized LMS filter.
- */
-
- typedef struct
- {
- uint16_t numTaps; /**< Number of coefficients in the filter. */
- q15_t *pState; /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
- q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps. */
- q15_t mu; /**< step size that controls filter coefficient updates. */
- uint8_t postShift; /**< bit shift applied to coefficients. */
- q15_t *recipTable; /**< Points to the reciprocal initial value table. */
- q15_t energy; /**< saves previous frame energy. */
- q15_t x0; /**< saves previous input sample. */
- } arm_lms_norm_instance_q15;
-
- /**
- * @brief Processing function for Q15 normalized LMS filter.
- * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[in] *pRef points to the block of reference data.
- * @param[out] *pOut points to the block of output data.
- * @param[out] *pErr points to the block of error data.
- * @param[in] blockSize number of samples to process.
- * @return none.
- */
-
- void arm_lms_norm_q15(
- arm_lms_norm_instance_q15 * S,
- q15_t * pSrc,
- q15_t * pRef,
- q15_t * pOut,
- q15_t * pErr,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for Q15 normalized LMS filter.
- * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.
- * @param[in] numTaps number of filter coefficients.
- * @param[in] *pCoeffs points to coefficient buffer.
- * @param[in] *pState points to state buffer.
- * @param[in] mu step size that controls filter coefficient updates.
- * @param[in] blockSize number of samples to process.
- * @param[in] postShift bit shift applied to coefficients.
- * @return none.
- */
-
- void arm_lms_norm_init_q15(
- arm_lms_norm_instance_q15 * S,
- uint16_t numTaps,
- q15_t * pCoeffs,
- q15_t * pState,
- q15_t mu,
- uint32_t blockSize,
- uint8_t postShift);
-
- /**
- * @brief Correlation of floating-point sequences.
- * @param[in] *pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] *pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
- * @return none.
- */
-
- void arm_correlate_f32(
- float32_t * pSrcA,
- uint32_t srcALen,
- float32_t * pSrcB,
- uint32_t srcBLen,
- float32_t * pDst);
-
-
- /**
- * @brief Correlation of Q15 sequences
- * @param[in] *pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] *pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
- * @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
- * @return none.
- */
- void arm_correlate_opt_q15(
- q15_t * pSrcA,
- uint32_t srcALen,
- q15_t * pSrcB,
- uint32_t srcBLen,
- q15_t * pDst,
- q15_t * pScratch);
-
-
- /**
- * @brief Correlation of Q15 sequences.
- * @param[in] *pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] *pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
- * @return none.
- */
-
- void arm_correlate_q15(
- q15_t * pSrcA,
- uint32_t srcALen,
- q15_t * pSrcB,
- uint32_t srcBLen,
- q15_t * pDst);
-
- /**
- * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
- * @param[in] *pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] *pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
- * @return none.
- */
-
- void arm_correlate_fast_q15(
- q15_t * pSrcA,
- uint32_t srcALen,
- q15_t * pSrcB,
- uint32_t srcBLen,
- q15_t * pDst);
-
-
-
- /**
- * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
- * @param[in] *pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] *pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
- * @param[in] *pScratch points to scratch buffer of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
- * @return none.
- */
-
- void arm_correlate_fast_opt_q15(
- q15_t * pSrcA,
- uint32_t srcALen,
- q15_t * pSrcB,
- uint32_t srcBLen,
- q15_t * pDst,
- q15_t * pScratch);
-
- /**
- * @brief Correlation of Q31 sequences.
- * @param[in] *pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] *pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
- * @return none.
- */
-
- void arm_correlate_q31(
- q31_t * pSrcA,
- uint32_t srcALen,
- q31_t * pSrcB,
- uint32_t srcBLen,
- q31_t * pDst);
-
- /**
- * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
- * @param[in] *pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] *pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
- * @return none.
- */
-
- void arm_correlate_fast_q31(
- q31_t * pSrcA,
- uint32_t srcALen,
- q31_t * pSrcB,
- uint32_t srcBLen,
- q31_t * pDst);
-
-
-
- /**
- * @brief Correlation of Q7 sequences.
- * @param[in] *pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] *pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
- * @param[in] *pScratch1 points to scratch buffer(of type q15_t) of size max(srcALen, srcBLen) + 2*min(srcALen, srcBLen) - 2.
- * @param[in] *pScratch2 points to scratch buffer (of type q15_t) of size min(srcALen, srcBLen).
- * @return none.
- */
-
- void arm_correlate_opt_q7(
- q7_t * pSrcA,
- uint32_t srcALen,
- q7_t * pSrcB,
- uint32_t srcBLen,
- q7_t * pDst,
- q15_t * pScratch1,
- q15_t * pScratch2);
-
-
- /**
- * @brief Correlation of Q7 sequences.
- * @param[in] *pSrcA points to the first input sequence.
- * @param[in] srcALen length of the first input sequence.
- * @param[in] *pSrcB points to the second input sequence.
- * @param[in] srcBLen length of the second input sequence.
- * @param[out] *pDst points to the block of output data Length 2 * max(srcALen, srcBLen) - 1.
- * @return none.
- */
-
- void arm_correlate_q7(
- q7_t * pSrcA,
- uint32_t srcALen,
- q7_t * pSrcB,
- uint32_t srcBLen,
- q7_t * pDst);
-
-
- /**
- * @brief Instance structure for the floating-point sparse FIR filter.
- */
- typedef struct
- {
- uint16_t numTaps; /**< number of coefficients in the filter. */
- uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
- float32_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
- float32_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
- uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
- int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
- } arm_fir_sparse_instance_f32;
-
- /**
- * @brief Instance structure for the Q31 sparse FIR filter.
- */
-
- typedef struct
- {
- uint16_t numTaps; /**< number of coefficients in the filter. */
- uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
- q31_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
- q31_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
- uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
- int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
- } arm_fir_sparse_instance_q31;
-
- /**
- * @brief Instance structure for the Q15 sparse FIR filter.
- */
-
- typedef struct
- {
- uint16_t numTaps; /**< number of coefficients in the filter. */
- uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
- q15_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
- q15_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
- uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
- int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
- } arm_fir_sparse_instance_q15;
-
- /**
- * @brief Instance structure for the Q7 sparse FIR filter.
- */
-
- typedef struct
- {
- uint16_t numTaps; /**< number of coefficients in the filter. */
- uint16_t stateIndex; /**< state buffer index. Points to the oldest sample in the state buffer. */
- q7_t *pState; /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
- q7_t *pCoeffs; /**< points to the coefficient array. The array is of length numTaps.*/
- uint16_t maxDelay; /**< maximum offset specified by the pTapDelay array. */
- int32_t *pTapDelay; /**< points to the array of delay values. The array is of length numTaps. */
- } arm_fir_sparse_instance_q7;
-
- /**
- * @brief Processing function for the floating-point sparse FIR filter.
- * @param[in] *S points to an instance of the floating-point sparse FIR structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data
- * @param[in] *pScratchIn points to a temporary buffer of size blockSize.
- * @param[in] blockSize number of input samples to process per call.
- * @return none.
- */
-
- void arm_fir_sparse_f32(
- arm_fir_sparse_instance_f32 * S,
- float32_t * pSrc,
- float32_t * pDst,
- float32_t * pScratchIn,
- uint32_t blockSize);
-
- /**
- * @brief Initialization function for the floating-point sparse FIR filter.
- * @param[in,out] *S points to an instance of the floating-point sparse FIR structure.
- * @param[in] numTaps number of nonzero coefficients in the filter.
- * @param[in] *pCoeffs points to the array of filter coefficients.
- * @param[in] *pState points to the state buffer.
- * @param[in] *pTapDelay points to the array of offset times.
- * @param[in] maxDelay maximum offset time supported.
- * @param[in] blockSize number of samples that will be processed per block.
- * @return none
- */
-
- void arm_fir_sparse_init_f32(
- arm_fir_sparse_instance_f32 * S,
- uint16_t numTaps,
- float32_t * pCoeffs,
- float32_t * pState,
- int32_t * pTapDelay,
- uint16_t maxDelay,
- uint32_t blockSize);
-
- /**
- * @brief Processing function for the Q31 sparse FIR filter.
- * @param[in] *S points to an instance of the Q31 sparse FIR structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data
- * @param[in] *pScratchIn points to a temporary buffer of size blockSize.
- * @param[in] blockSize number of input samples to process per call.
- * @return none.
- */
-
- void arm_fir_sparse_q31(
- arm_fir_sparse_instance_q31 * S,
- q31_t * pSrc,
- q31_t * pDst,
- q31_t * pScratchIn,
- uint32_t blockSize);
-
- /**
- * @brief Initialization function for the Q31 sparse FIR filter.
- * @param[in,out] *S points to an instance of the Q31 sparse FIR structure.
- * @param[in] numTaps number of nonzero coefficients in the filter.
- * @param[in] *pCoeffs points to the array of filter coefficients.
- * @param[in] *pState points to the state buffer.
- * @param[in] *pTapDelay points to the array of offset times.
- * @param[in] maxDelay maximum offset time supported.
- * @param[in] blockSize number of samples that will be processed per block.
- * @return none
- */
-
- void arm_fir_sparse_init_q31(
- arm_fir_sparse_instance_q31 * S,
- uint16_t numTaps,
- q31_t * pCoeffs,
- q31_t * pState,
- int32_t * pTapDelay,
- uint16_t maxDelay,
- uint32_t blockSize);
-
- /**
- * @brief Processing function for the Q15 sparse FIR filter.
- * @param[in] *S points to an instance of the Q15 sparse FIR structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data
- * @param[in] *pScratchIn points to a temporary buffer of size blockSize.
- * @param[in] *pScratchOut points to a temporary buffer of size blockSize.
- * @param[in] blockSize number of input samples to process per call.
- * @return none.
- */
-
- void arm_fir_sparse_q15(
- arm_fir_sparse_instance_q15 * S,
- q15_t * pSrc,
- q15_t * pDst,
- q15_t * pScratchIn,
- q31_t * pScratchOut,
- uint32_t blockSize);
-
-
- /**
- * @brief Initialization function for the Q15 sparse FIR filter.
- * @param[in,out] *S points to an instance of the Q15 sparse FIR structure.
- * @param[in] numTaps number of nonzero coefficients in the filter.
- * @param[in] *pCoeffs points to the array of filter coefficients.
- * @param[in] *pState points to the state buffer.
- * @param[in] *pTapDelay points to the array of offset times.
- * @param[in] maxDelay maximum offset time supported.
- * @param[in] blockSize number of samples that will be processed per block.
- * @return none
- */
-
- void arm_fir_sparse_init_q15(
- arm_fir_sparse_instance_q15 * S,
- uint16_t numTaps,
- q15_t * pCoeffs,
- q15_t * pState,
- int32_t * pTapDelay,
- uint16_t maxDelay,
- uint32_t blockSize);
-
- /**
- * @brief Processing function for the Q7 sparse FIR filter.
- * @param[in] *S points to an instance of the Q7 sparse FIR structure.
- * @param[in] *pSrc points to the block of input data.
- * @param[out] *pDst points to the block of output data
- * @param[in] *pScratchIn points to a temporary buffer of size blockSize.
- * @param[in] *pScratchOut points to a temporary buffer of size blockSize.
- * @param[in] blockSize number of input samples to process per call.
- * @return none.
- */
-
- void arm_fir_sparse_q7(
- arm_fir_sparse_instance_q7 * S,
- q7_t * pSrc,
- q7_t * pDst,
- q7_t * pScratchIn,
- q31_t * pScratchOut,
- uint32_t blockSize);
-
- /**
- * @brief Initialization function for the Q7 sparse FIR filter.
- * @param[in,out] *S points to an instance of the Q7 sparse FIR structure.
- * @param[in] numTaps number of nonzero coefficients in the filter.
- * @param[in] *pCoeffs points to the array of filter coefficients.
- * @param[in] *pState points to the state buffer.
- * @param[in] *pTapDelay points to the array of offset times.
- * @param[in] maxDelay maximum offset time supported.
- * @param[in] blockSize number of samples that will be processed per block.
- * @return none
- */
-
- void arm_fir_sparse_init_q7(
- arm_fir_sparse_instance_q7 * S,
- uint16_t numTaps,
- q7_t * pCoeffs,
- q7_t * pState,
- int32_t * pTapDelay,
- uint16_t maxDelay,
- uint32_t blockSize);
-
-
- /*
- * @brief Floating-point sin_cos function.
- * @param[in] theta input value in degrees
- * @param[out] *pSinVal points to the processed sine output.
- * @param[out] *pCosVal points to the processed cos output.
- * @return none.
- */
-
- void arm_sin_cos_f32(
- float32_t theta,
- float32_t * pSinVal,
- float32_t * pCcosVal);
-
- /*
- * @brief Q31 sin_cos function.
- * @param[in] theta scaled input value in degrees
- * @param[out] *pSinVal points to the processed sine output.
- * @param[out] *pCosVal points to the processed cosine output.
- * @return none.
- */
-
- void arm_sin_cos_q31(
- q31_t theta,
- q31_t * pSinVal,
- q31_t * pCosVal);
-
-
- /**
- * @brief Floating-point complex conjugate.
- * @param[in] *pSrc points to the input vector
- * @param[out] *pDst points to the output vector
- * @param[in] numSamples number of complex samples in each vector
- * @return none.
- */
-
- void arm_cmplx_conj_f32(
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t numSamples);
-
- /**
- * @brief Q31 complex conjugate.
- * @param[in] *pSrc points to the input vector
- * @param[out] *pDst points to the output vector
- * @param[in] numSamples number of complex samples in each vector
- * @return none.
- */
-
- void arm_cmplx_conj_q31(
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t numSamples);
-
- /**
- * @brief Q15 complex conjugate.
- * @param[in] *pSrc points to the input vector
- * @param[out] *pDst points to the output vector
- * @param[in] numSamples number of complex samples in each vector
- * @return none.
- */
-
- void arm_cmplx_conj_q15(
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t numSamples);
-
-
-
- /**
- * @brief Floating-point complex magnitude squared
- * @param[in] *pSrc points to the complex input vector
- * @param[out] *pDst points to the real output vector
- * @param[in] numSamples number of complex samples in the input vector
- * @return none.
- */
-
- void arm_cmplx_mag_squared_f32(
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t numSamples);
-
- /**
- * @brief Q31 complex magnitude squared
- * @param[in] *pSrc points to the complex input vector
- * @param[out] *pDst points to the real output vector
- * @param[in] numSamples number of complex samples in the input vector
- * @return none.
- */
-
- void arm_cmplx_mag_squared_q31(
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t numSamples);
-
- /**
- * @brief Q15 complex magnitude squared
- * @param[in] *pSrc points to the complex input vector
- * @param[out] *pDst points to the real output vector
- * @param[in] numSamples number of complex samples in the input vector
- * @return none.
- */
-
- void arm_cmplx_mag_squared_q15(
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t numSamples);
-
-
- /**
- * @ingroup groupController
- */
-
- /**
- * @defgroup PID PID Motor Control
- *
- * A Proportional Integral Derivative (PID) controller is a generic feedback control
- * loop mechanism widely used in industrial control systems.
- * A PID controller is the most commonly used type of feedback controller.
- *
- * This set of functions implements (PID) controllers
- * for Q15, Q31, and floating-point data types. The functions operate on a single sample
- * of data and each call to the function returns a single processed value.
- * <code>S</code> points to an instance of the PID control data structure. <code>in</code>
- * is the input sample value. The functions return the output value.
- *
- * \par Algorithm:
- * <pre>
- * y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
- * A0 = Kp + Ki + Kd
- * A1 = (-Kp ) - (2 * Kd )
- * A2 = Kd </pre>
- *
- * \par
- * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant
- *
- * \par
- * \image html PID.gif "Proportional Integral Derivative Controller"
- *
- * \par
- * The PID controller calculates an "error" value as the difference between
- * the measured output and the reference input.
- * The controller attempts to minimize the error by adjusting the process control inputs.
- * The proportional value determines the reaction to the current error,
- * the integral value determines the reaction based on the sum of recent errors,
- * and the derivative value determines the reaction based on the rate at which the error has been changing.
- *
- * \par Instance Structure
- * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure.
- * A separate instance structure must be defined for each PID Controller.
- * There are separate instance structure declarations for each of the 3 supported data types.
- *
- * \par Reset Functions
- * There is also an associated reset function for each data type which clears the state array.
- *
- * \par Initialization Functions
- * There is also an associated initialization function for each data type.
- * The initialization function performs the following operations:
- * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.
- * - Zeros out the values in the state buffer.
- *
- * \par
- * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.
- *
- * \par Fixed-Point Behavior
- * Care must be taken when using the fixed-point versions of the PID Controller functions.
- * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.
- * Refer to the function specific documentation below for usage guidelines.
- */
-
- /**
- * @addtogroup PID
- * @{
- */
-
- /**
- * @brief Process function for the floating-point PID Control.
- * @param[in,out] *S is an instance of the floating-point PID Control structure
- * @param[in] in input sample to process
- * @return out processed output sample.
- */
-
-
- static __INLINE float32_t arm_pid_f32(
- arm_pid_instance_f32 * S,
- float32_t in)
- {
- float32_t out;
-
- /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2] */
- out = (S->A0 * in) +
- (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);
-
- /* Update state */
- S->state[1] = S->state[0];
- S->state[0] = in;
- S->state[2] = out;
-
- /* return to application */
- return (out);
-
- }
-
- /**
- * @brief Process function for the Q31 PID Control.
- * @param[in,out] *S points to an instance of the Q31 PID Control structure
- * @param[in] in input sample to process
- * @return out processed output sample.
- *
- * <b>Scaling and Overflow Behavior:</b>
- * \par
- * The function is implemented using an internal 64-bit accumulator.
- * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.
- * Thus, if the accumulator result overflows it wraps around rather than clip.
- * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions.
- * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.
- */
-
- static __INLINE q31_t arm_pid_q31(
- arm_pid_instance_q31 * S,
- q31_t in)
- {
- q63_t acc;
- q31_t out;
-
- /* acc = A0 * x[n] */
- acc = (q63_t) S->A0 * in;
-
- /* acc += A1 * x[n-1] */
- acc += (q63_t) S->A1 * S->state[0];
-
- /* acc += A2 * x[n-2] */
- acc += (q63_t) S->A2 * S->state[1];
-
- /* convert output to 1.31 format to add y[n-1] */
- out = (q31_t) (acc >> 31u);
-
- /* out += y[n-1] */
- out += S->state[2];
-
- /* Update state */
- S->state[1] = S->state[0];
- S->state[0] = in;
- S->state[2] = out;
-
- /* return to application */
- return (out);
-
- }
-
- /**
- * @brief Process function for the Q15 PID Control.
- * @param[in,out] *S points to an instance of the Q15 PID Control structure
- * @param[in] in input sample to process
- * @return out processed output sample.
- *
- * <b>Scaling and Overflow Behavior:</b>
- * \par
- * The function is implemented using a 64-bit internal accumulator.
- * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result.
- * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.
- * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.
- * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.
- * Lastly, the accumulator is saturated to yield a result in 1.15 format.
- */
-
- static __INLINE q15_t arm_pid_q15(
- arm_pid_instance_q15 * S,
- q15_t in)
- {
- q63_t acc;
- q15_t out;
-
-#ifndef ARM_MATH_CM0_FAMILY
- __SIMD32_TYPE *vstate;
-
- /* Implementation of PID controller */
-
- /* acc = A0 * x[n] */
- acc = (q31_t) __SMUAD(S->A0, in);
-
- /* acc += A1 * x[n-1] + A2 * x[n-2] */
- vstate = __SIMD32_CONST(S->state);
- acc = __SMLALD(S->A1, (q31_t) *vstate, acc);
-
-#else
- /* acc = A0 * x[n] */
- acc = ((q31_t) S->A0) * in;
-
- /* acc += A1 * x[n-1] + A2 * x[n-2] */
- acc += (q31_t) S->A1 * S->state[0];
- acc += (q31_t) S->A2 * S->state[1];
-
-#endif
-
- /* acc += y[n-1] */
- acc += (q31_t) S->state[2] << 15;
-
- /* saturate the output */
- out = (q15_t) (__SSAT((acc >> 15), 16));
-
- /* Update state */
- S->state[1] = S->state[0];
- S->state[0] = in;
- S->state[2] = out;
-
- /* return to application */
- return (out);
-
- }
-
- /**
- * @} end of PID group
- */
-
-
- /**
- * @brief Floating-point matrix inverse.
- * @param[in] *src points to the instance of the input floating-point matrix structure.
- * @param[out] *dst points to the instance of the output floating-point matrix structure.
- * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
- * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
- */
-
- arm_status arm_mat_inverse_f32(
- const arm_matrix_instance_f32 * src,
- arm_matrix_instance_f32 * dst);
-
-
-
- /**
- * @ingroup groupController
- */
-
-
- /**
- * @defgroup clarke Vector Clarke Transform
- * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.
- * Generally the Clarke transform uses three-phase currents <code>Ia, Ib and Ic</code> to calculate currents
- * in the two-phase orthogonal stator axis <code>Ialpha</code> and <code>Ibeta</code>.
- * When <code>Ialpha</code> is superposed with <code>Ia</code> as shown in the figure below
- * \image html clarke.gif Stator current space vector and its components in (a,b).
- * and <code>Ia + Ib + Ic = 0</code>, in this condition <code>Ialpha</code> and <code>Ibeta</code>
- * can be calculated using only <code>Ia</code> and <code>Ib</code>.
- *
- * The function operates on a single sample of data and each call to the function returns the processed output.
- * The library provides separate functions for Q31 and floating-point data types.
- * \par Algorithm
- * \image html clarkeFormula.gif
- * where <code>Ia</code> and <code>Ib</code> are the instantaneous stator phases and
- * <code>pIalpha</code> and <code>pIbeta</code> are the two coordinates of time invariant vector.
- * \par Fixed-Point Behavior
- * Care must be taken when using the Q31 version of the Clarke transform.
- * In particular, the overflow and saturation behavior of the accumulator used must be considered.
- * Refer to the function specific documentation below for usage guidelines.
- */
-
- /**
- * @addtogroup clarke
- * @{
- */
-
- /**
- *
- * @brief Floating-point Clarke transform
- * @param[in] Ia input three-phase coordinate <code>a</code>
- * @param[in] Ib input three-phase coordinate <code>b</code>
- * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha
- * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta
- * @return none.
- */
-
- static __INLINE void arm_clarke_f32(
- float32_t Ia,
- float32_t Ib,
- float32_t * pIalpha,
- float32_t * pIbeta)
- {
- /* Calculate pIalpha using the equation, pIalpha = Ia */
- *pIalpha = Ia;
-
- /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */
- *pIbeta =
- ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);
-
- }
-
- /**
- * @brief Clarke transform for Q31 version
- * @param[in] Ia input three-phase coordinate <code>a</code>
- * @param[in] Ib input three-phase coordinate <code>b</code>
- * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha
- * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta
- * @return none.
- *
- * <b>Scaling and Overflow Behavior:</b>
- * \par
- * The function is implemented using an internal 32-bit accumulator.
- * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
- * There is saturation on the addition, hence there is no risk of overflow.
- */
-
- static __INLINE void arm_clarke_q31(
- q31_t Ia,
- q31_t Ib,
- q31_t * pIalpha,
- q31_t * pIbeta)
- {
- q31_t product1, product2; /* Temporary variables used to store intermediate results */
-
- /* Calculating pIalpha from Ia by equation pIalpha = Ia */
- *pIalpha = Ia;
-
- /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */
- product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);
-
- /* Intermediate product is calculated by (2/sqrt(3) * Ib) */
- product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);
-
- /* pIbeta is calculated by adding the intermediate products */
- *pIbeta = __QADD(product1, product2);
- }
-
- /**
- * @} end of clarke group
- */
-
- /**
- * @brief Converts the elements of the Q7 vector to Q31 vector.
- * @param[in] *pSrc input pointer
- * @param[out] *pDst output pointer
- * @param[in] blockSize number of samples to process
- * @return none.
- */
- void arm_q7_to_q31(
- q7_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
-
-
-
-
- /**
- * @ingroup groupController
- */
-
- /**
- * @defgroup inv_clarke Vector Inverse Clarke Transform
- * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.
- *
- * The function operates on a single sample of data and each call to the function returns the processed output.
- * The library provides separate functions for Q31 and floating-point data types.
- * \par Algorithm
- * \image html clarkeInvFormula.gif
- * where <code>pIa</code> and <code>pIb</code> are the instantaneous stator phases and
- * <code>Ialpha</code> and <code>Ibeta</code> are the two coordinates of time invariant vector.
- * \par Fixed-Point Behavior
- * Care must be taken when using the Q31 version of the Clarke transform.
- * In particular, the overflow and saturation behavior of the accumulator used must be considered.
- * Refer to the function specific documentation below for usage guidelines.
- */
-
- /**
- * @addtogroup inv_clarke
- * @{
- */
-
- /**
- * @brief Floating-point Inverse Clarke transform
- * @param[in] Ialpha input two-phase orthogonal vector axis alpha
- * @param[in] Ibeta input two-phase orthogonal vector axis beta
- * @param[out] *pIa points to output three-phase coordinate <code>a</code>
- * @param[out] *pIb points to output three-phase coordinate <code>b</code>
- * @return none.
- */
-
-
- static __INLINE void arm_inv_clarke_f32(
- float32_t Ialpha,
- float32_t Ibeta,
- float32_t * pIa,
- float32_t * pIb)
- {
- /* Calculating pIa from Ialpha by equation pIa = Ialpha */
- *pIa = Ialpha;
-
- /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */
- *pIb = -0.5 * Ialpha + (float32_t) 0.8660254039 *Ibeta;
-
- }
-
- /**
- * @brief Inverse Clarke transform for Q31 version
- * @param[in] Ialpha input two-phase orthogonal vector axis alpha
- * @param[in] Ibeta input two-phase orthogonal vector axis beta
- * @param[out] *pIa points to output three-phase coordinate <code>a</code>
- * @param[out] *pIb points to output three-phase coordinate <code>b</code>
- * @return none.
- *
- * <b>Scaling and Overflow Behavior:</b>
- * \par
- * The function is implemented using an internal 32-bit accumulator.
- * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
- * There is saturation on the subtraction, hence there is no risk of overflow.
- */
-
- static __INLINE void arm_inv_clarke_q31(
- q31_t Ialpha,
- q31_t Ibeta,
- q31_t * pIa,
- q31_t * pIb)
- {
- q31_t product1, product2; /* Temporary variables used to store intermediate results */
-
- /* Calculating pIa from Ialpha by equation pIa = Ialpha */
- *pIa = Ialpha;
-
- /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */
- product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);
-
- /* Intermediate product is calculated by (1/sqrt(3) * pIb) */
- product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);
-
- /* pIb is calculated by subtracting the products */
- *pIb = __QSUB(product2, product1);
-
- }
-
- /**
- * @} end of inv_clarke group
- */
-
- /**
- * @brief Converts the elements of the Q7 vector to Q15 vector.
- * @param[in] *pSrc input pointer
- * @param[out] *pDst output pointer
- * @param[in] blockSize number of samples to process
- * @return none.
- */
- void arm_q7_to_q15(
- q7_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
-
-
-
- /**
- * @ingroup groupController
- */
-
- /**
- * @defgroup park Vector Park Transform
- *
- * Forward Park transform converts the input two-coordinate vector to flux and torque components.
- * The Park transform can be used to realize the transformation of the <code>Ialpha</code> and the <code>Ibeta</code> currents
- * from the stationary to the moving reference frame and control the spatial relationship between
- * the stator vector current and rotor flux vector.
- * If we consider the d axis aligned with the rotor flux, the diagram below shows the
- * current vector and the relationship from the two reference frames:
- * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame"
- *
- * The function operates on a single sample of data and each call to the function returns the processed output.
- * The library provides separate functions for Q31 and floating-point data types.
- * \par Algorithm
- * \image html parkFormula.gif
- * where <code>Ialpha</code> and <code>Ibeta</code> are the stator vector components,
- * <code>pId</code> and <code>pIq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
- * cosine and sine values of theta (rotor flux position).
- * \par Fixed-Point Behavior
- * Care must be taken when using the Q31 version of the Park transform.
- * In particular, the overflow and saturation behavior of the accumulator used must be considered.
- * Refer to the function specific documentation below for usage guidelines.
- */
-
- /**
- * @addtogroup park
- * @{
- */
-
- /**
- * @brief Floating-point Park transform
- * @param[in] Ialpha input two-phase vector coordinate alpha
- * @param[in] Ibeta input two-phase vector coordinate beta
- * @param[out] *pId points to output rotor reference frame d
- * @param[out] *pIq points to output rotor reference frame q
- * @param[in] sinVal sine value of rotation angle theta
- * @param[in] cosVal cosine value of rotation angle theta
- * @return none.
- *
- * The function implements the forward Park transform.
- *
- */
-
- static __INLINE void arm_park_f32(
- float32_t Ialpha,
- float32_t Ibeta,
- float32_t * pId,
- float32_t * pIq,
- float32_t sinVal,
- float32_t cosVal)
- {
- /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */
- *pId = Ialpha * cosVal + Ibeta * sinVal;
-
- /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */
- *pIq = -Ialpha * sinVal + Ibeta * cosVal;
-
- }
-
- /**
- * @brief Park transform for Q31 version
- * @param[in] Ialpha input two-phase vector coordinate alpha
- * @param[in] Ibeta input two-phase vector coordinate beta
- * @param[out] *pId points to output rotor reference frame d
- * @param[out] *pIq points to output rotor reference frame q
- * @param[in] sinVal sine value of rotation angle theta
- * @param[in] cosVal cosine value of rotation angle theta
- * @return none.
- *
- * <b>Scaling and Overflow Behavior:</b>
- * \par
- * The function is implemented using an internal 32-bit accumulator.
- * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
- * There is saturation on the addition and subtraction, hence there is no risk of overflow.
- */
-
-
- static __INLINE void arm_park_q31(
- q31_t Ialpha,
- q31_t Ibeta,
- q31_t * pId,
- q31_t * pIq,
- q31_t sinVal,
- q31_t cosVal)
- {
- q31_t product1, product2; /* Temporary variables used to store intermediate results */
- q31_t product3, product4; /* Temporary variables used to store intermediate results */
-
- /* Intermediate product is calculated by (Ialpha * cosVal) */
- product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);
-
- /* Intermediate product is calculated by (Ibeta * sinVal) */
- product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);
-
-
- /* Intermediate product is calculated by (Ialpha * sinVal) */
- product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);
-
- /* Intermediate product is calculated by (Ibeta * cosVal) */
- product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);
-
- /* Calculate pId by adding the two intermediate products 1 and 2 */
- *pId = __QADD(product1, product2);
-
- /* Calculate pIq by subtracting the two intermediate products 3 from 4 */
- *pIq = __QSUB(product4, product3);
- }
-
- /**
- * @} end of park group
- */
-
- /**
- * @brief Converts the elements of the Q7 vector to floating-point vector.
- * @param[in] *pSrc is input pointer
- * @param[out] *pDst is output pointer
- * @param[in] blockSize is the number of samples to process
- * @return none.
- */
- void arm_q7_to_float(
- q7_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @ingroup groupController
- */
-
- /**
- * @defgroup inv_park Vector Inverse Park transform
- * Inverse Park transform converts the input flux and torque components to two-coordinate vector.
- *
- * The function operates on a single sample of data and each call to the function returns the processed output.
- * The library provides separate functions for Q31 and floating-point data types.
- * \par Algorithm
- * \image html parkInvFormula.gif
- * where <code>pIalpha</code> and <code>pIbeta</code> are the stator vector components,
- * <code>Id</code> and <code>Iq</code> are rotor vector components and <code>cosVal</code> and <code>sinVal</code> are the
- * cosine and sine values of theta (rotor flux position).
- * \par Fixed-Point Behavior
- * Care must be taken when using the Q31 version of the Park transform.
- * In particular, the overflow and saturation behavior of the accumulator used must be considered.
- * Refer to the function specific documentation below for usage guidelines.
- */
-
- /**
- * @addtogroup inv_park
- * @{
- */
-
- /**
- * @brief Floating-point Inverse Park transform
- * @param[in] Id input coordinate of rotor reference frame d
- * @param[in] Iq input coordinate of rotor reference frame q
- * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha
- * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta
- * @param[in] sinVal sine value of rotation angle theta
- * @param[in] cosVal cosine value of rotation angle theta
- * @return none.
- */
-
- static __INLINE void arm_inv_park_f32(
- float32_t Id,
- float32_t Iq,
- float32_t * pIalpha,
- float32_t * pIbeta,
- float32_t sinVal,
- float32_t cosVal)
- {
- /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */
- *pIalpha = Id * cosVal - Iq * sinVal;
-
- /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */
- *pIbeta = Id * sinVal + Iq * cosVal;
-
- }
-
-
- /**
- * @brief Inverse Park transform for Q31 version
- * @param[in] Id input coordinate of rotor reference frame d
- * @param[in] Iq input coordinate of rotor reference frame q
- * @param[out] *pIalpha points to output two-phase orthogonal vector axis alpha
- * @param[out] *pIbeta points to output two-phase orthogonal vector axis beta
- * @param[in] sinVal sine value of rotation angle theta
- * @param[in] cosVal cosine value of rotation angle theta
- * @return none.
- *
- * <b>Scaling and Overflow Behavior:</b>
- * \par
- * The function is implemented using an internal 32-bit accumulator.
- * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
- * There is saturation on the addition, hence there is no risk of overflow.
- */
-
-
- static __INLINE void arm_inv_park_q31(
- q31_t Id,
- q31_t Iq,
- q31_t * pIalpha,
- q31_t * pIbeta,
- q31_t sinVal,
- q31_t cosVal)
- {
- q31_t product1, product2; /* Temporary variables used to store intermediate results */
- q31_t product3, product4; /* Temporary variables used to store intermediate results */
-
- /* Intermediate product is calculated by (Id * cosVal) */
- product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);
-
- /* Intermediate product is calculated by (Iq * sinVal) */
- product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);
-
-
- /* Intermediate product is calculated by (Id * sinVal) */
- product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);
-
- /* Intermediate product is calculated by (Iq * cosVal) */
- product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);
-
- /* Calculate pIalpha by using the two intermediate products 1 and 2 */
- *pIalpha = __QSUB(product1, product2);
-
- /* Calculate pIbeta by using the two intermediate products 3 and 4 */
- *pIbeta = __QADD(product4, product3);
-
- }
-
- /**
- * @} end of Inverse park group
- */
-
-
- /**
- * @brief Converts the elements of the Q31 vector to floating-point vector.
- * @param[in] *pSrc is input pointer
- * @param[out] *pDst is output pointer
- * @param[in] blockSize is the number of samples to process
- * @return none.
- */
- void arm_q31_to_float(
- q31_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
-
- /**
- * @ingroup groupInterpolation
- */
-
- /**
- * @defgroup LinearInterpolate Linear Interpolation
- *
- * Linear interpolation is a method of curve fitting using linear polynomials.
- * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line
- *
- * \par
- * \image html LinearInterp.gif "Linear interpolation"
- *
- * \par
- * A Linear Interpolate function calculates an output value(y), for the input(x)
- * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)
- *
- * \par Algorithm:
- * <pre>
- * y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
- * where x0, x1 are nearest values of input x
- * y0, y1 are nearest values to output y
- * </pre>
- *
- * \par
- * This set of functions implements Linear interpolation process
- * for Q7, Q15, Q31, and floating-point data types. The functions operate on a single
- * sample of data and each call to the function returns a single processed value.
- * <code>S</code> points to an instance of the Linear Interpolate function data structure.
- * <code>x</code> is the input sample value. The functions returns the output value.
- *
- * \par
- * if x is outside of the table boundary, Linear interpolation returns first value of the table
- * if x is below input range and returns last value of table if x is above range.
- */
-
- /**
- * @addtogroup LinearInterpolate
- * @{
- */
-
- /**
- * @brief Process function for the floating-point Linear Interpolation Function.
- * @param[in,out] *S is an instance of the floating-point Linear Interpolation structure
- * @param[in] x input sample to process
- * @return y processed output sample.
- *
- */
-
- static __INLINE float32_t arm_linear_interp_f32(
- arm_linear_interp_instance_f32 * S,
- float32_t x)
- {
-
- float32_t y;
- float32_t x0, x1; /* Nearest input values */
- float32_t y0, y1; /* Nearest output values */
- float32_t xSpacing = S->xSpacing; /* spacing between input values */
- int32_t i; /* Index variable */
- float32_t *pYData = S->pYData; /* pointer to output table */
-
- /* Calculation of index */
- i = (int32_t) ((x - S->x1) / xSpacing);
-
- if(i < 0)
- {
- /* Iniatilize output for below specified range as least output value of table */
- y = pYData[0];
- }
- else if((uint32_t)i >= S->nValues)
- {
- /* Iniatilize output for above specified range as last output value of table */
- y = pYData[S->nValues - 1];
- }
- else
- {
- /* Calculation of nearest input values */
- x0 = S->x1 + i * xSpacing;
- x1 = S->x1 + (i + 1) * xSpacing;
-
- /* Read of nearest output values */
- y0 = pYData[i];
- y1 = pYData[i + 1];
-
- /* Calculation of output */
- y = y0 + (x - x0) * ((y1 - y0) / (x1 - x0));
-
- }
-
- /* returns output value */
- return (y);
- }
-
- /**
- *
- * @brief Process function for the Q31 Linear Interpolation Function.
- * @param[in] *pYData pointer to Q31 Linear Interpolation table
- * @param[in] x input sample to process
- * @param[in] nValues number of table values
- * @return y processed output sample.
- *
- * \par
- * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
- * This function can support maximum of table size 2^12.
- *
- */
-
-
- static __INLINE q31_t arm_linear_interp_q31(
- q31_t * pYData,
- q31_t x,
- uint32_t nValues)
- {
- q31_t y; /* output */
- q31_t y0, y1; /* Nearest output values */
- q31_t fract; /* fractional part */
- int32_t index; /* Index to read nearest output values */
-
- /* Input is in 12.20 format */
- /* 12 bits for the table index */
- /* Index value calculation */
- index = ((x & 0xFFF00000) >> 20);
-
- if(index >= (int32_t)(nValues - 1))
- {
- return (pYData[nValues - 1]);
- }
- else if(index < 0)
- {
- return (pYData[0]);
- }
- else
- {
-
- /* 20 bits for the fractional part */
- /* shift left by 11 to keep fract in 1.31 format */
- fract = (x & 0x000FFFFF) << 11;
-
- /* Read two nearest output values from the index in 1.31(q31) format */
- y0 = pYData[index];
- y1 = pYData[index + 1u];
-
- /* Calculation of y0 * (1-fract) and y is in 2.30 format */
- y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));
-
- /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */
- y += ((q31_t) (((q63_t) y1 * fract) >> 32));
-
- /* Convert y to 1.31 format */
- return (y << 1u);
-
- }
-
- }
-
- /**
- *
- * @brief Process function for the Q15 Linear Interpolation Function.
- * @param[in] *pYData pointer to Q15 Linear Interpolation table
- * @param[in] x input sample to process
- * @param[in] nValues number of table values
- * @return y processed output sample.
- *
- * \par
- * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
- * This function can support maximum of table size 2^12.
- *
- */
-
-
- static __INLINE q15_t arm_linear_interp_q15(
- q15_t * pYData,
- q31_t x,
- uint32_t nValues)
- {
- q63_t y; /* output */
- q15_t y0, y1; /* Nearest output values */
- q31_t fract; /* fractional part */
- int32_t index; /* Index to read nearest output values */
-
- /* Input is in 12.20 format */
- /* 12 bits for the table index */
- /* Index value calculation */
- index = ((x & 0xFFF00000) >> 20u);
-
- if(index >= (int32_t)(nValues - 1))
- {
- return (pYData[nValues - 1]);
- }
- else if(index < 0)
- {
- return (pYData[0]);
- }
- else
- {
- /* 20 bits for the fractional part */
- /* fract is in 12.20 format */
- fract = (x & 0x000FFFFF);
-
- /* Read two nearest output values from the index */
- y0 = pYData[index];
- y1 = pYData[index + 1u];
-
- /* Calculation of y0 * (1-fract) and y is in 13.35 format */
- y = ((q63_t) y0 * (0xFFFFF - fract));
-
- /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */
- y += ((q63_t) y1 * (fract));
-
- /* convert y to 1.15 format */
- return (y >> 20);
- }
-
-
- }
-
- /**
- *
- * @brief Process function for the Q7 Linear Interpolation Function.
- * @param[in] *pYData pointer to Q7 Linear Interpolation table
- * @param[in] x input sample to process
- * @param[in] nValues number of table values
- * @return y processed output sample.
- *
- * \par
- * Input sample <code>x</code> is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
- * This function can support maximum of table size 2^12.
- */
-
-
- static __INLINE q7_t arm_linear_interp_q7(
- q7_t * pYData,
- q31_t x,
- uint32_t nValues)
- {
- q31_t y; /* output */
- q7_t y0, y1; /* Nearest output values */
- q31_t fract; /* fractional part */
- uint32_t index; /* Index to read nearest output values */
-
- /* Input is in 12.20 format */
- /* 12 bits for the table index */
- /* Index value calculation */
- if (x < 0)
- {
- return (pYData[0]);
- }
- index = (x >> 20) & 0xfff;
-
-
- if(index >= (nValues - 1))
- {
- return (pYData[nValues - 1]);
- }
- else
- {
-
- /* 20 bits for the fractional part */
- /* fract is in 12.20 format */
- fract = (x & 0x000FFFFF);
-
- /* Read two nearest output values from the index and are in 1.7(q7) format */
- y0 = pYData[index];
- y1 = pYData[index + 1u];
-
- /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */
- y = ((y0 * (0xFFFFF - fract)));
-
- /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */
- y += (y1 * fract);
-
- /* convert y to 1.7(q7) format */
- return (y >> 20u);
-
- }
-
- }
- /**
- * @} end of LinearInterpolate group
- */
-
- /**
- * @brief Fast approximation to the trigonometric sine function for floating-point data.
- * @param[in] x input value in radians.
- * @return sin(x).
- */
-
- float32_t arm_sin_f32(
- float32_t x);
-
- /**
- * @brief Fast approximation to the trigonometric sine function for Q31 data.
- * @param[in] x Scaled input value in radians.
- * @return sin(x).
- */
-
- q31_t arm_sin_q31(
- q31_t x);
-
- /**
- * @brief Fast approximation to the trigonometric sine function for Q15 data.
- * @param[in] x Scaled input value in radians.
- * @return sin(x).
- */
-
- q15_t arm_sin_q15(
- q15_t x);
-
- /**
- * @brief Fast approximation to the trigonometric cosine function for floating-point data.
- * @param[in] x input value in radians.
- * @return cos(x).
- */
-
- float32_t arm_cos_f32(
- float32_t x);
-
- /**
- * @brief Fast approximation to the trigonometric cosine function for Q31 data.
- * @param[in] x Scaled input value in radians.
- * @return cos(x).
- */
-
- q31_t arm_cos_q31(
- q31_t x);
-
- /**
- * @brief Fast approximation to the trigonometric cosine function for Q15 data.
- * @param[in] x Scaled input value in radians.
- * @return cos(x).
- */
-
- q15_t arm_cos_q15(
- q15_t x);
-
-
- /**
- * @ingroup groupFastMath
- */
-
-
- /**
- * @defgroup SQRT Square Root
- *
- * Computes the square root of a number.
- * There are separate functions for Q15, Q31, and floating-point data types.
- * The square root function is computed using the Newton-Raphson algorithm.
- * This is an iterative algorithm of the form:
- * <pre>
- * x1 = x0 - f(x0)/f'(x0)
- * </pre>
- * where <code>x1</code> is the current estimate,
- * <code>x0</code> is the previous estimate, and
- * <code>f'(x0)</code> is the derivative of <code>f()</code> evaluated at <code>x0</code>.
- * For the square root function, the algorithm reduces to:
- * <pre>
- * x0 = in/2 [initial guess]
- * x1 = 1/2 * ( x0 + in / x0) [each iteration]
- * </pre>
- */
-
-
- /**
- * @addtogroup SQRT
- * @{
- */
-
- /**
- * @brief Floating-point square root function.
- * @param[in] in input value.
- * @param[out] *pOut square root of input value.
- * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
- * <code>in</code> is negative value and returns zero output for negative values.
- */
-
- static __INLINE arm_status arm_sqrt_f32(
- float32_t in,
- float32_t * pOut)
- {
- if(in > 0)
- {
-
-// #if __FPU_USED
-#if (__FPU_USED == 1) && defined ( __CC_ARM )
- *pOut = __sqrtf(in);
-#else
- *pOut = sqrtf(in);
-#endif
-
- return (ARM_MATH_SUCCESS);
- }
- else
- {
- *pOut = 0.0f;
- return (ARM_MATH_ARGUMENT_ERROR);
- }
-
- }
-
-
- /**
- * @brief Q31 square root function.
- * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.
- * @param[out] *pOut square root of input value.
- * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
- * <code>in</code> is negative value and returns zero output for negative values.
- */
- arm_status arm_sqrt_q31(
- q31_t in,
- q31_t * pOut);
-
- /**
- * @brief Q15 square root function.
- * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF.
- * @param[out] *pOut square root of input value.
- * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
- * <code>in</code> is negative value and returns zero output for negative values.
- */
- arm_status arm_sqrt_q15(
- q15_t in,
- q15_t * pOut);
-
- /**
- * @} end of SQRT group
- */
-
-
-
-
-
-
- /**
- * @brief floating-point Circular write function.
- */
-
- static __INLINE void arm_circularWrite_f32(
- int32_t * circBuffer,
- int32_t L,
- uint16_t * writeOffset,
- int32_t bufferInc,
- const int32_t * src,
- int32_t srcInc,
- uint32_t blockSize)
- {
- uint32_t i = 0u;
- int32_t wOffset;
-
- /* Copy the value of Index pointer that points
- * to the current location where the input samples to be copied */
- wOffset = *writeOffset;
-
- /* Loop over the blockSize */
- i = blockSize;
-
- while(i > 0u)
- {
- /* copy the input sample to the circular buffer */
- circBuffer[wOffset] = *src;
-
- /* Update the input pointer */
- src += srcInc;
-
- /* Circularly update wOffset. Watch out for positive and negative value */
- wOffset += bufferInc;
- if(wOffset >= L)
- wOffset -= L;
-
- /* Decrement the loop counter */
- i--;
- }
-
- /* Update the index pointer */
- *writeOffset = wOffset;
- }
-
-
-
- /**
- * @brief floating-point Circular Read function.
- */
- static __INLINE void arm_circularRead_f32(
- int32_t * circBuffer,
- int32_t L,
- int32_t * readOffset,
- int32_t bufferInc,
- int32_t * dst,
- int32_t * dst_base,
- int32_t dst_length,
- int32_t dstInc,
- uint32_t blockSize)
- {
- uint32_t i = 0u;
- int32_t rOffset, dst_end;
-
- /* Copy the value of Index pointer that points
- * to the current location from where the input samples to be read */
- rOffset = *readOffset;
- dst_end = (int32_t) (dst_base + dst_length);
-
- /* Loop over the blockSize */
- i = blockSize;
-
- while(i > 0u)
- {
- /* copy the sample from the circular buffer to the destination buffer */
- *dst = circBuffer[rOffset];
-
- /* Update the input pointer */
- dst += dstInc;
-
- if(dst == (int32_t *) dst_end)
- {
- dst = dst_base;
- }
-
- /* Circularly update rOffset. Watch out for positive and negative value */
- rOffset += bufferInc;
-
- if(rOffset >= L)
- {
- rOffset -= L;
- }
-
- /* Decrement the loop counter */
- i--;
- }
-
- /* Update the index pointer */
- *readOffset = rOffset;
- }
-
- /**
- * @brief Q15 Circular write function.
- */
-
- static __INLINE void arm_circularWrite_q15(
- q15_t * circBuffer,
- int32_t L,
- uint16_t * writeOffset,
- int32_t bufferInc,
- const q15_t * src,
- int32_t srcInc,
- uint32_t blockSize)
- {
- uint32_t i = 0u;
- int32_t wOffset;
-
- /* Copy the value of Index pointer that points
- * to the current location where the input samples to be copied */
- wOffset = *writeOffset;
-
- /* Loop over the blockSize */
- i = blockSize;
-
- while(i > 0u)
- {
- /* copy the input sample to the circular buffer */
- circBuffer[wOffset] = *src;
-
- /* Update the input pointer */
- src += srcInc;
-
- /* Circularly update wOffset. Watch out for positive and negative value */
- wOffset += bufferInc;
- if(wOffset >= L)
- wOffset -= L;
-
- /* Decrement the loop counter */
- i--;
- }
-
- /* Update the index pointer */
- *writeOffset = wOffset;
- }
-
-
-
- /**
- * @brief Q15 Circular Read function.
- */
- static __INLINE void arm_circularRead_q15(
- q15_t * circBuffer,
- int32_t L,
- int32_t * readOffset,
- int32_t bufferInc,
- q15_t * dst,
- q15_t * dst_base,
- int32_t dst_length,
- int32_t dstInc,
- uint32_t blockSize)
- {
- uint32_t i = 0;
- int32_t rOffset, dst_end;
-
- /* Copy the value of Index pointer that points
- * to the current location from where the input samples to be read */
- rOffset = *readOffset;
-
- dst_end = (int32_t) (dst_base + dst_length);
-
- /* Loop over the blockSize */
- i = blockSize;
-
- while(i > 0u)
- {
- /* copy the sample from the circular buffer to the destination buffer */
- *dst = circBuffer[rOffset];
-
- /* Update the input pointer */
- dst += dstInc;
-
- if(dst == (q15_t *) dst_end)
- {
- dst = dst_base;
- }
-
- /* Circularly update wOffset. Watch out for positive and negative value */
- rOffset += bufferInc;
-
- if(rOffset >= L)
- {
- rOffset -= L;
- }
-
- /* Decrement the loop counter */
- i--;
- }
-
- /* Update the index pointer */
- *readOffset = rOffset;
- }
-
-
- /**
- * @brief Q7 Circular write function.
- */
-
- static __INLINE void arm_circularWrite_q7(
- q7_t * circBuffer,
- int32_t L,
- uint16_t * writeOffset,
- int32_t bufferInc,
- const q7_t * src,
- int32_t srcInc,
- uint32_t blockSize)
- {
- uint32_t i = 0u;
- int32_t wOffset;
-
- /* Copy the value of Index pointer that points
- * to the current location where the input samples to be copied */
- wOffset = *writeOffset;
-
- /* Loop over the blockSize */
- i = blockSize;
-
- while(i > 0u)
- {
- /* copy the input sample to the circular buffer */
- circBuffer[wOffset] = *src;
-
- /* Update the input pointer */
- src += srcInc;
-
- /* Circularly update wOffset. Watch out for positive and negative value */
- wOffset += bufferInc;
- if(wOffset >= L)
- wOffset -= L;
-
- /* Decrement the loop counter */
- i--;
- }
-
- /* Update the index pointer */
- *writeOffset = wOffset;
- }
-
-
-
- /**
- * @brief Q7 Circular Read function.
- */
- static __INLINE void arm_circularRead_q7(
- q7_t * circBuffer,
- int32_t L,
- int32_t * readOffset,
- int32_t bufferInc,
- q7_t * dst,
- q7_t * dst_base,
- int32_t dst_length,
- int32_t dstInc,
- uint32_t blockSize)
- {
- uint32_t i = 0;
- int32_t rOffset, dst_end;
-
- /* Copy the value of Index pointer that points
- * to the current location from where the input samples to be read */
- rOffset = *readOffset;
-
- dst_end = (int32_t) (dst_base + dst_length);
-
- /* Loop over the blockSize */
- i = blockSize;
-
- while(i > 0u)
- {
- /* copy the sample from the circular buffer to the destination buffer */
- *dst = circBuffer[rOffset];
-
- /* Update the input pointer */
- dst += dstInc;
-
- if(dst == (q7_t *) dst_end)
- {
- dst = dst_base;
- }
-
- /* Circularly update rOffset. Watch out for positive and negative value */
- rOffset += bufferInc;
-
- if(rOffset >= L)
- {
- rOffset -= L;
- }
-
- /* Decrement the loop counter */
- i--;
- }
-
- /* Update the index pointer */
- *readOffset = rOffset;
- }
-
-
- /**
- * @brief Sum of the squares of the elements of a Q31 vector.
- * @param[in] *pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] *pResult is output value.
- * @return none.
- */
-
- void arm_power_q31(
- q31_t * pSrc,
- uint32_t blockSize,
- q63_t * pResult);
-
- /**
- * @brief Sum of the squares of the elements of a floating-point vector.
- * @param[in] *pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] *pResult is output value.
- * @return none.
- */
-
- void arm_power_f32(
- float32_t * pSrc,
- uint32_t blockSize,
- float32_t * pResult);
-
- /**
- * @brief Sum of the squares of the elements of a Q15 vector.
- * @param[in] *pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] *pResult is output value.
- * @return none.
- */
-
- void arm_power_q15(
- q15_t * pSrc,
- uint32_t blockSize,
- q63_t * pResult);
-
- /**
- * @brief Sum of the squares of the elements of a Q7 vector.
- * @param[in] *pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] *pResult is output value.
- * @return none.
- */
-
- void arm_power_q7(
- q7_t * pSrc,
- uint32_t blockSize,
- q31_t * pResult);
-
- /**
- * @brief Mean value of a Q7 vector.
- * @param[in] *pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] *pResult is output value.
- * @return none.
- */
-
- void arm_mean_q7(
- q7_t * pSrc,
- uint32_t blockSize,
- q7_t * pResult);
-
- /**
- * @brief Mean value of a Q15 vector.
- * @param[in] *pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] *pResult is output value.
- * @return none.
- */
- void arm_mean_q15(
- q15_t * pSrc,
- uint32_t blockSize,
- q15_t * pResult);
-
- /**
- * @brief Mean value of a Q31 vector.
- * @param[in] *pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] *pResult is output value.
- * @return none.
- */
- void arm_mean_q31(
- q31_t * pSrc,
- uint32_t blockSize,
- q31_t * pResult);
-
- /**
- * @brief Mean value of a floating-point vector.
- * @param[in] *pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] *pResult is output value.
- * @return none.
- */
- void arm_mean_f32(
- float32_t * pSrc,
- uint32_t blockSize,
- float32_t * pResult);
-
- /**
- * @brief Variance of the elements of a floating-point vector.
- * @param[in] *pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] *pResult is output value.
- * @return none.
- */
-
- void arm_var_f32(
- float32_t * pSrc,
- uint32_t blockSize,
- float32_t * pResult);
-
- /**
- * @brief Variance of the elements of a Q31 vector.
- * @param[in] *pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] *pResult is output value.
- * @return none.
- */
-
- void arm_var_q31(
- q31_t * pSrc,
- uint32_t blockSize,
- q63_t * pResult);
-
- /**
- * @brief Variance of the elements of a Q15 vector.
- * @param[in] *pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] *pResult is output value.
- * @return none.
- */
-
- void arm_var_q15(
- q15_t * pSrc,
- uint32_t blockSize,
- q31_t * pResult);
-
- /**
- * @brief Root Mean Square of the elements of a floating-point vector.
- * @param[in] *pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] *pResult is output value.
- * @return none.
- */
-
- void arm_rms_f32(
- float32_t * pSrc,
- uint32_t blockSize,
- float32_t * pResult);
-
- /**
- * @brief Root Mean Square of the elements of a Q31 vector.
- * @param[in] *pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] *pResult is output value.
- * @return none.
- */
-
- void arm_rms_q31(
- q31_t * pSrc,
- uint32_t blockSize,
- q31_t * pResult);
-
- /**
- * @brief Root Mean Square of the elements of a Q15 vector.
- * @param[in] *pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] *pResult is output value.
- * @return none.
- */
-
- void arm_rms_q15(
- q15_t * pSrc,
- uint32_t blockSize,
- q15_t * pResult);
-
- /**
- * @brief Standard deviation of the elements of a floating-point vector.
- * @param[in] *pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] *pResult is output value.
- * @return none.
- */
-
- void arm_std_f32(
- float32_t * pSrc,
- uint32_t blockSize,
- float32_t * pResult);
-
- /**
- * @brief Standard deviation of the elements of a Q31 vector.
- * @param[in] *pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] *pResult is output value.
- * @return none.
- */
-
- void arm_std_q31(
- q31_t * pSrc,
- uint32_t blockSize,
- q31_t * pResult);
-
- /**
- * @brief Standard deviation of the elements of a Q15 vector.
- * @param[in] *pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] *pResult is output value.
- * @return none.
- */
-
- void arm_std_q15(
- q15_t * pSrc,
- uint32_t blockSize,
- q15_t * pResult);
-
- /**
- * @brief Floating-point complex magnitude
- * @param[in] *pSrc points to the complex input vector
- * @param[out] *pDst points to the real output vector
- * @param[in] numSamples number of complex samples in the input vector
- * @return none.
- */
-
- void arm_cmplx_mag_f32(
- float32_t * pSrc,
- float32_t * pDst,
- uint32_t numSamples);
-
- /**
- * @brief Q31 complex magnitude
- * @param[in] *pSrc points to the complex input vector
- * @param[out] *pDst points to the real output vector
- * @param[in] numSamples number of complex samples in the input vector
- * @return none.
- */
-
- void arm_cmplx_mag_q31(
- q31_t * pSrc,
- q31_t * pDst,
- uint32_t numSamples);
-
- /**
- * @brief Q15 complex magnitude
- * @param[in] *pSrc points to the complex input vector
- * @param[out] *pDst points to the real output vector
- * @param[in] numSamples number of complex samples in the input vector
- * @return none.
- */
-
- void arm_cmplx_mag_q15(
- q15_t * pSrc,
- q15_t * pDst,
- uint32_t numSamples);
-
- /**
- * @brief Q15 complex dot product
- * @param[in] *pSrcA points to the first input vector
- * @param[in] *pSrcB points to the second input vector
- * @param[in] numSamples number of complex samples in each vector
- * @param[out] *realResult real part of the result returned here
- * @param[out] *imagResult imaginary part of the result returned here
- * @return none.
- */
-
- void arm_cmplx_dot_prod_q15(
- q15_t * pSrcA,
- q15_t * pSrcB,
- uint32_t numSamples,
- q31_t * realResult,
- q31_t * imagResult);
-
- /**
- * @brief Q31 complex dot product
- * @param[in] *pSrcA points to the first input vector
- * @param[in] *pSrcB points to the second input vector
- * @param[in] numSamples number of complex samples in each vector
- * @param[out] *realResult real part of the result returned here
- * @param[out] *imagResult imaginary part of the result returned here
- * @return none.
- */
-
- void arm_cmplx_dot_prod_q31(
- q31_t * pSrcA,
- q31_t * pSrcB,
- uint32_t numSamples,
- q63_t * realResult,
- q63_t * imagResult);
-
- /**
- * @brief Floating-point complex dot product
- * @param[in] *pSrcA points to the first input vector
- * @param[in] *pSrcB points to the second input vector
- * @param[in] numSamples number of complex samples in each vector
- * @param[out] *realResult real part of the result returned here
- * @param[out] *imagResult imaginary part of the result returned here
- * @return none.
- */
-
- void arm_cmplx_dot_prod_f32(
- float32_t * pSrcA,
- float32_t * pSrcB,
- uint32_t numSamples,
- float32_t * realResult,
- float32_t * imagResult);
-
- /**
- * @brief Q15 complex-by-real multiplication
- * @param[in] *pSrcCmplx points to the complex input vector
- * @param[in] *pSrcReal points to the real input vector
- * @param[out] *pCmplxDst points to the complex output vector
- * @param[in] numSamples number of samples in each vector
- * @return none.
- */
-
- void arm_cmplx_mult_real_q15(
- q15_t * pSrcCmplx,
- q15_t * pSrcReal,
- q15_t * pCmplxDst,
- uint32_t numSamples);
-
- /**
- * @brief Q31 complex-by-real multiplication
- * @param[in] *pSrcCmplx points to the complex input vector
- * @param[in] *pSrcReal points to the real input vector
- * @param[out] *pCmplxDst points to the complex output vector
- * @param[in] numSamples number of samples in each vector
- * @return none.
- */
-
- void arm_cmplx_mult_real_q31(
- q31_t * pSrcCmplx,
- q31_t * pSrcReal,
- q31_t * pCmplxDst,
- uint32_t numSamples);
-
- /**
- * @brief Floating-point complex-by-real multiplication
- * @param[in] *pSrcCmplx points to the complex input vector
- * @param[in] *pSrcReal points to the real input vector
- * @param[out] *pCmplxDst points to the complex output vector
- * @param[in] numSamples number of samples in each vector
- * @return none.
- */
-
- void arm_cmplx_mult_real_f32(
- float32_t * pSrcCmplx,
- float32_t * pSrcReal,
- float32_t * pCmplxDst,
- uint32_t numSamples);
-
- /**
- * @brief Minimum value of a Q7 vector.
- * @param[in] *pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] *result is output pointer
- * @param[in] index is the array index of the minimum value in the input buffer.
- * @return none.
- */
-
- void arm_min_q7(
- q7_t * pSrc,
- uint32_t blockSize,
- q7_t * result,
- uint32_t * index);
-
- /**
- * @brief Minimum value of a Q15 vector.
- * @param[in] *pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] *pResult is output pointer
- * @param[in] *pIndex is the array index of the minimum value in the input buffer.
- * @return none.
- */
-
- void arm_min_q15(
- q15_t * pSrc,
- uint32_t blockSize,
- q15_t * pResult,
- uint32_t * pIndex);
-
- /**
- * @brief Minimum value of a Q31 vector.
- * @param[in] *pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] *pResult is output pointer
- * @param[out] *pIndex is the array index of the minimum value in the input buffer.
- * @return none.
- */
- void arm_min_q31(
- q31_t * pSrc,
- uint32_t blockSize,
- q31_t * pResult,
- uint32_t * pIndex);
-
- /**
- * @brief Minimum value of a floating-point vector.
- * @param[in] *pSrc is input pointer
- * @param[in] blockSize is the number of samples to process
- * @param[out] *pResult is output pointer
- * @param[out] *pIndex is the array index of the minimum value in the input buffer.
- * @return none.
- */
-
- void arm_min_f32(
- float32_t * pSrc,
- uint32_t blockSize,
- float32_t * pResult,
- uint32_t * pIndex);
-
-/**
- * @brief Maximum value of a Q7 vector.
- * @param[in] *pSrc points to the input buffer
- * @param[in] blockSize length of the input vector
- * @param[out] *pResult maximum value returned here
- * @param[out] *pIndex index of maximum value returned here
- * @return none.
- */
-
- void arm_max_q7(
- q7_t * pSrc,
- uint32_t blockSize,
- q7_t * pResult,
- uint32_t * pIndex);
-
-/**
- * @brief Maximum value of a Q15 vector.
- * @param[in] *pSrc points to the input buffer
- * @param[in] blockSize length of the input vector
- * @param[out] *pResult maximum value returned here
- * @param[out] *pIndex index of maximum value returned here
- * @return none.
- */
-
- void arm_max_q15(
- q15_t * pSrc,
- uint32_t blockSize,
- q15_t * pResult,
- uint32_t * pIndex);
-
-/**
- * @brief Maximum value of a Q31 vector.
- * @param[in] *pSrc points to the input buffer
- * @param[in] blockSize length of the input vector
- * @param[out] *pResult maximum value returned here
- * @param[out] *pIndex index of maximum value returned here
- * @return none.
- */
-
- void arm_max_q31(
- q31_t * pSrc,
- uint32_t blockSize,
- q31_t * pResult,
- uint32_t * pIndex);
-
-/**
- * @brief Maximum value of a floating-point vector.
- * @param[in] *pSrc points to the input buffer
- * @param[in] blockSize length of the input vector
- * @param[out] *pResult maximum value returned here
- * @param[out] *pIndex index of maximum value returned here
- * @return none.
- */
-
- void arm_max_f32(
- float32_t * pSrc,
- uint32_t blockSize,
- float32_t * pResult,
- uint32_t * pIndex);
-
- /**
- * @brief Q15 complex-by-complex multiplication
- * @param[in] *pSrcA points to the first input vector
- * @param[in] *pSrcB points to the second input vector
- * @param[out] *pDst points to the output vector
- * @param[in] numSamples number of complex samples in each vector
- * @return none.
- */
-
- void arm_cmplx_mult_cmplx_q15(
- q15_t * pSrcA,
- q15_t * pSrcB,
- q15_t * pDst,
- uint32_t numSamples);
-
- /**
- * @brief Q31 complex-by-complex multiplication
- * @param[in] *pSrcA points to the first input vector
- * @param[in] *pSrcB points to the second input vector
- * @param[out] *pDst points to the output vector
- * @param[in] numSamples number of complex samples in each vector
- * @return none.
- */
-
- void arm_cmplx_mult_cmplx_q31(
- q31_t * pSrcA,
- q31_t * pSrcB,
- q31_t * pDst,
- uint32_t numSamples);
-
- /**
- * @brief Floating-point complex-by-complex multiplication
- * @param[in] *pSrcA points to the first input vector
- * @param[in] *pSrcB points to the second input vector
- * @param[out] *pDst points to the output vector
- * @param[in] numSamples number of complex samples in each vector
- * @return none.
- */
-
- void arm_cmplx_mult_cmplx_f32(
- float32_t * pSrcA,
- float32_t * pSrcB,
- float32_t * pDst,
- uint32_t numSamples);
-
- /**
- * @brief Converts the elements of the floating-point vector to Q31 vector.
- * @param[in] *pSrc points to the floating-point input vector
- * @param[out] *pDst points to the Q31 output vector
- * @param[in] blockSize length of the input vector
- * @return none.
- */
- void arm_float_to_q31(
- float32_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Converts the elements of the floating-point vector to Q15 vector.
- * @param[in] *pSrc points to the floating-point input vector
- * @param[out] *pDst points to the Q15 output vector
- * @param[in] blockSize length of the input vector
- * @return none
- */
- void arm_float_to_q15(
- float32_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Converts the elements of the floating-point vector to Q7 vector.
- * @param[in] *pSrc points to the floating-point input vector
- * @param[out] *pDst points to the Q7 output vector
- * @param[in] blockSize length of the input vector
- * @return none
- */
- void arm_float_to_q7(
- float32_t * pSrc,
- q7_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Converts the elements of the Q31 vector to Q15 vector.
- * @param[in] *pSrc is input pointer
- * @param[out] *pDst is output pointer
- * @param[in] blockSize is the number of samples to process
- * @return none.
- */
- void arm_q31_to_q15(
- q31_t * pSrc,
- q15_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Converts the elements of the Q31 vector to Q7 vector.
- * @param[in] *pSrc is input pointer
- * @param[out] *pDst is output pointer
- * @param[in] blockSize is the number of samples to process
- * @return none.
- */
- void arm_q31_to_q7(
- q31_t * pSrc,
- q7_t * pDst,
- uint32_t blockSize);
-
- /**
- * @brief Converts the elements of the Q15 vector to floating-point vector.
- * @param[in] *pSrc is input pointer
- * @param[out] *pDst is output pointer
- * @param[in] blockSize is the number of samples to process
- * @return none.
- */
- void arm_q15_to_float(
- q15_t * pSrc,
- float32_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Converts the elements of the Q15 vector to Q31 vector.
- * @param[in] *pSrc is input pointer
- * @param[out] *pDst is output pointer
- * @param[in] blockSize is the number of samples to process
- * @return none.
- */
- void arm_q15_to_q31(
- q15_t * pSrc,
- q31_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @brief Converts the elements of the Q15 vector to Q7 vector.
- * @param[in] *pSrc is input pointer
- * @param[out] *pDst is output pointer
- * @param[in] blockSize is the number of samples to process
- * @return none.
- */
- void arm_q15_to_q7(
- q15_t * pSrc,
- q7_t * pDst,
- uint32_t blockSize);
-
-
- /**
- * @ingroup groupInterpolation
- */
-
- /**
- * @defgroup BilinearInterpolate Bilinear Interpolation
- *
- * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.
- * The underlying function <code>f(x, y)</code> is sampled on a regular grid and the interpolation process
- * determines values between the grid points.
- * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.
- * Bilinear interpolation is often used in image processing to rescale images.
- * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.
- *
- * <b>Algorithm</b>
- * \par
- * The instance structure used by the bilinear interpolation functions describes a two dimensional data table.
- * For floating-point, the instance structure is defined as:
- * <pre>
- * typedef struct
- * {
- * uint16_t numRows;
- * uint16_t numCols;
- * float32_t *pData;
- * } arm_bilinear_interp_instance_f32;
- * </pre>
- *
- * \par
- * where <code>numRows</code> specifies the number of rows in the table;
- * <code>numCols</code> specifies the number of columns in the table;
- * and <code>pData</code> points to an array of size <code>numRows*numCols</code> values.
- * The data table <code>pTable</code> is organized in row order and the supplied data values fall on integer indexes.
- * That is, table element (x,y) is located at <code>pTable[x + y*numCols]</code> where x and y are integers.
- *
- * \par
- * Let <code>(x, y)</code> specify the desired interpolation point. Then define:
- * <pre>
- * XF = floor(x)
- * YF = floor(y)
- * </pre>
- * \par
- * The interpolated output point is computed as:
- * <pre>
- * f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
- * + f(XF+1, YF) * (x-XF)*(1-(y-YF))
- * + f(XF, YF+1) * (1-(x-XF))*(y-YF)
- * + f(XF+1, YF+1) * (x-XF)*(y-YF)
- * </pre>
- * Note that the coordinates (x, y) contain integer and fractional components.
- * The integer components specify which portion of the table to use while the
- * fractional components control the interpolation processor.
- *
- * \par
- * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output.
- */
-
- /**
- * @addtogroup BilinearInterpolate
- * @{
- */
-
- /**
- *
- * @brief Floating-point bilinear interpolation.
- * @param[in,out] *S points to an instance of the interpolation structure.
- * @param[in] X interpolation coordinate.
- * @param[in] Y interpolation coordinate.
- * @return out interpolated value.
- */
-
-
- static __INLINE float32_t arm_bilinear_interp_f32(
- const arm_bilinear_interp_instance_f32 * S,
- float32_t X,
- float32_t Y)
- {
- float32_t out;
- float32_t f00, f01, f10, f11;
- float32_t *pData = S->pData;
- int32_t xIndex, yIndex, index;
- float32_t xdiff, ydiff;
- float32_t b1, b2, b3, b4;
-
- xIndex = (int32_t) X;
- yIndex = (int32_t) Y;
-
- /* Care taken for table outside boundary */
- /* Returns zero output when values are outside table boundary */
- if(xIndex < 0 || xIndex > (S->numRows - 1) || yIndex < 0
- || yIndex > (S->numCols - 1))
- {
- return (0);
- }
-
- /* Calculation of index for two nearest points in X-direction */
- index = (xIndex - 1) + (yIndex - 1) * S->numCols;
-
-
- /* Read two nearest points in X-direction */
- f00 = pData[index];
- f01 = pData[index + 1];
-
- /* Calculation of index for two nearest points in Y-direction */
- index = (xIndex - 1) + (yIndex) * S->numCols;
-
-
- /* Read two nearest points in Y-direction */
- f10 = pData[index];
- f11 = pData[index + 1];
-
- /* Calculation of intermediate values */
- b1 = f00;
- b2 = f01 - f00;
- b3 = f10 - f00;
- b4 = f00 - f01 - f10 + f11;
-
- /* Calculation of fractional part in X */
- xdiff = X - xIndex;
-
- /* Calculation of fractional part in Y */
- ydiff = Y - yIndex;
-
- /* Calculation of bi-linear interpolated output */
- out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;
-
- /* return to application */
- return (out);
-
- }
-
- /**
- *
- * @brief Q31 bilinear interpolation.
- * @param[in,out] *S points to an instance of the interpolation structure.
- * @param[in] X interpolation coordinate in 12.20 format.
- * @param[in] Y interpolation coordinate in 12.20 format.
- * @return out interpolated value.
- */
-
- static __INLINE q31_t arm_bilinear_interp_q31(
- arm_bilinear_interp_instance_q31 * S,
- q31_t X,
- q31_t Y)
- {
- q31_t out; /* Temporary output */
- q31_t acc = 0; /* output */
- q31_t xfract, yfract; /* X, Y fractional parts */
- q31_t x1, x2, y1, y2; /* Nearest output values */
- int32_t rI, cI; /* Row and column indices */
- q31_t *pYData = S->pData; /* pointer to output table values */
- uint32_t nCols = S->numCols; /* num of rows */
-
-
- /* Input is in 12.20 format */
- /* 12 bits for the table index */
- /* Index value calculation */
- rI = ((X & 0xFFF00000) >> 20u);
-
- /* Input is in 12.20 format */
- /* 12 bits for the table index */
- /* Index value calculation */
- cI = ((Y & 0xFFF00000) >> 20u);
-
- /* Care taken for table outside boundary */
- /* Returns zero output when values are outside table boundary */
- if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
- {
- return (0);
- }
-
- /* 20 bits for the fractional part */
- /* shift left xfract by 11 to keep 1.31 format */
- xfract = (X & 0x000FFFFF) << 11u;
-
- /* Read two nearest output values from the index */
- x1 = pYData[(rI) + nCols * (cI)];
- x2 = pYData[(rI) + nCols * (cI) + 1u];
-
- /* 20 bits for the fractional part */
- /* shift left yfract by 11 to keep 1.31 format */
- yfract = (Y & 0x000FFFFF) << 11u;
-
- /* Read two nearest output values from the index */
- y1 = pYData[(rI) + nCols * (cI + 1)];
- y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
-
- /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */
- out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32));
- acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32));
-
- /* x2 * (xfract) * (1-yfract) in 3.29(q29) and adding to acc */
- out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32));
- acc += ((q31_t) ((q63_t) out * (xfract) >> 32));
-
- /* y1 * (1 - xfract) * (yfract) in 3.29(q29) and adding to acc */
- out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32));
- acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
-
- /* y2 * (xfract) * (yfract) in 3.29(q29) and adding to acc */
- out = ((q31_t) ((q63_t) y2 * (xfract) >> 32));
- acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
-
- /* Convert acc to 1.31(q31) format */
- return (acc << 2u);
-
- }
-
- /**
- * @brief Q15 bilinear interpolation.
- * @param[in,out] *S points to an instance of the interpolation structure.
- * @param[in] X interpolation coordinate in 12.20 format.
- * @param[in] Y interpolation coordinate in 12.20 format.
- * @return out interpolated value.
- */
-
- static __INLINE q15_t arm_bilinear_interp_q15(
- arm_bilinear_interp_instance_q15 * S,
- q31_t X,
- q31_t Y)
- {
- q63_t acc = 0; /* output */
- q31_t out; /* Temporary output */
- q15_t x1, x2, y1, y2; /* Nearest output values */
- q31_t xfract, yfract; /* X, Y fractional parts */
- int32_t rI, cI; /* Row and column indices */
- q15_t *pYData = S->pData; /* pointer to output table values */
- uint32_t nCols = S->numCols; /* num of rows */
-
- /* Input is in 12.20 format */
- /* 12 bits for the table index */
- /* Index value calculation */
- rI = ((X & 0xFFF00000) >> 20);
-
- /* Input is in 12.20 format */
- /* 12 bits for the table index */
- /* Index value calculation */
- cI = ((Y & 0xFFF00000) >> 20);
-
- /* Care taken for table outside boundary */
- /* Returns zero output when values are outside table boundary */
- if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
- {
- return (0);
- }
-
- /* 20 bits for the fractional part */
- /* xfract should be in 12.20 format */
- xfract = (X & 0x000FFFFF);
-
- /* Read two nearest output values from the index */
- x1 = pYData[(rI) + nCols * (cI)];
- x2 = pYData[(rI) + nCols * (cI) + 1u];
-
-
- /* 20 bits for the fractional part */
- /* yfract should be in 12.20 format */
- yfract = (Y & 0x000FFFFF);
-
- /* Read two nearest output values from the index */
- y1 = pYData[(rI) + nCols * (cI + 1)];
- y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
-
- /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */
-
- /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */
- /* convert 13.35 to 13.31 by right shifting and out is in 1.31 */
- out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u);
- acc = ((q63_t) out * (0xFFFFF - yfract));
-
- /* x2 * (xfract) * (1-yfract) in 1.51 and adding to acc */
- out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u);
- acc += ((q63_t) out * (xfract));
-
- /* y1 * (1 - xfract) * (yfract) in 1.51 and adding to acc */
- out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u);
- acc += ((q63_t) out * (yfract));
-
- /* y2 * (xfract) * (yfract) in 1.51 and adding to acc */
- out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u);
- acc += ((q63_t) out * (yfract));
-
- /* acc is in 13.51 format and down shift acc by 36 times */
- /* Convert out to 1.15 format */
- return (acc >> 36);
-
- }
-
- /**
- * @brief Q7 bilinear interpolation.
- * @param[in,out] *S points to an instance of the interpolation structure.
- * @param[in] X interpolation coordinate in 12.20 format.
- * @param[in] Y interpolation coordinate in 12.20 format.
- * @return out interpolated value.
- */
-
- static __INLINE q7_t arm_bilinear_interp_q7(
- arm_bilinear_interp_instance_q7 * S,
- q31_t X,
- q31_t Y)
- {
- q63_t acc = 0; /* output */
- q31_t out; /* Temporary output */
- q31_t xfract, yfract; /* X, Y fractional parts */
- q7_t x1, x2, y1, y2; /* Nearest output values */
- int32_t rI, cI; /* Row and column indices */
- q7_t *pYData = S->pData; /* pointer to output table values */
- uint32_t nCols = S->numCols; /* num of rows */
-
- /* Input is in 12.20 format */
- /* 12 bits for the table index */
- /* Index value calculation */
- rI = ((X & 0xFFF00000) >> 20);
-
- /* Input is in 12.20 format */
- /* 12 bits for the table index */
- /* Index value calculation */
- cI = ((Y & 0xFFF00000) >> 20);
-
- /* Care taken for table outside boundary */
- /* Returns zero output when values are outside table boundary */
- if(rI < 0 || rI > (S->numRows - 1) || cI < 0 || cI > (S->numCols - 1))
- {
- return (0);
- }
-
- /* 20 bits for the fractional part */
- /* xfract should be in 12.20 format */
- xfract = (X & 0x000FFFFF);
-
- /* Read two nearest output values from the index */
- x1 = pYData[(rI) + nCols * (cI)];
- x2 = pYData[(rI) + nCols * (cI) + 1u];
-
-
- /* 20 bits for the fractional part */
- /* yfract should be in 12.20 format */
- yfract = (Y & 0x000FFFFF);
-
- /* Read two nearest output values from the index */
- y1 = pYData[(rI) + nCols * (cI + 1)];
- y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
-
- /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */
- out = ((x1 * (0xFFFFF - xfract)));
- acc = (((q63_t) out * (0xFFFFF - yfract)));
-
- /* x2 * (xfract) * (1-yfract) in 2.22 and adding to acc */
- out = ((x2 * (0xFFFFF - yfract)));
- acc += (((q63_t) out * (xfract)));
-
- /* y1 * (1 - xfract) * (yfract) in 2.22 and adding to acc */
- out = ((y1 * (0xFFFFF - xfract)));
- acc += (((q63_t) out * (yfract)));
-
- /* y2 * (xfract) * (yfract) in 2.22 and adding to acc */
- out = ((y2 * (yfract)));
- acc += (((q63_t) out * (xfract)));
-
- /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */
- return (acc >> 40);
-
- }
-
- /**
- * @} end of BilinearInterpolate group
- */
-
-
-#if defined ( __CC_ARM ) //Keil
-//SMMLAR
- #define multAcc_32x32_keep32_R(a, x, y) \
- a = (q31_t) (((((q63_t) a) << 32) + ((q63_t) x * y) + 0x80000000LL ) >> 32)
-
-//SMMLSR
- #define multSub_32x32_keep32_R(a, x, y) \
- a = (q31_t) (((((q63_t) a) << 32) - ((q63_t) x * y) + 0x80000000LL ) >> 32)
-
-//SMMULR
- #define mult_32x32_keep32_R(a, x, y) \
- a = (q31_t) (((q63_t) x * y + 0x80000000LL ) >> 32)
-
-//Enter low optimization region - place directly above function definition
- #define LOW_OPTIMIZATION_ENTER \
- _Pragma ("push") \
- _Pragma ("O1")
-
-//Exit low optimization region - place directly after end of function definition
- #define LOW_OPTIMIZATION_EXIT \
- _Pragma ("pop")
-
-//Enter low optimization region - place directly above function definition
- #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
-
-//Exit low optimization region - place directly after end of function definition
- #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
-
-#elif defined(__ICCARM__) //IAR
- //SMMLA
- #define multAcc_32x32_keep32_R(a, x, y) \
- a += (q31_t) (((q63_t) x * y) >> 32)
-
- //SMMLS
- #define multSub_32x32_keep32_R(a, x, y) \
- a -= (q31_t) (((q63_t) x * y) >> 32)
-
-//SMMUL
- #define mult_32x32_keep32_R(a, x, y) \
- a = (q31_t) (((q63_t) x * y ) >> 32)
-
-//Enter low optimization region - place directly above function definition
- #define LOW_OPTIMIZATION_ENTER \
- _Pragma ("optimize=low")
-
-//Exit low optimization region - place directly after end of function definition
- #define LOW_OPTIMIZATION_EXIT
-
-//Enter low optimization region - place directly above function definition
- #define IAR_ONLY_LOW_OPTIMIZATION_ENTER \
- _Pragma ("optimize=low")
-
-//Exit low optimization region - place directly after end of function definition
- #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
-
-#elif defined(__GNUC__)
- //SMMLA
- #define multAcc_32x32_keep32_R(a, x, y) \
- a += (q31_t) (((q63_t) x * y) >> 32)
-
- //SMMLS
- #define multSub_32x32_keep32_R(a, x, y) \
- a -= (q31_t) (((q63_t) x * y) >> 32)
-
-//SMMUL
- #define mult_32x32_keep32_R(a, x, y) \
- a = (q31_t) (((q63_t) x * y ) >> 32)
-
- #define LOW_OPTIMIZATION_ENTER __attribute__(( optimize("-O1") ))
-
- #define LOW_OPTIMIZATION_EXIT
-
- #define IAR_ONLY_LOW_OPTIMIZATION_ENTER
-
- #define IAR_ONLY_LOW_OPTIMIZATION_EXIT
-
-#endif
-
-
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* _ARM_MATH_H */
-
-
-/**
- *
- * End of file.
- */
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Include/core_cm0.h b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Include/core_cm0.h
deleted file mode 100644
index ab31de0ee87f9cb566cef040364c80c1f09bbf86..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Include/core_cm0.h
+++ /dev/null
@@ -1,682 +0,0 @@
-/**************************************************************************//**
- * @file core_cm0.h
- * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
- * @version V3.20
- * @date 25. February 2013
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2009 - 2013 ARM LIMITED
-
- All rights reserved.
- Redistribution and use in source and binary forms, with or without
- modification, are permitted provided that the following conditions are met:
- - Redistributions of source code must retain the above copyright
- notice, this list of conditions and the following disclaimer.
- - Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the distribution.
- - Neither the name of ARM nor the names of its contributors may be used
- to endorse or promote products derived from this software without
- specific prior written permission.
- *
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- POSSIBILITY OF SUCH DAMAGE.
- ---------------------------------------------------------------------------*/
-
-
-#if defined ( __ICCARM__ )
- #pragma system_include /* treat file as system include file for MISRA check */
-#endif
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#ifndef __CORE_CM0_H_GENERIC
-#define __CORE_CM0_H_GENERIC
-
-/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
- CMSIS violates the following MISRA-C:2004 rules:
-
- \li Required Rule 8.5, object/function definition in header file.<br>
- Function definitions in header files are used to allow 'inlining'.
-
- \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
- Unions are used for effective representation of core registers.
-
- \li Advisory Rule 19.7, Function-like macro defined.<br>
- Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- * CMSIS definitions
- ******************************************************************************/
-/** \ingroup Cortex_M0
- @{
- */
-
-/* CMSIS CM0 definitions */
-#define __CM0_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
-#define __CM0_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
-#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \
- __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
-
-#define __CORTEX_M (0x00) /*!< Cortex-M Core */
-
-
-#if defined ( __CC_ARM )
- #define __ASM __asm /*!< asm keyword for ARM Compiler */
- #define __INLINE __inline /*!< inline keyword for ARM Compiler */
- #define __STATIC_INLINE static __inline
-
-#elif defined ( __ICCARM__ )
- #define __ASM __asm /*!< asm keyword for IAR Compiler */
- #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
- #define __STATIC_INLINE static inline
-
-#elif defined ( __GNUC__ )
- #define __ASM __asm /*!< asm keyword for GNU Compiler */
- #define __INLINE inline /*!< inline keyword for GNU Compiler */
- #define __STATIC_INLINE static inline
-
-#elif defined ( __TASKING__ )
- #define __ASM __asm /*!< asm keyword for TASKING Compiler */
- #define __INLINE inline /*!< inline keyword for TASKING Compiler */
- #define __STATIC_INLINE static inline
-
-#endif
-
-/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
-*/
-#define __FPU_USED 0
-
-#if defined ( __CC_ARM )
- #if defined __TARGET_FPU_VFP
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __ICCARM__ )
- #if defined __ARMVFP__
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __GNUC__ )
- #if defined (__VFP_FP__) && !defined(__SOFTFP__)
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __TASKING__ )
- #if defined __FPU_VFP__
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-#endif
-
-#include <stdint.h> /* standard types definitions */
-#include <core_cmInstr.h> /* Core Instruction Access */
-#include <core_cmFunc.h> /* Core Function Access */
-
-#endif /* __CORE_CM0_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM0_H_DEPENDANT
-#define __CORE_CM0_H_DEPENDANT
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
- #ifndef __CM0_REV
- #define __CM0_REV 0x0000
- #warning "__CM0_REV not defined in device header file; using default!"
- #endif
-
- #ifndef __NVIC_PRIO_BITS
- #define __NVIC_PRIO_BITS 2
- #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
- #endif
-
- #ifndef __Vendor_SysTickConfig
- #define __Vendor_SysTickConfig 0
- #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
- #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
- \defgroup CMSIS_glob_defs CMSIS Global Defines
-
- <strong>IO Type Qualifiers</strong> are used
- \li to specify the access to peripheral variables.
- \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
- #define __I volatile /*!< Defines 'read only' permissions */
-#else
- #define __I volatile const /*!< Defines 'read only' permissions */
-#endif
-#define __O volatile /*!< Defines 'write only' permissions */
-#define __IO volatile /*!< Defines 'read / write' permissions */
-
-/*@} end of group Cortex_M0 */
-
-
-
-/*******************************************************************************
- * Register Abstraction
- Core Register contain:
- - Core Register
- - Core NVIC Register
- - Core SCB Register
- - Core SysTick Register
- ******************************************************************************/
-/** \defgroup CMSIS_core_register Defines and Type Definitions
- \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_CORE Status and Control Registers
- \brief Core Register type definitions.
- @{
- */
-
-/** \brief Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
- struct
- {
-#if (__CORTEX_M != 0x04)
- uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
-#else
- uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
- uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
-#endif
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} APSR_Type;
-
-
-/** \brief Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
- uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} IPSR_Type;
-
-
-/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
-#if (__CORTEX_M != 0x04)
- uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
-#else
- uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
- uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
-#endif
- uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
- uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} xPSR_Type;
-
-
-/** \brief Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
- struct
- {
- uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
- uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
- uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
- uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} CONTROL_Type;
-
-/*@} end of group CMSIS_CORE */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
- \brief Type definitions for the NVIC Registers
- @{
- */
-
-/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
- __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
- uint32_t RESERVED0[31];
- __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
- uint32_t RSERVED1[31];
- __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
- uint32_t RESERVED2[31];
- __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
- uint32_t RESERVED3[31];
- uint32_t RESERVED4[64];
- __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
-} NVIC_Type;
-
-/*@} end of group CMSIS_NVIC */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_SCB System Control Block (SCB)
- \brief Type definitions for the System Control Block Registers
- @{
- */
-
-/** \brief Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
- __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
- __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
- uint32_t RESERVED0;
- __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
- __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
- __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
- uint32_t RESERVED1;
- __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
- __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_SysTick System Tick Timer (SysTick)
- \brief Type definitions for the System Timer Registers.
- @{
- */
-
-/** \brief Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
- __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
- __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
- __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
- __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
- \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)
- are only accessible over DAP and not via processor. Therefore
- they are not covered by the Cortex-M0 header file.
- @{
- */
-/*@} end of group CMSIS_CoreDebug */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_core_base Core Definitions
- \brief Definitions for base addresses, unions, and structures.
- @{
- */
-
-/* Memory mapping of Cortex-M0 Hardware */
-#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
-#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
-#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
-#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
-
-#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
-#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
-#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
-
-
-/*@} */
-
-
-
-/*******************************************************************************
- * Hardware Abstraction Layer
- Core Function Interface contains:
- - Core NVIC Functions
- - Core SysTick Functions
- - Core Register Access Functions
- ******************************************************************************/
-/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ########################## NVIC functions #################################### */
-/** \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_NVICFunctions NVIC Functions
- \brief Functions that manage interrupts and exceptions via the NVIC.
- @{
- */
-
-/* Interrupt Priorities are WORD accessible only under ARMv6M */
-/* The following MACROS handle generation of the register offset and byte masks */
-#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
-#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
-#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
-
-
-/** \brief Enable External Interrupt
-
- The function enables a device-specific interrupt in the NVIC interrupt controller.
-
- \param [in] IRQn External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
-{
- NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
-}
-
-
-/** \brief Disable External Interrupt
-
- The function disables a device-specific interrupt in the NVIC interrupt controller.
-
- \param [in] IRQn External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
-{
- NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
-}
-
-
-/** \brief Get Pending Interrupt
-
- The function reads the pending register in the NVIC and returns the pending bit
- for the specified interrupt.
-
- \param [in] IRQn Interrupt number.
-
- \return 0 Interrupt status is not pending.
- \return 1 Interrupt status is pending.
- */
-__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
- return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
-}
-
-
-/** \brief Set Pending Interrupt
-
- The function sets the pending bit of an external interrupt.
-
- \param [in] IRQn Interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
- NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
-}
-
-
-/** \brief Clear Pending Interrupt
-
- The function clears the pending bit of an external interrupt.
-
- \param [in] IRQn External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
- NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
-}
-
-
-/** \brief Set Interrupt Priority
-
- The function sets the priority of an interrupt.
-
- \note The priority cannot be set for every core interrupt.
-
- \param [in] IRQn Interrupt number.
- \param [in] priority Priority to set.
- */
-__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
- if(IRQn < 0) {
- SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
- (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
- else {
- NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
- (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
-}
-
-
-/** \brief Get Interrupt Priority
-
- The function reads the priority of an interrupt. The interrupt
- number can be positive to specify an external (device specific)
- interrupt, or negative to specify an internal (core) interrupt.
-
-
- \param [in] IRQn Interrupt number.
- \return Interrupt Priority. Value is aligned automatically to the implemented
- priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
-{
-
- if(IRQn < 0) {
- return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
- else {
- return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
-}
-
-
-/** \brief System Reset
-
- The function initiates a system reset request to reset the MCU.
- */
-__STATIC_INLINE void NVIC_SystemReset(void)
-{
- __DSB(); /* Ensure all outstanding memory accesses included
- buffered write are completed before reset */
- SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
- SCB_AIRCR_SYSRESETREQ_Msk);
- __DSB(); /* Ensure completion of memory access */
- while(1); /* wait until reset */
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-
-/* ################################## SysTick function ############################################ */
-/** \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
- \brief Functions that configure the System.
- @{
- */
-
-#if (__Vendor_SysTickConfig == 0)
-
-/** \brief System Tick Configuration
-
- The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
- Counter is in free running mode to generate periodic interrupts.
-
- \param [in] ticks Number of ticks between two interrupts.
-
- \return 0 Function succeeded.
- \return 1 Function failed.
-
- \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
- function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
- must contain a vendor-specific implementation of this function.
-
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
- if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
-
- SysTick->LOAD = ticks - 1; /* set reload register */
- NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
- SysTick->VAL = 0; /* Load the SysTick Counter Value */
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
- SysTick_CTRL_TICKINT_Msk |
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
- return (0); /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-
-#endif /* __CORE_CM0_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Include/core_cm0plus.h b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Include/core_cm0plus.h
deleted file mode 100644
index 5cea74e9af368d558cb8fca0b537eb0061006d92..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Include/core_cm0plus.h
+++ /dev/null
@@ -1,793 +0,0 @@
-/**************************************************************************//**
- * @file core_cm0plus.h
- * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
- * @version V3.20
- * @date 25. February 2013
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2009 - 2013 ARM LIMITED
-
- All rights reserved.
- Redistribution and use in source and binary forms, with or without
- modification, are permitted provided that the following conditions are met:
- - Redistributions of source code must retain the above copyright
- notice, this list of conditions and the following disclaimer.
- - Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the distribution.
- - Neither the name of ARM nor the names of its contributors may be used
- to endorse or promote products derived from this software without
- specific prior written permission.
- *
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- POSSIBILITY OF SUCH DAMAGE.
- ---------------------------------------------------------------------------*/
-
-
-#if defined ( __ICCARM__ )
- #pragma system_include /* treat file as system include file for MISRA check */
-#endif
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#ifndef __CORE_CM0PLUS_H_GENERIC
-#define __CORE_CM0PLUS_H_GENERIC
-
-/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
- CMSIS violates the following MISRA-C:2004 rules:
-
- \li Required Rule 8.5, object/function definition in header file.<br>
- Function definitions in header files are used to allow 'inlining'.
-
- \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
- Unions are used for effective representation of core registers.
-
- \li Advisory Rule 19.7, Function-like macro defined.<br>
- Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- * CMSIS definitions
- ******************************************************************************/
-/** \ingroup Cortex-M0+
- @{
- */
-
-/* CMSIS CM0P definitions */
-#define __CM0PLUS_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
-#define __CM0PLUS_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
-#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
- __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
-
-#define __CORTEX_M (0x00) /*!< Cortex-M Core */
-
-
-#if defined ( __CC_ARM )
- #define __ASM __asm /*!< asm keyword for ARM Compiler */
- #define __INLINE __inline /*!< inline keyword for ARM Compiler */
- #define __STATIC_INLINE static __inline
-
-#elif defined ( __ICCARM__ )
- #define __ASM __asm /*!< asm keyword for IAR Compiler */
- #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
- #define __STATIC_INLINE static inline
-
-#elif defined ( __GNUC__ )
- #define __ASM __asm /*!< asm keyword for GNU Compiler */
- #define __INLINE inline /*!< inline keyword for GNU Compiler */
- #define __STATIC_INLINE static inline
-
-#elif defined ( __TASKING__ )
- #define __ASM __asm /*!< asm keyword for TASKING Compiler */
- #define __INLINE inline /*!< inline keyword for TASKING Compiler */
- #define __STATIC_INLINE static inline
-
-#endif
-
-/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
-*/
-#define __FPU_USED 0
-
-#if defined ( __CC_ARM )
- #if defined __TARGET_FPU_VFP
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __ICCARM__ )
- #if defined __ARMVFP__
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __GNUC__ )
- #if defined (__VFP_FP__) && !defined(__SOFTFP__)
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __TASKING__ )
- #if defined __FPU_VFP__
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-#endif
-
-#include <stdint.h> /* standard types definitions */
-#include <core_cmInstr.h> /* Core Instruction Access */
-#include <core_cmFunc.h> /* Core Function Access */
-
-#endif /* __CORE_CM0PLUS_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM0PLUS_H_DEPENDANT
-#define __CORE_CM0PLUS_H_DEPENDANT
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
- #ifndef __CM0PLUS_REV
- #define __CM0PLUS_REV 0x0000
- #warning "__CM0PLUS_REV not defined in device header file; using default!"
- #endif
-
- #ifndef __MPU_PRESENT
- #define __MPU_PRESENT 0
- #warning "__MPU_PRESENT not defined in device header file; using default!"
- #endif
-
- #ifndef __VTOR_PRESENT
- #define __VTOR_PRESENT 0
- #warning "__VTOR_PRESENT not defined in device header file; using default!"
- #endif
-
- #ifndef __NVIC_PRIO_BITS
- #define __NVIC_PRIO_BITS 2
- #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
- #endif
-
- #ifndef __Vendor_SysTickConfig
- #define __Vendor_SysTickConfig 0
- #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
- #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
- \defgroup CMSIS_glob_defs CMSIS Global Defines
-
- <strong>IO Type Qualifiers</strong> are used
- \li to specify the access to peripheral variables.
- \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
- #define __I volatile /*!< Defines 'read only' permissions */
-#else
- #define __I volatile const /*!< Defines 'read only' permissions */
-#endif
-#define __O volatile /*!< Defines 'write only' permissions */
-#define __IO volatile /*!< Defines 'read / write' permissions */
-
-/*@} end of group Cortex-M0+ */
-
-
-
-/*******************************************************************************
- * Register Abstraction
- Core Register contain:
- - Core Register
- - Core NVIC Register
- - Core SCB Register
- - Core SysTick Register
- - Core MPU Register
- ******************************************************************************/
-/** \defgroup CMSIS_core_register Defines and Type Definitions
- \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_CORE Status and Control Registers
- \brief Core Register type definitions.
- @{
- */
-
-/** \brief Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
- struct
- {
-#if (__CORTEX_M != 0x04)
- uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
-#else
- uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
- uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
-#endif
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} APSR_Type;
-
-
-/** \brief Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
- uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} IPSR_Type;
-
-
-/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
-#if (__CORTEX_M != 0x04)
- uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
-#else
- uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
- uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
-#endif
- uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
- uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} xPSR_Type;
-
-
-/** \brief Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
- struct
- {
- uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
- uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
- uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
- uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} CONTROL_Type;
-
-/*@} end of group CMSIS_CORE */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
- \brief Type definitions for the NVIC Registers
- @{
- */
-
-/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
- __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
- uint32_t RESERVED0[31];
- __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
- uint32_t RSERVED1[31];
- __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
- uint32_t RESERVED2[31];
- __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
- uint32_t RESERVED3[31];
- uint32_t RESERVED4[64];
- __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
-} NVIC_Type;
-
-/*@} end of group CMSIS_NVIC */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_SCB System Control Block (SCB)
- \brief Type definitions for the System Control Block Registers
- @{
- */
-
-/** \brief Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
- __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
- __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
-#if (__VTOR_PRESENT == 1)
- __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
-#else
- uint32_t RESERVED0;
-#endif
- __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
- __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
- __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
- uint32_t RESERVED1;
- __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
- __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
-
-#if (__VTOR_PRESENT == 1)
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
-#endif
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_SysTick System Tick Timer (SysTick)
- \brief Type definitions for the System Timer Registers.
- @{
- */
-
-/** \brief Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
- __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
- __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
- __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
- __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-#if (__MPU_PRESENT == 1)
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_MPU Memory Protection Unit (MPU)
- \brief Type definitions for the Memory Protection Unit (MPU)
- @{
- */
-
-/** \brief Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct
-{
- __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
- __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
- __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
- __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
- __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
-} MPU_Type;
-
-/* MPU Type Register */
-#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register */
-#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register */
-#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register */
-#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
-
-#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
-
-/* MPU Region Attribute and Size Register */
-#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
-#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
-
-#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
-#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
-
-#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
-#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
-
-#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
-#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
-
-#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
-#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
-
-#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
-#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
-
-#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
-#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
-
-#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
-
-#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
-
-#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
- \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR)
- are only accessible over DAP and not via processor. Therefore
- they are not covered by the Cortex-M0 header file.
- @{
- */
-/*@} end of group CMSIS_CoreDebug */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_core_base Core Definitions
- \brief Definitions for base addresses, unions, and structures.
- @{
- */
-
-/* Memory mapping of Cortex-M0+ Hardware */
-#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
-#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
-#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
-#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
-
-#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
-#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
-#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
-
-#if (__MPU_PRESENT == 1)
- #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
- #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
-#endif
-
-/*@} */
-
-
-
-/*******************************************************************************
- * Hardware Abstraction Layer
- Core Function Interface contains:
- - Core NVIC Functions
- - Core SysTick Functions
- - Core Register Access Functions
- ******************************************************************************/
-/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ########################## NVIC functions #################################### */
-/** \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_NVICFunctions NVIC Functions
- \brief Functions that manage interrupts and exceptions via the NVIC.
- @{
- */
-
-/* Interrupt Priorities are WORD accessible only under ARMv6M */
-/* The following MACROS handle generation of the register offset and byte masks */
-#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
-#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
-#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
-
-
-/** \brief Enable External Interrupt
-
- The function enables a device-specific interrupt in the NVIC interrupt controller.
-
- \param [in] IRQn External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
-{
- NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
-}
-
-
-/** \brief Disable External Interrupt
-
- The function disables a device-specific interrupt in the NVIC interrupt controller.
-
- \param [in] IRQn External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
-{
- NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
-}
-
-
-/** \brief Get Pending Interrupt
-
- The function reads the pending register in the NVIC and returns the pending bit
- for the specified interrupt.
-
- \param [in] IRQn Interrupt number.
-
- \return 0 Interrupt status is not pending.
- \return 1 Interrupt status is pending.
- */
-__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
- return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
-}
-
-
-/** \brief Set Pending Interrupt
-
- The function sets the pending bit of an external interrupt.
-
- \param [in] IRQn Interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
- NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
-}
-
-
-/** \brief Clear Pending Interrupt
-
- The function clears the pending bit of an external interrupt.
-
- \param [in] IRQn External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
- NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
-}
-
-
-/** \brief Set Interrupt Priority
-
- The function sets the priority of an interrupt.
-
- \note The priority cannot be set for every core interrupt.
-
- \param [in] IRQn Interrupt number.
- \param [in] priority Priority to set.
- */
-__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
- if(IRQn < 0) {
- SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
- (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
- else {
- NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
- (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
-}
-
-
-/** \brief Get Interrupt Priority
-
- The function reads the priority of an interrupt. The interrupt
- number can be positive to specify an external (device specific)
- interrupt, or negative to specify an internal (core) interrupt.
-
-
- \param [in] IRQn Interrupt number.
- \return Interrupt Priority. Value is aligned automatically to the implemented
- priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
-{
-
- if(IRQn < 0) {
- return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
- else {
- return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
-}
-
-
-/** \brief System Reset
-
- The function initiates a system reset request to reset the MCU.
- */
-__STATIC_INLINE void NVIC_SystemReset(void)
-{
- __DSB(); /* Ensure all outstanding memory accesses included
- buffered write are completed before reset */
- SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
- SCB_AIRCR_SYSRESETREQ_Msk);
- __DSB(); /* Ensure completion of memory access */
- while(1); /* wait until reset */
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-
-/* ################################## SysTick function ############################################ */
-/** \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
- \brief Functions that configure the System.
- @{
- */
-
-#if (__Vendor_SysTickConfig == 0)
-
-/** \brief System Tick Configuration
-
- The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
- Counter is in free running mode to generate periodic interrupts.
-
- \param [in] ticks Number of ticks between two interrupts.
-
- \return 0 Function succeeded.
- \return 1 Function failed.
-
- \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
- function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
- must contain a vendor-specific implementation of this function.
-
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
- if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
-
- SysTick->LOAD = ticks - 1; /* set reload register */
- NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
- SysTick->VAL = 0; /* Load the SysTick Counter Value */
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
- SysTick_CTRL_TICKINT_Msk |
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
- return (0); /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-
-#endif /* __CORE_CM0PLUS_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Include/core_cm3.h b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Include/core_cm3.h
deleted file mode 100644
index 122c9aa4a8fd6832d39545a26636a662c7ff317c..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Include/core_cm3.h
+++ /dev/null
@@ -1,1627 +0,0 @@
-/**************************************************************************//**
- * @file core_cm3.h
- * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
- * @version V3.20
- * @date 25. February 2013
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2009 - 2013 ARM LIMITED
-
- All rights reserved.
- Redistribution and use in source and binary forms, with or without
- modification, are permitted provided that the following conditions are met:
- - Redistributions of source code must retain the above copyright
- notice, this list of conditions and the following disclaimer.
- - Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the distribution.
- - Neither the name of ARM nor the names of its contributors may be used
- to endorse or promote products derived from this software without
- specific prior written permission.
- *
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- POSSIBILITY OF SUCH DAMAGE.
- ---------------------------------------------------------------------------*/
-
-
-#if defined ( __ICCARM__ )
- #pragma system_include /* treat file as system include file for MISRA check */
-#endif
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#ifndef __CORE_CM3_H_GENERIC
-#define __CORE_CM3_H_GENERIC
-
-/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
- CMSIS violates the following MISRA-C:2004 rules:
-
- \li Required Rule 8.5, object/function definition in header file.<br>
- Function definitions in header files are used to allow 'inlining'.
-
- \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
- Unions are used for effective representation of core registers.
-
- \li Advisory Rule 19.7, Function-like macro defined.<br>
- Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- * CMSIS definitions
- ******************************************************************************/
-/** \ingroup Cortex_M3
- @{
- */
-
-/* CMSIS CM3 definitions */
-#define __CM3_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
-#define __CM3_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
-#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \
- __CM3_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
-
-#define __CORTEX_M (0x03) /*!< Cortex-M Core */
-
-
-#if defined ( __CC_ARM )
- #define __ASM __asm /*!< asm keyword for ARM Compiler */
- #define __INLINE __inline /*!< inline keyword for ARM Compiler */
- #define __STATIC_INLINE static __inline
-
-#elif defined ( __ICCARM__ )
- #define __ASM __asm /*!< asm keyword for IAR Compiler */
- #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
- #define __STATIC_INLINE static inline
-
-#elif defined ( __TMS470__ )
- #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
- #define __STATIC_INLINE static inline
-
-#elif defined ( __GNUC__ )
- #define __ASM __asm /*!< asm keyword for GNU Compiler */
- #define __INLINE inline /*!< inline keyword for GNU Compiler */
- #define __STATIC_INLINE static inline
-
-#elif defined ( __TASKING__ )
- #define __ASM __asm /*!< asm keyword for TASKING Compiler */
- #define __INLINE inline /*!< inline keyword for TASKING Compiler */
- #define __STATIC_INLINE static inline
-
-#endif
-
-/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
-*/
-#define __FPU_USED 0
-
-#if defined ( __CC_ARM )
- #if defined __TARGET_FPU_VFP
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __ICCARM__ )
- #if defined __ARMVFP__
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __TMS470__ )
- #if defined __TI__VFP_SUPPORT____
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __GNUC__ )
- #if defined (__VFP_FP__) && !defined(__SOFTFP__)
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __TASKING__ )
- #if defined __FPU_VFP__
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-#endif
-
-#include <stdint.h> /* standard types definitions */
-#include <core_cmInstr.h> /* Core Instruction Access */
-#include <core_cmFunc.h> /* Core Function Access */
-
-#endif /* __CORE_CM3_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM3_H_DEPENDANT
-#define __CORE_CM3_H_DEPENDANT
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
- #ifndef __CM3_REV
- #define __CM3_REV 0x0200
- #warning "__CM3_REV not defined in device header file; using default!"
- #endif
-
- #ifndef __MPU_PRESENT
- #define __MPU_PRESENT 0
- #warning "__MPU_PRESENT not defined in device header file; using default!"
- #endif
-
- #ifndef __NVIC_PRIO_BITS
- #define __NVIC_PRIO_BITS 4
- #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
- #endif
-
- #ifndef __Vendor_SysTickConfig
- #define __Vendor_SysTickConfig 0
- #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
- #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
- \defgroup CMSIS_glob_defs CMSIS Global Defines
-
- <strong>IO Type Qualifiers</strong> are used
- \li to specify the access to peripheral variables.
- \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
- #define __I volatile /*!< Defines 'read only' permissions */
-#else
- #define __I volatile const /*!< Defines 'read only' permissions */
-#endif
-#define __O volatile /*!< Defines 'write only' permissions */
-#define __IO volatile /*!< Defines 'read / write' permissions */
-
-/*@} end of group Cortex_M3 */
-
-
-
-/*******************************************************************************
- * Register Abstraction
- Core Register contain:
- - Core Register
- - Core NVIC Register
- - Core SCB Register
- - Core SysTick Register
- - Core Debug Register
- - Core MPU Register
- ******************************************************************************/
-/** \defgroup CMSIS_core_register Defines and Type Definitions
- \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_CORE Status and Control Registers
- \brief Core Register type definitions.
- @{
- */
-
-/** \brief Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
- struct
- {
-#if (__CORTEX_M != 0x04)
- uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
-#else
- uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
- uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
-#endif
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} APSR_Type;
-
-
-/** \brief Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
- uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} IPSR_Type;
-
-
-/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
-#if (__CORTEX_M != 0x04)
- uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
-#else
- uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
- uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
-#endif
- uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
- uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} xPSR_Type;
-
-
-/** \brief Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
- struct
- {
- uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
- uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
- uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
- uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} CONTROL_Type;
-
-/*@} end of group CMSIS_CORE */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
- \brief Type definitions for the NVIC Registers
- @{
- */
-
-/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
- __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
- uint32_t RESERVED0[24];
- __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
- uint32_t RSERVED1[24];
- __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
- uint32_t RESERVED2[24];
- __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
- uint32_t RESERVED3[24];
- __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
- uint32_t RESERVED4[56];
- __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
- uint32_t RESERVED5[644];
- __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
-} NVIC_Type;
-
-/* Software Triggered Interrupt Register Definitions */
-#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
-#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */
-
-/*@} end of group CMSIS_NVIC */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_SCB System Control Block (SCB)
- \brief Type definitions for the System Control Block Registers
- @{
- */
-
-/** \brief Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
- __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
- __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
- __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
- __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
- __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
- __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
- __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
- __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
- __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
- __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
- __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
- __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
- __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
- __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
- __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
- __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
- __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
- __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
- __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
- uint32_t RESERVED0[5];
- __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Vector Table Offset Register Definitions */
-#if (__CM3_REV < 0x0201) /* core r2p1 */
-#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
-#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
-
-#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
-#else
-#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
-#endif
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
-#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
-#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
-
-#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
-
-#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
-
-#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
-#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
-#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
-
-#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
-#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
-
-#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
-#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
-
-#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
-#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
-
-#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
-#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
-
-#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
-#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
-
-#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
-
-#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
-
-#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
-#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
-
-#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
-
-#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
-#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
-
-#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
-#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
-
-#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
-#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
-
-/* SCB Configurable Fault Status Registers Definitions */
-#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
-#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
-
-#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
-#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
-
-#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
-#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
-
-/* SCB Hard Fault Status Registers Definitions */
-#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
-#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
-
-#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
-#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
-
-#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
-#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
-
-/* SCB Debug Fault Status Register Definitions */
-#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
-#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
-
-#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
-#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
-
-#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
-#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
-
-#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
-#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
-
-#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
-#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
- \brief Type definitions for the System Control and ID Register not in the SCB
- @{
- */
-
-/** \brief Structure type to access the System Control and ID Register not in the SCB.
- */
-typedef struct
-{
- uint32_t RESERVED0[1];
- __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
-#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
- __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
-#else
- uint32_t RESERVED1[1];
-#endif
-} SCnSCB_Type;
-
-/* Interrupt Controller Type Register Definitions */
-#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
-#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */
-
-/* Auxiliary Control Register Definitions */
-
-#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
-#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
-
-#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */
-#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
-
-#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
-#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */
-
-/*@} end of group CMSIS_SCnotSCB */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_SysTick System Tick Timer (SysTick)
- \brief Type definitions for the System Timer Registers.
- @{
- */
-
-/** \brief Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
- __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
- __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
- __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
- __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
- \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
- @{
- */
-
-/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
- */
-typedef struct
-{
- __O union
- {
- __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
- __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
- __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
- } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
- uint32_t RESERVED0[864];
- __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
- uint32_t RESERVED1[15];
- __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
- uint32_t RESERVED2[15];
- __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
- uint32_t RESERVED3[29];
- __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
- __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
- __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
- uint32_t RESERVED4[43];
- __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
- __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
- uint32_t RESERVED5[6];
- __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
- __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
- __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
- __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
- __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
- __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
- __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
- __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
- __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
- __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
- __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
- __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
-} ITM_Type;
-
-/* ITM Trace Privilege Register Definitions */
-#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
-
-/* ITM Trace Control Register Definitions */
-#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
-#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
-
-#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
-#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
-
-#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
-#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
-
-#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
-#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
-
-#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
-#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
-
-#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
-#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
-
-#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
-#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
-
-#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
-#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
-
-#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
-
-/* ITM Integration Write Register Definitions */
-#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
-#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */
-
-/* ITM Integration Read Register Definitions */
-#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
-#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */
-
-/* ITM Integration Mode Control Register Definitions */
-#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
-#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */
-
-/* ITM Lock Status Register Definitions */
-#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
-#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
-
-#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
-#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
-
-#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
-#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */
-
-/*@}*/ /* end of group CMSIS_ITM */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
- \brief Type definitions for the Data Watchpoint and Trace (DWT)
- @{
- */
-
-/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
- */
-typedef struct
-{
- __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
- __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
- __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
- __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
- __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
- __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
- __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
- __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
- __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
- __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
- __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
- uint32_t RESERVED0[1];
- __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
- __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
- __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
- uint32_t RESERVED1[1];
- __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
- __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
- __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
- uint32_t RESERVED2[1];
- __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
- __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
- __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
-} DWT_Type;
-
-/* DWT Control Register Definitions */
-#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
-#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
-
-#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
-#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
-
-#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
-#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
-
-#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
-#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
-
-#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
-#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
-
-#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
-#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
-
-#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
-#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
-
-#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
-#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
-
-#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
-#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
-
-#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
-#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
-
-#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
-#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
-
-#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
-#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
-
-#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
-#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
-
-#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
-#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
-
-#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
-#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
-
-#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
-#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
-
-#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
-#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
-
-#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
-#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */
-
-/* DWT CPI Count Register Definitions */
-#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
-#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */
-
-/* DWT Exception Overhead Count Register Definitions */
-#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
-#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */
-
-/* DWT Sleep Count Register Definitions */
-#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
-#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
-
-/* DWT LSU Count Register Definitions */
-#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
-#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */
-
-/* DWT Folded-instruction Count Register Definitions */
-#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
-#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */
-
-/* DWT Comparator Mask Register Definitions */
-#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
-#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */
-
-/* DWT Comparator Function Register Definitions */
-#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
-#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
-
-#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
-#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
-
-#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
-#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
-
-#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
-#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
-
-#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
-#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
-
-#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
-#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
-
-#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
-#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
-
-#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
-#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
-
-#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
-#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */
-
-/*@}*/ /* end of group CMSIS_DWT */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_TPI Trace Port Interface (TPI)
- \brief Type definitions for the Trace Port Interface (TPI)
- @{
- */
-
-/** \brief Structure type to access the Trace Port Interface Register (TPI).
- */
-typedef struct
-{
- __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
- __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
- uint32_t RESERVED0[2];
- __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
- uint32_t RESERVED1[55];
- __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
- uint32_t RESERVED2[131];
- __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
- __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
- __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
- uint32_t RESERVED3[759];
- __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
- __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
- __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
- uint32_t RESERVED4[1];
- __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
- __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
- __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
- uint32_t RESERVED5[39];
- __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
- __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
- uint32_t RESERVED7[8];
- __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
- __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
-} TPI_Type;
-
-/* TPI Asynchronous Clock Prescaler Register Definitions */
-#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
-#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */
-
-/* TPI Selected Pin Protocol Register Definitions */
-#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
-#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */
-
-/* TPI Formatter and Flush Status Register Definitions */
-#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
-#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
-
-#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
-#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
-
-#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
-#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
-
-#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
-#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */
-
-/* TPI Formatter and Flush Control Register Definitions */
-#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
-#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
-
-#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
-#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
-
-/* TPI TRIGGER Register Definitions */
-#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
-#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */
-
-/* TPI Integration ETM Data Register Definitions (FIFO0) */
-#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
-#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
-
-#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
-#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
-
-#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
-#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
-
-#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
-#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
-
-#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
-#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
-
-#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
-#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
-
-#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
-#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */
-
-/* TPI ITATBCTR2 Register Definitions */
-#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
-#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */
-
-/* TPI Integration ITM Data Register Definitions (FIFO1) */
-#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
-#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
-
-#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
-#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
-
-#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
-#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
-
-#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
-#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
-
-#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
-#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
-
-#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
-#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
-
-#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
-#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */
-
-/* TPI ITATBCTR0 Register Definitions */
-#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
-#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */
-
-/* TPI Integration Mode Control Register Definitions */
-#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
-#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */
-
-/* TPI DEVID Register Definitions */
-#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
-#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
-
-#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
-#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
-
-#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
-#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
-
-#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
-#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
-
-#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
-#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
-
-#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
-#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */
-
-/* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
-#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */
-
-#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
-#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
-
-/*@}*/ /* end of group CMSIS_TPI */
-
-
-#if (__MPU_PRESENT == 1)
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_MPU Memory Protection Unit (MPU)
- \brief Type definitions for the Memory Protection Unit (MPU)
- @{
- */
-
-/** \brief Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct
-{
- __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
- __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
- __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
- __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
- __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
- __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
- __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
- __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
- __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
- __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
- __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
-} MPU_Type;
-
-/* MPU Type Register */
-#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register */
-#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register */
-#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register */
-#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
-
-#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
-
-/* MPU Region Attribute and Size Register */
-#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
-#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
-
-#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
-#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
-
-#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
-#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
-
-#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
-#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
-
-#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
-#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
-
-#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
-#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
-
-#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
-#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
-
-#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
-
-#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
-
-#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
- \brief Type definitions for the Core Debug Registers
- @{
- */
-
-/** \brief Structure type to access the Core Debug Register (CoreDebug).
- */
-typedef struct
-{
- __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
- __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
- __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
- __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
-} CoreDebug_Type;
-
-/* Debug Halting Control and Status Register */
-#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register */
-#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register */
-#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
-#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
-
-#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
-#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
-
-#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
-#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
-
-#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
-#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
-
-#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
-#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
-#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
-
-#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
-#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
-
-#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
-#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
-
-#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
-#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
-
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
-
-#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
-#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-
-/*@} end of group CMSIS_CoreDebug */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_core_base Core Definitions
- \brief Definitions for base addresses, unions, and structures.
- @{
- */
-
-/* Memory mapping of Cortex-M3 Hardware */
-#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
-#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
-#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
-#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
-#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
-#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
-#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
-#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
-
-#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
-#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
-#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
-#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
-#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
-#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
-#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
-#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
-
-#if (__MPU_PRESENT == 1)
- #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
- #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
-#endif
-
-/*@} */
-
-
-
-/*******************************************************************************
- * Hardware Abstraction Layer
- Core Function Interface contains:
- - Core NVIC Functions
- - Core SysTick Functions
- - Core Debug Functions
- - Core Register Access Functions
- ******************************************************************************/
-/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ########################## NVIC functions #################################### */
-/** \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_NVICFunctions NVIC Functions
- \brief Functions that manage interrupts and exceptions via the NVIC.
- @{
- */
-
-/** \brief Set Priority Grouping
-
- The function sets the priority grouping field using the required unlock sequence.
- The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
- Only values from 0..7 are used.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-
- \param [in] PriorityGroup Priority grouping field.
- */
-__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
- uint32_t reg_value;
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
-
- reg_value = SCB->AIRCR; /* read old register configuration */
- reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
- reg_value = (reg_value |
- ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
- (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
- SCB->AIRCR = reg_value;
-}
-
-
-/** \brief Get Priority Grouping
-
- The function reads the priority grouping field from the NVIC Interrupt Controller.
-
- \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
- */
-__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
-{
- return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
-}
-
-
-/** \brief Enable External Interrupt
-
- The function enables a device-specific interrupt in the NVIC interrupt controller.
-
- \param [in] IRQn External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
-{
- NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
-}
-
-
-/** \brief Disable External Interrupt
-
- The function disables a device-specific interrupt in the NVIC interrupt controller.
-
- \param [in] IRQn External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
-{
- NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
-}
-
-
-/** \brief Get Pending Interrupt
-
- The function reads the pending register in the NVIC and returns the pending bit
- for the specified interrupt.
-
- \param [in] IRQn Interrupt number.
-
- \return 0 Interrupt status is not pending.
- \return 1 Interrupt status is pending.
- */
-__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
- return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
-}
-
-
-/** \brief Set Pending Interrupt
-
- The function sets the pending bit of an external interrupt.
-
- \param [in] IRQn Interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
- NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
-}
-
-
-/** \brief Clear Pending Interrupt
-
- The function clears the pending bit of an external interrupt.
-
- \param [in] IRQn External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
- NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
-}
-
-
-/** \brief Get Active Interrupt
-
- The function reads the active register in NVIC and returns the active bit.
-
- \param [in] IRQn Interrupt number.
-
- \return 0 Interrupt status is not active.
- \return 1 Interrupt status is active.
- */
-__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
-{
- return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
-}
-
-
-/** \brief Set Interrupt Priority
-
- The function sets the priority of an interrupt.
-
- \note The priority cannot be set for every core interrupt.
-
- \param [in] IRQn Interrupt number.
- \param [in] priority Priority to set.
- */
-__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
- if(IRQn < 0) {
- SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
- else {
- NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
-}
-
-
-/** \brief Get Interrupt Priority
-
- The function reads the priority of an interrupt. The interrupt
- number can be positive to specify an external (device specific)
- interrupt, or negative to specify an internal (core) interrupt.
-
-
- \param [in] IRQn Interrupt number.
- \return Interrupt Priority. Value is aligned automatically to the implemented
- priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
-{
-
- if(IRQn < 0) {
- return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
- else {
- return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
-}
-
-
-/** \brief Encode Priority
-
- The function encodes the priority for an interrupt with the given priority group,
- preemptive priority value, and subpriority value.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
-
- \param [in] PriorityGroup Used priority group.
- \param [in] PreemptPriority Preemptive priority value (starting from 0).
- \param [in] SubPriority Subpriority value (starting from 0).
- \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
- */
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
- uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
- uint32_t PreemptPriorityBits;
- uint32_t SubPriorityBits;
-
- PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
- SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
-
- return (
- ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
- ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
- );
-}
-
-
-/** \brief Decode Priority
-
- The function decodes an interrupt priority value with a given priority group to
- preemptive priority value and subpriority value.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
-
- \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
- \param [in] PriorityGroup Used priority group.
- \param [out] pPreemptPriority Preemptive priority value (starting from 0).
- \param [out] pSubPriority Subpriority value (starting from 0).
- */
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
-{
- uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
- uint32_t PreemptPriorityBits;
- uint32_t SubPriorityBits;
-
- PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
- SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
-
- *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
- *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
-}
-
-
-/** \brief System Reset
-
- The function initiates a system reset request to reset the MCU.
- */
-__STATIC_INLINE void NVIC_SystemReset(void)
-{
- __DSB(); /* Ensure all outstanding memory accesses included
- buffered write are completed before reset */
- SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
- (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
- SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
- __DSB(); /* Ensure completion of memory access */
- while(1); /* wait until reset */
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-
-/* ################################## SysTick function ############################################ */
-/** \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
- \brief Functions that configure the System.
- @{
- */
-
-#if (__Vendor_SysTickConfig == 0)
-
-/** \brief System Tick Configuration
-
- The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
- Counter is in free running mode to generate periodic interrupts.
-
- \param [in] ticks Number of ticks between two interrupts.
-
- \return 0 Function succeeded.
- \return 1 Function failed.
-
- \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
- function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
- must contain a vendor-specific implementation of this function.
-
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
- if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
-
- SysTick->LOAD = ticks - 1; /* set reload register */
- NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
- SysTick->VAL = 0; /* Load the SysTick Counter Value */
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
- SysTick_CTRL_TICKINT_Msk |
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
- return (0); /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-/* ##################################### Debug In/Output function ########################################### */
-/** \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_core_DebugFunctions ITM Functions
- \brief Functions that access the ITM debug interface.
- @{
- */
-
-extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
-#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
-
-
-/** \brief ITM Send Character
-
- The function transmits a character via the ITM channel 0, and
- \li Just returns when no debugger is connected that has booked the output.
- \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
-
- \param [in] ch Character to transmit.
-
- \returns Character to transmit.
- */
-__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
-{
- if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
- (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
- {
- while (ITM->PORT[0].u32 == 0);
- ITM->PORT[0].u8 = (uint8_t) ch;
- }
- return (ch);
-}
-
-
-/** \brief ITM Receive Character
-
- The function inputs a character via the external variable \ref ITM_RxBuffer.
-
- \return Received character.
- \return -1 No character pending.
- */
-__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
- int32_t ch = -1; /* no character available */
-
- if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
- ch = ITM_RxBuffer;
- ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
- }
-
- return (ch);
-}
-
-
-/** \brief ITM Check Character
-
- The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
-
- \return 0 No character available.
- \return 1 Character available.
- */
-__STATIC_INLINE int32_t ITM_CheckChar (void) {
-
- if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
- return (0); /* no character available */
- } else {
- return (1); /* character available */
- }
-}
-
-/*@} end of CMSIS_core_DebugFunctions */
-
-#endif /* __CORE_CM3_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Include/core_cm4.h b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Include/core_cm4.h
deleted file mode 100644
index d65016c714944b5eb2d3dac3ea544d0decd231bc..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Include/core_cm4.h
+++ /dev/null
@@ -1,1772 +0,0 @@
-/**************************************************************************//**
- * @file core_cm4.h
- * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
- * @version V3.20
- * @date 25. February 2013
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2009 - 2013 ARM LIMITED
-
- All rights reserved.
- Redistribution and use in source and binary forms, with or without
- modification, are permitted provided that the following conditions are met:
- - Redistributions of source code must retain the above copyright
- notice, this list of conditions and the following disclaimer.
- - Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the distribution.
- - Neither the name of ARM nor the names of its contributors may be used
- to endorse or promote products derived from this software without
- specific prior written permission.
- *
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- POSSIBILITY OF SUCH DAMAGE.
- ---------------------------------------------------------------------------*/
-
-
-#if defined ( __ICCARM__ )
- #pragma system_include /* treat file as system include file for MISRA check */
-#endif
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#ifndef __CORE_CM4_H_GENERIC
-#define __CORE_CM4_H_GENERIC
-
-/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
- CMSIS violates the following MISRA-C:2004 rules:
-
- \li Required Rule 8.5, object/function definition in header file.<br>
- Function definitions in header files are used to allow 'inlining'.
-
- \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
- Unions are used for effective representation of core registers.
-
- \li Advisory Rule 19.7, Function-like macro defined.<br>
- Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- * CMSIS definitions
- ******************************************************************************/
-/** \ingroup Cortex_M4
- @{
- */
-
-/* CMSIS CM4 definitions */
-#define __CM4_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
-#define __CM4_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
-#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \
- __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
-
-#define __CORTEX_M (0x04) /*!< Cortex-M Core */
-
-
-#if defined ( __CC_ARM )
- #define __ASM __asm /*!< asm keyword for ARM Compiler */
- #define __INLINE __inline /*!< inline keyword for ARM Compiler */
- #define __STATIC_INLINE static __inline
-
-#elif defined ( __ICCARM__ )
- #define __ASM __asm /*!< asm keyword for IAR Compiler */
- #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
- #define __STATIC_INLINE static inline
-
-#elif defined ( __TMS470__ )
- #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
- #define __STATIC_INLINE static inline
-
-#elif defined ( __GNUC__ )
- #define __ASM __asm /*!< asm keyword for GNU Compiler */
- #define __INLINE inline /*!< inline keyword for GNU Compiler */
- #define __STATIC_INLINE static inline
-
-#elif defined ( __TASKING__ )
- #define __ASM __asm /*!< asm keyword for TASKING Compiler */
- #define __INLINE inline /*!< inline keyword for TASKING Compiler */
- #define __STATIC_INLINE static inline
-
-#endif
-
-/** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
-*/
-#if defined ( __CC_ARM )
- #if defined __TARGET_FPU_VFP
- #if (__FPU_PRESENT == 1)
- #define __FPU_USED 1
- #else
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0
- #endif
- #else
- #define __FPU_USED 0
- #endif
-
-#elif defined ( __ICCARM__ )
- #if defined __ARMVFP__
- #if (__FPU_PRESENT == 1)
- #define __FPU_USED 1
- #else
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0
- #endif
- #else
- #define __FPU_USED 0
- #endif
-
-#elif defined ( __TMS470__ )
- #if defined __TI_VFP_SUPPORT__
- #if (__FPU_PRESENT == 1)
- #define __FPU_USED 1
- #else
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0
- #endif
- #else
- #define __FPU_USED 0
- #endif
-
-#elif defined ( __GNUC__ )
- #if defined (__VFP_FP__) && !defined(__SOFTFP__)
- #if (__FPU_PRESENT == 1)
- #define __FPU_USED 1
- #else
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0
- #endif
- #else
- #define __FPU_USED 0
- #endif
-
-#elif defined ( __TASKING__ )
- #if defined __FPU_VFP__
- #if (__FPU_PRESENT == 1)
- #define __FPU_USED 1
- #else
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #define __FPU_USED 0
- #endif
- #else
- #define __FPU_USED 0
- #endif
-#endif
-
-#include <stdint.h> /* standard types definitions */
-#include <core_cmInstr.h> /* Core Instruction Access */
-#include <core_cmFunc.h> /* Core Function Access */
-#include <core_cm4_simd.h> /* Compiler specific SIMD Intrinsics */
-
-#endif /* __CORE_CM4_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_CM4_H_DEPENDANT
-#define __CORE_CM4_H_DEPENDANT
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
- #ifndef __CM4_REV
- #define __CM4_REV 0x0000
- #warning "__CM4_REV not defined in device header file; using default!"
- #endif
-
- #ifndef __FPU_PRESENT
- #define __FPU_PRESENT 0
- #warning "__FPU_PRESENT not defined in device header file; using default!"
- #endif
-
- #ifndef __MPU_PRESENT
- #define __MPU_PRESENT 0
- #warning "__MPU_PRESENT not defined in device header file; using default!"
- #endif
-
- #ifndef __NVIC_PRIO_BITS
- #define __NVIC_PRIO_BITS 4
- #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
- #endif
-
- #ifndef __Vendor_SysTickConfig
- #define __Vendor_SysTickConfig 0
- #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
- #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
- \defgroup CMSIS_glob_defs CMSIS Global Defines
-
- <strong>IO Type Qualifiers</strong> are used
- \li to specify the access to peripheral variables.
- \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
- #define __I volatile /*!< Defines 'read only' permissions */
-#else
- #define __I volatile const /*!< Defines 'read only' permissions */
-#endif
-#define __O volatile /*!< Defines 'write only' permissions */
-#define __IO volatile /*!< Defines 'read / write' permissions */
-
-/*@} end of group Cortex_M4 */
-
-
-
-/*******************************************************************************
- * Register Abstraction
- Core Register contain:
- - Core Register
- - Core NVIC Register
- - Core SCB Register
- - Core SysTick Register
- - Core Debug Register
- - Core MPU Register
- - Core FPU Register
- ******************************************************************************/
-/** \defgroup CMSIS_core_register Defines and Type Definitions
- \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_CORE Status and Control Registers
- \brief Core Register type definitions.
- @{
- */
-
-/** \brief Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
- struct
- {
-#if (__CORTEX_M != 0x04)
- uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
-#else
- uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
- uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
-#endif
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} APSR_Type;
-
-
-/** \brief Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
- uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} IPSR_Type;
-
-
-/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
-#if (__CORTEX_M != 0x04)
- uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
-#else
- uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
- uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
-#endif
- uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
- uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} xPSR_Type;
-
-
-/** \brief Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
- struct
- {
- uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
- uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
- uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
- uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} CONTROL_Type;
-
-/*@} end of group CMSIS_CORE */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
- \brief Type definitions for the NVIC Registers
- @{
- */
-
-/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
- __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
- uint32_t RESERVED0[24];
- __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
- uint32_t RSERVED1[24];
- __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
- uint32_t RESERVED2[24];
- __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
- uint32_t RESERVED3[24];
- __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
- uint32_t RESERVED4[56];
- __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
- uint32_t RESERVED5[644];
- __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
-} NVIC_Type;
-
-/* Software Triggered Interrupt Register Definitions */
-#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
-#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */
-
-/*@} end of group CMSIS_NVIC */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_SCB System Control Block (SCB)
- \brief Type definitions for the System Control Block Registers
- @{
- */
-
-/** \brief Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
- __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
- __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
- __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
- __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
- __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
- __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
- __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
- __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
- __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
- __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
- __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
- __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
- __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
- __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
- __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
- __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
- __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
- __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
- __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
- uint32_t RESERVED0[5];
- __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Vector Table Offset Register Definitions */
-#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
-#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
-#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
-
-#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
-
-#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
-
-#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
-#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
-#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
-
-#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
-#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
-
-#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
-#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
-
-#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
-#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
-
-#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
-#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
-
-#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
-#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
-
-#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
-
-#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
-
-#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
-#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
-
-#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
-
-#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
-#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
-
-#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
-#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
-
-#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
-#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
-
-/* SCB Configurable Fault Status Registers Definitions */
-#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
-#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
-
-#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
-#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
-
-#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
-#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
-
-/* SCB Hard Fault Status Registers Definitions */
-#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
-#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
-
-#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
-#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
-
-#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
-#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
-
-/* SCB Debug Fault Status Register Definitions */
-#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
-#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
-
-#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
-#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
-
-#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
-#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
-
-#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
-#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
-
-#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
-#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
- \brief Type definitions for the System Control and ID Register not in the SCB
- @{
- */
-
-/** \brief Structure type to access the System Control and ID Register not in the SCB.
- */
-typedef struct
-{
- uint32_t RESERVED0[1];
- __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
- __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
-} SCnSCB_Type;
-
-/* Interrupt Controller Type Register Definitions */
-#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
-#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */
-
-/* Auxiliary Control Register Definitions */
-#define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */
-#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */
-
-#define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */
-#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */
-
-#define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
-#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
-
-#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */
-#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
-
-#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
-#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */
-
-/*@} end of group CMSIS_SCnotSCB */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_SysTick System Tick Timer (SysTick)
- \brief Type definitions for the System Timer Registers.
- @{
- */
-
-/** \brief Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
- __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
- __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
- __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
- __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
- \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
- @{
- */
-
-/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
- */
-typedef struct
-{
- __O union
- {
- __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
- __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
- __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
- } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
- uint32_t RESERVED0[864];
- __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
- uint32_t RESERVED1[15];
- __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
- uint32_t RESERVED2[15];
- __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
- uint32_t RESERVED3[29];
- __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
- __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
- __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
- uint32_t RESERVED4[43];
- __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
- __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
- uint32_t RESERVED5[6];
- __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
- __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
- __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
- __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
- __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
- __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
- __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
- __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
- __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
- __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
- __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
- __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
-} ITM_Type;
-
-/* ITM Trace Privilege Register Definitions */
-#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
-
-/* ITM Trace Control Register Definitions */
-#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
-#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
-
-#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
-#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
-
-#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
-#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
-
-#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
-#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
-
-#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
-#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
-
-#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
-#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
-
-#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
-#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
-
-#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
-#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
-
-#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
-
-/* ITM Integration Write Register Definitions */
-#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
-#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */
-
-/* ITM Integration Read Register Definitions */
-#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
-#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */
-
-/* ITM Integration Mode Control Register Definitions */
-#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
-#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */
-
-/* ITM Lock Status Register Definitions */
-#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
-#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
-
-#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
-#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
-
-#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
-#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */
-
-/*@}*/ /* end of group CMSIS_ITM */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
- \brief Type definitions for the Data Watchpoint and Trace (DWT)
- @{
- */
-
-/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
- */
-typedef struct
-{
- __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
- __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
- __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
- __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
- __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
- __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
- __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
- __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
- __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
- __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
- __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
- uint32_t RESERVED0[1];
- __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
- __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
- __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
- uint32_t RESERVED1[1];
- __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
- __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
- __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
- uint32_t RESERVED2[1];
- __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
- __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
- __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
-} DWT_Type;
-
-/* DWT Control Register Definitions */
-#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
-#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
-
-#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
-#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
-
-#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
-#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
-
-#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
-#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
-
-#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
-#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
-
-#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
-#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
-
-#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
-#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
-
-#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
-#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
-
-#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
-#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
-
-#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
-#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
-
-#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
-#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
-
-#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
-#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
-
-#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
-#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
-
-#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
-#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
-
-#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
-#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
-
-#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
-#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
-
-#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
-#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
-
-#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
-#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */
-
-/* DWT CPI Count Register Definitions */
-#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
-#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */
-
-/* DWT Exception Overhead Count Register Definitions */
-#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
-#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */
-
-/* DWT Sleep Count Register Definitions */
-#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
-#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
-
-/* DWT LSU Count Register Definitions */
-#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
-#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */
-
-/* DWT Folded-instruction Count Register Definitions */
-#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
-#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */
-
-/* DWT Comparator Mask Register Definitions */
-#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
-#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */
-
-/* DWT Comparator Function Register Definitions */
-#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
-#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
-
-#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
-#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
-
-#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
-#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
-
-#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
-#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
-
-#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
-#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
-
-#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
-#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
-
-#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
-#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
-
-#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
-#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
-
-#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
-#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */
-
-/*@}*/ /* end of group CMSIS_DWT */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_TPI Trace Port Interface (TPI)
- \brief Type definitions for the Trace Port Interface (TPI)
- @{
- */
-
-/** \brief Structure type to access the Trace Port Interface Register (TPI).
- */
-typedef struct
-{
- __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
- __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
- uint32_t RESERVED0[2];
- __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
- uint32_t RESERVED1[55];
- __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
- uint32_t RESERVED2[131];
- __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
- __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
- __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
- uint32_t RESERVED3[759];
- __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
- __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
- __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
- uint32_t RESERVED4[1];
- __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
- __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
- __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
- uint32_t RESERVED5[39];
- __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
- __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
- uint32_t RESERVED7[8];
- __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
- __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
-} TPI_Type;
-
-/* TPI Asynchronous Clock Prescaler Register Definitions */
-#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
-#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */
-
-/* TPI Selected Pin Protocol Register Definitions */
-#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
-#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */
-
-/* TPI Formatter and Flush Status Register Definitions */
-#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
-#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
-
-#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
-#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
-
-#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
-#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
-
-#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
-#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */
-
-/* TPI Formatter and Flush Control Register Definitions */
-#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
-#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
-
-#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
-#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
-
-/* TPI TRIGGER Register Definitions */
-#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
-#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */
-
-/* TPI Integration ETM Data Register Definitions (FIFO0) */
-#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
-#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
-
-#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
-#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
-
-#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
-#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
-
-#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
-#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
-
-#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
-#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
-
-#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
-#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
-
-#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
-#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */
-
-/* TPI ITATBCTR2 Register Definitions */
-#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
-#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */
-
-/* TPI Integration ITM Data Register Definitions (FIFO1) */
-#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
-#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
-
-#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
-#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
-
-#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
-#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
-
-#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
-#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
-
-#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
-#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
-
-#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
-#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
-
-#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
-#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */
-
-/* TPI ITATBCTR0 Register Definitions */
-#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
-#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */
-
-/* TPI Integration Mode Control Register Definitions */
-#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
-#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */
-
-/* TPI DEVID Register Definitions */
-#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
-#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
-
-#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
-#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
-
-#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
-#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
-
-#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
-#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
-
-#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
-#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
-
-#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
-#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */
-
-/* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
-#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */
-
-#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
-#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
-
-/*@}*/ /* end of group CMSIS_TPI */
-
-
-#if (__MPU_PRESENT == 1)
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_MPU Memory Protection Unit (MPU)
- \brief Type definitions for the Memory Protection Unit (MPU)
- @{
- */
-
-/** \brief Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct
-{
- __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
- __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
- __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
- __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
- __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
- __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
- __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
- __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
- __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
- __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
- __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
-} MPU_Type;
-
-/* MPU Type Register */
-#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register */
-#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register */
-#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register */
-#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
-
-#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
-
-/* MPU Region Attribute and Size Register */
-#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
-#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
-
-#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
-#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
-
-#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
-#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
-
-#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
-#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
-
-#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
-#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
-
-#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
-#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
-
-#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
-#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
-
-#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
-
-#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
-
-#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-#if (__FPU_PRESENT == 1)
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_FPU Floating Point Unit (FPU)
- \brief Type definitions for the Floating Point Unit (FPU)
- @{
- */
-
-/** \brief Structure type to access the Floating Point Unit (FPU).
- */
-typedef struct
-{
- uint32_t RESERVED0[1];
- __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
- __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
- __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
- __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
- __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
-} FPU_Type;
-
-/* Floating-Point Context Control Register */
-#define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */
-#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
-
-#define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */
-#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
-
-#define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */
-#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
-
-#define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */
-#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
-
-#define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */
-#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
-
-#define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */
-#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
-
-#define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */
-#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
-
-#define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */
-#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
-
-#define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */
-#define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */
-
-/* Floating-Point Context Address Register */
-#define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */
-#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
-
-/* Floating-Point Default Status Control Register */
-#define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */
-#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
-
-#define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */
-#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
-
-#define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */
-#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
-
-#define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */
-#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
-
-/* Media and FP Feature Register 0 */
-#define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */
-#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
-
-#define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */
-#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
-
-#define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */
-#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
-
-#define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */
-#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
-
-#define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */
-#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
-
-#define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */
-#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
-
-#define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */
-#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
-
-#define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */
-#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */
-
-/* Media and FP Feature Register 1 */
-#define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */
-#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
-
-#define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */
-#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
-
-#define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */
-#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
-
-#define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */
-#define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */
-
-/*@} end of group CMSIS_FPU */
-#endif
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
- \brief Type definitions for the Core Debug Registers
- @{
- */
-
-/** \brief Structure type to access the Core Debug Register (CoreDebug).
- */
-typedef struct
-{
- __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
- __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
- __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
- __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
-} CoreDebug_Type;
-
-/* Debug Halting Control and Status Register */
-#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register */
-#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register */
-#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
-#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
-
-#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
-#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
-
-#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
-#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
-
-#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
-#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
-
-#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
-#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
-#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
-
-#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
-#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
-
-#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
-#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
-
-#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
-#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
-
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
-
-#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
-#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-
-/*@} end of group CMSIS_CoreDebug */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_core_base Core Definitions
- \brief Definitions for base addresses, unions, and structures.
- @{
- */
-
-/* Memory mapping of Cortex-M4 Hardware */
-#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
-#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
-#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
-#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
-#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
-#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
-#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
-#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
-
-#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
-#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
-#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
-#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
-#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
-#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
-#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
-#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
-
-#if (__MPU_PRESENT == 1)
- #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
- #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
-#endif
-
-#if (__FPU_PRESENT == 1)
- #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
- #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
-#endif
-
-/*@} */
-
-
-
-/*******************************************************************************
- * Hardware Abstraction Layer
- Core Function Interface contains:
- - Core NVIC Functions
- - Core SysTick Functions
- - Core Debug Functions
- - Core Register Access Functions
- ******************************************************************************/
-/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ########################## NVIC functions #################################### */
-/** \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_NVICFunctions NVIC Functions
- \brief Functions that manage interrupts and exceptions via the NVIC.
- @{
- */
-
-/** \brief Set Priority Grouping
-
- The function sets the priority grouping field using the required unlock sequence.
- The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
- Only values from 0..7 are used.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-
- \param [in] PriorityGroup Priority grouping field.
- */
-__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
- uint32_t reg_value;
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
-
- reg_value = SCB->AIRCR; /* read old register configuration */
- reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
- reg_value = (reg_value |
- ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
- (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
- SCB->AIRCR = reg_value;
-}
-
-
-/** \brief Get Priority Grouping
-
- The function reads the priority grouping field from the NVIC Interrupt Controller.
-
- \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
- */
-__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
-{
- return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
-}
-
-
-/** \brief Enable External Interrupt
-
- The function enables a device-specific interrupt in the NVIC interrupt controller.
-
- \param [in] IRQn External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-/* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */
- NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */
-}
-
-
-/** \brief Disable External Interrupt
-
- The function disables a device-specific interrupt in the NVIC interrupt controller.
-
- \param [in] IRQn External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
-{
- NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
-}
-
-
-/** \brief Get Pending Interrupt
-
- The function reads the pending register in the NVIC and returns the pending bit
- for the specified interrupt.
-
- \param [in] IRQn Interrupt number.
-
- \return 0 Interrupt status is not pending.
- \return 1 Interrupt status is pending.
- */
-__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
- return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
-}
-
-
-/** \brief Set Pending Interrupt
-
- The function sets the pending bit of an external interrupt.
-
- \param [in] IRQn Interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
- NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
-}
-
-
-/** \brief Clear Pending Interrupt
-
- The function clears the pending bit of an external interrupt.
-
- \param [in] IRQn External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
- NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
-}
-
-
-/** \brief Get Active Interrupt
-
- The function reads the active register in NVIC and returns the active bit.
-
- \param [in] IRQn Interrupt number.
-
- \return 0 Interrupt status is not active.
- \return 1 Interrupt status is active.
- */
-__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
-{
- return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
-}
-
-
-/** \brief Set Interrupt Priority
-
- The function sets the priority of an interrupt.
-
- \note The priority cannot be set for every core interrupt.
-
- \param [in] IRQn Interrupt number.
- \param [in] priority Priority to set.
- */
-__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
- if(IRQn < 0) {
- SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
- else {
- NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
-}
-
-
-/** \brief Get Interrupt Priority
-
- The function reads the priority of an interrupt. The interrupt
- number can be positive to specify an external (device specific)
- interrupt, or negative to specify an internal (core) interrupt.
-
-
- \param [in] IRQn Interrupt number.
- \return Interrupt Priority. Value is aligned automatically to the implemented
- priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
-{
-
- if(IRQn < 0) {
- return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
- else {
- return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
-}
-
-
-/** \brief Encode Priority
-
- The function encodes the priority for an interrupt with the given priority group,
- preemptive priority value, and subpriority value.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
-
- \param [in] PriorityGroup Used priority group.
- \param [in] PreemptPriority Preemptive priority value (starting from 0).
- \param [in] SubPriority Subpriority value (starting from 0).
- \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
- */
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
- uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
- uint32_t PreemptPriorityBits;
- uint32_t SubPriorityBits;
-
- PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
- SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
-
- return (
- ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
- ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
- );
-}
-
-
-/** \brief Decode Priority
-
- The function decodes an interrupt priority value with a given priority group to
- preemptive priority value and subpriority value.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
-
- \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
- \param [in] PriorityGroup Used priority group.
- \param [out] pPreemptPriority Preemptive priority value (starting from 0).
- \param [out] pSubPriority Subpriority value (starting from 0).
- */
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
-{
- uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
- uint32_t PreemptPriorityBits;
- uint32_t SubPriorityBits;
-
- PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
- SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
-
- *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
- *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
-}
-
-
-/** \brief System Reset
-
- The function initiates a system reset request to reset the MCU.
- */
-__STATIC_INLINE void NVIC_SystemReset(void)
-{
- __DSB(); /* Ensure all outstanding memory accesses included
- buffered write are completed before reset */
- SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
- (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
- SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
- __DSB(); /* Ensure completion of memory access */
- while(1); /* wait until reset */
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-
-/* ################################## SysTick function ############################################ */
-/** \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
- \brief Functions that configure the System.
- @{
- */
-
-#if (__Vendor_SysTickConfig == 0)
-
-/** \brief System Tick Configuration
-
- The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
- Counter is in free running mode to generate periodic interrupts.
-
- \param [in] ticks Number of ticks between two interrupts.
-
- \return 0 Function succeeded.
- \return 1 Function failed.
-
- \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
- function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
- must contain a vendor-specific implementation of this function.
-
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
- if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
-
- SysTick->LOAD = ticks - 1; /* set reload register */
- NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
- SysTick->VAL = 0; /* Load the SysTick Counter Value */
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
- SysTick_CTRL_TICKINT_Msk |
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
- return (0); /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-/* ##################################### Debug In/Output function ########################################### */
-/** \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_core_DebugFunctions ITM Functions
- \brief Functions that access the ITM debug interface.
- @{
- */
-
-extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
-#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
-
-
-/** \brief ITM Send Character
-
- The function transmits a character via the ITM channel 0, and
- \li Just returns when no debugger is connected that has booked the output.
- \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
-
- \param [in] ch Character to transmit.
-
- \returns Character to transmit.
- */
-__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
-{
- if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
- (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
- {
- while (ITM->PORT[0].u32 == 0);
- ITM->PORT[0].u8 = (uint8_t) ch;
- }
- return (ch);
-}
-
-
-/** \brief ITM Receive Character
-
- The function inputs a character via the external variable \ref ITM_RxBuffer.
-
- \return Received character.
- \return -1 No character pending.
- */
-__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
- int32_t ch = -1; /* no character available */
-
- if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
- ch = ITM_RxBuffer;
- ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
- }
-
- return (ch);
-}
-
-
-/** \brief ITM Check Character
-
- The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
-
- \return 0 No character available.
- \return 1 Character available.
- */
-__STATIC_INLINE int32_t ITM_CheckChar (void) {
-
- if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
- return (0); /* no character available */
- } else {
- return (1); /* character available */
- }
-}
-
-/*@} end of CMSIS_core_DebugFunctions */
-
-#endif /* __CORE_CM4_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Include/core_cm4_simd.h b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Include/core_cm4_simd.h
deleted file mode 100644
index 83db95b5f112dd3e86cdc24b885eef66eef4a067..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Include/core_cm4_simd.h
+++ /dev/null
@@ -1,673 +0,0 @@
-/**************************************************************************//**
- * @file core_cm4_simd.h
- * @brief CMSIS Cortex-M4 SIMD Header File
- * @version V3.20
- * @date 25. February 2013
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2009 - 2013 ARM LIMITED
-
- All rights reserved.
- Redistribution and use in source and binary forms, with or without
- modification, are permitted provided that the following conditions are met:
- - Redistributions of source code must retain the above copyright
- notice, this list of conditions and the following disclaimer.
- - Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the distribution.
- - Neither the name of ARM nor the names of its contributors may be used
- to endorse or promote products derived from this software without
- specific prior written permission.
- *
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- POSSIBILITY OF SUCH DAMAGE.
- ---------------------------------------------------------------------------*/
-
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#ifndef __CORE_CM4_SIMD_H
-#define __CORE_CM4_SIMD_H
-
-
-/*******************************************************************************
- * Hardware Abstraction Layer
- ******************************************************************************/
-
-
-/* ################### Compiler specific Intrinsics ########################### */
-/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
- Access to dedicated SIMD instructions
- @{
-*/
-
-#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
-/* ARM armcc specific functions */
-
-/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
-#define __SADD8 __sadd8
-#define __QADD8 __qadd8
-#define __SHADD8 __shadd8
-#define __UADD8 __uadd8
-#define __UQADD8 __uqadd8
-#define __UHADD8 __uhadd8
-#define __SSUB8 __ssub8
-#define __QSUB8 __qsub8
-#define __SHSUB8 __shsub8
-#define __USUB8 __usub8
-#define __UQSUB8 __uqsub8
-#define __UHSUB8 __uhsub8
-#define __SADD16 __sadd16
-#define __QADD16 __qadd16
-#define __SHADD16 __shadd16
-#define __UADD16 __uadd16
-#define __UQADD16 __uqadd16
-#define __UHADD16 __uhadd16
-#define __SSUB16 __ssub16
-#define __QSUB16 __qsub16
-#define __SHSUB16 __shsub16
-#define __USUB16 __usub16
-#define __UQSUB16 __uqsub16
-#define __UHSUB16 __uhsub16
-#define __SASX __sasx
-#define __QASX __qasx
-#define __SHASX __shasx
-#define __UASX __uasx
-#define __UQASX __uqasx
-#define __UHASX __uhasx
-#define __SSAX __ssax
-#define __QSAX __qsax
-#define __SHSAX __shsax
-#define __USAX __usax
-#define __UQSAX __uqsax
-#define __UHSAX __uhsax
-#define __USAD8 __usad8
-#define __USADA8 __usada8
-#define __SSAT16 __ssat16
-#define __USAT16 __usat16
-#define __UXTB16 __uxtb16
-#define __UXTAB16 __uxtab16
-#define __SXTB16 __sxtb16
-#define __SXTAB16 __sxtab16
-#define __SMUAD __smuad
-#define __SMUADX __smuadx
-#define __SMLAD __smlad
-#define __SMLADX __smladx
-#define __SMLALD __smlald
-#define __SMLALDX __smlaldx
-#define __SMUSD __smusd
-#define __SMUSDX __smusdx
-#define __SMLSD __smlsd
-#define __SMLSDX __smlsdx
-#define __SMLSLD __smlsld
-#define __SMLSLDX __smlsldx
-#define __SEL __sel
-#define __QADD __qadd
-#define __QSUB __qsub
-
-#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
- ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
-
-#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
- ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
-
-#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
- ((int64_t)(ARG3) << 32) ) >> 32))
-
-/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
-
-
-
-#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
-/* IAR iccarm specific functions */
-
-/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
-#include <cmsis_iar.h>
-
-/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
-
-
-
-#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
-/* TI CCS specific functions */
-
-/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
-#include <cmsis_ccs.h>
-
-/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
-
-
-
-#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
-/* GNU gcc specific functions */
-
-/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
-{
- uint32_t result;
-
- __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
- return(result);
-}
-
-#define __SSAT16(ARG1,ARG2) \
-({ \
- uint32_t __RES, __ARG1 = (ARG1); \
- __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
- __RES; \
- })
-
-#define __USAT16(ARG1,ARG2) \
-({ \
- uint32_t __RES, __ARG1 = (ARG1); \
- __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
- __RES; \
- })
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
-{
- uint32_t result;
-
- __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
-{
- uint32_t result;
-
- __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
-{
- uint32_t result;
-
- __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
-{
- uint32_t result;
-
- __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
- return(result);
-}
-
-#define __SMLALD(ARG1,ARG2,ARG3) \
-({ \
- uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
- __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
- (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
- })
-
-#define __SMLALDX(ARG1,ARG2,ARG3) \
-({ \
- uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
- __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
- (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
- })
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
-{
- uint32_t result;
-
- __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
-{
- uint32_t result;
-
- __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
- return(result);
-}
-
-#define __SMLSLD(ARG1,ARG2,ARG3) \
-({ \
- uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
- __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
- (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
- })
-
-#define __SMLSLDX(ARG1,ARG2,ARG3) \
-({ \
- uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
- __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
- (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
- })
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
-{
- uint32_t result;
-
- __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
- return(result);
-}
-
-#define __PKHBT(ARG1,ARG2,ARG3) \
-({ \
- uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
- __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
- __RES; \
- })
-
-#define __PKHTB(ARG1,ARG2,ARG3) \
-({ \
- uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
- if (ARG3 == 0) \
- __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
- else \
- __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
- __RES; \
- })
-
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
-{
- int32_t result;
-
- __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
- return(result);
-}
-
-/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
-
-
-
-#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
-/* TASKING carm specific functions */
-
-
-/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
-/* not yet supported */
-/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
-
-
-#endif
-
-/*@} end of group CMSIS_SIMD_intrinsics */
-
-
-#endif /* __CORE_CM4_SIMD_H */
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Include/core_cmFunc.h b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Include/core_cmFunc.h
deleted file mode 100644
index 0a18fafc301e003d348edf5cae39481d8e5fe7c3..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Include/core_cmFunc.h
+++ /dev/null
@@ -1,636 +0,0 @@
-/**************************************************************************//**
- * @file core_cmFunc.h
- * @brief CMSIS Cortex-M Core Function Access Header File
- * @version V3.20
- * @date 25. February 2013
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2009 - 2013 ARM LIMITED
-
- All rights reserved.
- Redistribution and use in source and binary forms, with or without
- modification, are permitted provided that the following conditions are met:
- - Redistributions of source code must retain the above copyright
- notice, this list of conditions and the following disclaimer.
- - Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the distribution.
- - Neither the name of ARM nor the names of its contributors may be used
- to endorse or promote products derived from this software without
- specific prior written permission.
- *
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- POSSIBILITY OF SUCH DAMAGE.
- ---------------------------------------------------------------------------*/
-
-
-#ifndef __CORE_CMFUNC_H
-#define __CORE_CMFUNC_H
-
-
-/* ########################### Core Function Access ########################### */
-/** \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
- @{
- */
-
-#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
-/* ARM armcc specific functions */
-
-#if (__ARMCC_VERSION < 400677)
- #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
-#endif
-
-/* intrinsic void __enable_irq(); */
-/* intrinsic void __disable_irq(); */
-
-/** \brief Get Control Register
-
- This function returns the content of the Control Register.
-
- \return Control Register value
- */
-__STATIC_INLINE uint32_t __get_CONTROL(void)
-{
- register uint32_t __regControl __ASM("control");
- return(__regControl);
-}
-
-
-/** \brief Set Control Register
-
- This function writes the given value to the Control Register.
-
- \param [in] control Control Register value to set
- */
-__STATIC_INLINE void __set_CONTROL(uint32_t control)
-{
- register uint32_t __regControl __ASM("control");
- __regControl = control;
-}
-
-
-/** \brief Get IPSR Register
-
- This function returns the content of the IPSR Register.
-
- \return IPSR Register value
- */
-__STATIC_INLINE uint32_t __get_IPSR(void)
-{
- register uint32_t __regIPSR __ASM("ipsr");
- return(__regIPSR);
-}
-
-
-/** \brief Get APSR Register
-
- This function returns the content of the APSR Register.
-
- \return APSR Register value
- */
-__STATIC_INLINE uint32_t __get_APSR(void)
-{
- register uint32_t __regAPSR __ASM("apsr");
- return(__regAPSR);
-}
-
-
-/** \brief Get xPSR Register
-
- This function returns the content of the xPSR Register.
-
- \return xPSR Register value
- */
-__STATIC_INLINE uint32_t __get_xPSR(void)
-{
- register uint32_t __regXPSR __ASM("xpsr");
- return(__regXPSR);
-}
-
-
-/** \brief Get Process Stack Pointer
-
- This function returns the current value of the Process Stack Pointer (PSP).
-
- \return PSP Register value
- */
-__STATIC_INLINE uint32_t __get_PSP(void)
-{
- register uint32_t __regProcessStackPointer __ASM("psp");
- return(__regProcessStackPointer);
-}
-
-
-/** \brief Set Process Stack Pointer
-
- This function assigns the given value to the Process Stack Pointer (PSP).
-
- \param [in] topOfProcStack Process Stack Pointer value to set
- */
-__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
-{
- register uint32_t __regProcessStackPointer __ASM("psp");
- __regProcessStackPointer = topOfProcStack;
-}
-
-
-/** \brief Get Main Stack Pointer
-
- This function returns the current value of the Main Stack Pointer (MSP).
-
- \return MSP Register value
- */
-__STATIC_INLINE uint32_t __get_MSP(void)
-{
- register uint32_t __regMainStackPointer __ASM("msp");
- return(__regMainStackPointer);
-}
-
-
-/** \brief Set Main Stack Pointer
-
- This function assigns the given value to the Main Stack Pointer (MSP).
-
- \param [in] topOfMainStack Main Stack Pointer value to set
- */
-__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
-{
- register uint32_t __regMainStackPointer __ASM("msp");
- __regMainStackPointer = topOfMainStack;
-}
-
-
-/** \brief Get Priority Mask
-
- This function returns the current state of the priority mask bit from the Priority Mask Register.
-
- \return Priority Mask value
- */
-__STATIC_INLINE uint32_t __get_PRIMASK(void)
-{
- register uint32_t __regPriMask __ASM("primask");
- return(__regPriMask);
-}
-
-
-/** \brief Set Priority Mask
-
- This function assigns the given value to the Priority Mask Register.
-
- \param [in] priMask Priority Mask
- */
-__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
-{
- register uint32_t __regPriMask __ASM("primask");
- __regPriMask = (priMask);
-}
-
-
-#if (__CORTEX_M >= 0x03)
-
-/** \brief Enable FIQ
-
- This function enables FIQ interrupts by clearing the F-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-#define __enable_fault_irq __enable_fiq
-
-
-/** \brief Disable FIQ
-
- This function disables FIQ interrupts by setting the F-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-#define __disable_fault_irq __disable_fiq
-
-
-/** \brief Get Base Priority
-
- This function returns the current value of the Base Priority register.
-
- \return Base Priority register value
- */
-__STATIC_INLINE uint32_t __get_BASEPRI(void)
-{
- register uint32_t __regBasePri __ASM("basepri");
- return(__regBasePri);
-}
-
-
-/** \brief Set Base Priority
-
- This function assigns the given value to the Base Priority register.
-
- \param [in] basePri Base Priority value to set
- */
-__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
-{
- register uint32_t __regBasePri __ASM("basepri");
- __regBasePri = (basePri & 0xff);
-}
-
-
-/** \brief Get Fault Mask
-
- This function returns the current value of the Fault Mask register.
-
- \return Fault Mask register value
- */
-__STATIC_INLINE uint32_t __get_FAULTMASK(void)
-{
- register uint32_t __regFaultMask __ASM("faultmask");
- return(__regFaultMask);
-}
-
-
-/** \brief Set Fault Mask
-
- This function assigns the given value to the Fault Mask register.
-
- \param [in] faultMask Fault Mask value to set
- */
-__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
-{
- register uint32_t __regFaultMask __ASM("faultmask");
- __regFaultMask = (faultMask & (uint32_t)1);
-}
-
-#endif /* (__CORTEX_M >= 0x03) */
-
-
-#if (__CORTEX_M == 0x04)
-
-/** \brief Get FPSCR
-
- This function returns the current value of the Floating Point Status/Control register.
-
- \return Floating Point Status/Control register value
- */
-__STATIC_INLINE uint32_t __get_FPSCR(void)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
- register uint32_t __regfpscr __ASM("fpscr");
- return(__regfpscr);
-#else
- return(0);
-#endif
-}
-
-
-/** \brief Set FPSCR
-
- This function assigns the given value to the Floating Point Status/Control register.
-
- \param [in] fpscr Floating Point Status/Control value to set
- */
-__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
- register uint32_t __regfpscr __ASM("fpscr");
- __regfpscr = (fpscr);
-#endif
-}
-
-#endif /* (__CORTEX_M == 0x04) */
-
-
-#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
-/* IAR iccarm specific functions */
-
-#include <cmsis_iar.h>
-
-
-#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
-/* TI CCS specific functions */
-
-#include <cmsis_ccs.h>
-
-
-#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
-/* GNU gcc specific functions */
-
-/** \brief Enable IRQ Interrupts
-
- This function enables IRQ interrupts by clearing the I-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
-{
- __ASM volatile ("cpsie i" : : : "memory");
-}
-
-
-/** \brief Disable IRQ Interrupts
-
- This function disables IRQ interrupts by setting the I-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
-{
- __ASM volatile ("cpsid i" : : : "memory");
-}
-
-
-/** \brief Get Control Register
-
- This function returns the content of the Control Register.
-
- \return Control Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, control" : "=r" (result) );
- return(result);
-}
-
-
-/** \brief Set Control Register
-
- This function writes the given value to the Control Register.
-
- \param [in] control Control Register value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
-{
- __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
-}
-
-
-/** \brief Get IPSR Register
-
- This function returns the content of the IPSR Register.
-
- \return IPSR Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
- return(result);
-}
-
-
-/** \brief Get APSR Register
-
- This function returns the content of the APSR Register.
-
- \return APSR Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, apsr" : "=r" (result) );
- return(result);
-}
-
-
-/** \brief Get xPSR Register
-
- This function returns the content of the xPSR Register.
-
- \return xPSR Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
- return(result);
-}
-
-
-/** \brief Get Process Stack Pointer
-
- This function returns the current value of the Process Stack Pointer (PSP).
-
- \return PSP Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
-{
- register uint32_t result;
-
- __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
- return(result);
-}
-
-
-/** \brief Set Process Stack Pointer
-
- This function assigns the given value to the Process Stack Pointer (PSP).
-
- \param [in] topOfProcStack Process Stack Pointer value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
-{
- __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
-}
-
-
-/** \brief Get Main Stack Pointer
-
- This function returns the current value of the Main Stack Pointer (MSP).
-
- \return MSP Register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
-{
- register uint32_t result;
-
- __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
- return(result);
-}
-
-
-/** \brief Set Main Stack Pointer
-
- This function assigns the given value to the Main Stack Pointer (MSP).
-
- \param [in] topOfMainStack Main Stack Pointer value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
-{
- __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
-}
-
-
-/** \brief Get Priority Mask
-
- This function returns the current state of the priority mask bit from the Priority Mask Register.
-
- \return Priority Mask value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, primask" : "=r" (result) );
- return(result);
-}
-
-
-/** \brief Set Priority Mask
-
- This function assigns the given value to the Priority Mask Register.
-
- \param [in] priMask Priority Mask
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
-{
- __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
-}
-
-
-#if (__CORTEX_M >= 0x03)
-
-/** \brief Enable FIQ
-
- This function enables FIQ interrupts by clearing the F-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
-{
- __ASM volatile ("cpsie f" : : : "memory");
-}
-
-
-/** \brief Disable FIQ
-
- This function disables FIQ interrupts by setting the F-bit in the CPSR.
- Can only be executed in Privileged modes.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
-{
- __ASM volatile ("cpsid f" : : : "memory");
-}
-
-
-/** \brief Get Base Priority
-
- This function returns the current value of the Base Priority register.
-
- \return Base Priority register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
- return(result);
-}
-
-
-/** \brief Set Base Priority
-
- This function assigns the given value to the Base Priority register.
-
- \param [in] basePri Base Priority value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
-{
- __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
-}
-
-
-/** \brief Get Fault Mask
-
- This function returns the current value of the Fault Mask register.
-
- \return Fault Mask register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
-{
- uint32_t result;
-
- __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
- return(result);
-}
-
-
-/** \brief Set Fault Mask
-
- This function assigns the given value to the Fault Mask register.
-
- \param [in] faultMask Fault Mask value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
-{
- __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
-}
-
-#endif /* (__CORTEX_M >= 0x03) */
-
-
-#if (__CORTEX_M == 0x04)
-
-/** \brief Get FPSCR
-
- This function returns the current value of the Floating Point Status/Control register.
-
- \return Floating Point Status/Control register value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
- uint32_t result;
-
- /* Empty asm statement works as a scheduling barrier */
- __ASM volatile ("");
- __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
- __ASM volatile ("");
- return(result);
-#else
- return(0);
-#endif
-}
-
-
-/** \brief Set FPSCR
-
- This function assigns the given value to the Floating Point Status/Control register.
-
- \param [in] fpscr Floating Point Status/Control value to set
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
-{
-#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
- /* Empty asm statement works as a scheduling barrier */
- __ASM volatile ("");
- __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
- __ASM volatile ("");
-#endif
-}
-
-#endif /* (__CORTEX_M == 0x04) */
-
-
-#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
-/* TASKING carm specific functions */
-
-/*
- * The CMSIS functions have been implemented as intrinsics in the compiler.
- * Please use "carm -?i" to get an up to date list of all instrinsics,
- * Including the CMSIS ones.
- */
-
-#endif
-
-/*@} end of CMSIS_Core_RegAccFunctions */
-
-
-#endif /* __CORE_CMFUNC_H */
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Include/core_cmInstr.h b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Include/core_cmInstr.h
deleted file mode 100644
index d213f0eed7ca9335e883a5b55b6de14ba9507f1e..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Include/core_cmInstr.h
+++ /dev/null
@@ -1,688 +0,0 @@
-/**************************************************************************//**
- * @file core_cmInstr.h
- * @brief CMSIS Cortex-M Core Instruction Access Header File
- * @version V3.20
- * @date 05. March 2013
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2009 - 2013 ARM LIMITED
-
- All rights reserved.
- Redistribution and use in source and binary forms, with or without
- modification, are permitted provided that the following conditions are met:
- - Redistributions of source code must retain the above copyright
- notice, this list of conditions and the following disclaimer.
- - Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the distribution.
- - Neither the name of ARM nor the names of its contributors may be used
- to endorse or promote products derived from this software without
- specific prior written permission.
- *
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- POSSIBILITY OF SUCH DAMAGE.
- ---------------------------------------------------------------------------*/
-
-
-#ifndef __CORE_CMINSTR_H
-#define __CORE_CMINSTR_H
-
-
-/* ########################## Core Instruction Access ######################### */
-/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
- Access to dedicated instructions
- @{
-*/
-
-#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
-/* ARM armcc specific functions */
-
-#if (__ARMCC_VERSION < 400677)
- #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
-#endif
-
-
-/** \brief No Operation
-
- No Operation does nothing. This instruction can be used for code alignment purposes.
- */
-#define __NOP __nop
-
-
-/** \brief Wait For Interrupt
-
- Wait For Interrupt is a hint instruction that suspends execution
- until one of a number of events occurs.
- */
-#define __WFI __wfi
-
-
-/** \brief Wait For Event
-
- Wait For Event is a hint instruction that permits the processor to enter
- a low-power state until one of a number of events occurs.
- */
-#define __WFE __wfe
-
-
-/** \brief Send Event
-
- Send Event is a hint instruction. It causes an event to be signaled to the CPU.
- */
-#define __SEV __sev
-
-
-/** \brief Instruction Synchronization Barrier
-
- Instruction Synchronization Barrier flushes the pipeline in the processor,
- so that all instructions following the ISB are fetched from cache or
- memory, after the instruction has been completed.
- */
-#define __ISB() __isb(0xF)
-
-
-/** \brief Data Synchronization Barrier
-
- This function acts as a special kind of Data Memory Barrier.
- It completes when all explicit memory accesses before this instruction complete.
- */
-#define __DSB() __dsb(0xF)
-
-
-/** \brief Data Memory Barrier
-
- This function ensures the apparent order of the explicit memory operations before
- and after the instruction, without ensuring their completion.
- */
-#define __DMB() __dmb(0xF)
-
-
-/** \brief Reverse byte order (32 bit)
-
- This function reverses the byte order in integer value.
-
- \param [in] value Value to reverse
- \return Reversed value
- */
-#define __REV __rev
-
-
-/** \brief Reverse byte order (16 bit)
-
- This function reverses the byte order in two unsigned short values.
-
- \param [in] value Value to reverse
- \return Reversed value
- */
-#ifndef __NO_EMBEDDED_ASM
-__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
-{
- rev16 r0, r0
- bx lr
-}
-#endif
-
-/** \brief Reverse byte order in signed short value
-
- This function reverses the byte order in a signed short value with sign extension to integer.
-
- \param [in] value Value to reverse
- \return Reversed value
- */
-#ifndef __NO_EMBEDDED_ASM
-__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
-{
- revsh r0, r0
- bx lr
-}
-#endif
-
-
-/** \brief Rotate Right in unsigned value (32 bit)
-
- This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
-
- \param [in] value Value to rotate
- \param [in] value Number of Bits to rotate
- \return Rotated value
- */
-#define __ROR __ror
-
-
-/** \brief Breakpoint
-
- This function causes the processor to enter Debug state.
- Debug tools can use this to investigate system state when the instruction at a particular address is reached.
-
- \param [in] value is ignored by the processor.
- If required, a debugger can use it to store additional information about the breakpoint.
- */
-#define __BKPT(value) __breakpoint(value)
-
-
-#if (__CORTEX_M >= 0x03)
-
-/** \brief Reverse bit order of value
-
- This function reverses the bit order of the given value.
-
- \param [in] value Value to reverse
- \return Reversed value
- */
-#define __RBIT __rbit
-
-
-/** \brief LDR Exclusive (8 bit)
-
- This function performs a exclusive LDR command for 8 bit value.
-
- \param [in] ptr Pointer to data
- \return value of type uint8_t at (*ptr)
- */
-#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
-
-
-/** \brief LDR Exclusive (16 bit)
-
- This function performs a exclusive LDR command for 16 bit values.
-
- \param [in] ptr Pointer to data
- \return value of type uint16_t at (*ptr)
- */
-#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
-
-
-/** \brief LDR Exclusive (32 bit)
-
- This function performs a exclusive LDR command for 32 bit values.
-
- \param [in] ptr Pointer to data
- \return value of type uint32_t at (*ptr)
- */
-#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
-
-
-/** \brief STR Exclusive (8 bit)
-
- This function performs a exclusive STR command for 8 bit values.
-
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
-#define __STREXB(value, ptr) __strex(value, ptr)
-
-
-/** \brief STR Exclusive (16 bit)
-
- This function performs a exclusive STR command for 16 bit values.
-
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
-#define __STREXH(value, ptr) __strex(value, ptr)
-
-
-/** \brief STR Exclusive (32 bit)
-
- This function performs a exclusive STR command for 32 bit values.
-
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
-#define __STREXW(value, ptr) __strex(value, ptr)
-
-
-/** \brief Remove the exclusive lock
-
- This function removes the exclusive lock which is created by LDREX.
-
- */
-#define __CLREX __clrex
-
-
-/** \brief Signed Saturate
-
- This function saturates a signed value.
-
- \param [in] value Value to be saturated
- \param [in] sat Bit position to saturate to (1..32)
- \return Saturated value
- */
-#define __SSAT __ssat
-
-
-/** \brief Unsigned Saturate
-
- This function saturates an unsigned value.
-
- \param [in] value Value to be saturated
- \param [in] sat Bit position to saturate to (0..31)
- \return Saturated value
- */
-#define __USAT __usat
-
-
-/** \brief Count leading zeros
-
- This function counts the number of leading zeros of a data value.
-
- \param [in] value Value to count the leading zeros
- \return number of leading zeros in value
- */
-#define __CLZ __clz
-
-#endif /* (__CORTEX_M >= 0x03) */
-
-
-
-#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
-/* IAR iccarm specific functions */
-
-#include <cmsis_iar.h>
-
-
-#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
-/* TI CCS specific functions */
-
-#include <cmsis_ccs.h>
-
-
-#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
-/* GNU gcc specific functions */
-
-/* Define macros for porting to both thumb1 and thumb2.
- * For thumb1, use low register (r0-r7), specified by constrant "l"
- * Otherwise, use general registers, specified by constrant "r" */
-#if defined (__thumb__) && !defined (__thumb2__)
-#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
-#define __CMSIS_GCC_USE_REG(r) "l" (r)
-#else
-#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
-#define __CMSIS_GCC_USE_REG(r) "r" (r)
-#endif
-
-/** \brief No Operation
-
- No Operation does nothing. This instruction can be used for code alignment purposes.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
-{
- __ASM volatile ("nop");
-}
-
-
-/** \brief Wait For Interrupt
-
- Wait For Interrupt is a hint instruction that suspends execution
- until one of a number of events occurs.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
-{
- __ASM volatile ("wfi");
-}
-
-
-/** \brief Wait For Event
-
- Wait For Event is a hint instruction that permits the processor to enter
- a low-power state until one of a number of events occurs.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
-{
- __ASM volatile ("wfe");
-}
-
-
-/** \brief Send Event
-
- Send Event is a hint instruction. It causes an event to be signaled to the CPU.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
-{
- __ASM volatile ("sev");
-}
-
-
-/** \brief Instruction Synchronization Barrier
-
- Instruction Synchronization Barrier flushes the pipeline in the processor,
- so that all instructions following the ISB are fetched from cache or
- memory, after the instruction has been completed.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
-{
- __ASM volatile ("isb");
-}
-
-
-/** \brief Data Synchronization Barrier
-
- This function acts as a special kind of Data Memory Barrier.
- It completes when all explicit memory accesses before this instruction complete.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
-{
- __ASM volatile ("dsb");
-}
-
-
-/** \brief Data Memory Barrier
-
- This function ensures the apparent order of the explicit memory operations before
- and after the instruction, without ensuring their completion.
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
-{
- __ASM volatile ("dmb");
-}
-
-
-/** \brief Reverse byte order (32 bit)
-
- This function reverses the byte order in integer value.
-
- \param [in] value Value to reverse
- \return Reversed value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
-{
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
- return __builtin_bswap32(value);
-#else
- uint32_t result;
-
- __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
- return(result);
-#endif
-}
-
-
-/** \brief Reverse byte order (16 bit)
-
- This function reverses the byte order in two unsigned short values.
-
- \param [in] value Value to reverse
- \return Reversed value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
-{
- uint32_t result;
-
- __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
- return(result);
-}
-
-
-/** \brief Reverse byte order in signed short value
-
- This function reverses the byte order in a signed short value with sign extension to integer.
-
- \param [in] value Value to reverse
- \return Reversed value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
-{
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
- return (short)__builtin_bswap16(value);
-#else
- uint32_t result;
-
- __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
- return(result);
-#endif
-}
-
-
-/** \brief Rotate Right in unsigned value (32 bit)
-
- This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
-
- \param [in] value Value to rotate
- \param [in] value Number of Bits to rotate
- \return Rotated value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
-{
- return (op1 >> op2) | (op1 << (32 - op2));
-}
-
-
-/** \brief Breakpoint
-
- This function causes the processor to enter Debug state.
- Debug tools can use this to investigate system state when the instruction at a particular address is reached.
-
- \param [in] value is ignored by the processor.
- If required, a debugger can use it to store additional information about the breakpoint.
- */
-#define __BKPT(value) __ASM volatile ("bkpt "#value)
-
-
-#if (__CORTEX_M >= 0x03)
-
-/** \brief Reverse bit order of value
-
- This function reverses the bit order of the given value.
-
- \param [in] value Value to reverse
- \return Reversed value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
-{
- uint32_t result;
-
- __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
- return(result);
-}
-
-
-/** \brief LDR Exclusive (8 bit)
-
- This function performs a exclusive LDR command for 8 bit value.
-
- \param [in] ptr Pointer to data
- \return value of type uint8_t at (*ptr)
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
-{
- uint32_t result;
-
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
- __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
-#else
- /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
- accepted by assembler. So has to use following less efficient pattern.
- */
- __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
-#endif
- return(result);
-}
-
-
-/** \brief LDR Exclusive (16 bit)
-
- This function performs a exclusive LDR command for 16 bit values.
-
- \param [in] ptr Pointer to data
- \return value of type uint16_t at (*ptr)
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
-{
- uint32_t result;
-
-#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
- __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
-#else
- /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
- accepted by assembler. So has to use following less efficient pattern.
- */
- __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
-#endif
- return(result);
-}
-
-
-/** \brief LDR Exclusive (32 bit)
-
- This function performs a exclusive LDR command for 32 bit values.
-
- \param [in] ptr Pointer to data
- \return value of type uint32_t at (*ptr)
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
-{
- uint32_t result;
-
- __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
- return(result);
-}
-
-
-/** \brief STR Exclusive (8 bit)
-
- This function performs a exclusive STR command for 8 bit values.
-
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
-{
- uint32_t result;
-
- __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
- return(result);
-}
-
-
-/** \brief STR Exclusive (16 bit)
-
- This function performs a exclusive STR command for 16 bit values.
-
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
-{
- uint32_t result;
-
- __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
- return(result);
-}
-
-
-/** \brief STR Exclusive (32 bit)
-
- This function performs a exclusive STR command for 32 bit values.
-
- \param [in] value Value to store
- \param [in] ptr Pointer to location
- \return 0 Function succeeded
- \return 1 Function failed
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
-{
- uint32_t result;
-
- __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
- return(result);
-}
-
-
-/** \brief Remove the exclusive lock
-
- This function removes the exclusive lock which is created by LDREX.
-
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
-{
- __ASM volatile ("clrex" ::: "memory");
-}
-
-
-/** \brief Signed Saturate
-
- This function saturates a signed value.
-
- \param [in] value Value to be saturated
- \param [in] sat Bit position to saturate to (1..32)
- \return Saturated value
- */
-#define __SSAT(ARG1,ARG2) \
-({ \
- uint32_t __RES, __ARG1 = (ARG1); \
- __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
- __RES; \
- })
-
-
-/** \brief Unsigned Saturate
-
- This function saturates an unsigned value.
-
- \param [in] value Value to be saturated
- \param [in] sat Bit position to saturate to (0..31)
- \return Saturated value
- */
-#define __USAT(ARG1,ARG2) \
-({ \
- uint32_t __RES, __ARG1 = (ARG1); \
- __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
- __RES; \
- })
-
-
-/** \brief Count leading zeros
-
- This function counts the number of leading zeros of a data value.
-
- \param [in] value Value to count the leading zeros
- \return number of leading zeros in value
- */
-__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
-{
- uint32_t result;
-
- __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
- return(result);
-}
-
-#endif /* (__CORTEX_M >= 0x03) */
-
-
-
-
-#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
-/* TASKING carm specific functions */
-
-/*
- * The CMSIS functions have been implemented as intrinsics in the compiler.
- * Please use "carm -?i" to get an up to date list of all intrinsics,
- * Including the CMSIS ones.
- */
-
-#endif
-
-/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
-
-#endif /* __CORE_CMINSTR_H */
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Include/core_sc000.h b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Include/core_sc000.h
deleted file mode 100644
index 1a2a0f2e300d83548c20c3998765a7e2460925d9..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Include/core_sc000.h
+++ /dev/null
@@ -1,813 +0,0 @@
-/**************************************************************************//**
- * @file core_sc000.h
- * @brief CMSIS SC000 Core Peripheral Access Layer Header File
- * @version V3.20
- * @date 25. February 2013
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2009 - 2013 ARM LIMITED
-
- All rights reserved.
- Redistribution and use in source and binary forms, with or without
- modification, are permitted provided that the following conditions are met:
- - Redistributions of source code must retain the above copyright
- notice, this list of conditions and the following disclaimer.
- - Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the distribution.
- - Neither the name of ARM nor the names of its contributors may be used
- to endorse or promote products derived from this software without
- specific prior written permission.
- *
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- POSSIBILITY OF SUCH DAMAGE.
- ---------------------------------------------------------------------------*/
-
-
-#if defined ( __ICCARM__ )
- #pragma system_include /* treat file as system include file for MISRA check */
-#endif
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#ifndef __CORE_SC000_H_GENERIC
-#define __CORE_SC000_H_GENERIC
-
-/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
- CMSIS violates the following MISRA-C:2004 rules:
-
- \li Required Rule 8.5, object/function definition in header file.<br>
- Function definitions in header files are used to allow 'inlining'.
-
- \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
- Unions are used for effective representation of core registers.
-
- \li Advisory Rule 19.7, Function-like macro defined.<br>
- Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- * CMSIS definitions
- ******************************************************************************/
-/** \ingroup SC000
- @{
- */
-
-/* CMSIS SC000 definitions */
-#define __SC000_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
-#define __SC000_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
-#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16) | \
- __SC000_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
-
-#define __CORTEX_SC (0) /*!< Cortex secure core */
-
-
-#if defined ( __CC_ARM )
- #define __ASM __asm /*!< asm keyword for ARM Compiler */
- #define __INLINE __inline /*!< inline keyword for ARM Compiler */
- #define __STATIC_INLINE static __inline
-
-#elif defined ( __ICCARM__ )
- #define __ASM __asm /*!< asm keyword for IAR Compiler */
- #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
- #define __STATIC_INLINE static inline
-
-#elif defined ( __GNUC__ )
- #define __ASM __asm /*!< asm keyword for GNU Compiler */
- #define __INLINE inline /*!< inline keyword for GNU Compiler */
- #define __STATIC_INLINE static inline
-
-#elif defined ( __TASKING__ )
- #define __ASM __asm /*!< asm keyword for TASKING Compiler */
- #define __INLINE inline /*!< inline keyword for TASKING Compiler */
- #define __STATIC_INLINE static inline
-
-#endif
-
-/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
-*/
-#define __FPU_USED 0
-
-#if defined ( __CC_ARM )
- #if defined __TARGET_FPU_VFP
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __ICCARM__ )
- #if defined __ARMVFP__
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __GNUC__ )
- #if defined (__VFP_FP__) && !defined(__SOFTFP__)
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __TASKING__ )
- #if defined __FPU_VFP__
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-#endif
-
-#include <stdint.h> /* standard types definitions */
-#include <core_cmInstr.h> /* Core Instruction Access */
-#include <core_cmFunc.h> /* Core Function Access */
-
-#endif /* __CORE_SC000_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_SC000_H_DEPENDANT
-#define __CORE_SC000_H_DEPENDANT
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
- #ifndef __SC000_REV
- #define __SC000_REV 0x0000
- #warning "__SC000_REV not defined in device header file; using default!"
- #endif
-
- #ifndef __MPU_PRESENT
- #define __MPU_PRESENT 0
- #warning "__MPU_PRESENT not defined in device header file; using default!"
- #endif
-
- #ifndef __NVIC_PRIO_BITS
- #define __NVIC_PRIO_BITS 2
- #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
- #endif
-
- #ifndef __Vendor_SysTickConfig
- #define __Vendor_SysTickConfig 0
- #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
- #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
- \defgroup CMSIS_glob_defs CMSIS Global Defines
-
- <strong>IO Type Qualifiers</strong> are used
- \li to specify the access to peripheral variables.
- \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
- #define __I volatile /*!< Defines 'read only' permissions */
-#else
- #define __I volatile const /*!< Defines 'read only' permissions */
-#endif
-#define __O volatile /*!< Defines 'write only' permissions */
-#define __IO volatile /*!< Defines 'read / write' permissions */
-
-/*@} end of group SC000 */
-
-
-
-/*******************************************************************************
- * Register Abstraction
- Core Register contain:
- - Core Register
- - Core NVIC Register
- - Core SCB Register
- - Core SysTick Register
- - Core MPU Register
- ******************************************************************************/
-/** \defgroup CMSIS_core_register Defines and Type Definitions
- \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_CORE Status and Control Registers
- \brief Core Register type definitions.
- @{
- */
-
-/** \brief Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
- struct
- {
-#if (__CORTEX_M != 0x04)
- uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
-#else
- uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
- uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
-#endif
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} APSR_Type;
-
-
-/** \brief Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
- uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} IPSR_Type;
-
-
-/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
-#if (__CORTEX_M != 0x04)
- uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
-#else
- uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
- uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
-#endif
- uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
- uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} xPSR_Type;
-
-
-/** \brief Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
- struct
- {
- uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
- uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
- uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
- uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} CONTROL_Type;
-
-/*@} end of group CMSIS_CORE */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
- \brief Type definitions for the NVIC Registers
- @{
- */
-
-/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
- __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
- uint32_t RESERVED0[31];
- __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
- uint32_t RSERVED1[31];
- __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
- uint32_t RESERVED2[31];
- __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
- uint32_t RESERVED3[31];
- uint32_t RESERVED4[64];
- __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
-} NVIC_Type;
-
-/*@} end of group CMSIS_NVIC */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_SCB System Control Block (SCB)
- \brief Type definitions for the System Control Block Registers
- @{
- */
-
-/** \brief Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
- __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
- __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
- __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
- __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
- __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
- __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
- uint32_t RESERVED0[1];
- __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
- __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
- uint32_t RESERVED1[154];
- __IO uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-/* SCB Security Features Register Definitions */
-#define SCB_SFCR_UNIBRTIMING_Pos 0 /*!< SCB SFCR: UNIBRTIMING Position */
-#define SCB_SFCR_UNIBRTIMING_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SFCR: UNIBRTIMING Mask */
-
-#define SCB_SFCR_SECKEY_Pos 16 /*!< SCB SFCR: SECKEY Position */
-#define SCB_SFCR_SECKEY_Msk (0xFFFFUL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SFCR: SECKEY Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
- \brief Type definitions for the System Control and ID Register not in the SCB
- @{
- */
-
-/** \brief Structure type to access the System Control and ID Register not in the SCB.
- */
-typedef struct
-{
- uint32_t RESERVED0[2];
- __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
-} SCnSCB_Type;
-
-/* Auxiliary Control Register Definitions */
-#define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
-#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */
-
-/*@} end of group CMSIS_SCnotSCB */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_SysTick System Tick Timer (SysTick)
- \brief Type definitions for the System Timer Registers.
- @{
- */
-
-/** \brief Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
- __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
- __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
- __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
- __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-#if (__MPU_PRESENT == 1)
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_MPU Memory Protection Unit (MPU)
- \brief Type definitions for the Memory Protection Unit (MPU)
- @{
- */
-
-/** \brief Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct
-{
- __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
- __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
- __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
- __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
- __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
-} MPU_Type;
-
-/* MPU Type Register */
-#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register */
-#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register */
-#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register */
-#define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
-
-#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
-
-/* MPU Region Attribute and Size Register */
-#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
-#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
-
-#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
-#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
-
-#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
-#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
-
-#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
-#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
-
-#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
-#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
-
-#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
-#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
-
-#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
-#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
-
-#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
-
-#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
-
-#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
- \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR)
- are only accessible over DAP and not via processor. Therefore
- they are not covered by the Cortex-M0 header file.
- @{
- */
-/*@} end of group CMSIS_CoreDebug */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_core_base Core Definitions
- \brief Definitions for base addresses, unions, and structures.
- @{
- */
-
-/* Memory mapping of SC000 Hardware */
-#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
-#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
-#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
-#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
-
-#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
-#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
-#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
-#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
-
-#if (__MPU_PRESENT == 1)
- #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
- #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
-#endif
-
-/*@} */
-
-
-
-/*******************************************************************************
- * Hardware Abstraction Layer
- Core Function Interface contains:
- - Core NVIC Functions
- - Core SysTick Functions
- - Core Register Access Functions
- ******************************************************************************/
-/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ########################## NVIC functions #################################### */
-/** \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_NVICFunctions NVIC Functions
- \brief Functions that manage interrupts and exceptions via the NVIC.
- @{
- */
-
-/* Interrupt Priorities are WORD accessible only under ARMv6M */
-/* The following MACROS handle generation of the register offset and byte masks */
-#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
-#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
-#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
-
-
-/** \brief Enable External Interrupt
-
- The function enables a device-specific interrupt in the NVIC interrupt controller.
-
- \param [in] IRQn External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
-{
- NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
-}
-
-
-/** \brief Disable External Interrupt
-
- The function disables a device-specific interrupt in the NVIC interrupt controller.
-
- \param [in] IRQn External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
-{
- NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
-}
-
-
-/** \brief Get Pending Interrupt
-
- The function reads the pending register in the NVIC and returns the pending bit
- for the specified interrupt.
-
- \param [in] IRQn Interrupt number.
-
- \return 0 Interrupt status is not pending.
- \return 1 Interrupt status is pending.
- */
-__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
- return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
-}
-
-
-/** \brief Set Pending Interrupt
-
- The function sets the pending bit of an external interrupt.
-
- \param [in] IRQn Interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
- NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
-}
-
-
-/** \brief Clear Pending Interrupt
-
- The function clears the pending bit of an external interrupt.
-
- \param [in] IRQn External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
- NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
-}
-
-
-/** \brief Set Interrupt Priority
-
- The function sets the priority of an interrupt.
-
- \note The priority cannot be set for every core interrupt.
-
- \param [in] IRQn Interrupt number.
- \param [in] priority Priority to set.
- */
-__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
- if(IRQn < 0) {
- SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
- (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
- else {
- NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
- (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
-}
-
-
-/** \brief Get Interrupt Priority
-
- The function reads the priority of an interrupt. The interrupt
- number can be positive to specify an external (device specific)
- interrupt, or negative to specify an internal (core) interrupt.
-
-
- \param [in] IRQn Interrupt number.
- \return Interrupt Priority. Value is aligned automatically to the implemented
- priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
-{
-
- if(IRQn < 0) {
- return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
- else {
- return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
-}
-
-
-/** \brief System Reset
-
- The function initiates a system reset request to reset the MCU.
- */
-__STATIC_INLINE void NVIC_SystemReset(void)
-{
- __DSB(); /* Ensure all outstanding memory accesses included
- buffered write are completed before reset */
- SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
- SCB_AIRCR_SYSRESETREQ_Msk);
- __DSB(); /* Ensure completion of memory access */
- while(1); /* wait until reset */
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-
-/* ################################## SysTick function ############################################ */
-/** \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
- \brief Functions that configure the System.
- @{
- */
-
-#if (__Vendor_SysTickConfig == 0)
-
-/** \brief System Tick Configuration
-
- The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
- Counter is in free running mode to generate periodic interrupts.
-
- \param [in] ticks Number of ticks between two interrupts.
-
- \return 0 Function succeeded.
- \return 1 Function failed.
-
- \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
- function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
- must contain a vendor-specific implementation of this function.
-
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
- if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
-
- SysTick->LOAD = ticks - 1; /* set reload register */
- NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
- SysTick->VAL = 0; /* Load the SysTick Counter Value */
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
- SysTick_CTRL_TICKINT_Msk |
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
- return (0); /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-
-#endif /* __CORE_SC000_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Include/core_sc300.h b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Include/core_sc300.h
deleted file mode 100644
index cc34d6fc0eee62d3b7f71e7a014417876c4fc277..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/CMSIS/Include/core_sc300.h
+++ /dev/null
@@ -1,1598 +0,0 @@
-/**************************************************************************//**
- * @file core_sc300.h
- * @brief CMSIS SC300 Core Peripheral Access Layer Header File
- * @version V3.20
- * @date 25. February 2013
- *
- * @note
- *
- ******************************************************************************/
-/* Copyright (c) 2009 - 2013 ARM LIMITED
-
- All rights reserved.
- Redistribution and use in source and binary forms, with or without
- modification, are permitted provided that the following conditions are met:
- - Redistributions of source code must retain the above copyright
- notice, this list of conditions and the following disclaimer.
- - Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the distribution.
- - Neither the name of ARM nor the names of its contributors may be used
- to endorse or promote products derived from this software without
- specific prior written permission.
- *
- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
- ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- POSSIBILITY OF SUCH DAMAGE.
- ---------------------------------------------------------------------------*/
-
-
-#if defined ( __ICCARM__ )
- #pragma system_include /* treat file as system include file for MISRA check */
-#endif
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#ifndef __CORE_SC300_H_GENERIC
-#define __CORE_SC300_H_GENERIC
-
-/** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
- CMSIS violates the following MISRA-C:2004 rules:
-
- \li Required Rule 8.5, object/function definition in header file.<br>
- Function definitions in header files are used to allow 'inlining'.
-
- \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
- Unions are used for effective representation of core registers.
-
- \li Advisory Rule 19.7, Function-like macro defined.<br>
- Function-like macros are used to allow more efficient code.
- */
-
-
-/*******************************************************************************
- * CMSIS definitions
- ******************************************************************************/
-/** \ingroup SC3000
- @{
- */
-
-/* CMSIS SC300 definitions */
-#define __SC300_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
-#define __SC300_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
-#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16) | \
- __SC300_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
-
-#define __CORTEX_SC (300) /*!< Cortex secure core */
-
-
-#if defined ( __CC_ARM )
- #define __ASM __asm /*!< asm keyword for ARM Compiler */
- #define __INLINE __inline /*!< inline keyword for ARM Compiler */
- #define __STATIC_INLINE static __inline
-
-#elif defined ( __ICCARM__ )
- #define __ASM __asm /*!< asm keyword for IAR Compiler */
- #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
- #define __STATIC_INLINE static inline
-
-#elif defined ( __GNUC__ )
- #define __ASM __asm /*!< asm keyword for GNU Compiler */
- #define __INLINE inline /*!< inline keyword for GNU Compiler */
- #define __STATIC_INLINE static inline
-
-#elif defined ( __TASKING__ )
- #define __ASM __asm /*!< asm keyword for TASKING Compiler */
- #define __INLINE inline /*!< inline keyword for TASKING Compiler */
- #define __STATIC_INLINE static inline
-
-#endif
-
-/** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
-*/
-#define __FPU_USED 0
-
-#if defined ( __CC_ARM )
- #if defined __TARGET_FPU_VFP
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __ICCARM__ )
- #if defined __ARMVFP__
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __GNUC__ )
- #if defined (__VFP_FP__) && !defined(__SOFTFP__)
- #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-
-#elif defined ( __TASKING__ )
- #if defined __FPU_VFP__
- #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
- #endif
-#endif
-
-#include <stdint.h> /* standard types definitions */
-#include <core_cmInstr.h> /* Core Instruction Access */
-#include <core_cmFunc.h> /* Core Function Access */
-
-#endif /* __CORE_SC300_H_GENERIC */
-
-#ifndef __CMSIS_GENERIC
-
-#ifndef __CORE_SC300_H_DEPENDANT
-#define __CORE_SC300_H_DEPENDANT
-
-/* check device defines and use defaults */
-#if defined __CHECK_DEVICE_DEFINES
- #ifndef __SC300_REV
- #define __SC300_REV 0x0000
- #warning "__SC300_REV not defined in device header file; using default!"
- #endif
-
- #ifndef __MPU_PRESENT
- #define __MPU_PRESENT 0
- #warning "__MPU_PRESENT not defined in device header file; using default!"
- #endif
-
- #ifndef __NVIC_PRIO_BITS
- #define __NVIC_PRIO_BITS 4
- #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
- #endif
-
- #ifndef __Vendor_SysTickConfig
- #define __Vendor_SysTickConfig 0
- #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
- #endif
-#endif
-
-/* IO definitions (access restrictions to peripheral registers) */
-/**
- \defgroup CMSIS_glob_defs CMSIS Global Defines
-
- <strong>IO Type Qualifiers</strong> are used
- \li to specify the access to peripheral variables.
- \li for automatic generation of peripheral register debug information.
-*/
-#ifdef __cplusplus
- #define __I volatile /*!< Defines 'read only' permissions */
-#else
- #define __I volatile const /*!< Defines 'read only' permissions */
-#endif
-#define __O volatile /*!< Defines 'write only' permissions */
-#define __IO volatile /*!< Defines 'read / write' permissions */
-
-/*@} end of group SC300 */
-
-
-
-/*******************************************************************************
- * Register Abstraction
- Core Register contain:
- - Core Register
- - Core NVIC Register
- - Core SCB Register
- - Core SysTick Register
- - Core Debug Register
- - Core MPU Register
- ******************************************************************************/
-/** \defgroup CMSIS_core_register Defines and Type Definitions
- \brief Type definitions and defines for Cortex-M processor based devices.
-*/
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_CORE Status and Control Registers
- \brief Core Register type definitions.
- @{
- */
-
-/** \brief Union type to access the Application Program Status Register (APSR).
- */
-typedef union
-{
- struct
- {
-#if (__CORTEX_M != 0x04)
- uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
-#else
- uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
- uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
-#endif
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} APSR_Type;
-
-
-/** \brief Union type to access the Interrupt Program Status Register (IPSR).
- */
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
- uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} IPSR_Type;
-
-
-/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
- */
-typedef union
-{
- struct
- {
- uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
-#if (__CORTEX_M != 0x04)
- uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
-#else
- uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
- uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
- uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
-#endif
- uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
- uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
- uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
- uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
- uint32_t C:1; /*!< bit: 29 Carry condition code flag */
- uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
- uint32_t N:1; /*!< bit: 31 Negative condition code flag */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} xPSR_Type;
-
-
-/** \brief Union type to access the Control Registers (CONTROL).
- */
-typedef union
-{
- struct
- {
- uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
- uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
- uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
- uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
- } b; /*!< Structure used for bit access */
- uint32_t w; /*!< Type used for word access */
-} CONTROL_Type;
-
-/*@} end of group CMSIS_CORE */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
- \brief Type definitions for the NVIC Registers
- @{
- */
-
-/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
- */
-typedef struct
-{
- __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
- uint32_t RESERVED0[24];
- __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
- uint32_t RSERVED1[24];
- __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
- uint32_t RESERVED2[24];
- __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
- uint32_t RESERVED3[24];
- __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
- uint32_t RESERVED4[56];
- __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
- uint32_t RESERVED5[644];
- __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
-} NVIC_Type;
-
-/* Software Triggered Interrupt Register Definitions */
-#define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
-#define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */
-
-/*@} end of group CMSIS_NVIC */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_SCB System Control Block (SCB)
- \brief Type definitions for the System Control Block Registers
- @{
- */
-
-/** \brief Structure type to access the System Control Block (SCB).
- */
-typedef struct
-{
- __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
- __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
- __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
- __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
- __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
- __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
- __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
- __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
- __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
- __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
- __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
- __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
- __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
- __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
- __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
- __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
- __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
- __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
- __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
- uint32_t RESERVED0[5];
- __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
-} SCB_Type;
-
-/* SCB CPUID Register Definitions */
-#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
-#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
-
-#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
-#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
-
-#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
-#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
-
-#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
-#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
-
-#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
-#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
-
-/* SCB Interrupt Control State Register Definitions */
-#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
-#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
-
-#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
-#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
-
-#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
-#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
-
-#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
-#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
-
-#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
-#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
-
-#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
-#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
-
-#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
-#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
-
-#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
-#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
-
-#define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
-#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
-
-#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
-#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
-
-/* SCB Vector Table Offset Register Definitions */
-#define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
-#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
-
-#define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
-#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
-
-/* SCB Application Interrupt and Reset Control Register Definitions */
-#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
-#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
-
-#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
-#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
-
-#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
-#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
-
-#define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
-#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
-
-#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
-#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
-
-#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
-#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
-
-#define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
-#define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
-
-/* SCB System Control Register Definitions */
-#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
-#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
-
-#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
-#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
-
-#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
-#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
-
-/* SCB Configuration Control Register Definitions */
-#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
-#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
-
-#define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
-#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
-
-#define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
-#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
-
-#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
-#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
-
-#define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
-#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
-
-#define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
-#define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
-
-/* SCB System Handler Control and State Register Definitions */
-#define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
-#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
-
-#define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
-#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
-
-#define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
-#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
-
-#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
-#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
-
-#define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
-#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
-
-#define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
-#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
-
-#define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
-#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
-
-#define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
-#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
-
-#define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
-#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
-
-#define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
-#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
-
-#define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
-#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
-
-#define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
-#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
-
-#define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
-#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
-
-#define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
-#define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
-
-/* SCB Configurable Fault Status Registers Definitions */
-#define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
-#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
-
-#define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
-#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
-
-#define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
-#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
-
-/* SCB Hard Fault Status Registers Definitions */
-#define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
-#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
-
-#define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
-#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
-
-#define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
-#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
-
-/* SCB Debug Fault Status Register Definitions */
-#define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
-#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
-
-#define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
-#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
-
-#define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
-#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
-
-#define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
-#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
-
-#define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
-#define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
-
-/*@} end of group CMSIS_SCB */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
- \brief Type definitions for the System Control and ID Register not in the SCB
- @{
- */
-
-/** \brief Structure type to access the System Control and ID Register not in the SCB.
- */
-typedef struct
-{
- uint32_t RESERVED0[1];
- __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
- uint32_t RESERVED1[1];
-} SCnSCB_Type;
-
-/* Interrupt Controller Type Register Definitions */
-#define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
-#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */
-
-/*@} end of group CMSIS_SCnotSCB */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_SysTick System Tick Timer (SysTick)
- \brief Type definitions for the System Timer Registers.
- @{
- */
-
-/** \brief Structure type to access the System Timer (SysTick).
- */
-typedef struct
-{
- __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
- __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
- __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
- __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
-} SysTick_Type;
-
-/* SysTick Control / Status Register Definitions */
-#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
-#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
-
-#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
-#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
-
-#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
-#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
-
-#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
-#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
-
-/* SysTick Reload Register Definitions */
-#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
-#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
-
-/* SysTick Current Register Definitions */
-#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
-#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
-
-/* SysTick Calibration Register Definitions */
-#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
-#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
-
-#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
-#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
-
-#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
-#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
-
-/*@} end of group CMSIS_SysTick */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
- \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
- @{
- */
-
-/** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
- */
-typedef struct
-{
- __O union
- {
- __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
- __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
- __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
- } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
- uint32_t RESERVED0[864];
- __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
- uint32_t RESERVED1[15];
- __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
- uint32_t RESERVED2[15];
- __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
- uint32_t RESERVED3[29];
- __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
- __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
- __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
- uint32_t RESERVED4[43];
- __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
- __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
- uint32_t RESERVED5[6];
- __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
- __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
- __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
- __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
- __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
- __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
- __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
- __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
- __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
- __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
- __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
- __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
-} ITM_Type;
-
-/* ITM Trace Privilege Register Definitions */
-#define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
-#define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
-
-/* ITM Trace Control Register Definitions */
-#define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
-#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
-
-#define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
-#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
-
-#define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
-#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
-
-#define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
-#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
-
-#define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
-#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
-
-#define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
-#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
-
-#define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
-#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
-
-#define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
-#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
-
-#define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
-#define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
-
-/* ITM Integration Write Register Definitions */
-#define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
-#define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */
-
-/* ITM Integration Read Register Definitions */
-#define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
-#define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */
-
-/* ITM Integration Mode Control Register Definitions */
-#define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
-#define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */
-
-/* ITM Lock Status Register Definitions */
-#define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
-#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
-
-#define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
-#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
-
-#define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
-#define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */
-
-/*@}*/ /* end of group CMSIS_ITM */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
- \brief Type definitions for the Data Watchpoint and Trace (DWT)
- @{
- */
-
-/** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
- */
-typedef struct
-{
- __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
- __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
- __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
- __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
- __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
- __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
- __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
- __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
- __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
- __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
- __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
- uint32_t RESERVED0[1];
- __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
- __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
- __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
- uint32_t RESERVED1[1];
- __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
- __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
- __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
- uint32_t RESERVED2[1];
- __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
- __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
- __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
-} DWT_Type;
-
-/* DWT Control Register Definitions */
-#define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
-#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
-
-#define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
-#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
-
-#define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
-#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
-
-#define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
-#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
-
-#define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
-#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
-
-#define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
-#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
-
-#define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
-#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
-
-#define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
-#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
-
-#define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
-#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
-
-#define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
-#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
-
-#define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
-#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
-
-#define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
-#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
-
-#define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
-#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
-
-#define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
-#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
-
-#define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
-#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
-
-#define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
-#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
-
-#define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
-#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
-
-#define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
-#define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */
-
-/* DWT CPI Count Register Definitions */
-#define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
-#define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */
-
-/* DWT Exception Overhead Count Register Definitions */
-#define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
-#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */
-
-/* DWT Sleep Count Register Definitions */
-#define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
-#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
-
-/* DWT LSU Count Register Definitions */
-#define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
-#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */
-
-/* DWT Folded-instruction Count Register Definitions */
-#define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
-#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */
-
-/* DWT Comparator Mask Register Definitions */
-#define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
-#define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */
-
-/* DWT Comparator Function Register Definitions */
-#define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
-#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
-
-#define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
-#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
-
-#define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
-#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
-
-#define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
-#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
-
-#define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
-#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
-
-#define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
-#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
-
-#define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
-#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
-
-#define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
-#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
-
-#define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
-#define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */
-
-/*@}*/ /* end of group CMSIS_DWT */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_TPI Trace Port Interface (TPI)
- \brief Type definitions for the Trace Port Interface (TPI)
- @{
- */
-
-/** \brief Structure type to access the Trace Port Interface Register (TPI).
- */
-typedef struct
-{
- __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
- __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
- uint32_t RESERVED0[2];
- __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
- uint32_t RESERVED1[55];
- __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
- uint32_t RESERVED2[131];
- __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
- __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
- __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
- uint32_t RESERVED3[759];
- __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
- __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
- __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
- uint32_t RESERVED4[1];
- __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
- __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
- __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
- uint32_t RESERVED5[39];
- __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
- __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
- uint32_t RESERVED7[8];
- __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
- __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
-} TPI_Type;
-
-/* TPI Asynchronous Clock Prescaler Register Definitions */
-#define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
-#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */
-
-/* TPI Selected Pin Protocol Register Definitions */
-#define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
-#define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */
-
-/* TPI Formatter and Flush Status Register Definitions */
-#define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
-#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
-
-#define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
-#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
-
-#define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
-#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
-
-#define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
-#define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */
-
-/* TPI Formatter and Flush Control Register Definitions */
-#define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
-#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
-
-#define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
-#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
-
-/* TPI TRIGGER Register Definitions */
-#define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
-#define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */
-
-/* TPI Integration ETM Data Register Definitions (FIFO0) */
-#define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
-#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
-
-#define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
-#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
-
-#define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
-#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
-
-#define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
-#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
-
-#define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
-#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
-
-#define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
-#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
-
-#define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
-#define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */
-
-/* TPI ITATBCTR2 Register Definitions */
-#define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
-#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */
-
-/* TPI Integration ITM Data Register Definitions (FIFO1) */
-#define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
-#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
-
-#define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
-#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
-
-#define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
-#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
-
-#define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
-#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
-
-#define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
-#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
-
-#define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
-#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
-
-#define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
-#define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */
-
-/* TPI ITATBCTR0 Register Definitions */
-#define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
-#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */
-
-/* TPI Integration Mode Control Register Definitions */
-#define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
-#define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */
-
-/* TPI DEVID Register Definitions */
-#define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
-#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
-
-#define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
-#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
-
-#define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
-#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
-
-#define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
-#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
-
-#define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
-#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
-
-#define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
-#define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */
-
-/* TPI DEVTYPE Register Definitions */
-#define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
-#define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */
-
-#define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
-#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
-
-/*@}*/ /* end of group CMSIS_TPI */
-
-
-#if (__MPU_PRESENT == 1)
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_MPU Memory Protection Unit (MPU)
- \brief Type definitions for the Memory Protection Unit (MPU)
- @{
- */
-
-/** \brief Structure type to access the Memory Protection Unit (MPU).
- */
-typedef struct
-{
- __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
- __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
- __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
- __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
- __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
- __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
- __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
- __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
- __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
- __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
- __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
-} MPU_Type;
-
-/* MPU Type Register */
-#define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
-#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
-
-#define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
-#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
-
-#define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
-#define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
-
-/* MPU Control Register */
-#define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
-#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
-
-#define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
-#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
-
-#define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
-#define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
-
-/* MPU Region Number Register */
-#define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
-#define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
-
-/* MPU Region Base Address Register */
-#define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
-#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
-
-#define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
-#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
-
-#define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
-#define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
-
-/* MPU Region Attribute and Size Register */
-#define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
-#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
-
-#define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
-#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
-
-#define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
-#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
-
-#define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
-#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
-
-#define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
-#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
-
-#define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
-#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
-
-#define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
-#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
-
-#define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
-#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
-
-#define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
-#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
-
-#define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
-#define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
-
-/*@} end of group CMSIS_MPU */
-#endif
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
- \brief Type definitions for the Core Debug Registers
- @{
- */
-
-/** \brief Structure type to access the Core Debug Register (CoreDebug).
- */
-typedef struct
-{
- __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
- __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
- __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
- __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
-} CoreDebug_Type;
-
-/* Debug Halting Control and Status Register */
-#define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
-#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
-
-#define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
-#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
-
-#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
-#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
-
-#define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
-#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
-
-#define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
-#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
-
-#define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
-#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
-
-#define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
-#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
-
-#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
-#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
-
-#define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
-#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
-
-#define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
-#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
-
-#define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
-#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
-
-#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
-#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
-
-/* Debug Core Register Selector Register */
-#define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
-#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
-
-#define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
-#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
-
-/* Debug Exception and Monitor Control Register */
-#define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
-#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
-
-#define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
-#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
-
-#define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
-#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
-
-#define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
-#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
-
-#define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
-#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
-
-#define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
-#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
-
-#define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
-#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
-
-#define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
-#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
-
-#define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
-#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
-
-#define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
-#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
-
-#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
-#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
-
-#define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
-#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
-
-#define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
-#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
-
-/*@} end of group CMSIS_CoreDebug */
-
-
-/** \ingroup CMSIS_core_register
- \defgroup CMSIS_core_base Core Definitions
- \brief Definitions for base addresses, unions, and structures.
- @{
- */
-
-/* Memory mapping of Cortex-M3 Hardware */
-#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
-#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
-#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
-#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
-#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
-#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
-#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
-#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
-
-#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
-#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
-#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
-#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
-#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
-#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
-#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
-#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
-
-#if (__MPU_PRESENT == 1)
- #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
- #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
-#endif
-
-/*@} */
-
-
-
-/*******************************************************************************
- * Hardware Abstraction Layer
- Core Function Interface contains:
- - Core NVIC Functions
- - Core SysTick Functions
- - Core Debug Functions
- - Core Register Access Functions
- ******************************************************************************/
-/** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
-*/
-
-
-
-/* ########################## NVIC functions #################################### */
-/** \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_NVICFunctions NVIC Functions
- \brief Functions that manage interrupts and exceptions via the NVIC.
- @{
- */
-
-/** \brief Set Priority Grouping
-
- The function sets the priority grouping field using the required unlock sequence.
- The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
- Only values from 0..7 are used.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
-
- \param [in] PriorityGroup Priority grouping field.
- */
-__STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
- uint32_t reg_value;
- uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
-
- reg_value = SCB->AIRCR; /* read old register configuration */
- reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
- reg_value = (reg_value |
- ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
- (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
- SCB->AIRCR = reg_value;
-}
-
-
-/** \brief Get Priority Grouping
-
- The function reads the priority grouping field from the NVIC Interrupt Controller.
-
- \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
- */
-__STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
-{
- return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
-}
-
-
-/** \brief Enable External Interrupt
-
- The function enables a device-specific interrupt in the NVIC interrupt controller.
-
- \param [in] IRQn External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
-{
- NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
-}
-
-
-/** \brief Disable External Interrupt
-
- The function disables a device-specific interrupt in the NVIC interrupt controller.
-
- \param [in] IRQn External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
-{
- NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
-}
-
-
-/** \brief Get Pending Interrupt
-
- The function reads the pending register in the NVIC and returns the pending bit
- for the specified interrupt.
-
- \param [in] IRQn Interrupt number.
-
- \return 0 Interrupt status is not pending.
- \return 1 Interrupt status is pending.
- */
-__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
- return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
-}
-
-
-/** \brief Set Pending Interrupt
-
- The function sets the pending bit of an external interrupt.
-
- \param [in] IRQn Interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
- NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
-}
-
-
-/** \brief Clear Pending Interrupt
-
- The function clears the pending bit of an external interrupt.
-
- \param [in] IRQn External interrupt number. Value cannot be negative.
- */
-__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
- NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
-}
-
-
-/** \brief Get Active Interrupt
-
- The function reads the active register in NVIC and returns the active bit.
-
- \param [in] IRQn Interrupt number.
-
- \return 0 Interrupt status is not active.
- \return 1 Interrupt status is active.
- */
-__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
-{
- return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
-}
-
-
-/** \brief Set Interrupt Priority
-
- The function sets the priority of an interrupt.
-
- \note The priority cannot be set for every core interrupt.
-
- \param [in] IRQn Interrupt number.
- \param [in] priority Priority to set.
- */
-__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
-{
- if(IRQn < 0) {
- SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
- else {
- NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
-}
-
-
-/** \brief Get Interrupt Priority
-
- The function reads the priority of an interrupt. The interrupt
- number can be positive to specify an external (device specific)
- interrupt, or negative to specify an internal (core) interrupt.
-
-
- \param [in] IRQn Interrupt number.
- \return Interrupt Priority. Value is aligned automatically to the implemented
- priority bits of the microcontroller.
- */
-__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
-{
-
- if(IRQn < 0) {
- return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
- else {
- return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
-}
-
-
-/** \brief Encode Priority
-
- The function encodes the priority for an interrupt with the given priority group,
- preemptive priority value, and subpriority value.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
-
- \param [in] PriorityGroup Used priority group.
- \param [in] PreemptPriority Preemptive priority value (starting from 0).
- \param [in] SubPriority Subpriority value (starting from 0).
- \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
- */
-__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
-{
- uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
- uint32_t PreemptPriorityBits;
- uint32_t SubPriorityBits;
-
- PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
- SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
-
- return (
- ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
- ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
- );
-}
-
-
-/** \brief Decode Priority
-
- The function decodes an interrupt priority value with a given priority group to
- preemptive priority value and subpriority value.
- In case of a conflict between priority grouping and available
- priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
-
- \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
- \param [in] PriorityGroup Used priority group.
- \param [out] pPreemptPriority Preemptive priority value (starting from 0).
- \param [out] pSubPriority Subpriority value (starting from 0).
- */
-__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
-{
- uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
- uint32_t PreemptPriorityBits;
- uint32_t SubPriorityBits;
-
- PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
- SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
-
- *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
- *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
-}
-
-
-/** \brief System Reset
-
- The function initiates a system reset request to reset the MCU.
- */
-__STATIC_INLINE void NVIC_SystemReset(void)
-{
- __DSB(); /* Ensure all outstanding memory accesses included
- buffered write are completed before reset */
- SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
- (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
- SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
- __DSB(); /* Ensure completion of memory access */
- while(1); /* wait until reset */
-}
-
-/*@} end of CMSIS_Core_NVICFunctions */
-
-
-
-/* ################################## SysTick function ############################################ */
-/** \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
- \brief Functions that configure the System.
- @{
- */
-
-#if (__Vendor_SysTickConfig == 0)
-
-/** \brief System Tick Configuration
-
- The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
- Counter is in free running mode to generate periodic interrupts.
-
- \param [in] ticks Number of ticks between two interrupts.
-
- \return 0 Function succeeded.
- \return 1 Function failed.
-
- \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
- function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
- must contain a vendor-specific implementation of this function.
-
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
- if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
-
- SysTick->LOAD = ticks - 1; /* set reload register */
- NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
- SysTick->VAL = 0; /* Load the SysTick Counter Value */
- SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
- SysTick_CTRL_TICKINT_Msk |
- SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
- return (0); /* Function successful */
-}
-
-#endif
-
-/*@} end of CMSIS_Core_SysTickFunctions */
-
-
-
-/* ##################################### Debug In/Output function ########################################### */
-/** \ingroup CMSIS_Core_FunctionInterface
- \defgroup CMSIS_core_DebugFunctions ITM Functions
- \brief Functions that access the ITM debug interface.
- @{
- */
-
-extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
-#define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
-
-
-/** \brief ITM Send Character
-
- The function transmits a character via the ITM channel 0, and
- \li Just returns when no debugger is connected that has booked the output.
- \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
-
- \param [in] ch Character to transmit.
-
- \returns Character to transmit.
- */
-__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
-{
- if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
- (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
- {
- while (ITM->PORT[0].u32 == 0);
- ITM->PORT[0].u8 = (uint8_t) ch;
- }
- return (ch);
-}
-
-
-/** \brief ITM Receive Character
-
- The function inputs a character via the external variable \ref ITM_RxBuffer.
-
- \return Received character.
- \return -1 No character pending.
- */
-__STATIC_INLINE int32_t ITM_ReceiveChar (void) {
- int32_t ch = -1; /* no character available */
-
- if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
- ch = ITM_RxBuffer;
- ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
- }
-
- return (ch);
-}
-
-
-/** \brief ITM Check Character
-
- The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
-
- \return 0 No character available.
- \return 1 Character available.
- */
-__STATIC_INLINE int32_t ITM_CheckChar (void) {
-
- if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
- return (0); /* no character available */
- } else {
- return (1); /* character available */
- }
-}
-
-/*@} end of CMSIS_core_DebugFunctions */
-
-#endif /* __CORE_SC300_H_DEPENDANT */
-
-#endif /* __CMSIS_GENERIC */
-
-#ifdef __cplusplus
-}
-#endif
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_adc.h b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_adc.h
deleted file mode 100644
index b5700687928258ea3ef9b646a7badf6fb9893ee3..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_adc.h
+++ /dev/null
@@ -1,450 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f0xx_adc.h
- * @author MCD Application Team
- * @version V1.3.0
- * @date 16-January-2014
- * @brief This file contains all the functions prototypes for the ADC firmware
- * library
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F0XX_ADC_H
-#define __STM32F0XX_ADC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup ADC
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/**
- * @brief ADC Init structure definition
- */
-
-typedef struct
-{
- uint32_t ADC_Resolution; /*!< Selects the resolution of the conversion.
- This parameter can be a value of @ref ADC_Resolution */
-
- FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion is performed in
- Continuous or Single mode.
- This parameter can be set to ENABLE or DISABLE. */
-
- uint32_t ADC_ExternalTrigConvEdge; /*!< Selects the external trigger Edge and enables the
- trigger of a regular group. This parameter can be a value
- of @ref ADC_external_trigger_edge_conversion */
-
- uint32_t ADC_ExternalTrigConv; /*!< Defines the external trigger used to start the analog
- to digital conversion of regular channels. This parameter
- can be a value of @ref ADC_external_trigger_sources_for_channels_conversion */
-
- uint32_t ADC_DataAlign; /*!< Specifies whether the ADC data alignment is left or right.
- This parameter can be a value of @ref ADC_data_align */
-
- uint32_t ADC_ScanDirection; /*!< Specifies in which direction the channels will be scanned
- in the sequence.
- This parameter can be a value of @ref ADC_Scan_Direction */
-}ADC_InitTypeDef;
-
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup ADC_Exported_Constants
- * @{
- */
-#define IS_ADC_ALL_PERIPH(PERIPH) ((PERIPH) == ADC1)
-
-/** @defgroup ADC_JitterOff
- * @{
- */
-/* These defines are obsolete and maintained for legacy purpose only. They are replaced by the ADC_ClockMode */
-#define ADC_JitterOff_PCLKDiv2 ADC_CFGR2_JITOFFDIV2
-#define ADC_JitterOff_PCLKDiv4 ADC_CFGR2_JITOFFDIV4
-
-#define IS_ADC_JITTEROFF(JITTEROFF) (((JITTEROFF) & 0x3FFFFFFF) == (uint32_t)RESET)
-
-/**
- * @}
- */
-
-/** @defgroup ADC_ClockMode
- * @{
- */
-#define ADC_ClockMode_AsynClk ((uint32_t)0x00000000) /*!< ADC Asynchronous clock mode */
-#define ADC_ClockMode_SynClkDiv2 ADC_CFGR2_CKMODE_0 /*!< Synchronous clock mode divided by 2 */
-#define ADC_ClockMode_SynClkDiv4 ADC_CFGR2_CKMODE_1 /*!< Synchronous clock mode divided by 4 */
-#define IS_ADC_CLOCKMODE(CLOCK) (((CLOCK) == ADC_ClockMode_AsynClk) ||\
- ((CLOCK) == ADC_ClockMode_SynClkDiv2) ||\
- ((CLOCK) == ADC_ClockMode_SynClkDiv4))
-
-/**
- * @}
- */
-
-/** @defgroup ADC_Resolution
- * @{
- */
-#define ADC_Resolution_12b ((uint32_t)0x00000000)
-#define ADC_Resolution_10b ADC_CFGR1_RES_0
-#define ADC_Resolution_8b ADC_CFGR1_RES_1
-#define ADC_Resolution_6b ADC_CFGR1_RES
-
-#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_Resolution_12b) || \
- ((RESOLUTION) == ADC_Resolution_10b) || \
- ((RESOLUTION) == ADC_Resolution_8b) || \
- ((RESOLUTION) == ADC_Resolution_6b))
-
-/**
- * @}
- */
-
-/** @defgroup ADC_external_trigger_edge_conversion
- * @{
- */
-#define ADC_ExternalTrigConvEdge_None ((uint32_t)0x00000000)
-#define ADC_ExternalTrigConvEdge_Rising ADC_CFGR1_EXTEN_0
-#define ADC_ExternalTrigConvEdge_Falling ADC_CFGR1_EXTEN_1
-#define ADC_ExternalTrigConvEdge_RisingFalling ADC_CFGR1_EXTEN
-
-#define IS_ADC_EXT_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigConvEdge_None) || \
- ((EDGE) == ADC_ExternalTrigConvEdge_Rising) || \
- ((EDGE) == ADC_ExternalTrigConvEdge_Falling) || \
- ((EDGE) == ADC_ExternalTrigConvEdge_RisingFalling))
-/**
- * @}
- */
-
-/** @defgroup ADC_external_trigger_sources_for_channels_conversion
- * @{
- */
-
-/* TIM1 */
-#define ADC_ExternalTrigConv_T1_TRGO ((uint32_t)0x00000000)
-#define ADC_ExternalTrigConv_T1_CC4 ADC_CFGR1_EXTSEL_0
-
-/* TIM2 */
-#define ADC_ExternalTrigConv_T2_TRGO ADC_CFGR1_EXTSEL_1
-
-/* TIM3 */
-#define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)(ADC_CFGR1_EXTSEL_0 | ADC_CFGR1_EXTSEL_1))
-
-/* TIM15 */
-#define ADC_ExternalTrigConv_T15_TRGO ADC_CFGR1_EXTSEL_2
-
-#define IS_ADC_EXTERNAL_TRIG_CONV(CONV) (((CONV) == ADC_ExternalTrigConv_T1_TRGO) || \
- ((CONV) == ADC_ExternalTrigConv_T1_CC4) || \
- ((CONV) == ADC_ExternalTrigConv_T2_TRGO) || \
- ((CONV) == ADC_ExternalTrigConv_T3_TRGO) || \
- ((CONV) == ADC_ExternalTrigConv_T15_TRGO))
-/**
- * @}
- */
-
-/** @defgroup ADC_data_align
- * @{
- */
-
-#define ADC_DataAlign_Right ((uint32_t)0x00000000)
-#define ADC_DataAlign_Left ADC_CFGR1_ALIGN
-
-#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \
- ((ALIGN) == ADC_DataAlign_Left))
-/**
- * @}
- */
-
-/** @defgroup ADC_Scan_Direction
- * @{
- */
-
-#define ADC_ScanDirection_Upward ((uint32_t)0x00000000)
-#define ADC_ScanDirection_Backward ADC_CFGR1_SCANDIR
-
-#define IS_ADC_SCAN_DIRECTION(DIRECTION) (((DIRECTION) == ADC_ScanDirection_Upward) || \
- ((DIRECTION) == ADC_ScanDirection_Backward))
-/**
- * @}
- */
-
-/** @defgroup ADC_DMA_Mode
- * @{
- */
-
-#define ADC_DMAMode_OneShot ((uint32_t)0x00000000)
-#define ADC_DMAMode_Circular ADC_CFGR1_DMACFG
-
-#define IS_ADC_DMA_MODE(MODE) (((MODE) == ADC_DMAMode_OneShot) || \
- ((MODE) == ADC_DMAMode_Circular))
-/**
- * @}
- */
-
-/** @defgroup ADC_analog_watchdog_selection
- * @{
- */
-
-#define ADC_AnalogWatchdog_Channel_0 ((uint32_t)0x00000000)
-#define ADC_AnalogWatchdog_Channel_1 ((uint32_t)0x04000000)
-#define ADC_AnalogWatchdog_Channel_2 ((uint32_t)0x08000000)
-#define ADC_AnalogWatchdog_Channel_3 ((uint32_t)0x0C000000)
-#define ADC_AnalogWatchdog_Channel_4 ((uint32_t)0x10000000)
-#define ADC_AnalogWatchdog_Channel_5 ((uint32_t)0x14000000)
-#define ADC_AnalogWatchdog_Channel_6 ((uint32_t)0x18000000)
-#define ADC_AnalogWatchdog_Channel_7 ((uint32_t)0x1C000000)
-#define ADC_AnalogWatchdog_Channel_8 ((uint32_t)0x20000000)
-#define ADC_AnalogWatchdog_Channel_9 ((uint32_t)0x24000000)
-#define ADC_AnalogWatchdog_Channel_10 ((uint32_t)0x28000000) /*!< Not available for STM32F031 devices */
-#define ADC_AnalogWatchdog_Channel_11 ((uint32_t)0x2C000000) /*!< Not available for STM32F031 devices */
-#define ADC_AnalogWatchdog_Channel_12 ((uint32_t)0x30000000) /*!< Not available for STM32F031 devices */
-#define ADC_AnalogWatchdog_Channel_13 ((uint32_t)0x34000000) /*!< Not available for STM32F031 devices */
-#define ADC_AnalogWatchdog_Channel_14 ((uint32_t)0x38000000) /*!< Not available for STM32F031 devices */
-#define ADC_AnalogWatchdog_Channel_15 ((uint32_t)0x3C000000) /*!< Not available for STM32F031 devices */
-#define ADC_AnalogWatchdog_Channel_16 ((uint32_t)0x40000000)
-#define ADC_AnalogWatchdog_Channel_17 ((uint32_t)0x44000000)
-#define ADC_AnalogWatchdog_Channel_18 ((uint32_t)0x48000000)
-
-
-#define IS_ADC_ANALOG_WATCHDOG_CHANNEL(CHANNEL) (((CHANNEL) == ADC_AnalogWatchdog_Channel_0) || \
- ((CHANNEL) == ADC_AnalogWatchdog_Channel_1) || \
- ((CHANNEL) == ADC_AnalogWatchdog_Channel_2) || \
- ((CHANNEL) == ADC_AnalogWatchdog_Channel_3) || \
- ((CHANNEL) == ADC_AnalogWatchdog_Channel_4) || \
- ((CHANNEL) == ADC_AnalogWatchdog_Channel_5) || \
- ((CHANNEL) == ADC_AnalogWatchdog_Channel_6) || \
- ((CHANNEL) == ADC_AnalogWatchdog_Channel_7) || \
- ((CHANNEL) == ADC_AnalogWatchdog_Channel_8) || \
- ((CHANNEL) == ADC_AnalogWatchdog_Channel_9) || \
- ((CHANNEL) == ADC_AnalogWatchdog_Channel_10) || \
- ((CHANNEL) == ADC_AnalogWatchdog_Channel_11) || \
- ((CHANNEL) == ADC_AnalogWatchdog_Channel_12) || \
- ((CHANNEL) == ADC_AnalogWatchdog_Channel_13) || \
- ((CHANNEL) == ADC_AnalogWatchdog_Channel_14) || \
- ((CHANNEL) == ADC_AnalogWatchdog_Channel_15) || \
- ((CHANNEL) == ADC_AnalogWatchdog_Channel_16) || \
- ((CHANNEL) == ADC_AnalogWatchdog_Channel_17) || \
- ((CHANNEL) == ADC_AnalogWatchdog_Channel_18))
-/**
- * @}
- */
-
-/** @defgroup ADC_sampling_times
- * @{
- */
-
-#define ADC_SampleTime_1_5Cycles ((uint32_t)0x00000000)
-#define ADC_SampleTime_7_5Cycles ((uint32_t)0x00000001)
-#define ADC_SampleTime_13_5Cycles ((uint32_t)0x00000002)
-#define ADC_SampleTime_28_5Cycles ((uint32_t)0x00000003)
-#define ADC_SampleTime_41_5Cycles ((uint32_t)0x00000004)
-#define ADC_SampleTime_55_5Cycles ((uint32_t)0x00000005)
-#define ADC_SampleTime_71_5Cycles ((uint32_t)0x00000006)
-#define ADC_SampleTime_239_5Cycles ((uint32_t)0x00000007)
-
-#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_1_5Cycles) || \
- ((TIME) == ADC_SampleTime_7_5Cycles) || \
- ((TIME) == ADC_SampleTime_13_5Cycles) || \
- ((TIME) == ADC_SampleTime_28_5Cycles) || \
- ((TIME) == ADC_SampleTime_41_5Cycles) || \
- ((TIME) == ADC_SampleTime_55_5Cycles) || \
- ((TIME) == ADC_SampleTime_71_5Cycles) || \
- ((TIME) == ADC_SampleTime_239_5Cycles))
-/**
- * @}
- */
-
-/** @defgroup ADC_thresholds
- * @{
- */
-
-#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF)
-
-/**
- * @}
- */
-
-/** @defgroup ADC_channels
- * @{
- */
-
-#define ADC_Channel_0 ADC_CHSELR_CHSEL0
-#define ADC_Channel_1 ADC_CHSELR_CHSEL1
-#define ADC_Channel_2 ADC_CHSELR_CHSEL2
-#define ADC_Channel_3 ADC_CHSELR_CHSEL3
-#define ADC_Channel_4 ADC_CHSELR_CHSEL4
-#define ADC_Channel_5 ADC_CHSELR_CHSEL5
-#define ADC_Channel_6 ADC_CHSELR_CHSEL6
-#define ADC_Channel_7 ADC_CHSELR_CHSEL7
-#define ADC_Channel_8 ADC_CHSELR_CHSEL8
-#define ADC_Channel_9 ADC_CHSELR_CHSEL9
-#define ADC_Channel_10 ADC_CHSELR_CHSEL10 /*!< Not available for STM32F031 devices */
-#define ADC_Channel_11 ADC_CHSELR_CHSEL11 /*!< Not available for STM32F031 devices */
-#define ADC_Channel_12 ADC_CHSELR_CHSEL12 /*!< Not available for STM32F031 devices */
-#define ADC_Channel_13 ADC_CHSELR_CHSEL13 /*!< Not available for STM32F031 devices */
-#define ADC_Channel_14 ADC_CHSELR_CHSEL14 /*!< Not available for STM32F031 devices */
-#define ADC_Channel_15 ADC_CHSELR_CHSEL15 /*!< Not available for STM32F031 devices */
-#define ADC_Channel_16 ADC_CHSELR_CHSEL16
-#define ADC_Channel_17 ADC_CHSELR_CHSEL17
-#define ADC_Channel_18 ADC_CHSELR_CHSEL18 /*!< Not available for STM32F030 devices */
-
-#define ADC_Channel_TempSensor ((uint32_t)ADC_Channel_16)
-#define ADC_Channel_Vrefint ((uint32_t)ADC_Channel_17)
-#define ADC_Channel_Vbat ((uint32_t)ADC_Channel_18) /*!< Not available for STM32F030 devices */
-
-#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) != (uint32_t)RESET) && (((CHANNEL) & 0xFFF80000) == (uint32_t)RESET))
-
-/**
- * @}
- */
-
-/** @defgroup ADC_interrupts_definition
- * @{
- */
-
-#define ADC_IT_ADRDY ADC_IER_ADRDYIE
-#define ADC_IT_EOSMP ADC_IER_EOSMPIE
-#define ADC_IT_EOC ADC_IER_EOCIE
-#define ADC_IT_EOSEQ ADC_IER_EOSEQIE
-#define ADC_IT_OVR ADC_IER_OVRIE
-#define ADC_IT_AWD ADC_IER_AWDIE
-
-#define IS_ADC_CONFIG_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFFFF60) == (uint32_t)RESET))
-
-#define IS_ADC_GET_IT(IT) (((IT) == ADC_IT_ADRDY) || ((IT) == ADC_IT_EOSMP) || \
- ((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_EOSEQ) || \
- ((IT) == ADC_IT_OVR) || ((IT) == ADC_IT_AWD))
-
-#define IS_ADC_CLEAR_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFFFF60) == (uint32_t)RESET))
-
-/**
- * @}
- */
-
-/** @defgroup ADC_flags_definition
- * @{
- */
-
-#define ADC_FLAG_ADRDY ADC_ISR_ADRDY
-#define ADC_FLAG_EOSMP ADC_ISR_EOSMP
-#define ADC_FLAG_EOC ADC_ISR_EOC
-#define ADC_FLAG_EOSEQ ADC_ISR_EOSEQ
-#define ADC_FLAG_OVR ADC_ISR_OVR
-#define ADC_FLAG_AWD ADC_ISR_AWD
-
-#define ADC_FLAG_ADEN ((uint32_t)0x01000001)
-#define ADC_FLAG_ADDIS ((uint32_t)0x01000002)
-#define ADC_FLAG_ADSTART ((uint32_t)0x01000004)
-#define ADC_FLAG_ADSTP ((uint32_t)0x01000010)
-#define ADC_FLAG_ADCAL ((uint32_t)0x81000000)
-
-#define IS_ADC_CLEAR_FLAG(FLAG) (((FLAG) != (uint32_t)RESET) && (((FLAG) & 0xFFFFFF60) == (uint32_t)RESET))
-
-#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_ADRDY) || ((FLAG) == ADC_FLAG_EOSMP) || \
- ((FLAG) == ADC_FLAG_EOC) || ((FLAG) == ADC_FLAG_EOSEQ) || \
- ((FLAG) == ADC_FLAG_AWD) || ((FLAG) == ADC_FLAG_OVR) || \
- ((FLAG) == ADC_FLAG_ADEN) || ((FLAG) == ADC_FLAG_ADDIS) || \
- ((FLAG) == ADC_FLAG_ADSTART) || ((FLAG) == ADC_FLAG_ADSTP) || \
- ((FLAG) == ADC_FLAG_ADCAL))
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-/* Function used to set the ADC configuration to the default reset state *****/
-void ADC_DeInit(ADC_TypeDef* ADCx);
-
-/* Initialization and Configuration functions *********************************/
-void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct);
-void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct);
-void ADC_ClockModeConfig(ADC_TypeDef* ADCx, uint32_t ADC_ClockMode);
-void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
-/* This Function is obsolete and maintained for legacy purpose only.
- ADC_ClockModeConfig() function should be used instead */
-void ADC_JitterCmd(ADC_TypeDef* ADCx, uint32_t ADC_JitterOff, FunctionalState NewState);
-
-/* Power saving functions *****************************************************/
-void ADC_AutoPowerOffCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
-void ADC_WaitModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
-
-/* Analog Watchdog configuration functions ************************************/
-void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
-void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,uint16_t LowThreshold);
-void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog_Channel);
-void ADC_AnalogWatchdogSingleChannelCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
-
-/* Temperature Sensor , Vrefint and Vbat management function ******************/
-void ADC_TempSensorCmd(FunctionalState NewState);
-void ADC_VrefintCmd(FunctionalState NewState);
-void ADC_VbatCmd(FunctionalState NewState); /*!< Not applicable for STM32F030 devices */
-
-/* Channels Configuration functions *******************************************/
-void ADC_ChannelConfig(ADC_TypeDef* ADCx, uint32_t ADC_Channel, uint32_t ADC_SampleTime);
-void ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
-void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
-void ADC_OverrunModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
-uint32_t ADC_GetCalibrationFactor(ADC_TypeDef* ADCx);
-void ADC_StopOfConversion(ADC_TypeDef* ADCx);
-void ADC_StartOfConversion(ADC_TypeDef* ADCx);
-uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx);
-
-/* Regular Channels DMA Configuration functions *******************************/
-void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState);
-void ADC_DMARequestModeConfig(ADC_TypeDef* ADCx, uint32_t ADC_DMARequestMode);
-
-/* Interrupts and flags management functions **********************************/
-void ADC_ITConfig(ADC_TypeDef* ADCx, uint32_t ADC_IT, FunctionalState NewState);
-FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint32_t ADC_FLAG);
-void ADC_ClearFlag(ADC_TypeDef* ADCx, uint32_t ADC_FLAG);
-ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint32_t ADC_IT);
-void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint32_t ADC_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F0XX_ADC_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_can.h b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_can.h
deleted file mode 100644
index 60a4098c146539f26e5d5bcfef4e7b893f0c06c7..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_can.h
+++ /dev/null
@@ -1,643 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f0xx_can.h
- * @author MCD Application Team
- * @version V1.3.0
- * @date 16-January-2014
- * @brief This file contains all the functions prototypes for the CAN firmware
- * library, applicable only for STM32F072 devices.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F0xx_CAN_H
-#define __STM32F0xx_CAN_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup CAN
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-#define IS_CAN_ALL_PERIPH(PERIPH) (((PERIPH) == CAN))
-
-/**
- * @brief CAN init structure definition
- */
-typedef struct
-{
- uint16_t CAN_Prescaler; /*!< Specifies the length of a time quantum.
- It ranges from 1 to 1024. */
-
- uint8_t CAN_Mode; /*!< Specifies the CAN operating mode.
- This parameter can be a value of @ref CAN_operating_mode */
-
- uint8_t CAN_SJW; /*!< Specifies the maximum number of time quanta
- the CAN hardware is allowed to lengthen or
- shorten a bit to perform resynchronization.
- This parameter can be a value of @ref CAN_synchronisation_jump_width */
-
- uint8_t CAN_BS1; /*!< Specifies the number of time quanta in Bit
- Segment 1. This parameter can be a value of
- @ref CAN_time_quantum_in_bit_segment_1 */
-
- uint8_t CAN_BS2; /*!< Specifies the number of time quanta in Bit Segment 2.
- This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */
-
- FunctionalState CAN_TTCM; /*!< Enable or disable the time triggered communication mode.
- This parameter can be set either to ENABLE or DISABLE. */
-
- FunctionalState CAN_ABOM; /*!< Enable or disable the automatic bus-off management.
- This parameter can be set either to ENABLE or DISABLE. */
-
- FunctionalState CAN_AWUM; /*!< Enable or disable the automatic wake-up mode.
- This parameter can be set either to ENABLE or DISABLE. */
-
- FunctionalState CAN_NART; /*!< Enable or disable the non-automatic retransmission mode.
- This parameter can be set either to ENABLE or DISABLE. */
-
- FunctionalState CAN_RFLM; /*!< Enable or disable the Receive FIFO Locked mode.
- This parameter can be set either to ENABLE or DISABLE. */
-
- FunctionalState CAN_TXFP; /*!< Enable or disable the transmit FIFO priority.
- This parameter can be set either to ENABLE or DISABLE. */
-} CAN_InitTypeDef;
-
-/**
- * @brief CAN filter init structure definition
- */
-typedef struct
-{
- uint16_t CAN_FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit
- configuration, first one for a 16-bit configuration).
- This parameter can be a value between 0x0000 and 0xFFFF */
-
- uint16_t CAN_FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit
- configuration, second one for a 16-bit configuration).
- This parameter can be a value between 0x0000 and 0xFFFF */
-
- uint16_t CAN_FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number,
- according to the mode (MSBs for a 32-bit configuration,
- first one for a 16-bit configuration).
- This parameter can be a value between 0x0000 and 0xFFFF */
-
- uint16_t CAN_FilterMaskIdLow; /*!< Specifies the filter mask number or identification number,
- according to the mode (LSBs for a 32-bit configuration,
- second one for a 16-bit configuration).
- This parameter can be a value between 0x0000 and 0xFFFF */
-
- uint16_t CAN_FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter.
- This parameter can be a value of @ref CAN_filter_FIFO */
-
- uint8_t CAN_FilterNumber; /*!< Specifies the filter which will be initialized. It ranges from 0 to 13. */
-
- uint8_t CAN_FilterMode; /*!< Specifies the filter mode to be initialized.
- This parameter can be a value of @ref CAN_filter_mode */
-
- uint8_t CAN_FilterScale; /*!< Specifies the filter scale.
- This parameter can be a value of @ref CAN_filter_scale */
-
- FunctionalState CAN_FilterActivation; /*!< Enable or disable the filter.
- This parameter can be set either to ENABLE or DISABLE. */
-} CAN_FilterInitTypeDef;
-
-/**
- * @brief CAN Tx message structure definition
- */
-typedef struct
-{
- uint32_t StdId; /*!< Specifies the standard identifier.
- This parameter can be a value between 0 to 0x7FF. */
-
- uint32_t ExtId; /*!< Specifies the extended identifier.
- This parameter can be a value between 0 to 0x1FFFFFFF. */
-
- uint8_t IDE; /*!< Specifies the type of identifier for the message that
- will be transmitted. This parameter can be a value
- of @ref CAN_identifier_type */
-
- uint8_t RTR; /*!< Specifies the type of frame for the message that will
- be transmitted. This parameter can be a value of
- @ref CAN_remote_transmission_request */
-
- uint8_t DLC; /*!< Specifies the length of the frame that will be
- transmitted. This parameter can be a value between
- 0 to 8 */
-
- uint8_t Data[8]; /*!< Contains the data to be transmitted. It ranges from 0
- to 0xFF. */
-} CanTxMsg;
-
-/**
- * @brief CAN Rx message structure definition
- */
-typedef struct
-{
- uint32_t StdId; /*!< Specifies the standard identifier.
- This parameter can be a value between 0 to 0x7FF. */
-
- uint32_t ExtId; /*!< Specifies the extended identifier.
- This parameter can be a value between 0 to 0x1FFFFFFF. */
-
- uint8_t IDE; /*!< Specifies the type of identifier for the message that
- will be received. This parameter can be a value of
- @ref CAN_identifier_type */
-
- uint8_t RTR; /*!< Specifies the type of frame for the received message.
- This parameter can be a value of
- @ref CAN_remote_transmission_request */
-
- uint8_t DLC; /*!< Specifies the length of the frame that will be received.
- This parameter can be a value between 0 to 8 */
-
- uint8_t Data[8]; /*!< Contains the data to be received. It ranges from 0 to
- 0xFF. */
-
- uint8_t FMI; /*!< Specifies the index of the filter the message stored in
- the mailbox passes through. This parameter can be a
- value between 0 to 0xFF */
-} CanRxMsg;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup CAN_Exported_Constants
- * @{
- */
-
-/** @defgroup CAN_InitStatus
- * @{
- */
-
-#define CAN_InitStatus_Failed ((uint8_t)0x00) /*!< CAN initialization failed */
-#define CAN_InitStatus_Success ((uint8_t)0x01) /*!< CAN initialization OK */
-
-
-/* Legacy defines */
-#define CANINITFAILED CAN_InitStatus_Failed
-#define CANINITOK CAN_InitStatus_Success
-/**
- * @}
- */
-
-/** @defgroup CAN_operating_mode
- * @{
- */
-
-#define CAN_Mode_Normal ((uint8_t)0x00) /*!< normal mode */
-#define CAN_Mode_LoopBack ((uint8_t)0x01) /*!< loopback mode */
-#define CAN_Mode_Silent ((uint8_t)0x02) /*!< silent mode */
-#define CAN_Mode_Silent_LoopBack ((uint8_t)0x03) /*!< loopback combined with silent mode */
-
-#define IS_CAN_MODE(MODE) (((MODE) == CAN_Mode_Normal) || \
- ((MODE) == CAN_Mode_LoopBack)|| \
- ((MODE) == CAN_Mode_Silent) || \
- ((MODE) == CAN_Mode_Silent_LoopBack))
-/**
- * @}
- */
-
-
- /**
- * @defgroup CAN_operating_mode
- * @{
- */
-#define CAN_OperatingMode_Initialization ((uint8_t)0x00) /*!< Initialization mode */
-#define CAN_OperatingMode_Normal ((uint8_t)0x01) /*!< Normal mode */
-#define CAN_OperatingMode_Sleep ((uint8_t)0x02) /*!< sleep mode */
-
-
-#define IS_CAN_OPERATING_MODE(MODE) (((MODE) == CAN_OperatingMode_Initialization) ||\
- ((MODE) == CAN_OperatingMode_Normal)|| \
- ((MODE) == CAN_OperatingMode_Sleep))
-/**
- * @}
- */
-
-/**
- * @defgroup CAN_operating_mode_status
- * @{
- */
-
-#define CAN_ModeStatus_Failed ((uint8_t)0x00) /*!< CAN entering the specific mode failed */
-#define CAN_ModeStatus_Success ((uint8_t)!CAN_ModeStatus_Failed) /*!< CAN entering the specific mode Succeed */
-/**
- * @}
- */
-
-/** @defgroup CAN_synchronisation_jump_width
- * @{
- */
-#define CAN_SJW_1tq ((uint8_t)0x00) /*!< 1 time quantum */
-#define CAN_SJW_2tq ((uint8_t)0x01) /*!< 2 time quantum */
-#define CAN_SJW_3tq ((uint8_t)0x02) /*!< 3 time quantum */
-#define CAN_SJW_4tq ((uint8_t)0x03) /*!< 4 time quantum */
-
-#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1tq) || ((SJW) == CAN_SJW_2tq)|| \
- ((SJW) == CAN_SJW_3tq) || ((SJW) == CAN_SJW_4tq))
-/**
- * @}
- */
-
-/** @defgroup CAN_time_quantum_in_bit_segment_1
- * @{
- */
-#define CAN_BS1_1tq ((uint8_t)0x00) /*!< 1 time quantum */
-#define CAN_BS1_2tq ((uint8_t)0x01) /*!< 2 time quantum */
-#define CAN_BS1_3tq ((uint8_t)0x02) /*!< 3 time quantum */
-#define CAN_BS1_4tq ((uint8_t)0x03) /*!< 4 time quantum */
-#define CAN_BS1_5tq ((uint8_t)0x04) /*!< 5 time quantum */
-#define CAN_BS1_6tq ((uint8_t)0x05) /*!< 6 time quantum */
-#define CAN_BS1_7tq ((uint8_t)0x06) /*!< 7 time quantum */
-#define CAN_BS1_8tq ((uint8_t)0x07) /*!< 8 time quantum */
-#define CAN_BS1_9tq ((uint8_t)0x08) /*!< 9 time quantum */
-#define CAN_BS1_10tq ((uint8_t)0x09) /*!< 10 time quantum */
-#define CAN_BS1_11tq ((uint8_t)0x0A) /*!< 11 time quantum */
-#define CAN_BS1_12tq ((uint8_t)0x0B) /*!< 12 time quantum */
-#define CAN_BS1_13tq ((uint8_t)0x0C) /*!< 13 time quantum */
-#define CAN_BS1_14tq ((uint8_t)0x0D) /*!< 14 time quantum */
-#define CAN_BS1_15tq ((uint8_t)0x0E) /*!< 15 time quantum */
-#define CAN_BS1_16tq ((uint8_t)0x0F) /*!< 16 time quantum */
-
-#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16tq)
-/**
- * @}
- */
-
-/** @defgroup CAN_time_quantum_in_bit_segment_2
- * @{
- */
-#define CAN_BS2_1tq ((uint8_t)0x00) /*!< 1 time quantum */
-#define CAN_BS2_2tq ((uint8_t)0x01) /*!< 2 time quantum */
-#define CAN_BS2_3tq ((uint8_t)0x02) /*!< 3 time quantum */
-#define CAN_BS2_4tq ((uint8_t)0x03) /*!< 4 time quantum */
-#define CAN_BS2_5tq ((uint8_t)0x04) /*!< 5 time quantum */
-#define CAN_BS2_6tq ((uint8_t)0x05) /*!< 6 time quantum */
-#define CAN_BS2_7tq ((uint8_t)0x06) /*!< 7 time quantum */
-#define CAN_BS2_8tq ((uint8_t)0x07) /*!< 8 time quantum */
-
-#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8tq)
-/**
- * @}
- */
-
-/** @defgroup CAN_clock_prescaler
- * @{
- */
-#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024))
-/**
- * @}
- */
-
-/** @defgroup CAN_filter_number
- * @{
- */
-#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27)
-/**
- * @}
- */
-
-/** @defgroup CAN_filter_mode
- * @{
- */
-#define CAN_FilterMode_IdMask ((uint8_t)0x00) /*!< identifier/mask mode */
-#define CAN_FilterMode_IdList ((uint8_t)0x01) /*!< identifier list mode */
-
-#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FilterMode_IdMask) || \
- ((MODE) == CAN_FilterMode_IdList))
-/**
- * @}
- */
-
-/** @defgroup CAN_filter_scale
- * @{
- */
-#define CAN_FilterScale_16bit ((uint8_t)0x00) /*!< Two 16-bit filters */
-#define CAN_FilterScale_32bit ((uint8_t)0x01) /*!< One 32-bit filter */
-
-#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FilterScale_16bit) || \
- ((SCALE) == CAN_FilterScale_32bit))
-/**
- * @}
- */
-
-/** @defgroup CAN_filter_FIFO
- * @{
- */
-#define CAN_Filter_FIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */
-#define CAN_Filter_FIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */
-#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FilterFIFO0) || \
- ((FIFO) == CAN_FilterFIFO1))
-
-/* Legacy defines */
-#define CAN_FilterFIFO0 CAN_Filter_FIFO0
-#define CAN_FilterFIFO1 CAN_Filter_FIFO1
-/**
- * @}
- */
-
-/** @defgroup CAN_Start_bank_filter_for_slave_CAN
- * @{
- */
-#define IS_CAN_BANKNUMBER(BANKNUMBER) (((BANKNUMBER) >= 1) && ((BANKNUMBER) <= 27))
-/**
- * @}
- */
-
-/** @defgroup CAN_Tx
- * @{
- */
-#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))
-#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF))
-#define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF))
-#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08))
-/**
- * @}
- */
-
-/** @defgroup CAN_identifier_type
- * @{
- */
-#define CAN_Id_Standard ((uint32_t)0x00000000) /*!< Standard Id */
-#define CAN_Id_Extended ((uint32_t)0x00000004) /*!< Extended Id */
-#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_Id_Standard) || \
- ((IDTYPE) == CAN_Id_Extended))
-
-/* Legacy defines */
-#define CAN_ID_STD CAN_Id_Standard
-#define CAN_ID_EXT CAN_Id_Extended
-/**
- * @}
- */
-
-/** @defgroup CAN_remote_transmission_request
- * @{
- */
-#define CAN_RTR_Data ((uint32_t)0x00000000) /*!< Data frame */
-#define CAN_RTR_Remote ((uint32_t)0x00000002) /*!< Remote frame */
-#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_Data) || ((RTR) == CAN_RTR_Remote))
-
-/* Legacy defines */
-#define CAN_RTR_DATA CAN_RTR_Data
-#define CAN_RTR_REMOTE CAN_RTR_Remote
-/**
- * @}
- */
-
-/** @defgroup CAN_transmit_constants
- * @{
- */
-#define CAN_TxStatus_Failed ((uint8_t)0x00)/*!< CAN transmission failed */
-#define CAN_TxStatus_Ok ((uint8_t)0x01) /*!< CAN transmission succeeded */
-#define CAN_TxStatus_Pending ((uint8_t)0x02) /*!< CAN transmission pending */
-#define CAN_TxStatus_NoMailBox ((uint8_t)0x04) /*!< CAN cell did not provide
- an empty mailbox */
-/* Legacy defines */
-#define CANTXFAILED CAN_TxStatus_Failed
-#define CANTXOK CAN_TxStatus_Ok
-#define CANTXPENDING CAN_TxStatus_Pending
-#define CAN_NO_MB CAN_TxStatus_NoMailBox
-/**
- * @}
- */
-
-/** @defgroup CAN_receive_FIFO_number_constants
- * @{
- */
-#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */
-#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */
-
-#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))
-/**
- * @}
- */
-
-/** @defgroup CAN_sleep_constants
- * @{
- */
-#define CAN_Sleep_Failed ((uint8_t)0x00) /*!< CAN did not enter the sleep mode */
-#define CAN_Sleep_Ok ((uint8_t)0x01) /*!< CAN entered the sleep mode */
-
-/* Legacy defines */
-#define CANSLEEPFAILED CAN_Sleep_Failed
-#define CANSLEEPOK CAN_Sleep_Ok
-/**
- * @}
- */
-
-/** @defgroup CAN_wake_up_constants
- * @{
- */
-#define CAN_WakeUp_Failed ((uint8_t)0x00) /*!< CAN did not leave the sleep mode */
-#define CAN_WakeUp_Ok ((uint8_t)0x01) /*!< CAN leaved the sleep mode */
-
-/* Legacy defines */
-#define CANWAKEUPFAILED CAN_WakeUp_Failed
-#define CANWAKEUPOK CAN_WakeUp_Ok
-/**
- * @}
- */
-
-/**
- * @defgroup CAN_Error_Code_constants
- * @{
- */
-#define CAN_ErrorCode_NoErr ((uint8_t)0x00) /*!< No Error */
-#define CAN_ErrorCode_StuffErr ((uint8_t)0x10) /*!< Stuff Error */
-#define CAN_ErrorCode_FormErr ((uint8_t)0x20) /*!< Form Error */
-#define CAN_ErrorCode_ACKErr ((uint8_t)0x30) /*!< Acknowledgment Error */
-#define CAN_ErrorCode_BitRecessiveErr ((uint8_t)0x40) /*!< Bit Recessive Error */
-#define CAN_ErrorCode_BitDominantErr ((uint8_t)0x50) /*!< Bit Dominant Error */
-#define CAN_ErrorCode_CRCErr ((uint8_t)0x60) /*!< CRC Error */
-#define CAN_ErrorCode_SoftwareSetErr ((uint8_t)0x70) /*!< Software Set Error */
-/**
- * @}
- */
-
-/** @defgroup CAN_flags
- * @{
- */
-/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus()
- and CAN_ClearFlag() functions. */
-/* If the flag is 0x1XXXXXXX, it means that it can only be used with
- CAN_GetFlagStatus() function. */
-
-/* Transmit Flags */
-#define CAN_FLAG_RQCP0 ((uint32_t)0x38000001) /*!< Request MailBox0 Flag */
-#define CAN_FLAG_RQCP1 ((uint32_t)0x38000100) /*!< Request MailBox1 Flag */
-#define CAN_FLAG_RQCP2 ((uint32_t)0x38010000) /*!< Request MailBox2 Flag */
-
-/* Receive Flags */
-#define CAN_FLAG_FMP0 ((uint32_t)0x12000003) /*!< FIFO 0 Message Pending Flag */
-#define CAN_FLAG_FF0 ((uint32_t)0x32000008) /*!< FIFO 0 Full Flag */
-#define CAN_FLAG_FOV0 ((uint32_t)0x32000010) /*!< FIFO 0 Overrun Flag */
-#define CAN_FLAG_FMP1 ((uint32_t)0x14000003) /*!< FIFO 1 Message Pending Flag */
-#define CAN_FLAG_FF1 ((uint32_t)0x34000008) /*!< FIFO 1 Full Flag */
-#define CAN_FLAG_FOV1 ((uint32_t)0x34000010) /*!< FIFO 1 Overrun Flag */
-
-/* Operating Mode Flags */
-#define CAN_FLAG_WKU ((uint32_t)0x31000008) /*!< Wake up Flag */
-#define CAN_FLAG_SLAK ((uint32_t)0x31000012) /*!< Sleep acknowledge Flag */
-/* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible.
- In this case the SLAK bit can be polled.*/
-
-/* Error Flags */
-#define CAN_FLAG_EWG ((uint32_t)0x10F00001) /*!< Error Warning Flag */
-#define CAN_FLAG_EPV ((uint32_t)0x10F00002) /*!< Error Passive Flag */
-#define CAN_FLAG_BOF ((uint32_t)0x10F00004) /*!< Bus-Off Flag */
-#define CAN_FLAG_LEC ((uint32_t)0x30F00070) /*!< Last error code Flag */
-
-#define IS_CAN_GET_FLAG(FLAG) (((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_BOF) || \
- ((FLAG) == CAN_FLAG_EPV) || ((FLAG) == CAN_FLAG_EWG) || \
- ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_FOV0) || \
- ((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FMP0) || \
- ((FLAG) == CAN_FLAG_FOV1) || ((FLAG) == CAN_FLAG_FF1) || \
- ((FLAG) == CAN_FLAG_FMP1) || ((FLAG) == CAN_FLAG_RQCP2) || \
- ((FLAG) == CAN_FLAG_RQCP1)|| ((FLAG) == CAN_FLAG_RQCP0) || \
- ((FLAG) == CAN_FLAG_SLAK ))
-
-#define IS_CAN_CLEAR_FLAG(FLAG)(((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_RQCP2) || \
- ((FLAG) == CAN_FLAG_RQCP1) || ((FLAG) == CAN_FLAG_RQCP0) || \
- ((FLAG) == CAN_FLAG_FF0) || ((FLAG) == CAN_FLAG_FOV0) ||\
- ((FLAG) == CAN_FLAG_FF1) || ((FLAG) == CAN_FLAG_FOV1) || \
- ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_SLAK))
-/**
- * @}
- */
-
-
-/** @defgroup CAN_interrupts
- * @{
- */
-#define CAN_IT_TME ((uint32_t)0x00000001) /*!< Transmit mailbox empty Interrupt*/
-
-/* Receive Interrupts */
-#define CAN_IT_FMP0 ((uint32_t)0x00000002) /*!< FIFO 0 message pending Interrupt*/
-#define CAN_IT_FF0 ((uint32_t)0x00000004) /*!< FIFO 0 full Interrupt*/
-#define CAN_IT_FOV0 ((uint32_t)0x00000008) /*!< FIFO 0 overrun Interrupt*/
-#define CAN_IT_FMP1 ((uint32_t)0x00000010) /*!< FIFO 1 message pending Interrupt*/
-#define CAN_IT_FF1 ((uint32_t)0x00000020) /*!< FIFO 1 full Interrupt*/
-#define CAN_IT_FOV1 ((uint32_t)0x00000040) /*!< FIFO 1 overrun Interrupt*/
-
-/* Operating Mode Interrupts */
-#define CAN_IT_WKU ((uint32_t)0x00010000) /*!< Wake-up Interrupt*/
-#define CAN_IT_SLK ((uint32_t)0x00020000) /*!< Sleep acknowledge Interrupt*/
-
-/* Error Interrupts */
-#define CAN_IT_EWG ((uint32_t)0x00000100) /*!< Error warning Interrupt*/
-#define CAN_IT_EPV ((uint32_t)0x00000200) /*!< Error passive Interrupt*/
-#define CAN_IT_BOF ((uint32_t)0x00000400) /*!< Bus-off Interrupt*/
-#define CAN_IT_LEC ((uint32_t)0x00000800) /*!< Last error code Interrupt*/
-#define CAN_IT_ERR ((uint32_t)0x00008000) /*!< Error Interrupt*/
-
-/* Flags named as Interrupts : kept only for FW compatibility */
-#define CAN_IT_RQCP0 CAN_IT_TME
-#define CAN_IT_RQCP1 CAN_IT_TME
-#define CAN_IT_RQCP2 CAN_IT_TME
-
-
-#define IS_CAN_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0) ||\
- ((IT) == CAN_IT_FF0) || ((IT) == CAN_IT_FOV0) ||\
- ((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1) ||\
- ((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG) ||\
- ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\
- ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\
- ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))
-
-#define IS_CAN_CLEAR_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FF0) ||\
- ((IT) == CAN_IT_FOV0)|| ((IT) == CAN_IT_FF1) ||\
- ((IT) == CAN_IT_FOV1)|| ((IT) == CAN_IT_EWG) ||\
- ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF) ||\
- ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR) ||\
- ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/* Function used to set the CAN configuration to the default reset state *****/
-void CAN_DeInit(CAN_TypeDef* CANx);
-
-/* Initialization and Configuration functions *********************************/
-uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct);
-void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct);
-void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct);
-void CAN_SlaveStartBank(uint8_t CAN_BankNumber);
-void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState);
-void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState);
-
-/* CAN Frames Transmission functions ******************************************/
-uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage);
-uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox);
-void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox);
-
-/* CAN Frames Reception functions *********************************************/
-void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage);
-void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber);
-uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber);
-
-/* Operation modes functions **************************************************/
-uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode);
-uint8_t CAN_Sleep(CAN_TypeDef* CANx);
-uint8_t CAN_WakeUp(CAN_TypeDef* CANx);
-
-/* CAN Bus Error management functions *****************************************/
-uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx);
-uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx);
-uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx);
-
-/* Interrupts and flags management functions **********************************/
-void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState);
-FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG);
-void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG);
-ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT);
-void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F0xx_CAN_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_cec.h b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_cec.h
deleted file mode 100644
index 29f06a68440c631bd4abb858aec2f337823a50fc..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_cec.h
+++ /dev/null
@@ -1,300 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f0xx_cec.h
- * @author MCD Application Team
- * @version V1.3.0
- * @date 16-January-2014
- * @brief This file contains all the functions prototypes for the CEC firmware
- * library, applicable only for STM32F051, STM32F042 and STM32F072 devices.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F0XX_CEC_H
-#define __STM32F0XX_CEC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup CEC
- * @{
- */
-/* Exported types ------------------------------------------------------------*/
-
-/**
- * @brief CEC Init structure definition
- */
-typedef struct
-{
- uint32_t CEC_SignalFreeTime; /*!< Specifies the CEC Signal Free Time configuration.
- This parameter can be a value of @ref CEC_Signal_Free_Time */
- uint32_t CEC_RxTolerance; /*!< Specifies the CEC Reception Tolerance.
- This parameter can be a value of @ref CEC_RxTolerance */
- uint32_t CEC_StopReception; /*!< Specifies the CEC Stop Reception.
- This parameter can be a value of @ref CEC_Stop_Reception */
- uint32_t CEC_BitRisingError; /*!< Specifies the CEC Bit Rising Error generation.
- This parameter can be a value of @ref CEC_Bit_Rising_Error_Generation */
- uint32_t CEC_LongBitPeriodError; /*!< Specifies the CEC Long Bit Error generation.
- This parameter can be a value of @ref CEC_Long_Bit_Error_Generation */
- uint32_t CEC_BRDNoGen; /*!< Specifies the CEC Broadcast Error generation.
- This parameter can be a value of @ref CEC_BDR_No_Gen */
- uint32_t CEC_SFTOption; /*!< Specifies the CEC Signal Free Time option.
- This parameter can be a value of @ref CEC_SFT_Option */
-
-}CEC_InitTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup CEC_Exported_Constants
- * @{
- */
-
-/** @defgroup CEC_Signal_Free_Time
- * @{
- */
-#define CEC_SignalFreeTime_Standard ((uint32_t)0x00000000) /*!< CEC Signal Free Time Standard */
-#define CEC_SignalFreeTime_1T ((uint32_t)0x00000001) /*!< CEC 1.5 nominal data bit periods */
-#define CEC_SignalFreeTime_2T ((uint32_t)0x00000002) /*!< CEC 2.5 nominal data bit periods */
-#define CEC_SignalFreeTime_3T ((uint32_t)0x00000003) /*!< CEC 3.5 nominal data bit periods */
-#define CEC_SignalFreeTime_4T ((uint32_t)0x00000004) /*!< CEC 4.5 nominal data bit periods */
-#define CEC_SignalFreeTime_5T ((uint32_t)0x00000005) /*!< CEC 5.5 nominal data bit periods */
-#define CEC_SignalFreeTime_6T ((uint32_t)0x00000006) /*!< CEC 6.5 nominal data bit periods */
-#define CEC_SignalFreeTime_7T ((uint32_t)0x00000007) /*!< CEC 7.5 nominal data bit periods */
-
-#define IS_CEC_SIGNAL_FREE_TIME(TIME) (((TIME) == CEC_SignalFreeTime_Standard) || \
- ((TIME) == CEC_SignalFreeTime_1T)|| \
- ((TIME) == CEC_SignalFreeTime_2T)|| \
- ((TIME) == CEC_SignalFreeTime_3T)|| \
- ((TIME) == CEC_SignalFreeTime_4T)|| \
- ((TIME) == CEC_SignalFreeTime_5T)|| \
- ((TIME) == CEC_SignalFreeTime_6T)|| \
- ((TIME) == CEC_SignalFreeTime_7T))
-/**
- * @}
- */
-
-/** @defgroup CEC_RxTolerance
- * @{
- */
-#define CEC_RxTolerance_Standard ((uint32_t)0x00000000) /*!< Standard Tolerance Margin */
-#define CEC_RxTolerance_Extended CEC_CFGR_RXTOL /*!< Extended Tolerance Margin */
-
-#define IS_CEC_RX_TOLERANCE(TOLERANCE) (((TOLERANCE) == CEC_RxTolerance_Standard) || \
- ((TOLERANCE) == CEC_RxTolerance_Extended))
-/**
- * @}
- */
-
-/** @defgroup CEC_Stop_Reception
- * @{
- */
-#define CEC_StopReception_Off ((uint32_t)0x00000000) /*!< No RX Stop on bit Rising Error (BRE) */
-#define CEC_StopReception_On CEC_CFGR_BRESTP /*!< RX Stop on bit Rising Error (BRE) */
-
-#define IS_CEC_STOP_RECEPTION(RECEPTION) (((RECEPTION) == CEC_StopReception_On) || \
- ((RECEPTION) == CEC_StopReception_Off))
-/**
- * @}
- */
-
-/** @defgroup CEC_Bit_Rising_Error_Generation
- * @{
- */
-#define CEC_BitRisingError_Off ((uint32_t)0x00000000) /*!< Bit Rising Error generation turned Off */
-#define CEC_BitRisingError_On CEC_CFGR_BREGEN /*!< Bit Rising Error generation turned On */
-
-#define IS_CEC_BIT_RISING_ERROR(ERROR) (((ERROR) == CEC_BitRisingError_Off) || \
- ((ERROR) == CEC_BitRisingError_On))
-/**
- * @}
- */
-
-/** @defgroup CEC_Long_Bit_Error_Generation
- * @{
- */
-#define CEC_LongBitPeriodError_Off ((uint32_t)0x00000000) /*!< Long Bit Period Error generation turned Off */
-#define CEC_LongBitPeriodError_On CEC_CFGR_LREGEN /*!< Long Bit Period Error generation turned On */
-
-#define IS_CEC_LONG_BIT_PERIOD_ERROR(ERROR) (((ERROR) == CEC_LongBitPeriodError_Off) || \
- ((ERROR) == CEC_LongBitPeriodError_On))
-/**
- * @}
- */
-
-/** @defgroup CEC_BDR_No_Gen
- * @{
- */
-
-#define CEC_BRDNoGen_Off ((uint32_t)0x00000000) /*!< Broadcast Bit Rising Error generation turned Off */
-#define CEC_BRDNoGen_On CEC_CFGR_BRDNOGEN /*!< Broadcast Bit Rising Error generation turned On */
-
-#define IS_CEC_BDR_NO_GEN_ERROR(ERROR) (((ERROR) == CEC_BRDNoGen_Off) || \
- ((ERROR) == CEC_BRDNoGen_On))
-/**
- * @}
- */
-
-/** @defgroup CEC_SFT_Option
- * @{
- */
-#define CEC_SFTOption_Off ((uint32_t)0x00000000) /*!< SFT option turned Off */
-#define CEC_SFTOption_On CEC_CFGR_SFTOPT /*!< SFT option turned On */
-
-#define IS_CEC_SFT_OPTION(OPTION) (((OPTION) == CEC_SFTOption_Off) || \
- ((OPTION) == CEC_SFTOption_On))
-/**
- * @}
- */
-
-/** @defgroup CEC_Own_Address
- * @{
- */
-#define IS_CEC_ADDRESS(ADDRESS) ((ADDRESS) < 0x10)
-
-/**
- * @}
- */
-
-/** @defgroup CEC_Interrupt_Configuration_definition
- * @{
- */
-#define CEC_IT_TXACKE CEC_IER_TXACKEIE
-#define CEC_IT_TXERR CEC_IER_TXERRIE
-#define CEC_IT_TXUDR CEC_IER_TXUDRIE
-#define CEC_IT_TXEND CEC_IER_TXENDIE
-#define CEC_IT_TXBR CEC_IER_TXBRIE
-#define CEC_IT_ARBLST CEC_IER_ARBLSTIE
-#define CEC_IT_RXACKE CEC_IER_RXACKEIE
-#define CEC_IT_LBPE CEC_IER_LBPEIE
-#define CEC_IT_SBPE CEC_IER_SBPEIE
-#define CEC_IT_BRE CEC_IER_BREIEIE
-#define CEC_IT_RXOVR CEC_IER_RXOVRIE
-#define CEC_IT_RXEND CEC_IER_RXENDIE
-#define CEC_IT_RXBR CEC_IER_RXBRIE
-
-#define IS_CEC_IT(IT) ((((IT) & (uint32_t)0xFFFFE000) == 0x00) && ((IT) != 0x00))
-
-#define IS_CEC_GET_IT(IT) (((IT) == CEC_IT_TXACKE) || \
- ((IT) == CEC_IT_TXERR)|| \
- ((IT) == CEC_IT_TXUDR)|| \
- ((IT) == CEC_IT_TXEND)|| \
- ((IT) == CEC_IT_TXBR)|| \
- ((IT) == CEC_IT_ARBLST)|| \
- ((IT) == CEC_IT_RXACKE)|| \
- ((IT) == CEC_IT_LBPE)|| \
- ((IT) == CEC_IT_SBPE)|| \
- ((IT) == CEC_IT_BRE)|| \
- ((IT) == CEC_IT_RXOVR)|| \
- ((IT) == CEC_IT_RXEND)|| \
- ((IT) == CEC_IT_RXBR))
-/**
- * @}
- */
-
-/** @defgroup CEC_ISR_register_flags_definition
- * @{
- */
-#define CEC_FLAG_TXACKE CEC_ISR_TXACKE
-#define CEC_FLAG_TXERR CEC_ISR_TXERR
-#define CEC_FLAG_TXUDR CEC_ISR_TXUDR
-#define CEC_FLAG_TXEND CEC_ISR_TXEND
-#define CEC_FLAG_TXBR CEC_ISR_TXBR
-#define CEC_FLAG_ARBLST CEC_ISR_ARBLST
-#define CEC_FLAG_RXACKE CEC_ISR_RXACKE
-#define CEC_FLAG_LBPE CEC_ISR_LBPE
-#define CEC_FLAG_SBPE CEC_ISR_SBPE
-#define CEC_FLAG_BRE CEC_ISR_BRE
-#define CEC_FLAG_RXOVR CEC_ISR_RXOVR
-#define CEC_FLAG_RXEND CEC_ISR_RXEND
-#define CEC_FLAG_RXBR CEC_ISR_RXBR
-
-#define IS_CEC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFE000) == 0x00) && ((FLAG) != 0x00))
-
-#define IS_CEC_GET_FLAG(FLAG) (((FLAG) == CEC_FLAG_TXACKE) || \
- ((FLAG) == CEC_FLAG_TXERR)|| \
- ((FLAG) == CEC_FLAG_TXUDR)|| \
- ((FLAG) == CEC_FLAG_TXEND)|| \
- ((FLAG) == CEC_FLAG_TXBR)|| \
- ((FLAG) == CEC_FLAG_ARBLST)|| \
- ((FLAG) == CEC_FLAG_RXACKE)|| \
- ((FLAG) == CEC_FLAG_LBPE)|| \
- ((FLAG) == CEC_FLAG_SBPE)|| \
- ((FLAG) == CEC_FLAG_BRE)|| \
- ((FLAG) == CEC_FLAG_RXOVR)|| \
- ((FLAG) == CEC_FLAG_RXEND)|| \
- ((FLAG) == CEC_FLAG_RXBR))
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-/* Function used to set the CEC configuration to the default reset state *****/
-void CEC_DeInit(void);
-
-/* CEC_Initialization and Configuration functions *****************************/
-void CEC_Init(CEC_InitTypeDef* CEC_InitStruct);
-void CEC_StructInit(CEC_InitTypeDef* CEC_InitStruct);
-void CEC_Cmd(FunctionalState NewState);
-void CEC_ListenModeCmd(FunctionalState NewState);
-void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress);
-void CEC_OwnAddressClear(void);
-
-/* CEC_Data transfers functions ***********************************************/
-void CEC_SendData(uint8_t Data);
-uint8_t CEC_ReceiveData(void);
-void CEC_StartOfMessage(void);
-void CEC_EndOfMessage(void);
-
-/* CEC_Interrupts and flags management functions ******************************/
-void CEC_ITConfig(uint16_t CEC_IT, FunctionalState NewState);
-FlagStatus CEC_GetFlagStatus(uint16_t CEC_FLAG);
-void CEC_ClearFlag(uint32_t CEC_FLAG);
-ITStatus CEC_GetITStatus(uint16_t CEC_IT);
-void CEC_ClearITPendingBit(uint16_t CEC_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F0XX_CEC_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_comp.h b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_comp.h
deleted file mode 100644
index da8b152a5d9c95da7c71dc134ab709baec74dc34..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_comp.h
+++ /dev/null
@@ -1,245 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f0xx_comp.h
- * @author MCD Application Team
- * @version V1.3.0
- * @date 16-January-2014
- * @brief This file contains all the functions prototypes for the COMP firmware
- * library, applicable only for STM32F051 and STM32F072 devices.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F0XX_COMP_H
-#define __STM32F0XX_COMP_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup COMP
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/**
- * @brief COMP Init structure definition
- */
-
-typedef struct
-{
-
- uint32_t COMP_InvertingInput; /*!< Selects the inverting input of the comparator.
- This parameter can be a value of @ref COMP_InvertingInput */
-
- uint32_t COMP_Output; /*!< Selects the output redirection of the comparator.
- This parameter can be a value of @ref COMP_Output */
-
- uint32_t COMP_OutputPol; /*!< Selects the output polarity of the comparator.
- This parameter can be a value of @ref COMP_OutputPolarity */
-
- uint32_t COMP_Hysteresis; /*!< Selects the hysteresis voltage of the comparator.
- This parameter can be a value of @ref COMP_Hysteresis */
-
- uint32_t COMP_Mode; /*!< Selects the operating mode of the comparator
- and allows to adjust the speed/consumption.
- This parameter can be a value of @ref COMP_Mode */
-
-}COMP_InitTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup COMP_Exported_Constants
- * @{
- */
-
-/** @defgroup COMP_Selection
- * @{
- */
-
-#define COMP_Selection_COMP1 ((uint32_t)0x00000000) /*!< COMP1 Selection */
-#define COMP_Selection_COMP2 ((uint32_t)0x00000010) /*!< COMP2 Selection */
-
-#define IS_COMP_ALL_PERIPH(PERIPH) (((PERIPH) == COMP_Selection_COMP1) || \
- ((PERIPH) == COMP_Selection_COMP2))
-
-/**
- * @}
- */
-
-/** @defgroup COMP_InvertingInput
- * @{
- */
-
-#define COMP_InvertingInput_1_4VREFINT ((uint32_t)0x00000000) /*!< 1/4 VREFINT connected to comparator inverting input */
-#define COMP_InvertingInput_1_2VREFINT COMP_CSR_COMP1INSEL_0 /*!< 1/2 VREFINT connected to comparator inverting input */
-#define COMP_InvertingInput_3_4VREFINT COMP_CSR_COMP1INSEL_1 /*!< 3/4 VREFINT connected to comparator inverting input */
-#define COMP_InvertingInput_VREFINT ((uint32_t)0x00000030) /*!< VREFINT connected to comparator inverting input */
-#define COMP_InvertingInput_DAC1 COMP_CSR_COMP1INSEL_2 /*!< DAC1_OUT (PA4) connected to comparator inverting input */
-#define COMP_InvertingInput_DAC2 ((uint32_t)0x00000050) /*!< DAC2_OUT (PA5) connected to comparator inverting input, applicable only for STM32F072 devices */
-#define COMP_InvertingInput_IO ((uint32_t)0x00000060) /*!< I/O (PA0 for COMP1 and PA2 for COMP2) connected to comparator inverting input */
-
-#define IS_COMP_INVERTING_INPUT(INPUT) (((INPUT) == COMP_InvertingInput_1_4VREFINT) || \
- ((INPUT) == COMP_InvertingInput_1_2VREFINT) || \
- ((INPUT) == COMP_InvertingInput_3_4VREFINT) || \
- ((INPUT) == COMP_InvertingInput_VREFINT) || \
- ((INPUT) == COMP_InvertingInput_DAC1) || \
- ((INPUT) == COMP_InvertingInput_DAC2) || \
- ((INPUT) == COMP_InvertingInput_1_4VREFINT) || \
- ((INPUT) == COMP_InvertingInput_IO))
-/**
- * @}
- */
-
-/** @defgroup COMP_Output
- * @{
- */
-
-#define COMP_Output_None ((uint32_t)0x00000000) /*!< COMP output isn't connected to other peripherals */
-#define COMP_Output_TIM1BKIN COMP_CSR_COMP1OUTSEL_0 /*!< COMP output connected to TIM1 Break Input (BKIN) */
-#define COMP_Output_TIM1IC1 COMP_CSR_COMP1OUTSEL_1 /*!< COMP output connected to TIM1 Input Capture 1 */
-#define COMP_Output_TIM1OCREFCLR ((uint32_t)0x00000300) /*!< COMP output connected to TIM1 OCREF Clear */
-#define COMP_Output_TIM2IC4 COMP_CSR_COMP1OUTSEL_2 /*!< COMP output connected to TIM2 Input Capture 4 */
-#define COMP_Output_TIM2OCREFCLR ((uint32_t)0x00000500) /*!< COMP output connected to TIM2 OCREF Clear */
-#define COMP_Output_TIM3IC1 ((uint32_t)0x00000600) /*!< COMP output connected to TIM3 Input Capture 1 */
-#define COMP_Output_TIM3OCREFCLR COMP_CSR_COMP1OUTSEL /*!< COMP output connected to TIM3 OCREF Clear */
-
-
-#define IS_COMP_OUTPUT(OUTPUT) (((OUTPUT) == COMP_Output_None) || \
- ((OUTPUT) == COMP_Output_TIM1BKIN) || \
- ((OUTPUT) == COMP_Output_TIM1IC1) || \
- ((OUTPUT) == COMP_Output_TIM1OCREFCLR) || \
- ((OUTPUT) == COMP_Output_TIM2IC4) || \
- ((OUTPUT) == COMP_Output_TIM2OCREFCLR) || \
- ((OUTPUT) == COMP_Output_TIM3IC1) || \
- ((OUTPUT) == COMP_Output_TIM3OCREFCLR))
-/**
- * @}
- */
-
-/** @defgroup COMP_OutputPolarity
- * @{
- */
-#define COMP_OutputPol_NonInverted ((uint32_t)0x00000000) /*!< COMP output on GPIO isn't inverted */
-#define COMP_OutputPol_Inverted COMP_CSR_COMP1POL /*!< COMP output on GPIO is inverted */
-
-#define IS_COMP_OUTPUT_POL(POL) (((POL) == COMP_OutputPol_NonInverted) || \
- ((POL) == COMP_OutputPol_Inverted))
-
-/**
- * @}
- */
-
-/** @defgroup COMP_Hysteresis
- * @{
- */
-/* Please refer to the electrical characteristics in the device datasheet for
- the hysteresis level */
-#define COMP_Hysteresis_No 0x00000000 /*!< No hysteresis */
-#define COMP_Hysteresis_Low COMP_CSR_COMP1HYST_0 /*!< Hysteresis level low */
-#define COMP_Hysteresis_Medium COMP_CSR_COMP1HYST_1 /*!< Hysteresis level medium */
-#define COMP_Hysteresis_High COMP_CSR_COMP1HYST /*!< Hysteresis level high */
-
-#define IS_COMP_HYSTERESIS(HYSTERESIS) (((HYSTERESIS) == COMP_Hysteresis_No) || \
- ((HYSTERESIS) == COMP_Hysteresis_Low) || \
- ((HYSTERESIS) == COMP_Hysteresis_Medium) || \
- ((HYSTERESIS) == COMP_Hysteresis_High))
-/**
- * @}
- */
-
-/** @defgroup COMP_Mode
- * @{
- */
-/* Please refer to the electrical characteristics in the device datasheet for
- the power consumption values */
-#define COMP_Mode_HighSpeed 0x00000000 /*!< High Speed */
-#define COMP_Mode_MediumSpeed COMP_CSR_COMP1MODE_0 /*!< Medium Speed */
-#define COMP_Mode_LowPower COMP_CSR_COMP1MODE_1 /*!< Low power mode */
-#define COMP_Mode_UltraLowPower COMP_CSR_COMP1MODE /*!< Ultra-low power mode */
-
-#define IS_COMP_MODE(MODE) (((MODE) == COMP_Mode_UltraLowPower) || \
- ((MODE) == COMP_Mode_LowPower) || \
- ((MODE) == COMP_Mode_MediumSpeed) || \
- ((MODE) == COMP_Mode_HighSpeed))
-/**
- * @}
- */
-
-/** @defgroup COMP_OutputLevel
- * @{
- */
-/* When output polarity is not inverted, comparator output is high when
- the non-inverting input is at a higher voltage than the inverting input */
-#define COMP_OutputLevel_High COMP_CSR_COMP1OUT
-/* When output polarity is not inverted, comparator output is low when
- the non-inverting input is at a lower voltage than the inverting input*/
-#define COMP_OutputLevel_Low ((uint32_t)0x00000000)
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-/* Function used to set the COMP configuration to the default reset state ****/
-void COMP_DeInit(void);
-
-/* Initialization and Configuration functions *********************************/
-void COMP_Init(uint32_t COMP_Selection, COMP_InitTypeDef* COMP_InitStruct);
-void COMP_StructInit(COMP_InitTypeDef* COMP_InitStruct);
-void COMP_Cmd(uint32_t COMP_Selection, FunctionalState NewState);
-void COMP_SwitchCmd(FunctionalState NewState);
-uint32_t COMP_GetOutputLevel(uint32_t COMP_Selection);
-
-/* Window mode control function ***********************************************/
-void COMP_WindowCmd(FunctionalState NewState);
-
-/* COMP configuration locking function ****************************************/
-void COMP_LockConfig(uint32_t COMP_Selection);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F0XX_COMP_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_crc.h b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_crc.h
deleted file mode 100644
index ef1d4369ab56d6d4ad666ebdc2a7e969dbc3d6b2..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_crc.h
+++ /dev/null
@@ -1,122 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f0xx_crc.h
- * @author MCD Application Team
- * @version V1.3.0
- * @date 16-January-2014
- * @brief This file contains all the functions prototypes for the CRC firmware
- * library.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F0XX_CRC_H
-#define __STM32F0XX_CRC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/*!< Includes ----------------------------------------------------------------*/
-#include "stm32f0xx.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup CRC
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup CRC_ReverseInputData
- * @{
- */
-#define CRC_ReverseInputData_No ((uint32_t)0x00000000) /*!< No reverse operation of Input Data */
-#define CRC_ReverseInputData_8bits CRC_CR_REV_IN_0 /*!< Reverse operation of Input Data on 8 bits */
-#define CRC_ReverseInputData_16bits CRC_CR_REV_IN_1 /*!< Reverse operation of Input Data on 16 bits */
-#define CRC_ReverseInputData_32bits CRC_CR_REV_IN /*!< Reverse operation of Input Data on 32 bits */
-
-#define IS_CRC_REVERSE_INPUT_DATA(DATA) (((DATA) == CRC_ReverseInputData_No) || \
- ((DATA) == CRC_ReverseInputData_8bits) || \
- ((DATA) == CRC_ReverseInputData_16bits) || \
- ((DATA) == CRC_ReverseInputData_32bits))
-
-/**
- * @}
- */
-
-/** @defgroup CRC_PolynomialSize
- * @brief Only applicable for STM32F042 and STM32F072 devices
- * @{
- */
-#define CRC_PolSize_7 CRC_CR_POLSIZE /*!< 7-bit polynomial for CRC calculation */
-#define CRC_PolSize_8 CRC_CR_POLSIZE_1 /*!< 8-bit polynomial for CRC calculation */
-#define CRC_PolSize_16 CRC_CR_POLSIZE_0 /*!< 16-bit polynomial for CRC calculation */
-#define CRC_PolSize_32 ((uint32_t)0x00000000)/*!< 32-bit polynomial for CRC calculation */
-
-#define IS_CRC_POL_SIZE(SIZE) (((SIZE) == CRC_PolSize_7) || \
- ((SIZE) == CRC_PolSize_8) || \
- ((SIZE) == CRC_PolSize_16) || \
- ((SIZE) == CRC_PolSize_32))
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-/* Configuration of the CRC computation unit **********************************/
-void CRC_DeInit(void);
-void CRC_ResetDR(void);
-void CRC_PolynomialSizeSelect(uint32_t CRC_PolSize); /*!< Only applicable for STM32F042 and STM32F072 devices */
-void CRC_ReverseInputDataSelect(uint32_t CRC_ReverseInputData);
-void CRC_ReverseOutputDataCmd(FunctionalState NewState);
-void CRC_SetInitRegister(uint32_t CRC_InitValue);
-void CRC_SetPolynomial(uint32_t CRC_Pol); /*!< Only applicable for STM32F042 and STM32F072 devices */
-
-/* CRC computation ************************************************************/
-uint32_t CRC_CalcCRC(uint32_t CRC_Data);
-uint32_t CRC_CalcCRC16bits(uint16_t CRC_Data); /*!< Only applicable for STM32F042 and STM32F072 devices */
-uint32_t CRC_CalcCRC8bits(uint8_t CRC_Data); /*!< Only applicable for STM32F042 and STM32F072 devices */
-uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength);
-uint32_t CRC_GetCRC(void);
-
-/* Independent register (IDR) access (write/read) *****************************/
-void CRC_SetIDRegister(uint8_t CRC_IDValue);
-uint8_t CRC_GetIDRegister(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F0XX_CRC_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_crs.h b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_crs.h
deleted file mode 100644
index 6f37b4f0d3579e4219b061743cf202837c860f45..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_crs.h
+++ /dev/null
@@ -1,183 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f0xx_crs.h
- * @author MCD Application Team
- * @version V1.3.0
- * @date 16-January-2014
- * @brief This file contains all the functions prototypes for the CRS firmware
- * library, applicable only for STM32F042 and STM32F072 devices.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F0XX_CRS_H
-#define __STM32F0XX_CRS_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/*!< Includes ----------------------------------------------------------------*/
-#include "stm32f0xx.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup CRS
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup CRS_Interrupt_Sources
- * @{
- */
-#define CRS_IT_SYNCOK CRS_ISR_SYNCOKF /*!< SYNC event OK */
-#define CRS_IT_SYNCWARN CRS_ISR_SYNCWARNF /*!< SYNC warning */
-#define CRS_IT_ERR CRS_ISR_ERRF /*!< error */
-#define CRS_IT_ESYNC CRS_ISR_ESYNCF /*!< Expected SYNC */
-#define CRS_IT_TRIMOVF CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */
-#define CRS_IT_SYNCERR CRS_ISR_SYNCERR /*!< SYNC error */
-#define CRS_IT_SYNCMISS CRS_ISR_SYNCMISS /*!< SYNC missed*/
-
-#define IS_CRS_IT(IT) (((IT) == CRS_IT_SYNCOK) || ((IT) == CRS_IT_SYNCWARN) || \
- ((IT) == CRS_IT_ERR) || ((IT) == CRS_IT_ESYNC))
-
-#define IS_CRS_GET_IT(IT) (((IT) == CRS_IT_SYNCOK) || ((IT) == CRS_IT_SYNCWARN) || \
- ((IT) == CRS_IT_ERR) || ((IT) == CRS_IT_ESYNC) || \
- ((IT) == CRS_IT_TRIMOVF) || ((IT) == CRS_IT_SYNCERR) || \
- ((IT) == CRS_IT_SYNCMISS))
-
-#define IS_CRS_CLEAR_IT(IT) ((IT) != 0x00)
-
-/**
- * @}
- */
-
-/** @defgroup CRS_Flags
- * @{
- */
-#define CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /*!< SYNC event OK */
-#define CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF /*!< SYNC warning */
-#define CRS_FLAG_ERR CRS_ISR_ERRF /*!< error */
-#define CRS_FLAG_ESYNC CRS_ISR_ESYNCF /*!< Expected SYNC */
-#define CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */
-#define CRS_FLAG_SYNCERR CRS_ISR_SYNCERR /*!< SYNC error */
-#define CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS /*!< SYNC missed*/
-
-#define IS_CRS_FLAG(FLAG) (((FLAG) == CRS_FLAG_SYNCOK) || ((FLAG) == CRS_FLAG_SYNCWARN) || \
- ((FLAG) == CRS_FLAG_ERR) || ((FLAG) == CRS_FLAG_ESYNC) || \
- ((FLAG) == CRS_FLAG_TRIMOVF) || ((FLAG) == CRS_FLAG_SYNCERR) || \
- ((FLAG) == CRS_FLAG_SYNCMISS))
-
-/**
- * @}
- */
-
-/** @defgroup CRS_Synchro_Source
- * @{
- */
-#define CRS_SYNCSource_GPIO ((uint32_t)0x00) /*!< Synchro Signal soucre GPIO */
-#define CRS_SYNCSource_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */
-#define CRS_SYNCSource_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF */
-
-#define IS_CRS_SYNC_SOURCE(SOURCE) (((SOURCE) == CRS_SYNCSource_GPIO) || \
- ((SOURCE) == CRS_SYNCSource_LSE) ||\
- ((SOURCE) == CRS_SYNCSource_USB))
-/**
- * @}
- */
-
-/** @defgroup CRS_SynchroDivider
- * @{
- */
-#define CRS_SYNC_Div1 ((uint32_t)0x00) /*!< Synchro Signal not divided */
-#define CRS_SYNC_Div2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */
-#define CRS_SYNC_Div4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */
-#define CRS_SYNC_Div8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */
-#define CRS_SYNC_Div16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */
-#define CRS_SYNC_Div32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */
-#define CRS_SYNC_Div64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */
-#define CRS_SYNC_Div128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */
-
-#define IS_CRS_SYNC_DIV(DIV) (((DIV) == CRS_SYNC_Div1) || ((DIV) == CRS_SYNC_Div2) ||\
- ((DIV) == CRS_SYNC_Div4) || ((DIV) == CRS_SYNC_Div8) || \
- ((DIV) == CRS_SYNC_Div16) || ((DIV) == CRS_SYNC_Div32) || \
- ((DIV) == CRS_SYNC_Div64) || ((DIV) == CRS_SYNC_Div128))
-/**
- * @}
- */
-
-/** @defgroup CRS_SynchroPolarity
- * @{
- */
-#define CRS_SYNCPolarity_Rising ((uint32_t)0x00) /*!< Synchro Active on rising edge */
-#define CRS_SYNCPolarity_Falling CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */
-
-#define IS_CRS_SYNC_POLARITY(POLARITY) (((POLARITY) == CRS_SYNCPolarity_Rising) || \
- ((POLARITY) == CRS_SYNCPolarity_Falling))
-/**
- * @}
- */
-
-
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-/* Configuration of the CRS **********************************/
-void CRS_DeInit(void);
-void CRS_AdjustHSI48CalibrationValue(uint8_t CRS_HSI48CalibrationValue);
-void CRS_FrequencyErrorCounterCmd(FunctionalState NewState);
-void CRS_AutomaticCalibrationCmd(FunctionalState NewState);
-void CRS_SoftwareSynchronizationGenerate(void);
-void CRS_FrequencyErrorCounterReload(uint32_t CRS_ReloadValue);
-void CRS_FrequencyErrorLimitConfig(uint8_t CRS_ErrorLimitValue);
-void CRS_SynchronizationPrescalerConfig(uint32_t CRS_Prescaler);
-void CRS_SynchronizationSourceConfig(uint32_t CRS_Source);
-void CRS_SynchronizationPolarityConfig(uint32_t CRS_Polarity);
-uint32_t CRS_GetReloadValue(void);
-uint32_t CRS_GetHSI48CalibrationValue(void);
-uint32_t CRS_GetFrequencyErrorValue(void);
-uint32_t CRS_GetFrequencyErrorDirection(void);
-
-/* Interrupts and flags management functions **********************************/
-void CRS_ITConfig(uint32_t CRS_IT, FunctionalState NewState);
-FlagStatus CRS_GetFlagStatus(uint32_t CRS_FLAG);
-void CRS_ClearFlag(uint32_t CRS_FLAG);
-ITStatus CRS_GetITStatus(uint32_t CRS_IT);
-void CRS_ClearITPendingBit(uint32_t CRS_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F0XX_CRS_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_dac.h b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_dac.h
deleted file mode 100644
index f2884bba9ab0ca45e223eeb2d9855f467e016c48..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_dac.h
+++ /dev/null
@@ -1,312 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f0xx_dac.h
- * @author MCD Application Team
- * @version V1.3.0
- * @date 16-January-2014
- * @brief This file contains all the functions prototypes for the DAC firmware
- * library, applicable only for STM32F051 and STM32F072 devices.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F0XX_DAC_H
-#define __STM32F0XX_DAC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup DAC
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/**
- * @brief DAC Init structure definition
- */
-
-typedef struct
-{
- uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel.
- This parameter can be a value of @ref DAC_trigger_selection */
-
- uint32_t DAC_WaveGeneration; /*!< Specifies whether DAC channel noise waves or triangle waves
- are generated, or whether no wave is generated.
- This parameter can be a value of @ref DAC_wave_generation
- This parameter is only applicable for STM32F072 devices */
-
- uint32_t DAC_LFSRUnmask_TriangleAmplitude; /*!< Specifies the LFSR mask for noise wave generation or
- the maximum amplitude triangle generation for the DAC channel.
- This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude
- This parameter is only applicable for STM32F072 devices */
-
- uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
- This parameter can be a value of @ref DAC_output_buffer */
-}DAC_InitTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup DAC_Exported_Constants
- * @{
- */
-
-/** @defgroup DAC_Trigger
- * @{
- */
-
-#define DAC_Trigger_None ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register
- has been loaded, and not by external trigger */
-#define DAC_Trigger_T6_TRGO ((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel1 */
-#define DAC_Trigger_T3_TRGO ((uint32_t)0x0000000C) /*!< TIM3 TRGO selected as external conversion trigger for DAC channel1 */
-#define DAC_Trigger_T7_TRGO ((uint32_t)0x00000014) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel1,
- applicable only for STM32F072 devices */
-#define DAC_Trigger_T15_TRGO ((uint32_t)0x0000001C) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel1 */
-#define DAC_Trigger_T2_TRGO ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel1 */
-#define DAC_Trigger_Ext_IT9 ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC channels */
-#define DAC_Trigger_Software ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC channels */
-
-#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \
- ((TRIGGER) == DAC_Trigger_T6_TRGO) || \
- ((TRIGGER) == DAC_Trigger_T7_TRGO) || \
- ((TRIGGER) == DAC_Trigger_T3_TRGO) || \
- ((TRIGGER) == DAC_Trigger_T15_TRGO) || \
- ((TRIGGER) == DAC_Trigger_T2_TRGO) || \
- ((TRIGGER) == DAC_Trigger_Ext_IT9) || \
- ((TRIGGER) == DAC_Trigger_Software))
-
-/**
- * @}
- */
-
-/** @defgroup DAC_wave_generation
- * @brief This parameters are only applicable for STM32F072 devices.
- * @{
- */
-
-#define DAC_WaveGeneration_None ((uint32_t)0x00000000)
-#define DAC_WaveGeneration_Noise ((uint32_t)0x00000040)
-#define DAC_WaveGeneration_Triangle ((uint32_t)0x00000080)
-#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \
- ((WAVE) == DAC_WaveGeneration_Noise) || \
- ((WAVE) == DAC_WaveGeneration_Triangle))
-/**
- * @}
- */
-
-/** @defgroup DAC_lfsrunmask_triangleamplitude
- * @brief These parameters are only applicable for STM32F072 devices.
- * @{
- */
-
-#define DAC_LFSRUnmask_Bit0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
-#define DAC_LFSRUnmask_Bits1_0 ((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
-#define DAC_LFSRUnmask_Bits2_0 ((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
-#define DAC_LFSRUnmask_Bits3_0 ((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
-#define DAC_LFSRUnmask_Bits4_0 ((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
-#define DAC_LFSRUnmask_Bits5_0 ((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
-#define DAC_LFSRUnmask_Bits6_0 ((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
-#define DAC_LFSRUnmask_Bits7_0 ((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
-#define DAC_LFSRUnmask_Bits8_0 ((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
-#define DAC_LFSRUnmask_Bits9_0 ((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
-#define DAC_LFSRUnmask_Bits10_0 ((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
-#define DAC_LFSRUnmask_Bits11_0 ((uint32_t)0x00000B00) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
-#define DAC_TriangleAmplitude_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */
-#define DAC_TriangleAmplitude_3 ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */
-#define DAC_TriangleAmplitude_7 ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */
-#define DAC_TriangleAmplitude_15 ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */
-#define DAC_TriangleAmplitude_31 ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */
-#define DAC_TriangleAmplitude_63 ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */
-#define DAC_TriangleAmplitude_127 ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */
-#define DAC_TriangleAmplitude_255 ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */
-#define DAC_TriangleAmplitude_511 ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */
-#define DAC_TriangleAmplitude_1023 ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */
-#define DAC_TriangleAmplitude_2047 ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */
-#define DAC_TriangleAmplitude_4095 ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */
-
-#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \
- ((VALUE) == DAC_LFSRUnmask_Bits1_0) || \
- ((VALUE) == DAC_LFSRUnmask_Bits2_0) || \
- ((VALUE) == DAC_LFSRUnmask_Bits3_0) || \
- ((VALUE) == DAC_LFSRUnmask_Bits4_0) || \
- ((VALUE) == DAC_LFSRUnmask_Bits5_0) || \
- ((VALUE) == DAC_LFSRUnmask_Bits6_0) || \
- ((VALUE) == DAC_LFSRUnmask_Bits7_0) || \
- ((VALUE) == DAC_LFSRUnmask_Bits8_0) || \
- ((VALUE) == DAC_LFSRUnmask_Bits9_0) || \
- ((VALUE) == DAC_LFSRUnmask_Bits10_0) || \
- ((VALUE) == DAC_LFSRUnmask_Bits11_0) || \
- ((VALUE) == DAC_TriangleAmplitude_1) || \
- ((VALUE) == DAC_TriangleAmplitude_3) || \
- ((VALUE) == DAC_TriangleAmplitude_7) || \
- ((VALUE) == DAC_TriangleAmplitude_15) || \
- ((VALUE) == DAC_TriangleAmplitude_31) || \
- ((VALUE) == DAC_TriangleAmplitude_63) || \
- ((VALUE) == DAC_TriangleAmplitude_127) || \
- ((VALUE) == DAC_TriangleAmplitude_255) || \
- ((VALUE) == DAC_TriangleAmplitude_511) || \
- ((VALUE) == DAC_TriangleAmplitude_1023) || \
- ((VALUE) == DAC_TriangleAmplitude_2047) || \
- ((VALUE) == DAC_TriangleAmplitude_4095))
-/**
- * @}
- */
-
-/** @defgroup DAC_OutputBuffer
- * @{
- */
-
-#define DAC_OutputBuffer_Enable ((uint32_t)0x00000000)
-#define DAC_OutputBuffer_Disable DAC_CR_BOFF1
-#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \
- ((STATE) == DAC_OutputBuffer_Disable))
-/**
- * @}
- */
-
-/** @defgroup DAC_Channel_selection
- * @{
- */
-
-#define DAC_Channel_1 ((uint32_t)0x00000000)
-#define DAC_Channel_2 ((uint32_t)0x00000010) /*!< Only applicable for STM32F072 devices */
-#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \
- ((CHANNEL) == DAC_Channel_2))
-
-/**
- * @}
- */
-
-/** @defgroup DAC_data_alignment
- * @{
- */
-
-#define DAC_Align_12b_R ((uint32_t)0x00000000)
-#define DAC_Align_12b_L ((uint32_t)0x00000004)
-#define DAC_Align_8b_R ((uint32_t)0x00000008)
-#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \
- ((ALIGN) == DAC_Align_12b_L) || \
- ((ALIGN) == DAC_Align_8b_R))
-/**
- * @}
- */
-
-/** @defgroup DAC_wave_generation
- * @brief These parameters are only applicable for STM32F072 devices.
- * @{
- */
-
-#define DAC_Wave_Noise ((uint32_t)0x00000040)
-#define DAC_Wave_Triangle ((uint32_t)0x00000080)
-#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \
- ((WAVE) == DAC_Wave_Triangle))
-/**
- * @}
- */
-
-/** @defgroup DAC_data
- * @{
- */
-
-#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0)
-
-/**
- * @}
- */
-
-/** @defgroup DAC_interrupts_definition
- * @{
- */
-
-#define DAC_IT_DMAUDR DAC_SR_DMAUDR1
-#define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR))
-
-/**
- * @}
- */
-
-
-/** @defgroup DAC_flags_definition
- * @{
- */
-
-#define DAC_FLAG_DMAUDR DAC_SR_DMAUDR1
-
-#define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR))
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-/* Function used to set the DAC configuration to the default reset state *****/
-void DAC_DeInit(void);
-
-/* DAC channels configuration: trigger, output buffer, data format functions */
-void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct);
-void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct);
-void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState);
-void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState);
-void DAC_DualSoftwareTriggerCmd(FunctionalState NewState); /*!< Only applicable for STM32F072 devices */
-void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState); /*!< Only applicable for STM32F072 devices */
-void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data);
-void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data); /*!< Only applicable for STM32F072 devices */
-void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1); /*!< Only applicable for STM32F072 devices */
-uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel);
-
-/* DMA management functions ***************************************************/
-void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState);
-
-/* Interrupts and flags management functions **********************************/
-void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState);
-FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG);
-void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG);
-ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT);
-void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F0XX_DAC_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_dbgmcu.h b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_dbgmcu.h
deleted file mode 100644
index 0ce7130832f9a0a8b62e0d3bcf16cb2930d46624..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_dbgmcu.h
+++ /dev/null
@@ -1,107 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f0xx_dbgmcu.h
- * @author MCD Application Team
- * @version V1.3.0
- * @date 16-January-2014
- * @brief This file contains all the functions prototypes for the DBGMCU firmware
- * library.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F0XX_DBGMCU_H
-#define __STM32F0XX_DBGMCU_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup DBGMCU
- * @{
- */
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-
-/** @defgroup DBGMCU_Exported_Constants
- * @{
- */
-
-#define DBGMCU_STOP DBGMCU_CR_DBG_STOP
-#define DBGMCU_STANDBY DBGMCU_CR_DBG_STANDBY
-#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFF9) == 0x00) && ((PERIPH) != 0x00))
-
-#define DBGMCU_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP /*!< Not applicable for STM32F030 devices */
-#define DBGMCU_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP
-#define DBGMCU_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP
-#define DBGMCU_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP /*!< Only applicable for STM32F072 devices */
-#define DBGMCU_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP
-#define DBGMCU_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP
-#define DBGMCU_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP
-#define DBGMCU_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP
-#define DBGMCU_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT
-#define DBGMCU_CAN1_STOP DBGMCU_APB1_FZ_DBG_CAN1_STOP /*!< Only applicable for STM32F042 and STM32F072 devices */
-#define IS_DBGMCU_APB1PERIPH(PERIPH) ((((PERIPH) & 0xFDDFE2CC) == 0x00) && ((PERIPH) != 0x00))
-
-#define DBGMCU_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP
-#define DBGMCU_TIM15_STOP DBGMCU_APB2_FZ_DBG_TIM15_STOP
-#define DBGMCU_TIM16_STOP DBGMCU_APB2_FZ_DBG_TIM16_STOP
-#define DBGMCU_TIM17_STOP DBGMCU_APB2_FZ_DBG_TIM17_STOP
-#define IS_DBGMCU_APB2PERIPH(PERIPH) ((((PERIPH) & 0xFFF8F7FF) == 0x00) && ((PERIPH) != 0x00))
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-/* Device and Revision ID management functions ********************************/
-uint32_t DBGMCU_GetREVID(void);
-uint32_t DBGMCU_GetDEVID(void);
-
-/* Peripherals Configuration functions ****************************************/
-void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState);
-void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState);
-void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F0XX_DBGMCU_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_dma.h b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_dma.h
deleted file mode 100644
index d24decb91ecd8a7cc618aee570ab90ed58676fc0..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_dma.h
+++ /dev/null
@@ -1,377 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f0xx_dma.h
- * @author MCD Application Team
- * @version V1.3.0
- * @date 16-January-2014
- * @brief This file contains all the functions prototypes for the DMA firmware
- * library.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F0XX_DMA_H
-#define __STM32F0XX_DMA_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup DMA
- * @{
- */
-/* Exported types ------------------------------------------------------------*/
-
-/**
- * @brief DMA Init structures definition
- */
-typedef struct
-{
- uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Channelx. */
-
- uint32_t DMA_MemoryBaseAddr; /*!< Specifies the memory base address for DMAy Channelx. */
-
- uint32_t DMA_DIR; /*!< Specifies if the peripheral is the source or destination.
- This parameter can be a value of @ref DMA_data_transfer_direction */
-
- uint32_t DMA_BufferSize; /*!< Specifies the buffer size, in data unit, of the specified Channel.
- The data unit is equal to the configuration set in DMA_PeripheralDataSize
- or DMA_MemoryDataSize members depending in the transfer direction */
-
- uint32_t DMA_PeripheralInc; /*!< Specifies whether the Peripheral address register is incremented or not.
- This parameter can be a value of @ref DMA_peripheral_incremented_mode */
-
- uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register is incremented or not.
- This parameter can be a value of @ref DMA_memory_incremented_mode */
-
- uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width.
- This parameter can be a value of @ref DMA_peripheral_data_size */
-
- uint32_t DMA_MemoryDataSize; /*!< Specifies the Memory data width.
- This parameter can be a value of @ref DMA_memory_data_size */
-
- uint32_t DMA_Mode; /*!< Specifies the operation mode of the DMAy Channelx.
- This parameter can be a value of @ref DMA_circular_normal_mode
- @note: The circular buffer mode cannot be used if the memory-to-memory
- data transfer is configured on the selected Channel */
-
- uint32_t DMA_Priority; /*!< Specifies the software priority for the DMAy Channelx.
- This parameter can be a value of @ref DMA_priority_level */
-
- uint32_t DMA_M2M; /*!< Specifies if the DMAy Channelx will be used in memory-to-memory transfer.
- This parameter can be a value of @ref DMA_memory_to_memory */
-}DMA_InitTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup DMA_Exported_Constants
- * @{
- */
-
-#define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Channel1) || \
- ((PERIPH) == DMA1_Channel2) || \
- ((PERIPH) == DMA1_Channel3) || \
- ((PERIPH) == DMA1_Channel4) || \
- ((PERIPH) == DMA1_Channel5) || \
- ((PERIPH) == DMA1_Channel6) || \
- ((PERIPH) == DMA1_Channel7))
-
-/** @defgroup DMA_data_transfer_direction
- * @{
- */
-
-#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000)
-#define DMA_DIR_PeripheralDST DMA_CCR_DIR
-
-#define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralSRC) || \
- ((DIR) == DMA_DIR_PeripheralDST))
-/**
- * @}
- */
-
-/** @defgroup DMA_peripheral_incremented_mode
- * @{
- */
-
-#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000)
-#define DMA_PeripheralInc_Enable DMA_CCR_PINC
-
-#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Disable) || \
- ((STATE) == DMA_PeripheralInc_Enable))
-/**
- * @}
- */
-
-/** @defgroup DMA_memory_incremented_mode
- * @{
- */
-
-#define DMA_MemoryInc_Disable ((uint32_t)0x00000000)
-#define DMA_MemoryInc_Enable DMA_CCR_MINC
-
-#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Disable) || \
- ((STATE) == DMA_MemoryInc_Enable))
-/**
- * @}
- */
-
-/** @defgroup DMA_peripheral_data_size
- * @{
- */
-
-#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000)
-#define DMA_PeripheralDataSize_HalfWord DMA_CCR_PSIZE_0
-#define DMA_PeripheralDataSize_Word DMA_CCR_PSIZE_1
-
-#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \
- ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \
- ((SIZE) == DMA_PeripheralDataSize_Word))
-/**
- * @}
- */
-
-/** @defgroup DMA_memory_data_size
- * @{
- */
-
-#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000)
-#define DMA_MemoryDataSize_HalfWord DMA_CCR_MSIZE_0
-#define DMA_MemoryDataSize_Word DMA_CCR_MSIZE_1
-
-#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \
- ((SIZE) == DMA_MemoryDataSize_HalfWord) || \
- ((SIZE) == DMA_MemoryDataSize_Word))
-/**
- * @}
- */
-
-/** @defgroup DMA_circular_normal_mode
- * @{
- */
-
-#define DMA_Mode_Normal ((uint32_t)0x00000000)
-#define DMA_Mode_Circular DMA_CCR_CIRC
-
-#define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Normal) || ((MODE) == DMA_Mode_Circular))
-/**
- * @}
- */
-
-/** @defgroup DMA_priority_level
- * @{
- */
-
-#define DMA_Priority_VeryHigh DMA_CCR_PL
-#define DMA_Priority_High DMA_CCR_PL_1
-#define DMA_Priority_Medium DMA_CCR_PL_0
-#define DMA_Priority_Low ((uint32_t)0x00000000)
-
-#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \
- ((PRIORITY) == DMA_Priority_High) || \
- ((PRIORITY) == DMA_Priority_Medium) || \
- ((PRIORITY) == DMA_Priority_Low))
-/**
- * @}
- */
-
-/** @defgroup DMA_memory_to_memory
- * @{
- */
-
-#define DMA_M2M_Disable ((uint32_t)0x00000000)
-#define DMA_M2M_Enable DMA_CCR_MEM2MEM
-
-#define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Disable) || ((STATE) == DMA_M2M_Enable))
-
-/**
- * @}
- */
-
-/** @defgroup DMA_interrupts_definition
- * @{
- */
-
-#define DMA_IT_TC DMA_CCR_TCIE
-#define DMA_IT_HT DMA_CCR_HTIE
-#define DMA_IT_TE DMA_CCR_TEIE
-
-#define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00))
-
-#define DMA1_IT_GL1 DMA_ISR_GIF1
-#define DMA1_IT_TC1 DMA_ISR_TCIF1
-#define DMA1_IT_HT1 DMA_ISR_HTIF1
-#define DMA1_IT_TE1 DMA_ISR_TEIF1
-#define DMA1_IT_GL2 DMA_ISR_GIF2
-#define DMA1_IT_TC2 DMA_ISR_TCIF2
-#define DMA1_IT_HT2 DMA_ISR_HTIF2
-#define DMA1_IT_TE2 DMA_ISR_TEIF2
-#define DMA1_IT_GL3 DMA_ISR_GIF3
-#define DMA1_IT_TC3 DMA_ISR_TCIF3
-#define DMA1_IT_HT3 DMA_ISR_HTIF3
-#define DMA1_IT_TE3 DMA_ISR_TEIF3
-#define DMA1_IT_GL4 DMA_ISR_GIF4
-#define DMA1_IT_TC4 DMA_ISR_TCIF4
-#define DMA1_IT_HT4 DMA_ISR_HTIF4
-#define DMA1_IT_TE4 DMA_ISR_TEIF4
-#define DMA1_IT_GL5 DMA_ISR_GIF5
-#define DMA1_IT_TC5 DMA_ISR_TCIF5
-#define DMA1_IT_HT5 DMA_ISR_HTIF5
-#define DMA1_IT_TE5 DMA_ISR_TEIF5
-#define DMA1_IT_GL6 DMA_ISR_GIF6 /*!< Only applicable for STM32F072 devices */
-#define DMA1_IT_TC6 DMA_ISR_TCIF6 /*!< Only applicable for STM32F072 devices */
-#define DMA1_IT_HT6 DMA_ISR_HTIF6 /*!< Only applicable for STM32F072 devices */
-#define DMA1_IT_TE6 DMA_ISR_TEIF6 /*!< Only applicable for STM32F072 devices */
-#define DMA1_IT_GL7 DMA_ISR_GIF7 /*!< Only applicable for STM32F072 devices */
-#define DMA1_IT_TC7 DMA_ISR_TCIF7 /*!< Only applicable for STM32F072 devices */
-#define DMA1_IT_HT7 DMA_ISR_HTIF7 /*!< Only applicable for STM32F072 devices */
-#define DMA1_IT_TE7 DMA_ISR_TEIF7 /*!< Only applicable for STM32F072 devices */
-
-#define IS_DMA_CLEAR_IT(IT) ((((IT) & 0xF0000000) == 0x00) && ((IT) != 0x00))
-
-#define IS_DMA_GET_IT(IT) (((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || \
- ((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || \
- ((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || \
- ((IT) == DMA1_IT_HT2) || ((IT) == DMA1_IT_TE2) || \
- ((IT) == DMA1_IT_GL3) || ((IT) == DMA1_IT_TC3) || \
- ((IT) == DMA1_IT_HT3) || ((IT) == DMA1_IT_TE3) || \
- ((IT) == DMA1_IT_GL4) || ((IT) == DMA1_IT_TC4) || \
- ((IT) == DMA1_IT_HT4) || ((IT) == DMA1_IT_TE4) || \
- ((IT) == DMA1_IT_GL5) || ((IT) == DMA1_IT_TC5) || \
- ((IT) == DMA1_IT_HT5) || ((IT) == DMA1_IT_TE5) || \
- ((IT) == DMA1_IT_GL6) || ((IT) == DMA1_IT_TC6) || \
- ((IT) == DMA1_IT_HT6) || ((IT) == DMA1_IT_TE6) || \
- ((IT) == DMA1_IT_GL7) || ((IT) == DMA1_IT_TC7) || \
- ((IT) == DMA1_IT_HT7) || ((IT) == DMA1_IT_TE7))
-
-/**
- * @}
- */
-
-/** @defgroup DMA_flags_definition
- * @{
- */
-#define DMA1_FLAG_GL1 DMA_ISR_GIF1
-#define DMA1_FLAG_TC1 DMA_ISR_TCIF1
-#define DMA1_FLAG_HT1 DMA_ISR_HTIF1
-#define DMA1_FLAG_TE1 DMA_ISR_TEIF1
-#define DMA1_FLAG_GL2 DMA_ISR_GIF2
-#define DMA1_FLAG_TC2 DMA_ISR_TCIF2
-#define DMA1_FLAG_HT2 DMA_ISR_HTIF2
-#define DMA1_FLAG_TE2 DMA_ISR_TEIF2
-#define DMA1_FLAG_GL3 DMA_ISR_GIF3
-#define DMA1_FLAG_TC3 DMA_ISR_TCIF3
-#define DMA1_FLAG_HT3 DMA_ISR_HTIF3
-#define DMA1_FLAG_TE3 DMA_ISR_TEIF3
-#define DMA1_FLAG_GL4 DMA_ISR_GIF4
-#define DMA1_FLAG_TC4 DMA_ISR_TCIF4
-#define DMA1_FLAG_HT4 DMA_ISR_HTIF4
-#define DMA1_FLAG_TE4 DMA_ISR_TEIF4
-#define DMA1_FLAG_GL5 DMA_ISR_GIF5
-#define DMA1_FLAG_TC5 DMA_ISR_TCIF5
-#define DMA1_FLAG_HT5 DMA_ISR_HTIF5
-#define DMA1_FLAG_TE5 DMA_ISR_TEIF5
-#define DMA1_FLAG_GL6 DMA_ISR_GIF6 /*!< Only applicable for STM32F072 devices */
-#define DMA1_FLAG_TC6 DMA_ISR_TCIF6 /*!< Only applicable for STM32F072 devices */
-#define DMA1_FLAG_HT6 DMA_ISR_HTIF6 /*!< Only applicable for STM32F072 devices */
-#define DMA1_FLAG_TE6 DMA_ISR_TEIF6 /*!< Only applicable for STM32F072 devices */
-#define DMA1_FLAG_GL7 DMA_ISR_GIF7 /*!< Only applicable for STM32F072 devices */
-#define DMA1_FLAG_TC7 DMA_ISR_TCIF7 /*!< Only applicable for STM32F072 devices */
-#define DMA1_FLAG_HT7 DMA_ISR_HTIF7 /*!< Only applicable for STM32F072 devices */
-#define DMA1_FLAG_TE7 DMA_ISR_TEIF7 /*!< Only applicable for STM32F072 devices */
-
-#define IS_DMA_CLEAR_FLAG(FLAG) ((((FLAG) & 0xF0000000) == 0x00) && ((FLAG) != 0x00))
-
-#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \
- ((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || \
- ((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \
- ((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_TE2) || \
- ((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || \
- ((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || \
- ((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || \
- ((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) || \
- ((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || \
- ((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_TE5) || \
- ((FLAG) == DMA1_FLAG_GL6) || ((FLAG) == DMA1_FLAG_TC6) || \
- ((FLAG) == DMA1_FLAG_HT6) || ((FLAG) == DMA1_FLAG_TE6) || \
- ((FLAG) == DMA1_FLAG_GL7) || ((FLAG) == DMA1_FLAG_TC7) || \
- ((FLAG) == DMA1_FLAG_HT7) || ((FLAG) == DMA1_FLAG_TE7))
-
-/**
- * @}
- */
-
-/** @defgroup DMA_Buffer_Size
- * @{
- */
-
-#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-/* Function used to set the DMA configuration to the default reset state ******/
-void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx);
-
-/* Initialization and Configuration functions *********************************/
-void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct);
-void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct);
-void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState);
-
-/* Data Counter functions******************************************************/
-void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber);
-uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx);
-
-/* Interrupts and flags management functions **********************************/
-void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState);
-FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG);
-void DMA_ClearFlag(uint32_t DMA_FLAG);
-ITStatus DMA_GetITStatus(uint32_t DMA_IT);
-void DMA_ClearITPendingBit(uint32_t DMA_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F0XX_DMA_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_exti.h b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_exti.h
deleted file mode 100644
index f2231664c01a2516c61306c6a85deb33a854924b..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_exti.h
+++ /dev/null
@@ -1,216 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f0xx_exti.h
- * @author MCD Application Team
- * @version V1.3.0
- * @date 16-January-2014
- * @brief This file contains all the functions prototypes for the EXTI
- * firmware library
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F0XX_EXTI_H
-#define __STM32F0XX_EXTI_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup EXTI
- * @{
- */
-/* Exported types ------------------------------------------------------------*/
-
-/**
- * @brief EXTI mode enumeration
- */
-
-typedef enum
-{
- EXTI_Mode_Interrupt = 0x00,
- EXTI_Mode_Event = 0x04
-}EXTIMode_TypeDef;
-
-#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event))
-
-/**
- * @brief EXTI Trigger enumeration
- */
-
-typedef enum
-{
- EXTI_Trigger_Rising = 0x08,
- EXTI_Trigger_Falling = 0x0C,
- EXTI_Trigger_Rising_Falling = 0x10
-}EXTITrigger_TypeDef;
-
-#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \
- ((TRIGGER) == EXTI_Trigger_Falling) || \
- ((TRIGGER) == EXTI_Trigger_Rising_Falling))
-/**
- * @brief EXTI Init Structure definition
- */
-
-typedef struct
-{
- uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled.
- This parameter can be any combination of @ref EXTI_Lines */
-
- EXTIMode_TypeDef EXTI_Mode; /*!< Specifies the mode for the EXTI lines.
- This parameter can be a value of @ref EXTIMode_TypeDef */
-
- EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.
- This parameter can be a value of @ref EXTIMode_TypeDef */
-
- FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI lines.
- This parameter can be set either to ENABLE or DISABLE */
-}EXTI_InitTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup EXTI_Exported_Constants
- * @{
- */
-/** @defgroup EXTI_Lines
- * @{
- */
-
-#define EXTI_Line0 ((uint32_t)0x00000001) /*!< External interrupt line 0 */
-#define EXTI_Line1 ((uint32_t)0x00000002) /*!< External interrupt line 1 */
-#define EXTI_Line2 ((uint32_t)0x00000004) /*!< External interrupt line 2 */
-#define EXTI_Line3 ((uint32_t)0x00000008) /*!< External interrupt line 3 */
-#define EXTI_Line4 ((uint32_t)0x00000010) /*!< External interrupt line 4 */
-#define EXTI_Line5 ((uint32_t)0x00000020) /*!< External interrupt line 5 */
-#define EXTI_Line6 ((uint32_t)0x00000040) /*!< External interrupt line 6 */
-#define EXTI_Line7 ((uint32_t)0x00000080) /*!< External interrupt line 7 */
-#define EXTI_Line8 ((uint32_t)0x00000100) /*!< External interrupt line 8 */
-#define EXTI_Line9 ((uint32_t)0x00000200) /*!< External interrupt line 9 */
-#define EXTI_Line10 ((uint32_t)0x00000400) /*!< External interrupt line 10 */
-#define EXTI_Line11 ((uint32_t)0x00000800) /*!< External interrupt line 11 */
-#define EXTI_Line12 ((uint32_t)0x00001000) /*!< External interrupt line 12 */
-#define EXTI_Line13 ((uint32_t)0x00002000) /*!< External interrupt line 13 */
-#define EXTI_Line14 ((uint32_t)0x00004000) /*!< External interrupt line 14 */
-#define EXTI_Line15 ((uint32_t)0x00008000) /*!< External interrupt line 15 */
-#define EXTI_Line16 ((uint32_t)0x00010000) /*!< External interrupt line 16
- Connected to the PVD Output,
- not applicable for STM32F030 devices */
-#define EXTI_Line17 ((uint32_t)0x00020000) /*!< Internal interrupt line 17
- Connected to the RTC Alarm
- event */
-#define EXTI_Line18 ((uint32_t)0x00040000) /*!< Internal interrupt line 18
- Connected to the USB
- event, only applicable for
- STM32F072 devices */
-#define EXTI_Line19 ((uint32_t)0x00080000) /*!< Internal interrupt line 19
- Connected to the RTC Tamper
- and Time Stamp events */
-#define EXTI_Line20 ((uint32_t)0x00100000) /*!< Internal interrupt line 20
- Connected to the RTC wakeup
- event, only applicable for
- STM32F072 devices */
-#define EXTI_Line21 ((uint32_t)0x00200000) /*!< Internal interrupt line 21
- Connected to the Comparator 1
- event, only applicable for STM32F051
- ans STM32F072 devices */
-#define EXTI_Line22 ((uint32_t)0x00400000) /*!< Internal interrupt line 22
- Connected to the Comparator 2
- event, only applicable for STM32F051
- and STM32F072 devices */
-#define EXTI_Line23 ((uint32_t)0x00800000) /*!< Internal interrupt line 23
- Connected to the I2C1 wakeup
- event, not applicable for STM32F030 devices */
-#define EXTI_Line25 ((uint32_t)0x02000000) /*!< Internal interrupt line 25
- Connected to the USART1 wakeup
- event, not applicable for STM32F030 devices */
-#define EXTI_Line26 ((uint32_t)0x04000000) /*!< Internal interrupt line 26
- Connected to the USART2 wakeup
- event, applicable only for
- STM32F072 devices */
-#define EXTI_Line27 ((uint32_t)0x08000000) /*!< Internal interrupt line 27
- Connected to the CEC wakeup
- event, applicable only for STM32F051
- and STM32F072 devices */
-#define EXTI_Line31 ((uint32_t)0x80000000) /*!< Internal interrupt line 31
- Connected to the VDD USB monitor
- event, applicable only for
- STM32F072 devices */
-#define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0x71000000) == 0x00) && ((LINE) != (uint16_t)0x00))
-
-#define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \
- ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \
- ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \
- ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \
- ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \
- ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \
- ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \
- ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \
- ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \
- ((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19) || \
- ((LINE) == EXTI_Line20) || ((LINE) == EXTI_Line21) || \
- ((LINE) == EXTI_Line22) || ((LINE) == EXTI_Line23) || \
- ((LINE) == EXTI_Line25) || ((LINE) == EXTI_Line26) || \
- ((LINE) == EXTI_Line27) || ((LINE) == EXTI_Line31))
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-/* Function used to set the EXTI configuration to the default reset state *****/
-void EXTI_DeInit(void);
-
-/* Initialization and Configuration functions *********************************/
-void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct);
-void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct);
-void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line);
-
-/* Interrupts and flags management functions **********************************/
-FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line);
-void EXTI_ClearFlag(uint32_t EXTI_Line);
-ITStatus EXTI_GetITStatus(uint32_t EXTI_Line);
-void EXTI_ClearITPendingBit(uint32_t EXTI_Line);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F0XX_EXTI_H */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_flash.h b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_flash.h
deleted file mode 100644
index 40a2976d2cfe32710795b888e506b361962f72ef..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_flash.h
+++ /dev/null
@@ -1,430 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f0xx_flash.h
- * @author MCD Application Team
- * @version V1.3.0
- * @date 16-January-2014
- * @brief This file contains all the functions prototypes for the FLASH
- * firmware library.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F0XX_FLASH_H
-#define __STM32F0XX_FLASH_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup FLASH
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/**
- * @brief FLASH Status
- */
-typedef enum
-{
- FLASH_BUSY = 1,
- FLASH_ERROR_WRP,
- FLASH_ERROR_PROGRAM,
- FLASH_COMPLETE,
- FLASH_TIMEOUT
-}FLASH_Status;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup FLASH_Exported_Constants
- * @{
- */
-
-/** @defgroup FLASH_Latency
- * @{
- */
-#define FLASH_Latency_0 ((uint32_t)0x00000000) /*!< FLASH Zero Latency cycle */
-#define FLASH_Latency_1 FLASH_ACR_LATENCY /*!< FLASH One Latency cycle */
-
-#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \
- ((LATENCY) == FLASH_Latency_1))
-/**
- * @}
- */
-
-/** @defgroup FLASH_Interrupts
- * @{
- */
-
-#define FLASH_IT_EOP FLASH_CR_EOPIE /*!< End of programming interrupt source */
-#define FLASH_IT_ERR FLASH_CR_ERRIE /*!< Error interrupt source */
-#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFFFFEBFF) == 0x00000000) && (((IT) != 0x00000000)))
-/**
- * @}
- */
-
-/** @defgroup FLASH_Address
- * @{
- */
-#ifndef STM32F072
- #define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0800FFFF))
-#else
- #define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0801FFFF))
-#endif /* STM32F072 */
-/**
- * @}
- */
-
-/** @defgroup FLASH_OB_DATA_ADDRESS
- * @{
- */
-#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == 0x1FFFF804) || ((ADDRESS) == 0x1FFFF806))
-
-/**
- * @}
- */
-
-/** @defgroup FLASH_Option_Bytes_Write_Protection
- * @{
- */
-
-#ifndef STM32F072
-
-#define OB_WRP_Pages0to3 ((uint32_t)0x00000001) /* Write protection of page 0 to 3 */
-#define OB_WRP_Pages4to7 ((uint32_t)0x00000002) /* Write protection of page 4 to 7 */
-#define OB_WRP_Pages8to11 ((uint32_t)0x00000004) /* Write protection of page 8 to 11 */
-#define OB_WRP_Pages12to15 ((uint32_t)0x00000008) /* Write protection of page 12 to 15 */
-#define OB_WRP_Pages16to19 ((uint32_t)0x00000010) /* Write protection of page 16 to 19 */
-#define OB_WRP_Pages20to23 ((uint32_t)0x00000020) /* Write protection of page 20 to 23 */
-#define OB_WRP_Pages24to27 ((uint32_t)0x00000040) /* Write protection of page 24 to 27 */
-#define OB_WRP_Pages28to31 ((uint32_t)0x00000080) /* Write protection of page 28 to 31 */
-#define OB_WRP_Pages32to35 ((uint32_t)0x00000100) /* Write protection of page 32 to 35 */
-#define OB_WRP_Pages36to39 ((uint32_t)0x00000200) /* Write protection of page 36 to 39 */
-#define OB_WRP_Pages40to43 ((uint32_t)0x00000400) /* Write protection of page 40 to 43 */
-#define OB_WRP_Pages44to47 ((uint32_t)0x00000800) /* Write protection of page 44 to 47 */
-#define OB_WRP_Pages48to51 ((uint32_t)0x00001000) /* Write protection of page 48 to 51 */
-#define OB_WRP_Pages52to55 ((uint32_t)0x00002000) /* Write protection of page 52 to 55 */
-#define OB_WRP_Pages56to59 ((uint32_t)0x00004000) /* Write protection of page 56 to 59 */
-#define OB_WRP_Pages60to63 ((uint32_t)0x00008000) /* Write protection of page 60 to 63 */
-
-#define OB_WRP_AllPages ((uint32_t)0x0000FFFF) /*!< Write protection of all Sectors */
-
-#define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000))
-
-#else
-
-#define OB_WRP_Pages0to1 ((uint32_t)0x00000001) /* Write protection of page 0 to 1 */
-#define OB_WRP_Pages2to3 ((uint32_t)0x00000002) /* Write protection of page 2 to 3 */
-#define OB_WRP_Pages4to5 ((uint32_t)0x00000004) /* Write protection of page 4 to 5 */
-#define OB_WRP_Pages6to7 ((uint32_t)0x00000008) /* Write protection of page 6 to 7 */
-#define OB_WRP_Pages8to9 ((uint32_t)0x00000010) /* Write protection of page 8 to 9 */
-#define OB_WRP_Pages10to11 ((uint32_t)0x00000020) /* Write protection of page 10 to 11 */
-#define OB_WRP_Pages12to13 ((uint32_t)0x00000040) /* Write protection of page 12 to 13 */
-#define OB_WRP_Pages14to15 ((uint32_t)0x00000080) /* Write protection of page 14 to 15 */
-#define OB_WRP_Pages16to17 ((uint32_t)0x00000100) /* Write protection of page 16 to 17 */
-#define OB_WRP_Pages18to19 ((uint32_t)0x00000200) /* Write protection of page 18 to 19 */
-#define OB_WRP_Pages20to21 ((uint32_t)0x00000400) /* Write protection of page 20 to 21 */
-#define OB_WRP_Pages22to23 ((uint32_t)0x00000800) /* Write protection of page 22 to 23 */
-#define OB_WRP_Pages24to25 ((uint32_t)0x00001000) /* Write protection of page 24 to 25 */
-#define OB_WRP_Pages26to27 ((uint32_t)0x00002000) /* Write protection of page 26 to 27 */
-#define OB_WRP_Pages28to29 ((uint32_t)0x00004000) /* Write protection of page 28 to 29 */
-#define OB_WRP_Pages30to31 ((uint32_t)0x00008000) /* Write protection of page 30 to 31 */
-#define OB_WRP_Pages32to33 ((uint32_t)0x00010000) /* Write protection of page 32 to 33 */
-#define OB_WRP_Pages34to35 ((uint32_t)0x00020000) /* Write protection of page 34 to 35 */
-#define OB_WRP_Pages36to37 ((uint32_t)0x00040000) /* Write protection of page 36 to 37 */
-#define OB_WRP_Pages38to39 ((uint32_t)0x00080000) /* Write protection of page 38 to 39 */
-#define OB_WRP_Pages40to41 ((uint32_t)0x00100000) /* Write protection of page 40 to 41 */
-#define OB_WRP_Pages42to43 ((uint32_t)0x00200000) /* Write protection of page 42 to 43 */
-#define OB_WRP_Pages44to45 ((uint32_t)0x00400000) /* Write protection of page 44 to 45 */
-#define OB_WRP_Pages46to47 ((uint32_t)0x00800000) /* Write protection of page 46 to 47 */
-#define OB_WRP_Pages48to49 ((uint32_t)0x01000000) /* Write protection of page 48 to 49 */
-#define OB_WRP_Pages50to51 ((uint32_t)0x02000000) /* Write protection of page 50 to 51 */
-#define OB_WRP_Pages52to53 ((uint32_t)0x04000000) /* Write protection of page 52 to 53 */
-#define OB_WRP_Pages54to55 ((uint32_t)0x08000000) /* Write protection of page 54 to 55 */
-#define OB_WRP_Pages56to57 ((uint32_t)0x10000000) /* Write protection of page 56 to 57 */
-#define OB_WRP_Pages58to59 ((uint32_t)0x20000000) /* Write protection of page 58 to 59 */
-#define OB_WRP_Pages60to61 ((uint32_t)0x40000000) /* Write protection of page 60 to 61 */
-#define OB_WRP_Pages62to63 ((uint32_t)0x80000000) /* Write protection of page 62 to 63 */
-
-#define OB_WRP_AllPages ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Sectors */
-
-#define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000))
-
-#endif /* STM32F072 */
-
-/**
- * @}
- */
-
-/** @defgroup FLASH_Option_Bytes_Read_Protection
- * @{
- */
-
-/**
- * @brief FLASH_Read Protection Level
- */
-#define OB_RDP_Level_0 ((uint8_t)0xAA)
-#define OB_RDP_Level_1 ((uint8_t)0xBB)
-/*#define OB_RDP_Level_2 ((uint8_t)0xCC)*/ /* Warning: When enabling read protection level 2
- it's no more possible to go back to level 1 or 0 */
-
-#define IS_OB_RDP(LEVEL) (((LEVEL) == OB_RDP_Level_0)||\
- ((LEVEL) == OB_RDP_Level_1))/*||\
- ((LEVEL) == OB_RDP_Level_2))*/
-/**
- * @}
- */
-
-/** @defgroup FLASH_Option_Bytes_IWatchdog
- * @{
- */
-
-#define OB_IWDG_SW ((uint8_t)0x01) /*!< Software IWDG selected */
-#define OB_IWDG_HW ((uint8_t)0x00) /*!< Hardware IWDG selected */
-#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
-
-/**
- * @}
- */
-
-/** @defgroup FLASH_Option_Bytes_nRST_STOP
- * @{
- */
-
-#define OB_STOP_NoRST ((uint8_t)0x02) /*!< No reset generated when entering in STOP */
-#define OB_STOP_RST ((uint8_t)0x00) /*!< Reset generated when entering in STOP */
-#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST))
-
-/**
- * @}
- */
-
-/** @defgroup FLASH_Option_Bytes_nRST_STDBY
- * @{
- */
-
-#define OB_STDBY_NoRST ((uint8_t)0x04) /*!< No reset generated when entering in STANDBY */
-#define OB_STDBY_RST ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */
-#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST))
-
-/**
- * @}
- */
-
-/** @defgroup FLASH_Option_Bytes_BOOT1
- * @{
- */
-
-#define OB_BOOT1_RESET ((uint8_t)0x00) /*!< BOOT1 Reset */
-#define OB_BOOT1_SET ((uint8_t)0x10) /*!< BOOT1 Set */
-#define IS_OB_BOOT1(BOOT1) (((BOOT1) == OB_BOOT1_RESET) || ((BOOT1) == OB_BOOT1_SET))
-
-/**
- * @}
- */
-
-/** @defgroup FLASH_Option_Bytes_BOOT0
- * @{
- */
-
-#define OB_BOOT0_RESET ((uint8_t)0x00) /*!< BOOT0 Reset */
-#define OB_BOOT0_SET ((uint8_t)0x08) /*!< BOOT0 Set */
-#define IS_OB_BOOT0(BOOT0) (((BOOT0) == OB_BOOT0_RESET) || ((BOOT0) == OB_BOOT0_SET))
-
-/**
- * @}
- */
-
-/** @defgroup FLASH_Option_Bytes_BOOT0SW
- * @{
- */
-
-#define OB_BOOT0_SW ((uint8_t)0x00) /*!< BOOT0 pin disabled */
-#define OB_BOOT0_HW ((uint8_t)0x80) /*!< BOOT0 pin bonded with GPIO */
-#define IS_OB_BOOT0SW(BOOT0) (((BOOT0) == OB_BOOT0_SW) || ((BOOT0) == OB_BOOT0_HW))
-
-/**
- * @}
- */
-
-/** @defgroup FLASH_Option_Bytes_VDDA_Analog_Monitoring
- * @{
- */
-
-#define OB_VDDA_ANALOG_ON ((uint8_t)0x20) /*!< Analog monitoring on VDDA Power source ON */
-#define OB_VDDA_ANALOG_OFF ((uint8_t)0x00) /*!< Analog monitoring on VDDA Power source OFF */
-
-#define IS_OB_VDDA_ANALOG(ANALOG) (((ANALOG) == OB_VDDA_ANALOG_ON) || ((ANALOG) == OB_VDDA_ANALOG_OFF))
-
-/**
- * @}
- */
-
-/** @defgroup FLASH_Option_Bytes_SRAM_Parity_Enable
- * @{
- */
-
-#define OB_SRAM_PARITY_SET ((uint8_t)0x00) /*!< SRAM parity enable Set */
-#define OB_SRAM_PARITY_RESET ((uint8_t)0x40) /*!< SRAM parity enable reset */
-
-#define IS_OB_SRAM_PARITY(PARITY) (((PARITY) == OB_SRAM_PARITY_SET) || ((PARITY) == OB_SRAM_PARITY_RESET))
-
-/**
- * @}
- */
-
-/** @defgroup FLASH_Flags
- * @{
- */
-
-#define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */
-#define FLASH_FLAG_PGERR FLASH_SR_PGERR /*!< FLASH Programming error flag */
-#define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< FLASH Write protected error flag */
-#define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of Programming flag */
-
-#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFCB) == 0x00000000) && ((FLAG) != 0x00000000))
-
-#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_PGERR) || \
- ((FLAG) == FLASH_FLAG_WRPERR) || ((FLAG) == FLASH_FLAG_EOP))
-/**
- * @}
- */
-
-/** @defgroup FLASH_Timeout_definition
- * @{
- */
-#define FLASH_ER_PRG_TIMEOUT ((uint32_t)0x000B0000)
-
-/**
- * @}
- */
-
-/** @defgroup FLASH_Legacy
- * @{
- */
-#define FLASH_WRProt_Pages0to3 OB_WRP_Pages0to3
-#define FLASH_WRProt_Pages4to7 OB_WRP_Pages4to7
-#define FLASH_WRProt_Pages8to11 OB_WRP_Pages8to11
-#define FLASH_WRProt_Pages12to15 OB_WRP_Pages12to15
-#define FLASH_WRProt_Pages16to19 OB_WRP_Pages16to19
-#define FLASH_WRProt_Pages20to23 OB_WRP_Pages20to23
-#define FLASH_WRProt_Pages24to27 OB_WRP_Pages24to27
-#define FLASH_WRProt_Pages28to31 OB_WRP_Pages28to31
-#define FLASH_WRProt_Pages32to35 OB_WRP_Pages32to35
-#define FLASH_WRProt_Pages36to39 OB_WRP_Pages36to39
-#define FLASH_WRProt_Pages40to43 OB_WRP_Pages40to21
-#define FLASH_WRProt_Pages44to47 OB_WRP_Pages44to23
-#define FLASH_WRProt_Pages48to51 OB_WRP_Pages48to51
-#define FLASH_WRProt_Pages52to55 OB_WRP_Pages52to55
-#define FLASH_WRProt_Pages56to59 OB_WRP_Pages56to59
-#define FLASH_WRProt_Pages60to63 OB_WRP_Pages60to63
-
-
-#define FLASH_WRProt_AllPages OB_WRP_AllPages
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-/**
- * @brief FLASH memory functions that can be executed from FLASH.
- */
-/* FLASH Interface configuration functions ************************************/
-void FLASH_SetLatency(uint32_t FLASH_Latency);
-void FLASH_PrefetchBufferCmd(FunctionalState NewState);
-FlagStatus FLASH_GetPrefetchBufferStatus(void);
-
-/* FLASH Memory Programming functions *****************************************/
-void FLASH_Unlock(void);
-void FLASH_Lock(void);
-FLASH_Status FLASH_ErasePage(uint32_t Page_Address);
-FLASH_Status FLASH_EraseAllPages(void);
-FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data);
-FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data);
-
-/* FLASH Option Bytes Programming functions *****************************************/
-void FLASH_OB_Unlock(void);
-void FLASH_OB_Lock(void);
-void FLASH_OB_Launch(void);
-FLASH_Status FLASH_OB_Erase(void);
-FLASH_Status FLASH_OB_EnableWRP(uint32_t OB_WRP);
-FLASH_Status FLASH_OB_RDPConfig(uint8_t OB_RDP);
-FLASH_Status FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY);
-FLASH_Status FLASH_OB_BOOTConfig(uint8_t OB_BOOT1);
-FLASH_Status FLASH_OB_BOOT0Config(uint8_t OB_BOOT0);
-FLASH_Status FLASH_OB_BOOT0SWConfig(uint8_t OB_BOOT0SW);
-FLASH_Status FLASH_OB_VDDAConfig(uint8_t OB_VDDA_ANALOG);
-FLASH_Status FLASH_OB_SRAMParityConfig(uint8_t OB_SRAM_Parity);
-FLASH_Status FLASH_OB_WriteUser(uint8_t OB_USER);
-FLASH_Status FLASH_OB_ProgramData(uint32_t Address, uint8_t Data);
-uint8_t FLASH_OB_GetUser(void);
-uint32_t FLASH_OB_GetWRP(void);
-FlagStatus FLASH_OB_GetRDP(void);
-
-/* FLASH Interrupts and flags management functions **********************************/
-void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState);
-FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG);
-void FLASH_ClearFlag(uint32_t FLASH_FLAG);
-FLASH_Status FLASH_GetStatus(void);
-FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout);
-
-/** @defgroup FLASH_Legacy
- * @{
- */
-#define FLASH_EraseOptionBytes FLASH_OB_Erase
-#define FLASH_EnableWriteProtection FLASH_OB_EnableWRP
-#define FLASH_UserOptionByteConfig FLASH_OB_UserConfig
-#define FLASH_ProgramOptionByteData FLASH_OB_ProgramData
-#define FLASH_GetUserOptionByte FLASH_OB_GetUser
-#define FLASH_GetWriteProtectionOptionByte FLASH_OB_GetWRP
-
-/**
- * @}
- */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F0XX_FLASH_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_gpio.h b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_gpio.h
deleted file mode 100644
index b2625b6a3f027ddecbccc266441b327e38be81b4..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_gpio.h
+++ /dev/null
@@ -1,358 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f0xx_gpio.h
- * @author MCD Application Team
- * @version V1.3.0
- * @date 16-January-2014
- * @brief This file contains all the functions prototypes for the GPIO
- * firmware library.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F0XX_GPIO_H
-#define __STM32F0XX_GPIO_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup GPIO
- * @{
- */
-/* Exported types ------------------------------------------------------------*/
-
-#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \
- ((PERIPH) == GPIOB) || \
- ((PERIPH) == GPIOC) || \
- ((PERIPH) == GPIOD) || \
- ((PERIPH) == GPIOE) || \
- ((PERIPH) == GPIOF))
-
-#define IS_GPIO_LIST_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \
- ((PERIPH) == GPIOB))
-
-/** @defgroup Configuration_Mode_enumeration
- * @{
- */
-typedef enum
-{
- GPIO_Mode_IN = 0x00, /*!< GPIO Input Mode */
- GPIO_Mode_OUT = 0x01, /*!< GPIO Output Mode */
- GPIO_Mode_AF = 0x02, /*!< GPIO Alternate function Mode */
- GPIO_Mode_AN = 0x03 /*!< GPIO Analog In/Out Mode */
-}GPIOMode_TypeDef;
-
-#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_IN)|| ((MODE) == GPIO_Mode_OUT) || \
- ((MODE) == GPIO_Mode_AF)|| ((MODE) == GPIO_Mode_AN))
-/**
- * @}
- */
-
-/** @defgroup Output_type_enumeration
- * @{
- */
-typedef enum
-{
- GPIO_OType_PP = 0x00,
- GPIO_OType_OD = 0x01
-}GPIOOType_TypeDef;
-
-#define IS_GPIO_OTYPE(OTYPE) (((OTYPE) == GPIO_OType_PP) || ((OTYPE) == GPIO_OType_OD))
-
-/**
- * @}
- */
-
-/** @defgroup Output_Maximum_frequency_enumeration
- * @{
- */
-typedef enum
-{
- GPIO_Speed_Level_1 = 0x00, /*!< I/O output speed: Low 2 MHz */
- GPIO_Speed_Level_2 = 0x01, /*!< I/O output speed: Medium 10 MHz */
- GPIO_Speed_Level_3 = 0x03 /*!< I/O output speed: High 50 MHz */
-}GPIOSpeed_TypeDef;
-
-#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_Level_1) || ((SPEED) == GPIO_Speed_Level_2) || \
- ((SPEED) == GPIO_Speed_Level_3))
-/**
- * @}
- */
-
-/** @defgroup Configuration_Pull-Up_Pull-Down_enumeration
- * @{
- */
-typedef enum
-{
- GPIO_PuPd_NOPULL = 0x00,
- GPIO_PuPd_UP = 0x01,
- GPIO_PuPd_DOWN = 0x02
-}GPIOPuPd_TypeDef;
-
-#define IS_GPIO_PUPD(PUPD) (((PUPD) == GPIO_PuPd_NOPULL) || ((PUPD) == GPIO_PuPd_UP) || \
- ((PUPD) == GPIO_PuPd_DOWN))
-/**
- * @}
- */
-
-/** @defgroup Bit_SET_and_Bit_RESET_enumeration
- * @{
- */
-typedef enum
-{
- Bit_RESET = 0,
- Bit_SET
-}BitAction;
-
-#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET))
-/**
- * @}
- */
-
-/**
- * @brief GPIO Init structure definition
- */
-typedef struct
-{
- uint32_t GPIO_Pin; /*!< Specifies the GPIO pins to be configured.
- This parameter can be any value of @ref GPIO_pins_define */
-
- GPIOMode_TypeDef GPIO_Mode; /*!< Specifies the operating mode for the selected pins.
- This parameter can be a value of @ref GPIOMode_TypeDef */
-
- GPIOSpeed_TypeDef GPIO_Speed; /*!< Specifies the speed for the selected pins.
- This parameter can be a value of @ref GPIOSpeed_TypeDef */
-
- GPIOOType_TypeDef GPIO_OType; /*!< Specifies the operating output type for the selected pins.
- This parameter can be a value of @ref GPIOOType_TypeDef */
-
- GPIOPuPd_TypeDef GPIO_PuPd; /*!< Specifies the operating Pull-up/Pull down for the selected pins.
- This parameter can be a value of @ref GPIOPuPd_TypeDef */
-}GPIO_InitTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup GPIO_Exported_Constants
- * @{
- */
-
-/** @defgroup GPIO_pins_define
- * @{
- */
-#define GPIO_Pin_0 ((uint16_t)0x0001) /*!< Pin 0 selected */
-#define GPIO_Pin_1 ((uint16_t)0x0002) /*!< Pin 1 selected */
-#define GPIO_Pin_2 ((uint16_t)0x0004) /*!< Pin 2 selected */
-#define GPIO_Pin_3 ((uint16_t)0x0008) /*!< Pin 3 selected */
-#define GPIO_Pin_4 ((uint16_t)0x0010) /*!< Pin 4 selected */
-#define GPIO_Pin_5 ((uint16_t)0x0020) /*!< Pin 5 selected */
-#define GPIO_Pin_6 ((uint16_t)0x0040) /*!< Pin 6 selected */
-#define GPIO_Pin_7 ((uint16_t)0x0080) /*!< Pin 7 selected */
-#define GPIO_Pin_8 ((uint16_t)0x0100) /*!< Pin 8 selected */
-#define GPIO_Pin_9 ((uint16_t)0x0200) /*!< Pin 9 selected */
-#define GPIO_Pin_10 ((uint16_t)0x0400) /*!< Pin 10 selected */
-#define GPIO_Pin_11 ((uint16_t)0x0800) /*!< Pin 11 selected */
-#define GPIO_Pin_12 ((uint16_t)0x1000) /*!< Pin 12 selected */
-#define GPIO_Pin_13 ((uint16_t)0x2000) /*!< Pin 13 selected */
-#define GPIO_Pin_14 ((uint16_t)0x4000) /*!< Pin 14 selected */
-#define GPIO_Pin_15 ((uint16_t)0x8000) /*!< Pin 15 selected */
-#define GPIO_Pin_All ((uint16_t)0xFFFF) /*!< All pins selected */
-
-#define IS_GPIO_PIN(PIN) ((PIN) != (uint16_t)0x00)
-
-#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \
- ((PIN) == GPIO_Pin_1) || \
- ((PIN) == GPIO_Pin_2) || \
- ((PIN) == GPIO_Pin_3) || \
- ((PIN) == GPIO_Pin_4) || \
- ((PIN) == GPIO_Pin_5) || \
- ((PIN) == GPIO_Pin_6) || \
- ((PIN) == GPIO_Pin_7) || \
- ((PIN) == GPIO_Pin_8) || \
- ((PIN) == GPIO_Pin_9) || \
- ((PIN) == GPIO_Pin_10) || \
- ((PIN) == GPIO_Pin_11) || \
- ((PIN) == GPIO_Pin_12) || \
- ((PIN) == GPIO_Pin_13) || \
- ((PIN) == GPIO_Pin_14) || \
- ((PIN) == GPIO_Pin_15))
-
-/**
- * @}
- */
-
-/** @defgroup GPIO_Pin_sources
- * @{
- */
-#define GPIO_PinSource0 ((uint8_t)0x00)
-#define GPIO_PinSource1 ((uint8_t)0x01)
-#define GPIO_PinSource2 ((uint8_t)0x02)
-#define GPIO_PinSource3 ((uint8_t)0x03)
-#define GPIO_PinSource4 ((uint8_t)0x04)
-#define GPIO_PinSource5 ((uint8_t)0x05)
-#define GPIO_PinSource6 ((uint8_t)0x06)
-#define GPIO_PinSource7 ((uint8_t)0x07)
-#define GPIO_PinSource8 ((uint8_t)0x08)
-#define GPIO_PinSource9 ((uint8_t)0x09)
-#define GPIO_PinSource10 ((uint8_t)0x0A)
-#define GPIO_PinSource11 ((uint8_t)0x0B)
-#define GPIO_PinSource12 ((uint8_t)0x0C)
-#define GPIO_PinSource13 ((uint8_t)0x0D)
-#define GPIO_PinSource14 ((uint8_t)0x0E)
-#define GPIO_PinSource15 ((uint8_t)0x0F)
-
-#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \
- ((PINSOURCE) == GPIO_PinSource1) || \
- ((PINSOURCE) == GPIO_PinSource2) || \
- ((PINSOURCE) == GPIO_PinSource3) || \
- ((PINSOURCE) == GPIO_PinSource4) || \
- ((PINSOURCE) == GPIO_PinSource5) || \
- ((PINSOURCE) == GPIO_PinSource6) || \
- ((PINSOURCE) == GPIO_PinSource7) || \
- ((PINSOURCE) == GPIO_PinSource8) || \
- ((PINSOURCE) == GPIO_PinSource9) || \
- ((PINSOURCE) == GPIO_PinSource10) || \
- ((PINSOURCE) == GPIO_PinSource11) || \
- ((PINSOURCE) == GPIO_PinSource12) || \
- ((PINSOURCE) == GPIO_PinSource13) || \
- ((PINSOURCE) == GPIO_PinSource14) || \
- ((PINSOURCE) == GPIO_PinSource15))
-/**
- * @}
- */
-
-/** @defgroup GPIO_Alternate_function_selection_define
- * @{
- */
-
-/**
- * @brief AF 0 selection
- */
-#define GPIO_AF_0 ((uint8_t)0x00) /* WKUP, EVENTOUT, TIM15, SPI1, TIM17,
- MCO, SWDAT, SWCLK, TIM14, BOOT,
- USART1, CEC, IR_OUT, SPI2, TS, TIM3,
- USART4, CAN, TIM3, USART2, USART3,
- CRS, TIM16, TIM1 */
-/**
- * @brief AF 1 selection
- */
-#define GPIO_AF_1 ((uint8_t)0x01) /* USART2, CEC, TIM3, USART1, IR,
- EVENTOUT, I2C1, I2C2, TIM15, SPI2,
- USART3, TS, SPI1 */
-/**
- * @brief AF 2 selection
- */
-#define GPIO_AF_2 ((uint8_t)0x02) /* TIM2, TIM1, EVENTOUT, TIM16, TIM17,
- USB */
-/**
- * @brief AF 3 selection
- */
-#define GPIO_AF_3 ((uint8_t)0x03) /* TS, I2C1, TIM15, EVENTOUT */
-
-/**
- * @brief AF 4 selection
- */
-#define GPIO_AF_4 ((uint8_t)0x04) /* TIM14, USART4, USART3, CRS, CAN,
- I2C1 */
-
-/**
- * @brief AF 5 selection
- */
-#define GPIO_AF_5 ((uint8_t)0x05) /* TIM16, TIM17, TIM15, SPI2, I2C2,
- MCO, I2C1, USB */
-
-/**
- * @brief AF 6 selection
- */
-#define GPIO_AF_6 ((uint8_t)0x06) /* EVENTOUT */
-/**
- * @brief AF 7 selection
- */
-#define GPIO_AF_7 ((uint8_t)0x07) /* COMP1 OUT and COMP2 OUT */
-
-#define IS_GPIO_AF(AF) (((AF) == GPIO_AF_0) || ((AF) == GPIO_AF_1) || \
- ((AF) == GPIO_AF_2) || ((AF) == GPIO_AF_3) || \
- ((AF) == GPIO_AF_4) || ((AF) == GPIO_AF_5) || \
- ((AF) == GPIO_AF_6) || ((AF) == GPIO_AF_7))
-
-/**
- * @}
- */
-
-/** @defgroup GPIO_Speed_Legacy
- * @{
- */
-
-#define GPIO_Speed_2MHz GPIO_Speed_Level_1 /*!< I/O output speed: Low 2 MHz */
-#define GPIO_Speed_10MHz GPIO_Speed_Level_2 /*!< I/O output speed: Medium 10 MHz */
-#define GPIO_Speed_50MHz GPIO_Speed_Level_3 /*!< I/O output speed: High 50 MHz */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-/* Function used to set the GPIO configuration to the default reset state *****/
-void GPIO_DeInit(GPIO_TypeDef* GPIOx);
-
-/* Initialization and Configuration functions *********************************/
-void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct);
-void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct);
-void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-
-/* GPIO Read and Write functions **********************************************/
-uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx);
-uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx);
-void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal);
-void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal);
-
-/* GPIO Alternate functions configuration functions ***************************/
-void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F0XX_GPIO_H */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_i2c.h b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_i2c.h
deleted file mode 100644
index 1c56b9c9689dd3d9fc205b89b4c8cc9acd13c7a7..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_i2c.h
+++ /dev/null
@@ -1,478 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f0xx_i2c.h
- * @author MCD Application Team
- * @version V1.3.0
- * @date 16-January-2014
- * @brief This file contains all the functions prototypes for the I2C firmware
- * library
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F0XX_I2C_H
-#define __STM32F0XX_I2C_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup I2C
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/**
- * @brief I2C Init structure definition
- */
-
-typedef struct
-{
- uint32_t I2C_Timing; /*!< Specifies the I2C_TIMINGR_register value.
- This parameter must be set by referring to I2C_Timing_Config_Tool*/
-
- uint32_t I2C_AnalogFilter; /*!< Enables or disables analog noise filter.
- This parameter can be a value of @ref I2C_Analog_Filter*/
-
- uint32_t I2C_DigitalFilter; /*!< Configures the digital noise filter.
- This parameter can be a number between 0x00 and 0x0F*/
-
- uint32_t I2C_Mode; /*!< Specifies the I2C mode.
- This parameter can be a value of @ref I2C_mode*/
-
- uint32_t I2C_OwnAddress1; /*!< Specifies the device own address 1.
- This parameter can be a 7-bit or 10-bit address*/
-
- uint32_t I2C_Ack; /*!< Enables or disables the acknowledgement.
- This parameter can be a value of @ref I2C_acknowledgement*/
-
- uint32_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged.
- This parameter can be a value of @ref I2C_acknowledged_address*/
-}I2C_InitTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-
-
-/** @defgroup I2C_Exported_Constants
- * @{
- */
-
-#define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \
- ((PERIPH) == I2C2))
-
-#define IS_I2C_1_PERIPH(PERIPH) ((PERIPH) == I2C1)
-
-/** @defgroup I2C_Analog_Filter
- * @{
- */
-
-#define I2C_AnalogFilter_Enable ((uint32_t)0x00000000)
-#define I2C_AnalogFilter_Disable I2C_CR1_ANFOFF
-
-#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_AnalogFilter_Enable) || \
- ((FILTER) == I2C_AnalogFilter_Disable))
-/**
- * @}
- */
-
-/** @defgroup I2C_Digital_Filter
- * @{
- */
-
-#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000F)
-/**
- * @}
- */
-
-/** @defgroup I2C_mode
- * @{
- */
-
-#define I2C_Mode_I2C ((uint32_t)0x00000000)
-#define I2C_Mode_SMBusDevice I2C_CR1_SMBDEN
-#define I2C_Mode_SMBusHost I2C_CR1_SMBHEN
-
-#define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \
- ((MODE) == I2C_Mode_SMBusDevice) || \
- ((MODE) == I2C_Mode_SMBusHost))
-/**
- * @}
- */
-
-/** @defgroup I2C_acknowledgement
- * @{
- */
-
-#define I2C_Ack_Enable ((uint32_t)0x00000000)
-#define I2C_Ack_Disable I2C_CR2_NACK
-
-#define IS_I2C_ACK(ACK) (((ACK) == I2C_Ack_Enable) || \
- ((ACK) == I2C_Ack_Disable))
-/**
- * @}
- */
-
-/** @defgroup I2C_acknowledged_address
- * @{
- */
-
-#define I2C_AcknowledgedAddress_7bit ((uint32_t)0x00000000)
-#define I2C_AcknowledgedAddress_10bit I2C_OAR1_OA1MODE
-
-#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \
- ((ADDRESS) == I2C_AcknowledgedAddress_10bit))
-/**
- * @}
- */
-
-/** @defgroup I2C_own_address1
- * @{
- */
-
-#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= (uint32_t)0x000003FF)
-/**
- * @}
- */
-
-/** @defgroup I2C_transfer_direction
- * @{
- */
-
-#define I2C_Direction_Transmitter ((uint16_t)0x0000)
-#define I2C_Direction_Receiver ((uint16_t)0x0400)
-
-#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \
- ((DIRECTION) == I2C_Direction_Receiver))
-/**
- * @}
- */
-
-/** @defgroup I2C_DMA_transfer_requests
- * @{
- */
-
-#define I2C_DMAReq_Tx I2C_CR1_TXDMAEN
-#define I2C_DMAReq_Rx I2C_CR1_RXDMAEN
-
-#define IS_I2C_DMA_REQ(REQ) ((((REQ) & (uint32_t)0xFFFF3FFF) == 0x00) && ((REQ) != 0x00))
-/**
- * @}
- */
-
-/** @defgroup I2C_slave_address
- * @{
- */
-
-#define IS_I2C_SLAVE_ADDRESS(ADDRESS) ((ADDRESS) <= (uint16_t)0x03FF)
-/**
- * @}
- */
-
-
-/** @defgroup I2C_own_address2
- * @{
- */
-
-#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FF)
-
-/**
- * @}
- */
-
-/** @defgroup I2C_own_address2_mask
- * @{
- */
-
-#define I2C_OA2_NoMask ((uint8_t)0x00)
-#define I2C_OA2_Mask01 ((uint8_t)0x01)
-#define I2C_OA2_Mask02 ((uint8_t)0x02)
-#define I2C_OA2_Mask03 ((uint8_t)0x03)
-#define I2C_OA2_Mask04 ((uint8_t)0x04)
-#define I2C_OA2_Mask05 ((uint8_t)0x05)
-#define I2C_OA2_Mask06 ((uint8_t)0x06)
-#define I2C_OA2_Mask07 ((uint8_t)0x07)
-
-#define IS_I2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == I2C_OA2_NoMask) || \
- ((MASK) == I2C_OA2_Mask01) || \
- ((MASK) == I2C_OA2_Mask02) || \
- ((MASK) == I2C_OA2_Mask03) || \
- ((MASK) == I2C_OA2_Mask04) || \
- ((MASK) == I2C_OA2_Mask05) || \
- ((MASK) == I2C_OA2_Mask06) || \
- ((MASK) == I2C_OA2_Mask07))
-
-/**
- * @}
- */
-
-/** @defgroup I2C_timeout
- * @{
- */
-
-#define IS_I2C_TIMEOUT(TIMEOUT) ((TIMEOUT) <= (uint16_t)0x0FFF)
-
-/**
- * @}
- */
-
-/** @defgroup I2C_registers
- * @{
- */
-
-#define I2C_Register_CR1 ((uint8_t)0x00)
-#define I2C_Register_CR2 ((uint8_t)0x04)
-#define I2C_Register_OAR1 ((uint8_t)0x08)
-#define I2C_Register_OAR2 ((uint8_t)0x0C)
-#define I2C_Register_TIMINGR ((uint8_t)0x10)
-#define I2C_Register_TIMEOUTR ((uint8_t)0x14)
-#define I2C_Register_ISR ((uint8_t)0x18)
-#define I2C_Register_ICR ((uint8_t)0x1C)
-#define I2C_Register_PECR ((uint8_t)0x20)
-#define I2C_Register_RXDR ((uint8_t)0x24)
-#define I2C_Register_TXDR ((uint8_t)0x28)
-
-#define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \
- ((REGISTER) == I2C_Register_CR2) || \
- ((REGISTER) == I2C_Register_OAR1) || \
- ((REGISTER) == I2C_Register_OAR2) || \
- ((REGISTER) == I2C_Register_TIMINGR) || \
- ((REGISTER) == I2C_Register_TIMEOUTR) || \
- ((REGISTER) == I2C_Register_ISR) || \
- ((REGISTER) == I2C_Register_ICR) || \
- ((REGISTER) == I2C_Register_PECR) || \
- ((REGISTER) == I2C_Register_RXDR) || \
- ((REGISTER) == I2C_Register_TXDR))
-/**
- * @}
- */
-
-/** @defgroup I2C_interrupts_definition
- * @{
- */
-
-#define I2C_IT_ERRI I2C_CR1_ERRIE
-#define I2C_IT_TCI I2C_CR1_TCIE
-#define I2C_IT_STOPI I2C_CR1_STOPIE
-#define I2C_IT_NACKI I2C_CR1_NACKIE
-#define I2C_IT_ADDRI I2C_CR1_ADDRIE
-#define I2C_IT_RXI I2C_CR1_RXIE
-#define I2C_IT_TXI I2C_CR1_TXIE
-
-#define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint32_t)0xFFFFFF01) == 0x00) && ((IT) != 0x00))
-
-/**
- * @}
- */
-
-/** @defgroup I2C_flags_definition
- * @{
- */
-
-#define I2C_FLAG_TXE I2C_ISR_TXE
-#define I2C_FLAG_TXIS I2C_ISR_TXIS
-#define I2C_FLAG_RXNE I2C_ISR_RXNE
-#define I2C_FLAG_ADDR I2C_ISR_ADDR
-#define I2C_FLAG_NACKF I2C_ISR_NACKF
-#define I2C_FLAG_STOPF I2C_ISR_STOPF
-#define I2C_FLAG_TC I2C_ISR_TC
-#define I2C_FLAG_TCR I2C_ISR_TCR
-#define I2C_FLAG_BERR I2C_ISR_BERR
-#define I2C_FLAG_ARLO I2C_ISR_ARLO
-#define I2C_FLAG_OVR I2C_ISR_OVR
-#define I2C_FLAG_PECERR I2C_ISR_PECERR
-#define I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT
-#define I2C_FLAG_ALERT I2C_ISR_ALERT
-#define I2C_FLAG_BUSY I2C_ISR_BUSY
-
-#define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFF4000) == 0x00) && ((FLAG) != 0x00))
-
-#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_TXIS) || \
- ((FLAG) == I2C_FLAG_RXNE) || ((FLAG) == I2C_FLAG_ADDR) || \
- ((FLAG) == I2C_FLAG_NACKF) || ((FLAG) == I2C_FLAG_STOPF) || \
- ((FLAG) == I2C_FLAG_TC) || ((FLAG) == I2C_FLAG_TCR) || \
- ((FLAG) == I2C_FLAG_BERR) || ((FLAG) == I2C_FLAG_ARLO) || \
- ((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_PECERR) || \
- ((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_ALERT) || \
- ((FLAG) == I2C_FLAG_BUSY))
-
-/**
- * @}
- */
-
-
-/** @defgroup I2C_interrupts_definition
- * @{
- */
-
-#define I2C_IT_TXIS I2C_ISR_TXIS
-#define I2C_IT_RXNE I2C_ISR_RXNE
-#define I2C_IT_ADDR I2C_ISR_ADDR
-#define I2C_IT_NACKF I2C_ISR_NACKF
-#define I2C_IT_STOPF I2C_ISR_STOPF
-#define I2C_IT_TC I2C_ISR_TC
-#define I2C_IT_TCR I2C_ISR_TCR
-#define I2C_IT_BERR I2C_ISR_BERR
-#define I2C_IT_ARLO I2C_ISR_ARLO
-#define I2C_IT_OVR I2C_ISR_OVR
-#define I2C_IT_PECERR I2C_ISR_PECERR
-#define I2C_IT_TIMEOUT I2C_ISR_TIMEOUT
-#define I2C_IT_ALERT I2C_ISR_ALERT
-
-#define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFFFFC001) == 0x00) && ((IT) != 0x00))
-
-#define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_TXIS) || ((IT) == I2C_IT_RXNE) || \
- ((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_NACKF) || \
- ((IT) == I2C_IT_STOPF) || ((IT) == I2C_IT_TC) || \
- ((IT) == I2C_IT_TCR) || ((IT) == I2C_IT_BERR) || \
- ((IT) == I2C_IT_ARLO) || ((IT) == I2C_IT_OVR) || \
- ((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_TIMEOUT) || \
- ((IT) == I2C_IT_ALERT))
-
-
-/**
- * @}
- */
-
-/** @defgroup I2C_ReloadEndMode_definition
- * @{
- */
-
-#define I2C_Reload_Mode I2C_CR2_RELOAD
-#define I2C_AutoEnd_Mode I2C_CR2_AUTOEND
-#define I2C_SoftEnd_Mode ((uint32_t)0x00000000)
-
-
-#define IS_RELOAD_END_MODE(MODE) (((MODE) == I2C_Reload_Mode) || \
- ((MODE) == I2C_AutoEnd_Mode) || \
- ((MODE) == I2C_SoftEnd_Mode))
-
-
-/**
- * @}
- */
-
-/** @defgroup I2C_StartStopMode_definition
- * @{
- */
-
-#define I2C_No_StartStop ((uint32_t)0x00000000)
-#define I2C_Generate_Stop I2C_CR2_STOP
-#define I2C_Generate_Start_Read (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)
-#define I2C_Generate_Start_Write I2C_CR2_START
-
-
-#define IS_START_STOP_MODE(MODE) (((MODE) == I2C_Generate_Stop) || \
- ((MODE) == I2C_Generate_Start_Read) || \
- ((MODE) == I2C_Generate_Start_Write) || \
- ((MODE) == I2C_No_StartStop))
-
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-
-/* Initialization and Configuration functions *********************************/
-void I2C_DeInit(I2C_TypeDef* I2Cx);
-void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct);
-void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct);
-void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx);
-void I2C_ITConfig(I2C_TypeDef* I2Cx, uint32_t I2C_IT, FunctionalState NewState);
-void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_StopModeCmd(I2C_TypeDef* I2Cx, FunctionalState NewState); /*!< not applicable for STM32F030 devices */
-void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint16_t Address, uint8_t Mask);
-void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_SlaveByteControlCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_SlaveAddressConfig(I2C_TypeDef* I2Cx, uint16_t Address);
-void I2C_10BitAddressingModeCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-
-/* Communications handling functions ******************************************/
-void I2C_AutoEndCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_ReloadCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_NumberOfBytesConfig(I2C_TypeDef* I2Cx, uint8_t Number_Bytes);
-void I2C_MasterRequestConfig(I2C_TypeDef* I2Cx, uint16_t I2C_Direction);
-void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_10BitAddressHeaderCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState);
-uint8_t I2C_GetAddressMatched(I2C_TypeDef* I2Cx);
-uint16_t I2C_GetTransferDirection(I2C_TypeDef* I2Cx);
-void I2C_TransferHandling(I2C_TypeDef* I2Cx, uint16_t Address, uint8_t Number_Bytes, uint32_t ReloadEndMode, uint32_t StartStopMode);
-
-/* SMBUS management functions ************************************************/
-void I2C_SMBusAlertCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_ClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_ExtendedClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_IdleClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_TimeoutAConfig(I2C_TypeDef* I2Cx, uint16_t Timeout);
-void I2C_TimeoutBConfig(I2C_TypeDef* I2Cx, uint16_t Timeout);
-void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
-void I2C_PECRequestCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
-uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx);
-
-/* I2C registers management functions *****************************************/
-uint32_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register);
-
-/* Data transfers management functions ****************************************/
-void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data);
-uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx);
-
-/* DMA transfers management functions *****************************************/
-void I2C_DMACmd(I2C_TypeDef* I2Cx, uint32_t I2C_DMAReq, FunctionalState NewState);
-
-/* Interrupts and flags management functions **********************************/
-FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
-void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
-ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
-void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F0XX_I2C_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_iwdg.h b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_iwdg.h
deleted file mode 100644
index 4ad0f3827239e1a42f8b7247db7f55fee54feb39..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_iwdg.h
+++ /dev/null
@@ -1,140 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f0xx_iwdg.h
- * @author MCD Application Team
- * @version V1.3.0
- * @date 16-January-2014
- * @brief This file contains all the functions prototypes for the IWDG
- * firmware library.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F0XX_IWDG_H
-#define __STM32F0XX_IWDG_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup IWDG
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup IWDG_Exported_Constants
- * @{
- */
-
-/** @defgroup IWDG_WriteAccess
- * @{
- */
-
-#define IWDG_WriteAccess_Enable ((uint16_t)0x5555)
-#define IWDG_WriteAccess_Disable ((uint16_t)0x0000)
-#define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \
- ((ACCESS) == IWDG_WriteAccess_Disable))
-/**
- * @}
- */
-
-/** @defgroup IWDG_prescaler
- * @{
- */
-
-#define IWDG_Prescaler_4 ((uint8_t)0x00)
-#define IWDG_Prescaler_8 ((uint8_t)0x01)
-#define IWDG_Prescaler_16 ((uint8_t)0x02)
-#define IWDG_Prescaler_32 ((uint8_t)0x03)
-#define IWDG_Prescaler_64 ((uint8_t)0x04)
-#define IWDG_Prescaler_128 ((uint8_t)0x05)
-#define IWDG_Prescaler_256 ((uint8_t)0x06)
-#define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4) || \
- ((PRESCALER) == IWDG_Prescaler_8) || \
- ((PRESCALER) == IWDG_Prescaler_16) || \
- ((PRESCALER) == IWDG_Prescaler_32) || \
- ((PRESCALER) == IWDG_Prescaler_64) || \
- ((PRESCALER) == IWDG_Prescaler_128)|| \
- ((PRESCALER) == IWDG_Prescaler_256))
-/**
- * @}
- */
-
-/** @defgroup IWDG_Flag
- * @{
- */
-
-#define IWDG_FLAG_PVU IWDG_SR_PVU
-#define IWDG_FLAG_RVU IWDG_SR_RVU
-#define IWDG_FLAG_WVU IWDG_SR_WVU
-#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU) || \
- ((FLAG) == IWDG_FLAG_WVU))
-
-#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF)
-
-#define IS_IWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0xFFF)
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-/* Prescaler and Counter configuration functions ******************************/
-void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess);
-void IWDG_SetPrescaler(uint8_t IWDG_Prescaler);
-void IWDG_SetReload(uint16_t Reload);
-void IWDG_ReloadCounter(void);
-void IWDG_SetWindowValue(uint16_t WindowValue);
-
-/* IWDG activation function ***************************************************/
-void IWDG_Enable(void);
-
-/* Flag management function ***************************************************/
-FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F0XX_IWDG_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_misc.h b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_misc.h
deleted file mode 100644
index f5ea6bd5820b570fcd923f6f4d347648a40c93bc..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_misc.h
+++ /dev/null
@@ -1,143 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f0xx_misc.h
- * @author MCD Application Team
- * @version V1.3.0
- * @date 16-January-2014
- * @brief This file contains all the functions prototypes for the miscellaneous
- * firmware library functions (add-on to CMSIS functions).
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F0XX_MISC_H
-#define __STM32F0XX_MISC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup MISC
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/**
- * @brief NVIC Init Structure definition
- */
-
-typedef struct
-{
- uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled.
- This parameter can be a value of @ref IRQn_Type
- (For the complete STM32 Devices IRQ Channels list,
- please refer to stm32f0xx.h file) */
-
- uint8_t NVIC_IRQChannelPriority; /*!< Specifies the priority level for the IRQ channel specified
- in NVIC_IRQChannel. This parameter can be a value
- between 0 and 3. */
-
- FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel
- will be enabled or disabled.
- This parameter can be set either to ENABLE or DISABLE */
-} NVIC_InitTypeDef;
-
-/**
- *
-@verbatim
-
-@endverbatim
-*/
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup MISC_Exported_Constants
- * @{
- */
-
-/** @defgroup MISC_System_Low_Power
- * @{
- */
-
-#define NVIC_LP_SEVONPEND ((uint8_t)0x10)
-#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04)
-#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02)
-#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \
- ((LP) == NVIC_LP_SLEEPDEEP) || \
- ((LP) == NVIC_LP_SLEEPONEXIT))
-/**
- * @}
- */
-
-/** @defgroup MISC_Preemption_Priority_Group
- * @{
- */
-#define IS_NVIC_PRIORITY(PRIORITY) ((PRIORITY) < 0x04)
-
-/**
- * @}
- */
-
-/** @defgroup MISC_SysTick_clock_source
- * @{
- */
-
-#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB)
-#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004)
-#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \
- ((SOURCE) == SysTick_CLKSource_HCLK_Div8))
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);
-void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState);
-void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F0XX_MISC_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_pwr.h b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_pwr.h
deleted file mode 100644
index 491368c193e71d0d7eaa3ffe09396fb442c53568..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_pwr.h
+++ /dev/null
@@ -1,197 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f0xx_pwr.h
- * @author MCD Application Team
- * @version V1.3.0
- * @date 16-January-2014
- * @brief This file contains all the functions prototypes for the PWR firmware
- * library.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F0XX_PWR_H
-#define __STM32F0XX_PWR_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup PWR
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup PWR_Exported_Constants
- * @{
- */
-
-/** @defgroup PWR_PVD_detection_level
- * @brief This parameters are only applicable for STM32F051 and STM32F072 devices
- * @{
- */
-
-#define PWR_PVDLevel_0 PWR_CR_PLS_LEV0
-#define PWR_PVDLevel_1 PWR_CR_PLS_LEV1
-#define PWR_PVDLevel_2 PWR_CR_PLS_LEV2
-#define PWR_PVDLevel_3 PWR_CR_PLS_LEV3
-#define PWR_PVDLevel_4 PWR_CR_PLS_LEV4
-#define PWR_PVDLevel_5 PWR_CR_PLS_LEV5
-#define PWR_PVDLevel_6 PWR_CR_PLS_LEV6
-#define PWR_PVDLevel_7 PWR_CR_PLS_LEV7
-
-#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_0) || ((LEVEL) == PWR_PVDLevel_1)|| \
- ((LEVEL) == PWR_PVDLevel_2) || ((LEVEL) == PWR_PVDLevel_3)|| \
- ((LEVEL) == PWR_PVDLevel_4) || ((LEVEL) == PWR_PVDLevel_5)|| \
- ((LEVEL) == PWR_PVDLevel_6) || ((LEVEL) == PWR_PVDLevel_7))
-/**
- * @}
- */
-
-/** @defgroup PWR_WakeUp_Pins
- * @{
- */
-
-#define PWR_WakeUpPin_1 PWR_CSR_EWUP1
-#define PWR_WakeUpPin_2 PWR_CSR_EWUP2
-#define PWR_WakeUpPin_3 PWR_CSR_EWUP3 /*!< only applicable for STM32F072 devices */
-#define PWR_WakeUpPin_4 PWR_CSR_EWUP4 /*!< only applicable for STM32F072 devices */
-#define PWR_WakeUpPin_5 PWR_CSR_EWUP5 /*!< only applicable for STM32F072 devices */
-#define PWR_WakeUpPin_6 PWR_CSR_EWUP6 /*!< only applicable for STM32F072 devices */
-#define PWR_WakeUpPin_7 PWR_CSR_EWUP7 /*!< only applicable for STM32F072 devices */
-#define PWR_WakeUpPin_8 PWR_CSR_EWUP8 /*!< only applicable for STM32F072 devices */
-#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WakeUpPin_1) || ((PIN) == PWR_WakeUpPin_2) || \
- ((PIN) == PWR_WakeUpPin_3) || ((PIN) == PWR_WakeUpPin_4) || \
- ((PIN) == PWR_WakeUpPin_5) || ((PIN) == PWR_WakeUpPin_6) || \
- ((PIN) == PWR_WakeUpPin_7) || ((PIN) == PWR_WakeUpPin_8))
-/**
- * @}
- */
-
-
-/** @defgroup PWR_Regulator_state_is_Sleep_STOP_mode
- * @{
- */
-
-#define PWR_Regulator_ON ((uint32_t)0x00000000)
-#define PWR_Regulator_LowPower PWR_CR_LPSDSR
-#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \
- ((REGULATOR) == PWR_Regulator_LowPower))
-/**
- * @}
- */
-
-/** @defgroup PWR_SLEEP_mode_entry
- * @{
- */
-
-#define PWR_SLEEPEntry_WFI ((uint8_t)0x01)
-#define PWR_SLEEPEntry_WFE ((uint8_t)0x02)
-#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPEntry_WFI) || ((ENTRY) == PWR_SLEEPEntry_WFE))
-
-/**
- * @}
- */
-
-/** @defgroup PWR_STOP_mode_entry
- * @{
- */
-
-#define PWR_STOPEntry_WFI ((uint8_t)0x01)
-#define PWR_STOPEntry_WFE ((uint8_t)0x02)
-#define PWR_STOPEntry_SLEEPONEXIT ((uint8_t)0x03)
-#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE) ||\
- ((ENTRY) == PWR_STOPEntry_SLEEPONEXIT))
-
-/**
- * @}
- */
-
-/** @defgroup PWR_Flag
- * @{
- */
-
-#define PWR_FLAG_WU PWR_CSR_WUF
-#define PWR_FLAG_SB PWR_CSR_SBF
-#define PWR_FLAG_PVDO PWR_CSR_PVDO /*!< Not applicable for STM32F030 devices */
-#define PWR_FLAG_VREFINTRDY PWR_CSR_VREFINTRDYF
-
-#define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \
- ((FLAG) == PWR_FLAG_PVDO) || ((FLAG) == PWR_FLAG_VREFINTRDY))
-
-#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB))
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-/* Function used to set the PWR configuration to the default reset state ******/
-void PWR_DeInit(void);
-
-/* Backup Domain Access function **********************************************/
-void PWR_BackupAccessCmd(FunctionalState NewState);
-
-/* PVD configuration functions ************************************************/
-void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel); /*!< only applicable for STM32F051 and STM32F072 devices */
-void PWR_PVDCmd(FunctionalState NewState); /*!< only applicable for STM32F051 and STM32F072 devices */
-
-/* WakeUp pins configuration functions ****************************************/
-void PWR_WakeUpPinCmd(uint32_t PWR_WakeUpPin, FunctionalState NewState);
-
-/* Low Power modes configuration functions ************************************/
-void PWR_EnterSleepMode(uint8_t PWR_SLEEPEntry);
-void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);
-void PWR_EnterSTANDBYMode(void);
-
-/* Flags management functions *************************************************/
-FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG);
-void PWR_ClearFlag(uint32_t PWR_FLAG);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F0XX_PWR_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_rcc.h b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_rcc.h
deleted file mode 100644
index cd0899c31795bf9792ac9866e362bb3396793b99..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_rcc.h
+++ /dev/null
@@ -1,608 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f0xx_rcc.h
- * @author MCD Application Team
- * @version V1.3.0
- * @date 16-January-2014
- * @brief This file contains all the functions prototypes for the RCC
- * firmware library.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F0XX_RCC_H
-#define __STM32F0XX_RCC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup RCC
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-typedef struct
-{
- uint32_t SYSCLK_Frequency;
- uint32_t HCLK_Frequency;
- uint32_t PCLK_Frequency;
- uint32_t ADCCLK_Frequency;
- uint32_t CECCLK_Frequency;
- uint32_t I2C1CLK_Frequency;
- uint32_t USART1CLK_Frequency;
- uint32_t USART2CLK_Frequency; /*!< Only applicable for STM32F072 devices */
- uint32_t USBCLK_Frequency; /*!< Only applicable for STM32F072 devices */
-}RCC_ClocksTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup RCC_Exported_Constants
- * @{
- */
-
-/** @defgroup RCC_HSE_configuration
- * @{
- */
-
-#define RCC_HSE_OFF ((uint8_t)0x00)
-#define RCC_HSE_ON ((uint8_t)0x01)
-#define RCC_HSE_Bypass ((uint8_t)0x05)
-#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
- ((HSE) == RCC_HSE_Bypass))
-
-/**
- * @}
- */
-
-/** @defgroup RCC_PLL_Clock_Source
- * @{
- */
-
-#define RCC_PLLSource_HSI_Div2 RCC_CFGR_PLLSRC_HSI_Div2
-#define RCC_PLLSource_PREDIV1 RCC_CFGR_PLLSRC_HSE_PREDIV /* Old HSEPREDIV1 bit definition, maintained for legacy purpose */
-#define RCC_PLLSource_HSE RCC_CFGR_PLLSRC_HSE_PREDIV /*!< Only applicable for STM32F072 devices */
-#define RCC_PLLSource_HSI48 RCC_CFGR_PLLSRC_HSI48_PREDIV /*!< Only applicable for STM32F072 devices */
-#define RCC_PLLSource_HSI RCC_CFGR_PLLSRC_HSI_PREDIV /*!< Only applicable for STM32F072 devices */
-
-#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \
- ((SOURCE) == RCC_PLLSource_HSI48) || \
- ((SOURCE) == RCC_PLLSource_HSI) || \
- ((SOURCE) == RCC_PLLSource_HSE) || \
- ((SOURCE) == RCC_PLLSource_PREDIV1))
-/**
- * @}
- */
-
-/** @defgroup RCC_PLL_Multiplication_Factor
- * @{
- */
-
-#define RCC_PLLMul_2 RCC_CFGR_PLLMULL2
-#define RCC_PLLMul_3 RCC_CFGR_PLLMULL3
-#define RCC_PLLMul_4 RCC_CFGR_PLLMULL4
-#define RCC_PLLMul_5 RCC_CFGR_PLLMULL5
-#define RCC_PLLMul_6 RCC_CFGR_PLLMULL6
-#define RCC_PLLMul_7 RCC_CFGR_PLLMULL7
-#define RCC_PLLMul_8 RCC_CFGR_PLLMULL8
-#define RCC_PLLMul_9 RCC_CFGR_PLLMULL9
-#define RCC_PLLMul_10 RCC_CFGR_PLLMULL10
-#define RCC_PLLMul_11 RCC_CFGR_PLLMULL11
-#define RCC_PLLMul_12 RCC_CFGR_PLLMULL12
-#define RCC_PLLMul_13 RCC_CFGR_PLLMULL13
-#define RCC_PLLMul_14 RCC_CFGR_PLLMULL14
-#define RCC_PLLMul_15 RCC_CFGR_PLLMULL15
-#define RCC_PLLMul_16 RCC_CFGR_PLLMULL16
-#define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3) || \
- ((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \
- ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \
- ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \
- ((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || \
- ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || \
- ((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || \
- ((MUL) == RCC_PLLMul_16))
-/**
- * @}
- */
-
-/** @defgroup RCC_PREDIV1_division_factor
- * @{
- */
-#define RCC_PREDIV1_Div1 RCC_CFGR2_PREDIV1_DIV1
-#define RCC_PREDIV1_Div2 RCC_CFGR2_PREDIV1_DIV2
-#define RCC_PREDIV1_Div3 RCC_CFGR2_PREDIV1_DIV3
-#define RCC_PREDIV1_Div4 RCC_CFGR2_PREDIV1_DIV4
-#define RCC_PREDIV1_Div5 RCC_CFGR2_PREDIV1_DIV5
-#define RCC_PREDIV1_Div6 RCC_CFGR2_PREDIV1_DIV6
-#define RCC_PREDIV1_Div7 RCC_CFGR2_PREDIV1_DIV7
-#define RCC_PREDIV1_Div8 RCC_CFGR2_PREDIV1_DIV8
-#define RCC_PREDIV1_Div9 RCC_CFGR2_PREDIV1_DIV9
-#define RCC_PREDIV1_Div10 RCC_CFGR2_PREDIV1_DIV10
-#define RCC_PREDIV1_Div11 RCC_CFGR2_PREDIV1_DIV11
-#define RCC_PREDIV1_Div12 RCC_CFGR2_PREDIV1_DIV12
-#define RCC_PREDIV1_Div13 RCC_CFGR2_PREDIV1_DIV13
-#define RCC_PREDIV1_Div14 RCC_CFGR2_PREDIV1_DIV14
-#define RCC_PREDIV1_Div15 RCC_CFGR2_PREDIV1_DIV15
-#define RCC_PREDIV1_Div16 RCC_CFGR2_PREDIV1_DIV16
-
-#define IS_RCC_PREDIV1(PREDIV1) (((PREDIV1) == RCC_PREDIV1_Div1) || ((PREDIV1) == RCC_PREDIV1_Div2) || \
- ((PREDIV1) == RCC_PREDIV1_Div3) || ((PREDIV1) == RCC_PREDIV1_Div4) || \
- ((PREDIV1) == RCC_PREDIV1_Div5) || ((PREDIV1) == RCC_PREDIV1_Div6) || \
- ((PREDIV1) == RCC_PREDIV1_Div7) || ((PREDIV1) == RCC_PREDIV1_Div8) || \
- ((PREDIV1) == RCC_PREDIV1_Div9) || ((PREDIV1) == RCC_PREDIV1_Div10) || \
- ((PREDIV1) == RCC_PREDIV1_Div11) || ((PREDIV1) == RCC_PREDIV1_Div12) || \
- ((PREDIV1) == RCC_PREDIV1_Div13) || ((PREDIV1) == RCC_PREDIV1_Div14) || \
- ((PREDIV1) == RCC_PREDIV1_Div15) || ((PREDIV1) == RCC_PREDIV1_Div16))
-/**
- * @}
- */
-
-/** @defgroup RCC_System_Clock_Source
- * @{
- */
-
-#define RCC_SYSCLKSource_HSI RCC_CFGR_SW_HSI
-#define RCC_SYSCLKSource_HSE RCC_CFGR_SW_HSE
-#define RCC_SYSCLKSource_PLLCLK RCC_CFGR_SW_PLL
-#define RCC_SYSCLKSource_HSI48 RCC_CFGR_SW_HSI48 /*!< Only applicable for STM32F072 devices */
-
-#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \
- ((SOURCE) == RCC_SYSCLKSource_HSE) || \
- ((SOURCE) == RCC_SYSCLKSource_HSI48) || \
- ((SOURCE) == RCC_SYSCLKSource_PLLCLK))
-/**
- * @}
- */
-
-/** @defgroup RCC_AHB_Clock_Source
- * @{
- */
-
-#define RCC_SYSCLK_Div1 RCC_CFGR_HPRE_DIV1
-#define RCC_SYSCLK_Div2 RCC_CFGR_HPRE_DIV2
-#define RCC_SYSCLK_Div4 RCC_CFGR_HPRE_DIV4
-#define RCC_SYSCLK_Div8 RCC_CFGR_HPRE_DIV8
-#define RCC_SYSCLK_Div16 RCC_CFGR_HPRE_DIV16
-#define RCC_SYSCLK_Div64 RCC_CFGR_HPRE_DIV64
-#define RCC_SYSCLK_Div128 RCC_CFGR_HPRE_DIV128
-#define RCC_SYSCLK_Div256 RCC_CFGR_HPRE_DIV256
-#define RCC_SYSCLK_Div512 RCC_CFGR_HPRE_DIV512
-#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \
- ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \
- ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \
- ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \
- ((HCLK) == RCC_SYSCLK_Div512))
-/**
- * @}
- */
-
-/** @defgroup RCC_APB_Clock_Source
- * @{
- */
-
-#define RCC_HCLK_Div1 RCC_CFGR_PPRE_DIV1
-#define RCC_HCLK_Div2 RCC_CFGR_PPRE_DIV2
-#define RCC_HCLK_Div4 RCC_CFGR_PPRE_DIV4
-#define RCC_HCLK_Div8 RCC_CFGR_PPRE_DIV8
-#define RCC_HCLK_Div16 RCC_CFGR_PPRE_DIV16
-#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \
- ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \
- ((PCLK) == RCC_HCLK_Div16))
-/**
- * @}
- */
-
-/** @defgroup RCC_ADC_clock_source
- * @{
- */
-/* These defines are obsolete and kept for legacy purpose only.
-Proper ADC clock selection is done within ADC driver by mean of the ADC_ClockModeConfig() function */
-#define RCC_ADCCLK_HSI14 ((uint32_t)0x00000000)
-#define RCC_ADCCLK_PCLK_Div2 ((uint32_t)0x01000000)
-#define RCC_ADCCLK_PCLK_Div4 ((uint32_t)0x01004000)
-
-#define IS_RCC_ADCCLK(ADCCLK) (((ADCCLK) == RCC_ADCCLK_HSI14) || ((ADCCLK) == RCC_ADCCLK_PCLK_Div2) || \
- ((ADCCLK) == RCC_ADCCLK_PCLK_Div4))
-
-/**
- * @}
- */
-
-/** @defgroup RCC_CEC_clock_source
- * @{
- */
-
-#define RCC_CECCLK_HSI_Div244 ((uint32_t)0x00000000)
-#define RCC_CECCLK_LSE RCC_CFGR3_CECSW
-
-#define IS_RCC_CECCLK(CECCLK) (((CECCLK) == RCC_CECCLK_HSI_Div244) || ((CECCLK) == RCC_CECCLK_LSE))
-
-/**
- * @}
- */
-
-/** @defgroup RCC_I2C_clock_source
- * @{
- */
-
-#define RCC_I2C1CLK_HSI ((uint32_t)0x00000000)
-#define RCC_I2C1CLK_SYSCLK RCC_CFGR3_I2C1SW
-
-#define IS_RCC_I2CCLK(I2CCLK) (((I2CCLK) == RCC_I2C1CLK_HSI) || ((I2CCLK) == RCC_I2C1CLK_SYSCLK))
-
-/**
- * @}
- */
-
-/** @defgroup RCC_USB_clock_source
- * @brief Applicable only for STM32F072 devices
- * @{
- */
-
-#define RCC_USBCLK_HSI48 ((uint32_t)0x00000000)
-#define RCC_USBCLK_PLLCLK RCC_CFGR3_USBSW
-
-#define IS_RCC_USBCLK(USBCLK) (((USBCLK) == RCC_USBCLK_HSI48) || ((USBCLK) == RCC_USBCLK_PLLCLK))
-
-/**
- * @}
- */
-
-/** @defgroup RCC_USART_clock_source
- * @{
- */
-
-#define RCC_USART1CLK_PCLK ((uint32_t)0x10000000)
-#define RCC_USART1CLK_SYSCLK ((uint32_t)0x10000001)
-#define RCC_USART1CLK_LSE ((uint32_t)0x10000002)
-#define RCC_USART1CLK_HSI ((uint32_t)0x10000003)
-
-#define RCC_USART2CLK_PCLK ((uint32_t)0x20000000) /*!< Only applicable for STM32F072 devices */
-#define RCC_USART2CLK_SYSCLK ((uint32_t)0x20010000) /*!< Only applicable for STM32F072 devices */
-#define RCC_USART2CLK_LSE ((uint32_t)0x20020000) /*!< Only applicable for STM32F072 devices */
-#define RCC_USART2CLK_HSI ((uint32_t)0x20030000) /*!< Only applicable for STM32F072 devices */
-
-#define IS_RCC_USARTCLK(USARTCLK) (((USARTCLK) == RCC_USART1CLK_PCLK) || \
- ((USARTCLK) == RCC_USART1CLK_SYSCLK) || \
- ((USARTCLK) == RCC_USART1CLK_LSE) || \
- ((USARTCLK) == RCC_USART1CLK_HSI) || \
- ((USARTCLK) == RCC_USART2CLK_PCLK) || \
- ((USARTCLK) == RCC_USART2CLK_SYSCLK) || \
- ((USARTCLK) == RCC_USART2CLK_LSE) || \
- ((USARTCLK) == RCC_USART2CLK_HSI))
-
-/**
- * @}
- */
-
-/** @defgroup RCC_Interrupt_Source
- * @{
- */
-
-#define RCC_IT_LSIRDY ((uint8_t)0x01)
-#define RCC_IT_LSERDY ((uint8_t)0x02)
-#define RCC_IT_HSIRDY ((uint8_t)0x04)
-#define RCC_IT_HSERDY ((uint8_t)0x08)
-#define RCC_IT_PLLRDY ((uint8_t)0x10)
-#define RCC_IT_HSI14RDY ((uint8_t)0x20)
-#define RCC_IT_HSI48RDY ((uint8_t)0x40) /*!< Only applicable for STM32F072 devices */
-#define RCC_IT_CSS ((uint8_t)0x80)
-
-#define IS_RCC_IT(IT) ((((IT) & (uint8_t)0x80) == 0x00) && ((IT) != 0x00))
-
-#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
- ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
- ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_HSI14RDY) || \
- ((IT) == RCC_IT_CSS) || ((IT) == RCC_IT_HSI48RDY))
-
-#define IS_RCC_CLEAR_IT(IT) ((IT) != 0x00)
-
-/**
- * @}
- */
-
-/** @defgroup RCC_LSE_Configuration
- * @{
- */
-
-#define RCC_LSE_OFF ((uint32_t)0x00000000)
-#define RCC_LSE_ON RCC_BDCR_LSEON
-#define RCC_LSE_Bypass ((uint32_t)(RCC_BDCR_LSEON | RCC_BDCR_LSEBYP))
-#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
- ((LSE) == RCC_LSE_Bypass))
-/**
- * @}
- */
-
-/** @defgroup RCC_RTC_Clock_Source
- * @{
- */
-
-#define RCC_RTCCLKSource_LSE RCC_BDCR_RTCSEL_LSE
-#define RCC_RTCCLKSource_LSI RCC_BDCR_RTCSEL_LSI
-#define RCC_RTCCLKSource_HSE_Div32 RCC_BDCR_RTCSEL_HSE
-
-#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \
- ((SOURCE) == RCC_RTCCLKSource_LSI) || \
- ((SOURCE) == RCC_RTCCLKSource_HSE_Div32))
-/**
- * @}
- */
-
-/** @defgroup RCC_LSE_Drive_Configuration
- * @{
- */
-
-#define RCC_LSEDrive_Low ((uint32_t)0x00000000)
-#define RCC_LSEDrive_MediumLow RCC_BDCR_LSEDRV_0
-#define RCC_LSEDrive_MediumHigh RCC_BDCR_LSEDRV_1
-#define RCC_LSEDrive_High RCC_BDCR_LSEDRV
-#define IS_RCC_LSE_DRIVE(DRIVE) (((DRIVE) == RCC_LSEDrive_Low) || ((DRIVE) == RCC_LSEDrive_MediumLow) || \
- ((DRIVE) == RCC_LSEDrive_MediumHigh) || ((DRIVE) == RCC_LSEDrive_High))
-/**
- * @}
- */
-
-/** @defgroup RCC_AHB_Peripherals
- * @{
- */
-
-#define RCC_AHBPeriph_GPIOA RCC_AHBENR_GPIOAEN
-#define RCC_AHBPeriph_GPIOB RCC_AHBENR_GPIOBEN
-#define RCC_AHBPeriph_GPIOC RCC_AHBENR_GPIOCEN
-#define RCC_AHBPeriph_GPIOD RCC_AHBENR_GPIODEN
-#define RCC_AHBPeriph_GPIOE RCC_AHBENR_GPIOEEN /*!< Only applicable for STM32F072 devices */
-#define RCC_AHBPeriph_GPIOF RCC_AHBENR_GPIOFEN
-#define RCC_AHBPeriph_TS RCC_AHBENR_TSEN
-#define RCC_AHBPeriph_CRC RCC_AHBENR_CRCEN
-#define RCC_AHBPeriph_FLITF RCC_AHBENR_FLITFEN
-#define RCC_AHBPeriph_SRAM RCC_AHBENR_SRAMEN
-#define RCC_AHBPeriph_DMA1 RCC_AHBENR_DMA1EN
-
-#define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFE81FFAA) == 0x00) && ((PERIPH) != 0x00))
-#define IS_RCC_AHB_RST_PERIPH(PERIPH) ((((PERIPH) & 0xFE81FFFF) == 0x00) && ((PERIPH) != 0x00))
-
-/**
- * @}
- */
-
-/** @defgroup RCC_APB2_Peripherals
- * @{
- */
-
-#define RCC_APB2Periph_SYSCFG RCC_APB2ENR_SYSCFGEN
-#define RCC_APB2Periph_ADC1 RCC_APB2ENR_ADC1EN
-#define RCC_APB2Periph_TIM1 RCC_APB2ENR_TIM1EN
-#define RCC_APB2Periph_SPI1 RCC_APB2ENR_SPI1EN
-#define RCC_APB2Periph_USART1 RCC_APB2ENR_USART1EN
-#define RCC_APB2Periph_TIM15 RCC_APB2ENR_TIM15EN
-#define RCC_APB2Periph_TIM16 RCC_APB2ENR_TIM16EN
-#define RCC_APB2Periph_TIM17 RCC_APB2ENR_TIM17EN
-#define RCC_APB2Periph_DBGMCU RCC_APB2ENR_DBGMCUEN
-
-#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFB8A5FE) == 0x00) && ((PERIPH) != 0x00))
-
-/**
- * @}
- */
-
-/** @defgroup RCC_APB1_Peripherals
- * @{
- */
-
-#define RCC_APB1Periph_TIM2 RCC_APB1ENR_TIM2EN /*!< Only applicable for STM32F051 and STM32F072 devices */
-#define RCC_APB1Periph_TIM3 RCC_APB1ENR_TIM3EN
-#define RCC_APB1Periph_TIM6 RCC_APB1ENR_TIM6EN
-#define RCC_APB1Periph_TIM7 RCC_APB1ENR_TIM7EN /*!< Only applicable for STM32F072 devices */
-#define RCC_APB1Periph_TIM14 RCC_APB1ENR_TIM14EN
-#define RCC_APB1Periph_WWDG RCC_APB1ENR_WWDGEN
-#define RCC_APB1Periph_SPI2 RCC_APB1ENR_SPI2EN
-#define RCC_APB1Periph_USART2 RCC_APB1ENR_USART2EN
-#define RCC_APB1Periph_USART3 RCC_APB1ENR_USART3EN /*!< Only applicable for STM32F072 devices */
-#define RCC_APB1Periph_USART4 RCC_APB1ENR_USART4EN /*!< Only applicable for STM32F072 devices */
-#define RCC_APB1Periph_I2C1 RCC_APB1ENR_I2C1EN
-#define RCC_APB1Periph_I2C2 RCC_APB1ENR_I2C2EN
-#define RCC_APB1Periph_USB RCC_APB1ENR_USBEN /*!< Only applicable for STM32F072 and STM32F042 devices */
-#define RCC_APB1Periph_CAN RCC_APB1ENR_CANEN /*!< Only applicable for STM32F072 and STM32F042 devices */
-#define RCC_APB1Periph_CRS RCC_APB1ENR_CRSEN /*!< Only applicable for STM32F072 and STM32F042 devices*/
-#define RCC_APB1Periph_PWR RCC_APB1ENR_PWREN
-#define RCC_APB1Periph_DAC RCC_APB1ENR_DACEN /*!< Only applicable for STM32F051 and STM32F072 devices */
-#define RCC_APB1Periph_CEC RCC_APB1ENR_CECEN /*!< Only applicable for STM32F051, STM32F042 and STM32F072 devices */
-
-#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x8511B6CC) == 0x00) && ((PERIPH) != 0x00))
-/**
- * @}
- */
-
-/** @defgroup RCC_MCO_Clock_Source
- * @{
- */
-
-#define RCC_MCOSource_NoClock ((uint8_t)0x00)
-#define RCC_MCOSource_HSI14 ((uint8_t)0x01)
-#define RCC_MCOSource_LSI ((uint8_t)0x02)
-#define RCC_MCOSource_LSE ((uint8_t)0x03)
-#define RCC_MCOSource_SYSCLK ((uint8_t)0x04)
-#define RCC_MCOSource_HSI ((uint8_t)0x05)
-#define RCC_MCOSource_HSE ((uint8_t)0x06)
-#define RCC_MCOSource_PLLCLK_Div2 ((uint8_t)0x07)
-#define RCC_MCOSource_HSI48 ((uint8_t)0x08) /*!< Only applicable for STM32F072 devices */
-#define RCC_MCOSource_PLLCLK ((uint8_t)0x87)
-
-#define IS_RCC_MCO_SOURCE(SOURCE) (((SOURCE) == RCC_MCOSource_NoClock) || ((SOURCE) == RCC_MCOSource_HSI14) || \
- ((SOURCE) == RCC_MCOSource_SYSCLK) || ((SOURCE) == RCC_MCOSource_HSI) || \
- ((SOURCE) == RCC_MCOSource_HSE) || ((SOURCE) == RCC_MCOSource_PLLCLK_Div2)|| \
- ((SOURCE) == RCC_MCOSource_LSI) || ((SOURCE) == RCC_MCOSource_HSI48) || \
- ((SOURCE) == RCC_MCOSource_PLLCLK) || ((SOURCE) == RCC_MCOSource_LSE))
-/**
- * @}
- */
-
-/** @defgroup RCC_MCOPrescaler
- * @{
- */
-#if !defined (STM32F051)
-#define RCC_MCOPrescaler_1 RCC_CFGR_MCO_PRE_1
-#define RCC_MCOPrescaler_2 RCC_CFGR_MCO_PRE_2
-#define RCC_MCOPrescaler_4 RCC_CFGR_MCO_PRE_4
-#define RCC_MCOPrescaler_8 RCC_CFGR_MCO_PRE_8
-#define RCC_MCOPrescaler_16 RCC_CFGR_MCO_PRE_16
-#define RCC_MCOPrescaler_32 RCC_CFGR_MCO_PRE_32
-#define RCC_MCOPrescaler_64 RCC_CFGR_MCO_PRE_64
-#define RCC_MCOPrescaler_128 RCC_CFGR_MCO_PRE_128
-
-#define IS_RCC_MCO_PRESCALER(PRESCALER) (((PRESCALER) == RCC_MCOPrescaler_1) || \
- ((PRESCALER) == RCC_MCOPrescaler_2) || \
- ((PRESCALER) == RCC_MCOPrescaler_4) || \
- ((PRESCALER) == RCC_MCOPrescaler_8) || \
- ((PRESCALER) == RCC_MCOPrescaler_16) || \
- ((PRESCALER) == RCC_MCOPrescaler_32) || \
- ((PRESCALER) == RCC_MCOPrescaler_64) || \
- ((PRESCALER) == RCC_MCOPrescaler_128))
-#endif /* STM32F051 */
-/**
- * @}
- */
-
-/** @defgroup RCC_Flag
- * @{
- */
-#define RCC_FLAG_HSIRDY ((uint8_t)0x01)
-#define RCC_FLAG_HSERDY ((uint8_t)0x11)
-#define RCC_FLAG_PLLRDY ((uint8_t)0x19)
-#define RCC_FLAG_LSERDY ((uint8_t)0x21)
-#define RCC_FLAG_LSIRDY ((uint8_t)0x41)
-#define RCC_FLAG_V18PWRRSTF ((uint8_t)0x57)
-#define RCC_FLAG_OBLRST ((uint8_t)0x59)
-#define RCC_FLAG_PINRST ((uint8_t)0x5A)
-#define RCC_FLAG_PORRST ((uint8_t)0x5B)
-#define RCC_FLAG_SFTRST ((uint8_t)0x5C)
-#define RCC_FLAG_IWDGRST ((uint8_t)0x5D)
-#define RCC_FLAG_WWDGRST ((uint8_t)0x5E)
-#define RCC_FLAG_LPWRRST ((uint8_t)0x5F)
-#define RCC_FLAG_HSI14RDY ((uint8_t)0x61)
-#define RCC_FLAG_HSI48RDY ((uint8_t)0x71) /*!< Only applicable for STM32F072 devices */
-
-#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
- ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \
- ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_OBLRST) || \
- ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \
- ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST) || \
- ((FLAG) == RCC_FLAG_WWDGRST) || ((FLAG) == RCC_FLAG_LPWRRST) || \
- ((FLAG) == RCC_FLAG_HSI14RDY)|| ((FLAG) == RCC_FLAG_HSI48RDY)|| \
- ((FLAG) == RCC_FLAG_V18PWRRSTF))
-
-#define IS_RCC_HSI_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
-#define IS_RCC_HSI14_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-/* Function used to set the RCC clock configuration to the default reset state */
-void RCC_DeInit(void);
-
-/* Internal/external clocks, PLL, CSS and MCO configuration functions *********/
-void RCC_HSEConfig(uint8_t RCC_HSE);
-ErrorStatus RCC_WaitForHSEStartUp(void);
-void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
-void RCC_HSICmd(FunctionalState NewState);
-void RCC_AdjustHSI14CalibrationValue(uint8_t HSI14CalibrationValue);
-void RCC_HSI14Cmd(FunctionalState NewState);
-void RCC_HSI14ADCRequestCmd(FunctionalState NewState);
-void RCC_LSEConfig(uint32_t RCC_LSE);
-void RCC_LSEDriveConfig(uint32_t RCC_LSEDrive);
-void RCC_LSICmd(FunctionalState NewState);
-void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul);
-void RCC_PLLCmd(FunctionalState NewState);
-void RCC_HSI48Cmd(FunctionalState NewState); /*!< Only applicable for STM32F072 devices */
-uint32_t RCC_GetHSI48CalibrationValue(void); /*!< Only applicable for STM32F072 devices */
-void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Div);
-void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
-#ifdef STM32F051
-void RCC_MCOConfig(uint8_t RCC_MCOSource);
-#else
-void RCC_MCOConfig(uint8_t RCC_MCOSource,uint32_t RCC_MCOPrescaler);
-#endif /* STM32F051 */
-
-/* System, AHB and APB busses clocks configuration functions ******************/
-void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
-uint8_t RCC_GetSYSCLKSource(void);
-void RCC_HCLKConfig(uint32_t RCC_SYSCLK);
-void RCC_PCLKConfig(uint32_t RCC_HCLK);
-void RCC_ADCCLKConfig(uint32_t RCC_ADCCLK); /* This function is obsolete.
- For proper ADC clock selection, refer to
- ADC_ClockModeConfig() in the ADC driver */
-void RCC_CECCLKConfig(uint32_t RCC_CECCLK);
-void RCC_I2CCLKConfig(uint32_t RCC_I2CCLK);
-void RCC_USARTCLKConfig(uint32_t RCC_USARTCLK);
-void RCC_USBCLKConfig(uint32_t RCC_USBCLK); /*!< Only applicable for STM32F042 and STM32F072 devices */
-void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);
-
-/* Peripheral clocks configuration functions **********************************/
-void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
-void RCC_RTCCLKCmd(FunctionalState NewState);
-void RCC_BackupResetCmd(FunctionalState NewState);
-
-void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
-void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
-void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
-
-void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
-void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
-void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
-
-/* Interrupts and flags management functions **********************************/
-void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
-FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
-void RCC_ClearFlag(void);
-ITStatus RCC_GetITStatus(uint8_t RCC_IT);
-void RCC_ClearITPendingBit(uint8_t RCC_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F0XX_RCC_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_rtc.h b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_rtc.h
deleted file mode 100644
index 598ed660d9097ea6bbf2d43b1cf6ca713776de2f..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_rtc.h
+++ /dev/null
@@ -1,807 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f0xx_rtc.h
- * @author MCD Application Team
- * @version V1.3.0
- * @date 16-January-2014
- * @brief This file contains all the functions prototypes for the RTC firmware
- * library.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F0XX_RTC_H
-#define __STM32F0XX_RTC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup RTC
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/**
- * @brief RTC Init structures definition
- */
-typedef struct
-{
- uint32_t RTC_HourFormat; /*!< Specifies the RTC Hour Format.
- This parameter can be a value of @ref RTC_Hour_Formats */
-
- uint32_t RTC_AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value.
- This parameter must be set to a value lower than 0x7F */
-
- uint32_t RTC_SynchPrediv; /*!< Specifies the RTC Synchronous Predivider value.
- This parameter must be set to a value lower than 0x1FFF */
-}RTC_InitTypeDef;
-
-/**
- * @brief RTC Time structure definition
- */
-typedef struct
-{
- uint8_t RTC_Hours; /*!< Specifies the RTC Time Hour.
- This parameter must be set to a value in the 0-12 range
- if the RTC_HourFormat_12 is selected or 0-23 range if
- the RTC_HourFormat_24 is selected. */
-
- uint8_t RTC_Minutes; /*!< Specifies the RTC Time Minutes.
- This parameter must be set to a value in the 0-59 range. */
-
- uint8_t RTC_Seconds; /*!< Specifies the RTC Time Seconds.
- This parameter must be set to a value in the 0-59 range. */
-
- uint8_t RTC_H12; /*!< Specifies the RTC AM/PM Time.
- This parameter can be a value of @ref RTC_AM_PM_Definitions */
-}RTC_TimeTypeDef;
-
-/**
- * @brief RTC Date structure definition
- */
-typedef struct
-{
- uint8_t RTC_WeekDay; /*!< Specifies the RTC Date WeekDay.
- This parameter can be a value of @ref RTC_WeekDay_Definitions */
-
- uint8_t RTC_Month; /*!< Specifies the RTC Date Month.
- This parameter can be a value of @ref RTC_Month_Date_Definitions */
-
- uint8_t RTC_Date; /*!< Specifies the RTC Date.
- This parameter must be set to a value in the 1-31 range. */
-
- uint8_t RTC_Year; /*!< Specifies the RTC Date Year.
- This parameter must be set to a value in the 0-99 range. */
-}RTC_DateTypeDef;
-
-/**
- * @brief RTC Alarm structure definition
- */
-typedef struct
-{
- RTC_TimeTypeDef RTC_AlarmTime; /*!< Specifies the RTC Alarm Time members. */
-
- uint32_t RTC_AlarmMask; /*!< Specifies the RTC Alarm Masks.
- This parameter can be a value of @ref RTC_AlarmMask_Definitions */
-
- uint32_t RTC_AlarmDateWeekDaySel; /*!< Specifies the RTC Alarm is on Date or WeekDay.
- This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */
-
- uint8_t RTC_AlarmDateWeekDay; /*!< Specifies the RTC Alarm Date/WeekDay.
- This parameter must be set to a value in the 1-31 range
- if the Alarm Date is selected.
- This parameter can be a value of @ref RTC_WeekDay_Definitions
- if the Alarm WeekDay is selected. */
-}RTC_AlarmTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup RTC_Exported_Constants
- * @{
- */
-
-
-/** @defgroup RTC_Hour_Formats
- * @{
- */
-#define RTC_HourFormat_24 ((uint32_t)0x00000000)
-#define RTC_HourFormat_12 ((uint32_t)0x00000040)
-#define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HourFormat_12) || \
- ((FORMAT) == RTC_HourFormat_24))
-/**
- * @}
- */
-
-/** @defgroup RTC_Asynchronous_Predivider
- * @{
- */
-#define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7F)
-
-/**
- * @}
- */
-
-
-/** @defgroup RTC_Synchronous_Predivider
- * @{
- */
-#define IS_RTC_SYNCH_PREDIV(PREDIV) ((PREDIV) <= 0x7FFF)
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Time_Definitions
- * @{
- */
-#define IS_RTC_HOUR12(HOUR) (((HOUR) > 0) && ((HOUR) <= 12))
-#define IS_RTC_HOUR24(HOUR) ((HOUR) <= 23)
-#define IS_RTC_MINUTES(MINUTES) ((MINUTES) <= 59)
-#define IS_RTC_SECONDS(SECONDS) ((SECONDS) <= 59)
-
-/**
- * @}
- */
-
-/** @defgroup RTC_AM_PM_Definitions
- * @{
- */
-#define RTC_H12_AM ((uint8_t)0x00)
-#define RTC_H12_PM ((uint8_t)0x40)
-#define IS_RTC_H12(PM) (((PM) == RTC_H12_AM) || ((PM) == RTC_H12_PM))
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Year_Date_Definitions
- * @{
- */
-#define IS_RTC_YEAR(YEAR) ((YEAR) <= 99)
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Month_Date_Definitions
- * @{
- */
-#define RTC_Month_January ((uint8_t)0x01)
-#define RTC_Month_February ((uint8_t)0x02)
-#define RTC_Month_March ((uint8_t)0x03)
-#define RTC_Month_April ((uint8_t)0x04)
-#define RTC_Month_May ((uint8_t)0x05)
-#define RTC_Month_June ((uint8_t)0x06)
-#define RTC_Month_July ((uint8_t)0x07)
-#define RTC_Month_August ((uint8_t)0x08)
-#define RTC_Month_September ((uint8_t)0x09)
-#define RTC_Month_October ((uint8_t)0x10)
-#define RTC_Month_November ((uint8_t)0x11)
-#define RTC_Month_December ((uint8_t)0x12)
-#define IS_RTC_MONTH(MONTH) (((MONTH) >= 1) && ((MONTH) <= 12))
-#define IS_RTC_DATE(DATE) (((DATE) >= 1) && ((DATE) <= 31))
-
-/**
- * @}
- */
-
-/** @defgroup RTC_WeekDay_Definitions
- * @{
- */
-
-#define RTC_Weekday_Monday ((uint8_t)0x01)
-#define RTC_Weekday_Tuesday ((uint8_t)0x02)
-#define RTC_Weekday_Wednesday ((uint8_t)0x03)
-#define RTC_Weekday_Thursday ((uint8_t)0x04)
-#define RTC_Weekday_Friday ((uint8_t)0x05)
-#define RTC_Weekday_Saturday ((uint8_t)0x6)
-#define RTC_Weekday_Sunday ((uint8_t)0x07)
-#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \
- ((WEEKDAY) == RTC_Weekday_Tuesday) || \
- ((WEEKDAY) == RTC_Weekday_Wednesday) || \
- ((WEEKDAY) == RTC_Weekday_Thursday) || \
- ((WEEKDAY) == RTC_Weekday_Friday) || \
- ((WEEKDAY) == RTC_Weekday_Saturday) || \
- ((WEEKDAY) == RTC_Weekday_Sunday))
-/**
- * @}
- */
-
-
-/** @defgroup RTC_Alarm_Definitions
- * @{
- */
-#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) > 0) && ((DATE) <= 31))
-#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \
- ((WEEKDAY) == RTC_Weekday_Tuesday) || \
- ((WEEKDAY) == RTC_Weekday_Wednesday) || \
- ((WEEKDAY) == RTC_Weekday_Thursday) || \
- ((WEEKDAY) == RTC_Weekday_Friday) || \
- ((WEEKDAY) == RTC_Weekday_Saturday) || \
- ((WEEKDAY) == RTC_Weekday_Sunday))
-
-/**
- * @}
- */
-
-
-/** @defgroup RTC_AlarmDateWeekDay_Definitions
- * @{
- */
-#define RTC_AlarmDateWeekDaySel_Date ((uint32_t)0x00000000)
-#define RTC_AlarmDateWeekDaySel_WeekDay ((uint32_t)0x40000000)
-
-#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_AlarmDateWeekDaySel_Date) || \
- ((SEL) == RTC_AlarmDateWeekDaySel_WeekDay))
-
-/**
- * @}
- */
-
-
-/** @defgroup RTC_AlarmMask_Definitions
- * @{
- */
-#define RTC_AlarmMask_None ((uint32_t)0x00000000)
-#define RTC_AlarmMask_DateWeekDay ((uint32_t)0x80000000)
-#define RTC_AlarmMask_Hours ((uint32_t)0x00800000)
-#define RTC_AlarmMask_Minutes ((uint32_t)0x00008000)
-#define RTC_AlarmMask_Seconds ((uint32_t)0x00000080)
-#define RTC_AlarmMask_All ((uint32_t)0x80808080)
-#define IS_RTC_ALARM_MASK(MASK) (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET)
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Alarms_Definitions
- * @{
- */
-#define RTC_Alarm_A ((uint32_t)0x00000100)
-#define IS_RTC_ALARM(ALARM) ((ALARM) == RTC_Alarm_A)
-#define IS_RTC_CMD_ALARM(ALARM) (((ALARM) & (RTC_Alarm_A)) != (uint32_t)RESET)
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Alarm_Sub_Seconds_Masks Definitions.
- * @{
- */
-#define RTC_AlarmSubSecondMask_All ((uint8_t)0x00) /*!< All Alarm SS fields are masked.
- There is no comparison on sub seconds
- for Alarm */
-#define RTC_AlarmSubSecondMask_SS14_1 ((uint8_t)0x01) /*!< SS[14:1] are don't care in Alarm
- comparison. Only SS[0] is compared. */
-#define RTC_AlarmSubSecondMask_SS14_2 ((uint8_t)0x02) /*!< SS[14:2] are don't care in Alarm
- comparison. Only SS[1:0] are compared */
-#define RTC_AlarmSubSecondMask_SS14_3 ((uint8_t)0x03) /*!< SS[14:3] are don't care in Alarm
- comparison. Only SS[2:0] are compared */
-#define RTC_AlarmSubSecondMask_SS14_4 ((uint8_t)0x04) /*!< SS[14:4] are don't care in Alarm
- comparison. Only SS[3:0] are compared */
-#define RTC_AlarmSubSecondMask_SS14_5 ((uint8_t)0x05) /*!< SS[14:5] are don't care in Alarm
- comparison. Only SS[4:0] are compared */
-#define RTC_AlarmSubSecondMask_SS14_6 ((uint8_t)0x06) /*!< SS[14:6] are don't care in Alarm
- comparison. Only SS[5:0] are compared */
-#define RTC_AlarmSubSecondMask_SS14_7 ((uint8_t)0x07) /*!< SS[14:7] are don't care in Alarm
- comparison. Only SS[6:0] are compared */
-#define RTC_AlarmSubSecondMask_SS14_8 ((uint8_t)0x08) /*!< SS[14:8] are don't care in Alarm
- comparison. Only SS[7:0] are compared */
-#define RTC_AlarmSubSecondMask_SS14_9 ((uint8_t)0x09) /*!< SS[14:9] are don't care in Alarm
- comparison. Only SS[8:0] are compared */
-#define RTC_AlarmSubSecondMask_SS14_10 ((uint8_t)0x0A) /*!< SS[14:10] are don't care in Alarm
- comparison. Only SS[9:0] are compared */
-#define RTC_AlarmSubSecondMask_SS14_11 ((uint8_t)0x0B) /*!< SS[14:11] are don't care in Alarm
- comparison. Only SS[10:0] are compared */
-#define RTC_AlarmSubSecondMask_SS14_12 ((uint8_t)0x0C) /*!< SS[14:12] are don't care in Alarm
- comparison.Only SS[11:0] are compared */
-#define RTC_AlarmSubSecondMask_SS14_13 ((uint8_t)0x0D) /*!< SS[14:13] are don't care in Alarm
- comparison. Only SS[12:0] are compared */
-#define RTC_AlarmSubSecondMask_SS14 ((uint8_t)0x0E) /*!< SS[14] is don't care in Alarm
- comparison.Only SS[13:0] are compared */
-#define RTC_AlarmSubSecondMask_None ((uint8_t)0x0F) /*!< SS[14:0] are compared and must match
- to activate alarm. */
-#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK) (((MASK) == RTC_AlarmSubSecondMask_All) || \
- ((MASK) == RTC_AlarmSubSecondMask_SS14_1) || \
- ((MASK) == RTC_AlarmSubSecondMask_SS14_2) || \
- ((MASK) == RTC_AlarmSubSecondMask_SS14_3) || \
- ((MASK) == RTC_AlarmSubSecondMask_SS14_4) || \
- ((MASK) == RTC_AlarmSubSecondMask_SS14_5) || \
- ((MASK) == RTC_AlarmSubSecondMask_SS14_6) || \
- ((MASK) == RTC_AlarmSubSecondMask_SS14_7) || \
- ((MASK) == RTC_AlarmSubSecondMask_SS14_8) || \
- ((MASK) == RTC_AlarmSubSecondMask_SS14_9) || \
- ((MASK) == RTC_AlarmSubSecondMask_SS14_10) || \
- ((MASK) == RTC_AlarmSubSecondMask_SS14_11) || \
- ((MASK) == RTC_AlarmSubSecondMask_SS14_12) || \
- ((MASK) == RTC_AlarmSubSecondMask_SS14_13) || \
- ((MASK) == RTC_AlarmSubSecondMask_SS14) || \
- ((MASK) == RTC_AlarmSubSecondMask_None))
-/**
- * @}
- */
-
-/** @defgroup RTC_Alarm_Sub_Seconds_Value
- * @{
- */
-
-#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= 0x00007FFF)
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Wakeup_Timer_Definitions
- * @brief These parameters are only available for STM32F072 devices
- * @{
- */
-#define RTC_WakeUpClock_RTCCLK_Div16 ((uint32_t)0x00000000)
-#define RTC_WakeUpClock_RTCCLK_Div8 ((uint32_t)0x00000001)
-#define RTC_WakeUpClock_RTCCLK_Div4 ((uint32_t)0x00000002)
-#define RTC_WakeUpClock_RTCCLK_Div2 ((uint32_t)0x00000003)
-#define RTC_WakeUpClock_CK_SPRE_16bits ((uint32_t)0x00000004)
-#define RTC_WakeUpClock_CK_SPRE_17bits ((uint32_t)0x00000006)
-#define IS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WakeUpClock_RTCCLK_Div16) || \
- ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div8) || \
- ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div4) || \
- ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div2) || \
- ((CLOCK) == RTC_WakeUpClock_CK_SPRE_16bits) || \
- ((CLOCK) == RTC_WakeUpClock_CK_SPRE_17bits))
-#define IS_RTC_WAKEUP_COUNTER(COUNTER) ((COUNTER) <= 0xFFFF)
-/**
- * @}
- */
-
-/** @defgroup RTC_Time_Stamp_Edges_definitions
- * @{
- */
-#define RTC_TimeStampEdge_Rising ((uint32_t)0x00000000)
-#define RTC_TimeStampEdge_Falling ((uint32_t)0x00000008)
-#define IS_RTC_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TimeStampEdge_Rising) || \
- ((EDGE) == RTC_TimeStampEdge_Falling))
-/**
- * @}
- */
-
-/** @defgroup RTC_Output_selection_Definitions
- * @{
- */
-#define RTC_Output_Disable ((uint32_t)0x00000000)
-#define RTC_Output_AlarmA ((uint32_t)0x00200000)
-#define RTC_Output_WakeUp ((uint32_t)0x00600000) /*!< available only for STM32F072 devices */
-
-#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_Output_Disable) || \
- ((OUTPUT) == RTC_Output_AlarmA) || \
- ((OUTPUT) == RTC_Output_WakeUp))
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Output_Polarity_Definitions
- * @{
- */
-#define RTC_OutputPolarity_High ((uint32_t)0x00000000)
-#define RTC_OutputPolarity_Low ((uint32_t)0x00100000)
-#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OutputPolarity_High) || \
- ((POL) == RTC_OutputPolarity_Low))
-/**
- * @}
- */
-
-
-/** @defgroup RTC_Calib_Output_selection_Definitions
- * @{
- */
-#define RTC_CalibOutput_512Hz ((uint32_t)0x00000000)
-#define RTC_CalibOutput_1Hz ((uint32_t)0x00080000)
-#define IS_RTC_CALIB_OUTPUT(OUTPUT) (((OUTPUT) == RTC_CalibOutput_512Hz) || \
- ((OUTPUT) == RTC_CalibOutput_1Hz))
-/**
- * @}
- */
-
-/** @defgroup RTC_Smooth_calib_period_Definitions
- * @{
- */
-#define RTC_SmoothCalibPeriod_32sec ((uint32_t)0x00000000) /*!< if RTCCLK = 32768 Hz, Smooth calibation
- period is 32s, else 2exp20 RTCCLK seconds */
-#define RTC_SmoothCalibPeriod_16sec ((uint32_t)0x00002000) /*!< if RTCCLK = 32768 Hz, Smooth calibation
- period is 16s, else 2exp19 RTCCLK seconds */
-#define RTC_SmoothCalibPeriod_8sec ((uint32_t)0x00004000) /*!< if RTCCLK = 32768 Hz, Smooth calibation
- period is 8s, else 2exp18 RTCCLK seconds */
-#define IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD) (((PERIOD) == RTC_SmoothCalibPeriod_32sec) || \
- ((PERIOD) == RTC_SmoothCalibPeriod_16sec) || \
- ((PERIOD) == RTC_SmoothCalibPeriod_8sec))
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Smooth_calib_Plus_pulses_Definitions
- * @{
- */
-#define RTC_SmoothCalibPlusPulses_Set ((uint32_t)0x00008000) /*!< The number of RTCCLK pulses added
- during a X -second window = Y - CALM[8:0].
- with Y = 512, 256, 128 when X = 32, 16, 8 */
-#define RTC_SmoothCalibPlusPulses_Reset ((uint32_t)0x00000000) /*!< The number of RTCCLK pulses subbstited
- during a 32-second window = CALM[8:0]. */
-#define IS_RTC_SMOOTH_CALIB_PLUS(PLUS) (((PLUS) == RTC_SmoothCalibPlusPulses_Set) || \
- ((PLUS) == RTC_SmoothCalibPlusPulses_Reset))
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Smooth_calib_Minus_pulses_Definitions
- * @{
- */
-#define IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FF)
-
-/**
- * @}
- */
-
-/** @defgroup RTC_DayLightSaving_Definitions
- * @{
- */
-#define RTC_DayLightSaving_SUB1H ((uint32_t)0x00020000)
-#define RTC_DayLightSaving_ADD1H ((uint32_t)0x00010000)
-#define IS_RTC_DAYLIGHT_SAVING(SAVING) (((SAVING) == RTC_DayLightSaving_SUB1H) || \
- ((SAVING) == RTC_DayLightSaving_ADD1H))
-
-#define RTC_StoreOperation_Reset ((uint32_t)0x00000000)
-#define RTC_StoreOperation_Set ((uint32_t)0x00040000)
-#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_StoreOperation_Reset) || \
- ((OPERATION) == RTC_StoreOperation_Set))
-/**
- * @}
- */
-
-/** @defgroup RTC_Tamper_Trigger_Definitions
- * @{
- */
-#define RTC_TamperTrigger_RisingEdge ((uint32_t)0x00000000)
-#define RTC_TamperTrigger_FallingEdge ((uint32_t)0x00000001)
-#define RTC_TamperTrigger_LowLevel ((uint32_t)0x00000000)
-#define RTC_TamperTrigger_HighLevel ((uint32_t)0x00000001)
-#define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TamperTrigger_RisingEdge) || \
- ((TRIGGER) == RTC_TamperTrigger_FallingEdge) || \
- ((TRIGGER) == RTC_TamperTrigger_LowLevel) || \
- ((TRIGGER) == RTC_TamperTrigger_HighLevel))
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Tamper_Filter_Definitions
- * @{
- */
-#define RTC_TamperFilter_Disable ((uint32_t)0x00000000) /*!< Tamper filter is disabled */
-
-#define RTC_TamperFilter_2Sample ((uint32_t)0x00000800) /*!< Tamper is activated after 2
- consecutive samples at the active level */
-#define RTC_TamperFilter_4Sample ((uint32_t)0x00001000) /*!< Tamper is activated after 4
- consecutive samples at the active level */
-#define RTC_TamperFilter_8Sample ((uint32_t)0x00001800) /*!< Tamper is activated after 8
- consecutive samples at the active leve. */
-#define IS_RTC_TAMPER_FILTER(FILTER) (((FILTER) == RTC_TamperFilter_Disable) || \
- ((FILTER) == RTC_TamperFilter_2Sample) || \
- ((FILTER) == RTC_TamperFilter_4Sample) || \
- ((FILTER) == RTC_TamperFilter_8Sample))
-/**
- * @}
- */
-
-/** @defgroup RTC_Tamper_Sampling_Frequencies_Definitions
- * @{
- */
-#define RTC_TamperSamplingFreq_RTCCLK_Div32768 ((uint32_t)0x00000000) /*!< Each of the tamper inputs are sampled
- with a frequency = RTCCLK / 32768 */
-#define RTC_TamperSamplingFreq_RTCCLK_Div16384 ((uint32_t)0x00000100) /*!< Each of the tamper inputs are sampled
- with a frequency = RTCCLK / 16384 */
-#define RTC_TamperSamplingFreq_RTCCLK_Div8192 ((uint32_t)0x00000200) /*!< Each of the tamper inputs are sampled
- with a frequency = RTCCLK / 8192 */
-#define RTC_TamperSamplingFreq_RTCCLK_Div4096 ((uint32_t)0x00000300) /*!< Each of the tamper inputs are sampled
- with a frequency = RTCCLK / 4096 */
-#define RTC_TamperSamplingFreq_RTCCLK_Div2048 ((uint32_t)0x00000400) /*!< Each of the tamper inputs are sampled
- with a frequency = RTCCLK / 2048 */
-#define RTC_TamperSamplingFreq_RTCCLK_Div1024 ((uint32_t)0x00000500) /*!< Each of the tamper inputs are sampled
- with a frequency = RTCCLK / 1024 */
-#define RTC_TamperSamplingFreq_RTCCLK_Div512 ((uint32_t)0x00000600) /*!< Each of the tamper inputs are sampled
- with a frequency = RTCCLK / 512 */
-#define RTC_TamperSamplingFreq_RTCCLK_Div256 ((uint32_t)0x00000700) /*!< Each of the tamper inputs are sampled
- with a frequency = RTCCLK / 256 */
-#define IS_RTC_TAMPER_SAMPLING_FREQ(FREQ) (((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div32768) || \
- ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div16384) || \
- ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div8192) || \
- ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div4096) || \
- ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div2048) || \
- ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div1024) || \
- ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div512) || \
- ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div256))
-
-/**
- * @}
- */
-
- /** @defgroup RTC_Tamper_Pin_Precharge_Duration_Definitions
- * @{
- */
-#define RTC_TamperPrechargeDuration_1RTCCLK ((uint32_t)0x00000000) /*!< Tamper pins are pre-charged before
- sampling during 1 RTCCLK cycle */
-#define RTC_TamperPrechargeDuration_2RTCCLK ((uint32_t)0x00002000) /*!< Tamper pins are pre-charged before
- sampling during 2 RTCCLK cycles */
-#define RTC_TamperPrechargeDuration_4RTCCLK ((uint32_t)0x00004000) /*!< Tamper pins are pre-charged before
- sampling during 4 RTCCLK cycles */
-#define RTC_TamperPrechargeDuration_8RTCCLK ((uint32_t)0x00006000) /*!< Tamper pins are pre-charged before
- sampling during 8 RTCCLK cycles */
-
-#define IS_RTC_TAMPER_PRECHARGE_DURATION(DURATION) (((DURATION) == RTC_TamperPrechargeDuration_1RTCCLK) || \
- ((DURATION) == RTC_TamperPrechargeDuration_2RTCCLK) || \
- ((DURATION) == RTC_TamperPrechargeDuration_4RTCCLK) || \
- ((DURATION) == RTC_TamperPrechargeDuration_8RTCCLK))
-/**
- * @}
- */
-
-/** @defgroup RTC_Tamper_Pins_Definitions
- * @{
- */
-#define RTC_Tamper_1 RTC_TAFCR_TAMP1E /*!< Tamper detection enable for
- input tamper 1 */
-#define RTC_Tamper_2 RTC_TAFCR_TAMP2E /*!< Tamper detection enable for
- input tamper 2 */
-#define RTC_Tamper_3 RTC_TAFCR_TAMP3E /*!< Tamper detection enable for
- input tamper 3, available only
- for STM32F072 devices */
-#define IS_RTC_TAMPER(TAMPER) ((((TAMPER) & (uint32_t)0xFFFFFFD6) == 0x00) && ((TAMPER) != (uint32_t)RESET))
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Output_Type_ALARM_OUT
- * @{
- */
-#define RTC_OutputType_OpenDrain ((uint32_t)0x00000000)
-#define RTC_OutputType_PushPull ((uint32_t)0x00040000)
-#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OutputType_OpenDrain) || \
- ((TYPE) == RTC_OutputType_PushPull))
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Add_1_Second_Parameter_Definitions
- * @{
- */
-#define RTC_ShiftAdd1S_Reset ((uint32_t)0x00000000)
-#define RTC_ShiftAdd1S_Set ((uint32_t)0x80000000)
-#define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_ShiftAdd1S_Reset) || \
- ((SEL) == RTC_ShiftAdd1S_Set))
-/**
- * @}
- */
-
-/** @defgroup RTC_Substract_Fraction_Of_Second_Value
- * @{
- */
-#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFF)
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Backup_Registers_Definitions
- * @{
- */
-
-#define RTC_BKP_DR0 ((uint32_t)0x00000000)
-#define RTC_BKP_DR1 ((uint32_t)0x00000001)
-#define RTC_BKP_DR2 ((uint32_t)0x00000002)
-#define RTC_BKP_DR3 ((uint32_t)0x00000003)
-#define RTC_BKP_DR4 ((uint32_t)0x00000004)
-#define IS_RTC_BKP(BKP) (((BKP) == RTC_BKP_DR0) || \
- ((BKP) == RTC_BKP_DR1) || \
- ((BKP) == RTC_BKP_DR2) || \
- ((BKP) == RTC_BKP_DR3) || \
- ((BKP) == RTC_BKP_DR4))
-/**
- * @}
- */
-
-/** @defgroup RTC_Input_parameter_format_definitions
- * @{
- */
-#define RTC_Format_BIN ((uint32_t)0x000000000)
-#define RTC_Format_BCD ((uint32_t)0x000000001)
-#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_Format_BIN) || ((FORMAT) == RTC_Format_BCD))
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Flags_Definitions
- * @{
- */
-#define RTC_FLAG_RECALPF RTC_ISR_RECALPF
-#define RTC_FLAG_TAMP3F RTC_ISR_TAMP3F /*!< Only available for STM32F072 devices */
-#define RTC_FLAG_TAMP2F RTC_ISR_TAMP2F
-#define RTC_FLAG_TAMP1F RTC_ISR_TAMP1F
-#define RTC_FLAG_TSOVF RTC_ISR_TSOVF
-#define RTC_FLAG_TSF RTC_ISR_TSF
-#define RTC_FLAG_WUTF RTC_ISR_WUTF /*!< Only available for STM32F072 devices */
-#define RTC_FLAG_ALRAF RTC_ISR_ALRAF
-#define RTC_FLAG_INITF RTC_ISR_INITF
-#define RTC_FLAG_RSF RTC_ISR_RSF
-#define RTC_FLAG_INITS RTC_ISR_INITS
-#define RTC_FLAG_SHPF RTC_ISR_SHPF
-#define RTC_FLAG_WUTWF RTC_ISR_WUTWF /*!< Only available for STM32F072 devices */
-#define RTC_FLAG_ALRAWF RTC_ISR_ALRAWF
-
-#define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_TSOVF) || ((FLAG) == RTC_FLAG_TSF) || \
- ((FLAG) == RTC_FLAG_WUTF) || ((FLAG) == RTC_FLAG_ALRAWF) || \
- ((FLAG) == RTC_FLAG_ALRAF) || ((FLAG) == RTC_FLAG_INITF) || \
- ((FLAG) == RTC_FLAG_RSF) || ((FLAG) == RTC_FLAG_WUTWF) || \
- ((FLAG) == RTC_FLAG_TAMP1F) || ((FLAG) == RTC_FLAG_TAMP2F) || \
- ((FLAG) == RTC_FLAG_TAMP3F) || ((FLAG) == RTC_FLAG_RECALPF) || \
- ((FLAG) == RTC_FLAG_SHPF))
-#define IS_RTC_CLEAR_FLAG(FLAG) (((FLAG) != (uint32_t)RESET) && (((FLAG) & 0xFFFF02DF) == (uint32_t)RESET))
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Interrupts_Definitions
- * @{
- */
-#define RTC_IT_TS ((uint32_t)0x00008000)
-#define RTC_IT_WUT ((uint32_t)0x00004000) /* Available only for STM32F072 devices */
-#define RTC_IT_ALRA ((uint32_t)0x00001000)
-#define RTC_IT_TAMP ((uint32_t)0x00000004) /* Used only to Enable the Tamper Interrupt */
-#define RTC_IT_TAMP1 ((uint32_t)0x00020000)
-#define RTC_IT_TAMP2 ((uint32_t)0x00040000)
-#define RTC_IT_TAMP3 ((uint32_t)0x00080000) /* Available only for STM32F072 devices */
-
-#define IS_RTC_CONFIG_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFF2FFB) == (uint32_t)RESET))
-#define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_TS) || ((IT) == RTC_IT_ALRA) || \
- ((IT) == RTC_IT_TAMP1) || ((IT) == RTC_IT_WUT) || \
- ((IT) == RTC_IT_TAMP2) || ((IT) == RTC_IT_TAMP3))
-
-#define IS_RTC_CLEAR_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFF12FFF) == (uint32_t)RESET))
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-/* Function used to set the RTC configuration to the default reset state *****/
-ErrorStatus RTC_DeInit(void);
-
-
-/* Initialization and Configuration functions *********************************/
-ErrorStatus RTC_Init(RTC_InitTypeDef* RTC_InitStruct);
-void RTC_StructInit(RTC_InitTypeDef* RTC_InitStruct);
-void RTC_WriteProtectionCmd(FunctionalState NewState);
-ErrorStatus RTC_EnterInitMode(void);
-void RTC_ExitInitMode(void);
-ErrorStatus RTC_WaitForSynchro(void);
-ErrorStatus RTC_RefClockCmd(FunctionalState NewState);
-void RTC_BypassShadowCmd(FunctionalState NewState);
-
-/* Time and Date configuration functions **************************************/
-ErrorStatus RTC_SetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct);
-void RTC_TimeStructInit(RTC_TimeTypeDef* RTC_TimeStruct);
-void RTC_GetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct);
-uint32_t RTC_GetSubSecond(void);
-ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct);
-void RTC_DateStructInit(RTC_DateTypeDef* RTC_DateStruct);
-void RTC_GetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct);
-
-/* Alarms (Alarm A) configuration functions **********************************/
-void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct);
-void RTC_AlarmStructInit(RTC_AlarmTypeDef* RTC_AlarmStruct);
-void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct);
-ErrorStatus RTC_AlarmCmd(uint32_t RTC_Alarm, FunctionalState NewState);
-void RTC_AlarmSubSecondConfig(uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondValue, uint8_t RTC_AlarmSubSecondMask);
-uint32_t RTC_GetAlarmSubSecond(uint32_t RTC_Alarm);
-
-/* WakeUp Timer configuration functions ***************************************/
-void RTC_WakeUpClockConfig(uint32_t RTC_WakeUpClock); /*!< available only for STM32F072 devices */
-void RTC_SetWakeUpCounter(uint32_t RTC_WakeUpCounter); /*!< available only for STM32F072 devices */
-uint32_t RTC_GetWakeUpCounter(void); /*!< available only for STM32F072 devices */
-ErrorStatus RTC_WakeUpCmd(FunctionalState NewState); /*!< available only for STM32F072 devices */
-
-/* Daylight Saving configuration functions ************************************/
-void RTC_DayLightSavingConfig(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation);
-uint32_t RTC_GetStoreOperation(void);
-
-/* Output pin Configuration function ******************************************/
-void RTC_OutputConfig(uint32_t RTC_Output, uint32_t RTC_OutputPolarity);
-
-/* Digital Calibration configuration functions ********************************/
-void RTC_CalibOutputCmd(FunctionalState NewState);
-void RTC_CalibOutputConfig(uint32_t RTC_CalibOutput);
-ErrorStatus RTC_SmoothCalibConfig(uint32_t RTC_SmoothCalibPeriod,
- uint32_t RTC_SmoothCalibPlusPulses,
- uint32_t RTC_SmouthCalibMinusPulsesValue);
-
-/* TimeStamp configuration functions ******************************************/
-void RTC_TimeStampCmd(uint32_t RTC_TimeStampEdge, FunctionalState NewState);
-void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_StampTimeStruct, RTC_DateTypeDef* RTC_StampDateStruct);
-uint32_t RTC_GetTimeStampSubSecond(void);
-
-/* Tampers configuration functions ********************************************/
-void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger);
-void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState);
-void RTC_TamperFilterConfig(uint32_t RTC_TamperFilter);
-void RTC_TamperSamplingFreqConfig(uint32_t RTC_TamperSamplingFreq);
-void RTC_TamperPinsPrechargeDuration(uint32_t RTC_TamperPrechargeDuration);
-void RTC_TimeStampOnTamperDetectionCmd(FunctionalState NewState);
-void RTC_TamperPullUpCmd(FunctionalState NewState);
-
-/* Backup Data Registers configuration functions ******************************/
-void RTC_WriteBackupRegister(uint32_t RTC_BKP_DR, uint32_t Data);
-uint32_t RTC_ReadBackupRegister(uint32_t RTC_BKP_DR);
-
-/* Output Type Config configuration functions *********************************/
-void RTC_OutputTypeConfig(uint32_t RTC_OutputType);
-
-/* RTC_Shift_control_synchonisation_functions *********************************/
-ErrorStatus RTC_SynchroShiftConfig(uint32_t RTC_ShiftAdd1S, uint32_t RTC_ShiftSubFS);
-
-/* Interrupts and flags management functions **********************************/
-void RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState);
-FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG);
-void RTC_ClearFlag(uint32_t RTC_FLAG);
-ITStatus RTC_GetITStatus(uint32_t RTC_IT);
-void RTC_ClearITPendingBit(uint32_t RTC_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F0XX_RTC_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_spi.h b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_spi.h
deleted file mode 100644
index 7b95f833c60bf3e19bd54cb593e264c082ad37fa..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_spi.h
+++ /dev/null
@@ -1,588 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f0xx_spi.h
- * @author MCD Application Team
- * @version V1.3.0
- * @date 16-January-2014
- * @brief This file contains all the functions prototypes for the SPI
- * firmware library.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F0XX_SPI_H
-#define __STM32F0XX_SPI_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup SPI
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/**
- * @brief SPI Init structure definition
- */
-
-typedef struct
-{
- uint16_t SPI_Direction; /*!< Specifies the SPI unidirectional or bidirectional data mode.
- This parameter can be a value of @ref SPI_data_direction */
-
- uint16_t SPI_Mode; /*!< Specifies the SPI mode (Master/Slave).
- This parameter can be a value of @ref SPI_mode */
-
- uint16_t SPI_DataSize; /*!< Specifies the SPI data size.
- This parameter can be a value of @ref SPI_data_size */
-
- uint16_t SPI_CPOL; /*!< Specifies the serial clock steady state.
- This parameter can be a value of @ref SPI_Clock_Polarity */
-
- uint16_t SPI_CPHA; /*!< Specifies the clock active edge for the bit capture.
- This parameter can be a value of @ref SPI_Clock_Phase */
-
- uint16_t SPI_NSS; /*!< Specifies whether the NSS signal is managed by
- hardware (NSS pin) or by software using the SSI bit.
- This parameter can be a value of @ref SPI_Slave_Select_management */
-
- uint16_t SPI_BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
- used to configure the transmit and receive SCK clock.
- This parameter can be a value of @ref SPI_BaudRate_Prescaler
- @note The communication clock is derived from the master
- clock. The slave clock does not need to be set. */
-
- uint16_t SPI_FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
- This parameter can be a value of @ref SPI_MSB_LSB_transmission */
-
- uint16_t SPI_CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. */
-}SPI_InitTypeDef;
-
-
-/**
- * @brief I2S Init structure definition
- * @note These parameters are not available for STM32F030 devices.
- */
-
-typedef struct
-{
- uint16_t I2S_Mode; /*!< Specifies the I2S operating mode.
- This parameter can be a value of @ref SPI_I2S_Mode */
-
- uint16_t I2S_Standard; /*!< Specifies the standard used for the I2S communication.
- This parameter can be a value of @ref SPI_I2S_Standard */
-
- uint16_t I2S_DataFormat; /*!< Specifies the data format for the I2S communication.
- This parameter can be a value of @ref SPI_I2S_Data_Format */
-
- uint16_t I2S_MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not.
- This parameter can be a value of @ref SPI_I2S_MCLK_Output */
-
- uint32_t I2S_AudioFreq; /*!< Specifies the frequency selected for the I2S communication.
- This parameter can be a value of @ref SPI_I2S_Audio_Frequency */
-
- uint16_t I2S_CPOL; /*!< Specifies the idle state of the I2S clock.
- This parameter can be a value of @ref SPI_I2S_Clock_Polarity */
-}I2S_InitTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup SPI_Exported_Constants
- * @{
- */
-
-#define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \
- ((PERIPH) == SPI2))
-
-#define IS_SPI_1_PERIPH(PERIPH) (((PERIPH) == SPI1))
-
-/** @defgroup SPI_data_direction
- * @{
- */
-
-#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000)
-#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400)
-#define SPI_Direction_1Line_Rx ((uint16_t)0x8000)
-#define SPI_Direction_1Line_Tx ((uint16_t)0xC000)
-#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \
- ((MODE) == SPI_Direction_2Lines_RxOnly) || \
- ((MODE) == SPI_Direction_1Line_Rx) || \
- ((MODE) == SPI_Direction_1Line_Tx))
-/**
- * @}
- */
-
-/** @defgroup SPI_mode
- * @{
- */
-
-#define SPI_Mode_Master ((uint16_t)0x0104)
-#define SPI_Mode_Slave ((uint16_t)0x0000)
-#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \
- ((MODE) == SPI_Mode_Slave))
-/**
- * @}
- */
-
-/** @defgroup SPI_data_size
- * @{
- */
-
-#define SPI_DataSize_4b ((uint16_t)0x0300)
-#define SPI_DataSize_5b ((uint16_t)0x0400)
-#define SPI_DataSize_6b ((uint16_t)0x0500)
-#define SPI_DataSize_7b ((uint16_t)0x0600)
-#define SPI_DataSize_8b ((uint16_t)0x0700)
-#define SPI_DataSize_9b ((uint16_t)0x0800)
-#define SPI_DataSize_10b ((uint16_t)0x0900)
-#define SPI_DataSize_11b ((uint16_t)0x0A00)
-#define SPI_DataSize_12b ((uint16_t)0x0B00)
-#define SPI_DataSize_13b ((uint16_t)0x0C00)
-#define SPI_DataSize_14b ((uint16_t)0x0D00)
-#define SPI_DataSize_15b ((uint16_t)0x0E00)
-#define SPI_DataSize_16b ((uint16_t)0x0F00)
-#define IS_SPI_DATA_SIZE(SIZE) (((SIZE) == SPI_DataSize_4b) || \
- ((SIZE) == SPI_DataSize_5b) || \
- ((SIZE) == SPI_DataSize_6b) || \
- ((SIZE) == SPI_DataSize_7b) || \
- ((SIZE) == SPI_DataSize_8b) || \
- ((SIZE) == SPI_DataSize_9b) || \
- ((SIZE) == SPI_DataSize_10b) || \
- ((SIZE) == SPI_DataSize_11b) || \
- ((SIZE) == SPI_DataSize_12b) || \
- ((SIZE) == SPI_DataSize_13b) || \
- ((SIZE) == SPI_DataSize_14b) || \
- ((SIZE) == SPI_DataSize_15b) || \
- ((SIZE) == SPI_DataSize_16b))
-/**
- * @}
- */
-
-/** @defgroup SPI_CRC_length
- * @{
- */
-
-#define SPI_CRCLength_8b ((uint16_t)0x0000)
-#define SPI_CRCLength_16b SPI_CR1_CRCL
-#define IS_SPI_CRC_LENGTH(LENGTH) (((LENGTH) == SPI_CRCLength_8b) || \
- ((LENGTH) == SPI_CRCLength_16b))
-/**
- * @}
- */
-
-/** @defgroup SPI_Clock_Polarity
- * @{
- */
-
-#define SPI_CPOL_Low ((uint16_t)0x0000)
-#define SPI_CPOL_High SPI_CR1_CPOL
-#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \
- ((CPOL) == SPI_CPOL_High))
-/**
- * @}
- */
-
-/** @defgroup SPI_Clock_Phase
- * @{
- */
-
-#define SPI_CPHA_1Edge ((uint16_t)0x0000)
-#define SPI_CPHA_2Edge SPI_CR1_CPHA
-#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \
- ((CPHA) == SPI_CPHA_2Edge))
-/**
- * @}
- */
-
-/** @defgroup SPI_Slave_Select_management
- * @{
- */
-
-#define SPI_NSS_Soft SPI_CR1_SSM
-#define SPI_NSS_Hard ((uint16_t)0x0000)
-#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \
- ((NSS) == SPI_NSS_Hard))
-/**
- * @}
- */
-
-/** @defgroup SPI_BaudRate_Prescaler
- * @{
- */
-
-#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000)
-#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008)
-#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010)
-#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018)
-#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020)
-#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028)
-#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030)
-#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038)
-#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \
- ((PRESCALER) == SPI_BaudRatePrescaler_4) || \
- ((PRESCALER) == SPI_BaudRatePrescaler_8) || \
- ((PRESCALER) == SPI_BaudRatePrescaler_16) || \
- ((PRESCALER) == SPI_BaudRatePrescaler_32) || \
- ((PRESCALER) == SPI_BaudRatePrescaler_64) || \
- ((PRESCALER) == SPI_BaudRatePrescaler_128) || \
- ((PRESCALER) == SPI_BaudRatePrescaler_256))
-/**
- * @}
- */
-
-/** @defgroup SPI_MSB_LSB_transmission
- * @{
- */
-
-#define SPI_FirstBit_MSB ((uint16_t)0x0000)
-#define SPI_FirstBit_LSB SPI_CR1_LSBFIRST
-#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \
- ((BIT) == SPI_FirstBit_LSB))
-/**
- * @}
- */
-
-/** @defgroup SPI_I2S_Mode
- * @{
- */
-
-#define I2S_Mode_SlaveTx ((uint16_t)0x0000)
-#define I2S_Mode_SlaveRx ((uint16_t)0x0100)
-#define I2S_Mode_MasterTx ((uint16_t)0x0200)
-#define I2S_Mode_MasterRx ((uint16_t)0x0300)
-#define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \
- ((MODE) == I2S_Mode_SlaveRx) || \
- ((MODE) == I2S_Mode_MasterTx)|| \
- ((MODE) == I2S_Mode_MasterRx))
-/**
- * @}
- */
-
-/** @defgroup SPI_I2S_Standard
- * @{
- */
-
-#define I2S_Standard_Phillips ((uint16_t)0x0000)
-#define I2S_Standard_MSB ((uint16_t)0x0010)
-#define I2S_Standard_LSB ((uint16_t)0x0020)
-#define I2S_Standard_PCMShort ((uint16_t)0x0030)
-#define I2S_Standard_PCMLong ((uint16_t)0x00B0)
-#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \
- ((STANDARD) == I2S_Standard_MSB) || \
- ((STANDARD) == I2S_Standard_LSB) || \
- ((STANDARD) == I2S_Standard_PCMShort) || \
- ((STANDARD) == I2S_Standard_PCMLong))
-/**
- * @}
- */
-
-/** @defgroup SPI_I2S_Data_Format
- * @{
- */
-
-#define I2S_DataFormat_16b ((uint16_t)0x0000)
-#define I2S_DataFormat_16bextended ((uint16_t)0x0001)
-#define I2S_DataFormat_24b ((uint16_t)0x0003)
-#define I2S_DataFormat_32b ((uint16_t)0x0005)
-#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \
- ((FORMAT) == I2S_DataFormat_16bextended) || \
- ((FORMAT) == I2S_DataFormat_24b) || \
- ((FORMAT) == I2S_DataFormat_32b))
-/**
- * @}
- */
-
-/** @defgroup SPI_I2S_MCLK_Output
- * @{
- */
-
-#define I2S_MCLKOutput_Enable SPI_I2SPR_MCKOE
-#define I2S_MCLKOutput_Disable ((uint16_t)0x0000)
-#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \
- ((OUTPUT) == I2S_MCLKOutput_Disable))
-/**
- * @}
- */
-
-/** @defgroup SPI_I2S_Audio_Frequency
- * @{
- */
-
-#define I2S_AudioFreq_192k ((uint32_t)192000)
-#define I2S_AudioFreq_96k ((uint32_t)96000)
-#define I2S_AudioFreq_48k ((uint32_t)48000)
-#define I2S_AudioFreq_44k ((uint32_t)44100)
-#define I2S_AudioFreq_32k ((uint32_t)32000)
-#define I2S_AudioFreq_22k ((uint32_t)22050)
-#define I2S_AudioFreq_16k ((uint32_t)16000)
-#define I2S_AudioFreq_11k ((uint32_t)11025)
-#define I2S_AudioFreq_8k ((uint32_t)8000)
-#define I2S_AudioFreq_Default ((uint32_t)2)
-
-#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AudioFreq_8k) && \
- ((FREQ) <= I2S_AudioFreq_192k)) || \
- ((FREQ) == I2S_AudioFreq_Default))
-/**
- * @}
- */
-
-/** @defgroup SPI_I2S_Clock_Polarity
- * @{
- */
-
-#define I2S_CPOL_Low ((uint16_t)0x0000)
-#define I2S_CPOL_High SPI_I2SCFGR_CKPOL
-#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \
- ((CPOL) == I2S_CPOL_High))
-/**
- * @}
- */
-
-/** @defgroup SPI_FIFO_reception_threshold
- * @{
- */
-
-#define SPI_RxFIFOThreshold_HF ((uint16_t)0x0000)
-#define SPI_RxFIFOThreshold_QF SPI_CR2_FRXTH
-#define IS_SPI_RX_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == SPI_RxFIFOThreshold_HF) || \
- ((THRESHOLD) == SPI_RxFIFOThreshold_QF))
-/**
- * @}
- */
-
-/** @defgroup SPI_I2S_DMA_transfer_requests
- * @{
- */
-
-#define SPI_I2S_DMAReq_Tx SPI_CR2_TXDMAEN
-#define SPI_I2S_DMAReq_Rx SPI_CR2_RXDMAEN
-#define IS_SPI_I2S_DMA_REQ(REQ) ((((REQ) & (uint16_t)0xFFFC) == 0x00) && ((REQ) != 0x00))
-/**
- * @}
- */
-
-/** @defgroup SPI_last_DMA_transfers
- * @{
- */
-
-#define SPI_LastDMATransfer_TxEvenRxEven ((uint16_t)0x0000)
-#define SPI_LastDMATransfer_TxOddRxEven ((uint16_t)0x4000)
-#define SPI_LastDMATransfer_TxEvenRxOdd ((uint16_t)0x2000)
-#define SPI_LastDMATransfer_TxOddRxOdd ((uint16_t)0x6000)
-#define IS_SPI_LAST_DMA_TRANSFER(TRANSFER) (((TRANSFER) == SPI_LastDMATransfer_TxEvenRxEven) || \
- ((TRANSFER) == SPI_LastDMATransfer_TxOddRxEven) || \
- ((TRANSFER) == SPI_LastDMATransfer_TxEvenRxOdd) || \
- ((TRANSFER) == SPI_LastDMATransfer_TxOddRxOdd))
-/**
- * @}
- */
-/** @defgroup SPI_NSS_internal_software_management
- * @{
- */
-
-#define SPI_NSSInternalSoft_Set SPI_CR1_SSI
-#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF)
-#define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \
- ((INTERNAL) == SPI_NSSInternalSoft_Reset))
-/**
- * @}
- */
-
-/** @defgroup SPI_CRC_Transmit_Receive
- * @{
- */
-
-#define SPI_CRC_Tx ((uint8_t)0x00)
-#define SPI_CRC_Rx ((uint8_t)0x01)
-#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx))
-/**
- * @}
- */
-
-/** @defgroup SPI_direction_transmit_receive
- * @{
- */
-
-#define SPI_Direction_Rx ((uint16_t)0xBFFF)
-#define SPI_Direction_Tx ((uint16_t)0x4000)
-#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \
- ((DIRECTION) == SPI_Direction_Tx))
-/**
- * @}
- */
-
-/** @defgroup SPI_I2S_interrupts_definition
- * @{
- */
-
-#define SPI_I2S_IT_TXE ((uint8_t)0x71)
-#define SPI_I2S_IT_RXNE ((uint8_t)0x60)
-#define SPI_I2S_IT_ERR ((uint8_t)0x50)
-
-#define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \
- ((IT) == SPI_I2S_IT_RXNE) || \
- ((IT) == SPI_I2S_IT_ERR))
-
-#define I2S_IT_UDR ((uint8_t)0x53)
-#define SPI_IT_MODF ((uint8_t)0x55)
-#define SPI_I2S_IT_OVR ((uint8_t)0x56)
-#define SPI_I2S_IT_FRE ((uint8_t)0x58)
-
-#define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE) || ((IT) == SPI_I2S_IT_TXE) || \
- ((IT) == SPI_I2S_IT_OVR) || ((IT) == SPI_IT_MODF) || \
- ((IT) == SPI_I2S_IT_FRE)|| ((IT) == I2S_IT_UDR))
-/**
- * @}
- */
-
-
-/** @defgroup SPI_transmission_fifo_status_level
- * @{
- */
-
-#define SPI_TransmissionFIFOStatus_Empty ((uint16_t)0x0000)
-#define SPI_TransmissionFIFOStatus_1QuarterFull ((uint16_t)0x0800)
-#define SPI_TransmissionFIFOStatus_HalfFull ((uint16_t)0x1000)
-#define SPI_TransmissionFIFOStatus_Full ((uint16_t)0x1800)
-
-/**
- * @}
- */
-
-/** @defgroup SPI_reception_fifo_status_level
- * @{
- */
-#define SPI_ReceptionFIFOStatus_Empty ((uint16_t)0x0000)
-#define SPI_ReceptionFIFOStatus_1QuarterFull ((uint16_t)0x0200)
-#define SPI_ReceptionFIFOStatus_HalfFull ((uint16_t)0x0400)
-#define SPI_ReceptionFIFOStatus_Full ((uint16_t)0x0600)
-
-/**
- * @}
- */
-
-
-/** @defgroup SPI_I2S_flags_definition
- * @{
- */
-
-#define SPI_I2S_FLAG_RXNE SPI_SR_RXNE
-#define SPI_I2S_FLAG_TXE SPI_SR_TXE
-#define I2S_FLAG_CHSIDE SPI_SR_CHSIDE
-#define I2S_FLAG_UDR SPI_SR_UDR
-#define SPI_FLAG_CRCERR SPI_SR_CRCERR
-#define SPI_FLAG_MODF SPI_SR_MODF
-#define SPI_I2S_FLAG_OVR SPI_SR_OVR
-#define SPI_I2S_FLAG_BSY SPI_SR_BSY
-#define SPI_I2S_FLAG_FRE SPI_SR_FRE
-
-
-
-#define IS_SPI_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR))
-#define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \
- ((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \
- ((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE)|| \
- ((FLAG) == SPI_I2S_FLAG_FRE)|| ((FLAG) == I2S_FLAG_CHSIDE)|| \
- ((FLAG) == I2S_FLAG_UDR))
-/**
- * @}
- */
-
-/** @defgroup SPI_CRC_polynomial
- * @{
- */
-
-#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1)
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-/* Initialization and Configuration functions *********************************/
-void SPI_I2S_DeInit(SPI_TypeDef* SPIx);
-void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct);
-void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct); /*!< Not applicable for STM32F030 devices */
-void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct);
-void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct); /*!< Not applicable for STM32F030 devices */
-void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
-void SPI_NSSPulseModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
-void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
-void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState); /*!< Not applicable for STM32F030 devices */
-void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize);
-void SPI_RxFIFOThresholdConfig(SPI_TypeDef* SPIx, uint16_t SPI_RxFIFOThreshold);
-void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction);
-void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft);
-void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
-
-/* Data transfers functions ***************************************************/
-void SPI_SendData8(SPI_TypeDef* SPIx, uint8_t Data);
-void SPI_I2S_SendData16(SPI_TypeDef* SPIx, uint16_t Data);
-uint8_t SPI_ReceiveData8(SPI_TypeDef* SPIx);
-uint16_t SPI_I2S_ReceiveData16(SPI_TypeDef* SPIx);
-
-/* Hardware CRC Calculation functions *****************************************/
-void SPI_CRCLengthConfig(SPI_TypeDef* SPIx, uint16_t SPI_CRCLength);
-void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState);
-void SPI_TransmitCRC(SPI_TypeDef* SPIx);
-uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC);
-uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx);
-
-/* DMA transfers management functions *****************************************/
-void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState);
-void SPI_LastDMATransferCmd(SPI_TypeDef* SPIx, uint16_t SPI_LastDMATransfer);
-
-/* Interrupts and flags management functions **********************************/
-void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState);
-uint16_t SPI_GetTransmissionFIFOStatus(SPI_TypeDef* SPIx);
-uint16_t SPI_GetReceptionFIFOStatus(SPI_TypeDef* SPIx);
-FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
-void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
-ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F0XX_SPI_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_syscfg.h b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_syscfg.h
deleted file mode 100644
index 1a1d56618ee9b995e06d0f29fa9c18b533964c96..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_syscfg.h
+++ /dev/null
@@ -1,262 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f0xx_syscfg.h
- * @author MCD Application Team
- * @version V1.3.0
- * @date 16-January-2014
- * @brief This file contains all the functions prototypes for the SYSCFG firmware
- * library.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/*!< Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F0XX_SYSCFG_H
-#define __STM32F0XX_SYSCFG_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/*!< Includes ------------------------------------------------------------------*/
-#include "stm32f0xx.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup SYSCFG
- * @{
- */
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup SYSCFG_Exported_Constants
- * @{
- */
-
-/** @defgroup SYSCFG_EXTI_Port_Sources
- * @{
- */
-#define EXTI_PortSourceGPIOA ((uint8_t)0x00)
-#define EXTI_PortSourceGPIOB ((uint8_t)0x01)
-#define EXTI_PortSourceGPIOC ((uint8_t)0x02)
-#define EXTI_PortSourceGPIOD ((uint8_t)0x03) /*!< not available for STM32F031 devices */
-#define EXTI_PortSourceGPIOE ((uint8_t)0x04) /*!< only available for STM32F072 devices */
-#define EXTI_PortSourceGPIOF ((uint8_t)0x05)
-
-#define IS_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == EXTI_PortSourceGPIOA) || \
- ((PORTSOURCE) == EXTI_PortSourceGPIOB) || \
- ((PORTSOURCE) == EXTI_PortSourceGPIOC) || \
- ((PORTSOURCE) == EXTI_PortSourceGPIOD) || \
- ((PORTSOURCE) == EXTI_PortSourceGPIOE) || \
- ((PORTSOURCE) == EXTI_PortSourceGPIOF))
-/**
- * @}
- */
-
-/** @defgroup SYSCFG_EXTI_Pin_sources
- * @{
- */
-#define EXTI_PinSource0 ((uint8_t)0x00)
-#define EXTI_PinSource1 ((uint8_t)0x01)
-#define EXTI_PinSource2 ((uint8_t)0x02)
-#define EXTI_PinSource3 ((uint8_t)0x03)
-#define EXTI_PinSource4 ((uint8_t)0x04)
-#define EXTI_PinSource5 ((uint8_t)0x05)
-#define EXTI_PinSource6 ((uint8_t)0x06)
-#define EXTI_PinSource7 ((uint8_t)0x07)
-#define EXTI_PinSource8 ((uint8_t)0x08)
-#define EXTI_PinSource9 ((uint8_t)0x09)
-#define EXTI_PinSource10 ((uint8_t)0x0A)
-#define EXTI_PinSource11 ((uint8_t)0x0B)
-#define EXTI_PinSource12 ((uint8_t)0x0C)
-#define EXTI_PinSource13 ((uint8_t)0x0D)
-#define EXTI_PinSource14 ((uint8_t)0x0E)
-#define EXTI_PinSource15 ((uint8_t)0x0F)
-
-#define IS_EXTI_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == EXTI_PinSource0) || \
- ((PINSOURCE) == EXTI_PinSource1) || \
- ((PINSOURCE) == EXTI_PinSource2) || \
- ((PINSOURCE) == EXTI_PinSource3) || \
- ((PINSOURCE) == EXTI_PinSource4) || \
- ((PINSOURCE) == EXTI_PinSource5) || \
- ((PINSOURCE) == EXTI_PinSource6) || \
- ((PINSOURCE) == EXTI_PinSource7) || \
- ((PINSOURCE) == EXTI_PinSource8) || \
- ((PINSOURCE) == EXTI_PinSource9) || \
- ((PINSOURCE) == EXTI_PinSource10) || \
- ((PINSOURCE) == EXTI_PinSource11) || \
- ((PINSOURCE) == EXTI_PinSource12) || \
- ((PINSOURCE) == EXTI_PinSource13) || \
- ((PINSOURCE) == EXTI_PinSource14) || \
- ((PINSOURCE) == EXTI_PinSource15))
-/**
- * @}
- */
-
-/** @defgroup SYSCFG_Memory_Remap_Config
- * @{
- */
-#define SYSCFG_MemoryRemap_Flash ((uint8_t)0x00)
-#define SYSCFG_MemoryRemap_SystemMemory ((uint8_t)0x01)
-#define SYSCFG_MemoryRemap_SRAM ((uint8_t)0x03)
-
-
-#define IS_SYSCFG_MEMORY_REMAP(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || \
- ((REMAP) == SYSCFG_MemoryRemap_SystemMemory) || \
- ((REMAP) == SYSCFG_MemoryRemap_SRAM))
-
-/**
- * @}
- */
-
-/** @defgroup SYSCFG_DMA_Remap_Config
- * @{
- */
-#define SYSCFG_DMARemap_TIM3 SYSCFG_CFGR1_TIM3_DMA_RMP /* Remap TIM3 DMA requests from channel4 to channel6,
- available only for STM32F072 devices */
-#define SYSCFG_DMARemap_TIM2 SYSCFG_CFGR1_TIM2_DMA_RMP /* Remap TIM2 DMA requests from channel3/4 to channel7,
- available only for STM32F072 devices */
-#define SYSCFG_DMARemap_TIM1 SYSCFG_CFGR1_TIM1_DMA_RMP /* Remap TIM1 DMA requests from channel2/3/4 to channel6,
- available only for STM32F072 devices */
-#define SYSCFG_DMARemap_I2C1 SYSCFG_CFGR1_I2C1_DMA_RMP /* Remap I2C1 DMA requests from channel3/2 to channel7/6,
- available only for STM32F072 devices */
-#define SYSCFG_DMARemap_USART3 SYSCFG_CFGR1_USART3_DMA_RMP /* Remap USART3 DMA requests from channel6/7 to channel3/2,
- available only for STM32F072 devices */
-#define SYSCFG_DMARemap_USART2 SYSCFG_CFGR1_USART2_DMA_RMP /* Remap USART2 DMA requests from channel4/5 to channel6/7,
- available only for STM32F072 devices */
-#define SYSCFG_DMARemap_SPI2 SYSCFG_CFGR1_SPI2_DMA_RMP /* Remap SPI2 DMA requests from channel4/5 to channel6/7,
- available only for STM32F072 devices */
-#define SYSCFG_DMARemap_TIM17_2 SYSCFG_CFGR1_TIM17_DMA_RMP2 /* Remap TIM17 DMA requests from channel1/2 to channel7,
- available only for STM32F072 devices */
-#define SYSCFG_DMARemap_TIM16_2 SYSCFG_CFGR1_TIM16_DMA_RMP2 /* Remap TIM16 DMA requests from channel3/4 to channel6,
- available only for STM32F072 devices */
-#define SYSCFG_DMARemap_TIM17 SYSCFG_CFGR1_TIM17_DMA_RMP /* Remap TIM17 DMA requests from channel1 to channel2 */
-#define SYSCFG_DMARemap_TIM16 SYSCFG_CFGR1_TIM16_DMA_RMP /* Remap TIM16 DMA requests from channel3 to channel4 */
-#define SYSCFG_DMARemap_USART1Rx SYSCFG_CFGR1_USART1RX_DMA_RMP /* Remap USART1 Rx DMA requests from channel3 to channel5 */
-#define SYSCFG_DMARemap_USART1Tx SYSCFG_CFGR1_USART1TX_DMA_RMP /* Remap USART1 Tx DMA requests from channel2 to channel4 */
-#define SYSCFG_DMARemap_ADC1 SYSCFG_CFGR1_ADC_DMA_RMP /* Remap ADC1 DMA requests from channel1 to channel2 */
-
-#define IS_SYSCFG_DMA_REMAP(REMAP) (((REMAP) == SYSCFG_DMARemap_TIM17) || \
- ((REMAP) == SYSCFG_DMARemap_TIM16) || \
- ((REMAP) == SYSCFG_DMARemap_USART1Rx) || \
- ((REMAP) == SYSCFG_DMARemap_USART1Tx) || \
- ((REMAP) == SYSCFG_CFGR1_TIM3_DMA_RMP) || \
- ((REMAP) == SYSCFG_CFGR1_TIM2_DMA_RMP) || \
- ((REMAP) == SYSCFG_CFGR1_TIM1_DMA_RMP) || \
- ((REMAP) == SYSCFG_CFGR1_I2C1_DMA_RMP) || \
- ((REMAP) == SYSCFG_CFGR1_USART3_DMA_RMP) || \
- ((REMAP) == SYSCFG_CFGR1_USART2_DMA_RMP) || \
- ((REMAP) == SYSCFG_CFGR1_SPI2_DMA_RMP) || \
- ((REMAP) == SYSCFG_CFGR1_TIM17_DMA_RMP2) || \
- ((REMAP) == SYSCFG_CFGR1_TIM16_DMA_RMP2) || \
- ((REMAP) == SYSCFG_DMARemap_ADC1))
-
-/**
- * @}
- */
-
-/** @defgroup SYSCFG_I2C_FastModePlus_Config
- * @{
- */
-#define SYSCFG_I2CFastModePlus_PB6 SYSCFG_CFGR1_I2C_FMP_PB6 /* Enable Fast Mode Plus on PB6 */
-#define SYSCFG_I2CFastModePlus_PB7 SYSCFG_CFGR1_I2C_FMP_PB7 /* Enable Fast Mode Plus on PB7 */
-#define SYSCFG_I2CFastModePlus_PB8 SYSCFG_CFGR1_I2C_FMP_PB8 /* Enable Fast Mode Plus on PB8 */
-#define SYSCFG_I2CFastModePlus_PB9 SYSCFG_CFGR1_I2C_FMP_PB9 /* Enable Fast Mode Plus on PB9 */
-#define SYSCFG_I2CFastModePlus_I2C1 SYSCFG_CFGR1_I2C_FMP_I2C1 /* Enable Fast Mode Plus on PB10, PB11, PF6 and PF7(only for STM32F0031 and STM32F030 devices) */
-#define SYSCFG_I2CFastModePlus_I2C2 SYSCFG_CFGR1_I2C_FMP_I2C2 /* Enable Fast Mode Plus on I2C2 pins, available only for STM32F072 devices */
-#define SYSCFG_I2CFastModePlus_PA9 SYSCFG_CFGR1_I2C_FMP_PA9 /* Enable Fast Mode Plus on PA9 (only for STM32F031 and STM32F030 devices) */
-#define SYSCFG_I2CFastModePlus_PA10 SYSCFG_CFGR1_I2C_FMP_PA10/* Enable Fast Mode Plus on PA10(only for STM32F031 and STM32F030 devices) */
-
-#define IS_SYSCFG_I2C_FMP(PIN) (((PIN) == SYSCFG_I2CFastModePlus_PB6) || \
- ((PIN) == SYSCFG_I2CFastModePlus_PB7) || \
- ((PIN) == SYSCFG_I2CFastModePlus_PB8) || \
- ((PIN) == SYSCFG_I2CFastModePlus_PB9) || \
- ((PIN) == SYSCFG_I2CFastModePlus_I2C1) || \
- ((PIN) == SYSCFG_I2CFastModePlus_I2C2) || \
- ((PIN) == SYSCFG_I2CFastModePlus_PA9) || \
- ((PIN) == SYSCFG_I2CFastModePlus_PA10))
-
-
-/**
- * @}
- */
-
-/** @defgroup SYSCFG_Lock_Config
- * @{
- */
-#define SYSCFG_Break_PVD SYSCFG_CFGR2_PVD_LOCK /*!< Connects the PVD event to the Break Input of TIM1, not available for STM32F030 devices */
-#define SYSCFG_Break_SRAMParity SYSCFG_CFGR2_SRAM_PARITY_LOCK /*!< Connects the SRAM_PARITY error signal to the Break Input of TIM1 */
-#define SYSCFG_Break_Lockup SYSCFG_CFGR2_LOCKUP_LOCK /*!< Connects Lockup output of CortexM0 to the break input of TIM1 */
-
-#define IS_SYSCFG_LOCK_CONFIG(CONFIG) (((CONFIG) == SYSCFG_Break_PVD) || \
- ((CONFIG) == SYSCFG_Break_SRAMParity) || \
- ((CONFIG) == SYSCFG_Break_Lockup))
-
-/**
- * @}
- */
-
-/** @defgroup SYSCFG_flags_definition
- * @{
- */
-
-#define SYSCFG_FLAG_PE SYSCFG_CFGR2_SRAM_PE
-
-#define IS_SYSCFG_FLAG(FLAG) (((FLAG) == SYSCFG_FLAG_PE))
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-/* Function used to set the SYSCFG configuration to the default reset state **/
-void SYSCFG_DeInit(void);
-
-/* SYSCFG configuration functions *********************************************/
-void SYSCFG_MemoryRemapConfig(uint32_t SYSCFG_MemoryRemap);
-void SYSCFG_DMAChannelRemapConfig(uint32_t SYSCFG_DMARemap, FunctionalState NewState);
-void SYSCFG_I2CFastModePlusConfig(uint32_t SYSCFG_I2CFastModePlus, FunctionalState NewState);
-void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex);
-void SYSCFG_BreakConfig(uint32_t SYSCFG_Break);
-FlagStatus SYSCFG_GetFlagStatus(uint32_t SYSCFG_Flag);
-void SYSCFG_ClearFlag(uint32_t SYSCFG_Flag);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F0XX_SYSCFG_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_tim.h b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_tim.h
deleted file mode 100644
index 1b7c74543f21c5f4ad989bfe2a3bafe5f44e99f1..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_tim.h
+++ /dev/null
@@ -1,1186 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f0xx_tim.h
- * @author MCD Application Team
- * @version V1.3.0
- * @date 16-January-2014
- * @brief This file contains all the functions prototypes for the TIM
- * firmware library.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F0XX_TIM_H
-#define __STM32F0XX_TIM_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup TIM
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/**
- * @brief TIM Time Base Init structure definition
- * @note This sturcture is used with all TIMx.
- */
-
-typedef struct
-{
- uint16_t TIM_Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
- This parameter can be a number between 0x0000 and 0xFFFF */
-
- uint16_t TIM_CounterMode; /*!< Specifies the counter mode.
- This parameter can be a value of @ref TIM_Counter_Mode */
-
- uint32_t TIM_Period; /*!< Specifies the period value to be loaded into the active
- Auto-Reload Register at the next update event.
- This parameter must be a number between 0x0000 and 0xFFFF. */
-
- uint16_t TIM_ClockDivision; /*!< Specifies the clock division.
- This parameter can be a value of @ref TIM_Clock_Division_CKD */
-
- uint8_t TIM_RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
- reaches zero, an update event is generated and counting restarts
- from the RCR value (N).
- This means in PWM mode that (N+1) corresponds to:
- - the number of PWM periods in edge-aligned mode
- - the number of half PWM period in center-aligned mode
- This parameter must be a number between 0x00 and 0xFF.
- @note This parameter is valid only for TIM1. */
-} TIM_TimeBaseInitTypeDef;
-
-/**
- * @brief TIM Output Compare Init structure definition
- */
-
-typedef struct
-{
- uint16_t TIM_OCMode; /*!< Specifies the TIM mode.
- This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
-
- uint16_t TIM_OutputState; /*!< Specifies the TIM Output Compare state.
- This parameter can be a value of @ref TIM_Output_Compare_state */
-
- uint16_t TIM_OutputNState; /*!< Specifies the TIM complementary Output Compare state.
- This parameter can be a value of @ref TIM_Output_Compare_N_state
- @note This parameter is valid only for TIM1. */
-
- uint32_t TIM_Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
- This parameter can be a number between 0x0000 and 0xFFFF ( or 0xFFFFFFFF
- for TIM2) */
-
- uint16_t TIM_OCPolarity; /*!< Specifies the output polarity.
- This parameter can be a value of @ref TIM_Output_Compare_Polarity */
-
- uint16_t TIM_OCNPolarity; /*!< Specifies the complementary output polarity.
- This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
- @note This parameter is valid only for TIM1. */
-
- uint16_t TIM_OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
- This parameter can be a value of @ref TIM_Output_Compare_Idle_State
- @note This parameter is valid only for TIM1. */
-
- uint16_t TIM_OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
- This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
- @note This parameter is valid only for TIM1. */
-} TIM_OCInitTypeDef;
-
-/**
- * @brief TIM Input Capture Init structure definition
- */
-
-typedef struct
-{
-
- uint16_t TIM_Channel; /*!< Specifies the TIM channel.
- This parameter can be a value of @ref TIM_Channel */
-
- uint16_t TIM_ICPolarity; /*!< Specifies the active edge of the input signal.
- This parameter can be a value of @ref TIM_Input_Capture_Polarity */
-
- uint16_t TIM_ICSelection; /*!< Specifies the input.
- This parameter can be a value of @ref TIM_Input_Capture_Selection */
-
- uint16_t TIM_ICPrescaler; /*!< Specifies the Input Capture Prescaler.
- This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
-
- uint16_t TIM_ICFilter; /*!< Specifies the input capture filter.
- This parameter can be a number between 0x0 and 0xF */
-} TIM_ICInitTypeDef;
-
-/**
- * @brief TIM_BDTR structure definition
- * @note This sturcture is used only with TIM1.
- */
-
-typedef struct
-{
-
- uint16_t TIM_OSSRState; /*!< Specifies the Off-State selection used in Run mode.
- This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
-
- uint16_t TIM_OSSIState; /*!< Specifies the Off-State used in Idle state.
- This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
-
- uint16_t TIM_LOCKLevel; /*!< Specifies the LOCK level parameters.
- This parameter can be a value of @ref TIM_Lock_level */
-
- uint16_t TIM_DeadTime; /*!< Specifies the delay time between the switching-off and the
- switching-on of the outputs.
- This parameter can be a number between 0x00 and 0xFF */
-
- uint16_t TIM_Break; /*!< Specifies whether the TIM Break input is enabled or not.
- This parameter can be a value of @ref TIM_Break_Input_enable_disable */
-
- uint16_t TIM_BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
- This parameter can be a value of @ref TIM_Break_Polarity */
-
- uint16_t TIM_AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
- This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
-} TIM_BDTRInitTypeDef;
-
-/**
- * @brief TIM Input Capture Init structure definition
- */
-
-/* Exported constants --------------------------------------------------------*/
-
-
-/** @defgroup TIM_Exported_constants
- * @{
- */
-
-#define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
- ((PERIPH) == TIM2) || \
- ((PERIPH) == TIM3) || \
- ((PERIPH) == TIM6) || \
- ((PERIPH) == TIM7) || \
- ((PERIPH) == TIM14)|| \
- ((PERIPH) == TIM15)|| \
- ((PERIPH) == TIM16)|| \
- ((PERIPH) == TIM17))
-
-/* LIST1: TIM 1 */
-#define IS_TIM_LIST1_PERIPH(PERIPH) ((PERIPH) == TIM1)
-
-/* LIST2: TIM 1, 15, 16 and 17 */
-#define IS_TIM_LIST2_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
- ((PERIPH) == TIM15)|| \
- ((PERIPH) == TIM16)|| \
- ((PERIPH) == TIM17))
-
-/* LIST3: TIM 1, 2 and 3 */
-#define IS_TIM_LIST3_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
- ((PERIPH) == TIM2) || \
- ((PERIPH) == TIM3))
-
-/* LIST4: TIM 1, 2, 3, 14, 15, 16 and 17 */
-#define IS_TIM_LIST4_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
- ((PERIPH) == TIM2) || \
- ((PERIPH) == TIM3) || \
- ((PERIPH) == TIM14) || \
- ((PERIPH) == TIM15)|| \
- ((PERIPH) == TIM16)|| \
- ((PERIPH) == TIM17))
-
-/* LIST5: TIM 1, 2, 3, 15, 16 and 17 */
-#define IS_TIM_LIST5_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
- ((PERIPH) == TIM2) || \
- ((PERIPH) == TIM3) || \
- ((PERIPH) == TIM15)|| \
- ((PERIPH) == TIM16)|| \
- ((PERIPH) == TIM17))
-
-/* LIST6: TIM 1, 2, 3 and 15 */
-#define IS_TIM_LIST6_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
- ((PERIPH) == TIM2) || \
- ((PERIPH) == TIM3) || \
- ((PERIPH) == TIM15))
-
-/* LIST7: TIM 1, 2, 3, 6, 7 and 14 */
-#define IS_TIM_LIST7_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
- ((PERIPH) == TIM2) || \
- ((PERIPH) == TIM3) || \
- ((PERIPH) == TIM6) || \
- ((PERIPH) == TIM7) || \
- ((PERIPH) == TIM14))
-
-/* LIST8: TIM 1, 2, 3 and 14 */
-#define IS_TIM_LIST8_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
- ((PERIPH) == TIM2) || \
- ((PERIPH) == TIM3) || \
- ((PERIPH) == TIM14))
-
-/* LIST9: TIM 1, 2, 3, 6, 7 and 15 */
-#define IS_TIM_LIST9_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
- ((PERIPH) == TIM2) || \
- ((PERIPH) == TIM3) || \
- ((PERIPH) == TIM6) || \
- ((PERIPH) == TIM7) || \
- ((PERIPH) == TIM15))
-
-/* LIST10: TIM 1, 2, 3, 6, 7, 15, 16 and 17 */
-#define IS_TIM_LIST10_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
- ((PERIPH) == TIM2) || \
- ((PERIPH) == TIM3) || \
- ((PERIPH) == TIM6) || \
- ((PERIPH) == TIM7) || \
- ((PERIPH) == TIM15)|| \
- ((PERIPH) == TIM16)|| \
- ((PERIPH) == TIM17))
-
-/* LIST1: TIM 11 */
-#define IS_TIM_LIST11_PERIPH(PERIPH) ((PERIPH) == TIM14)
-
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Compare_and_PWM_modes
- * @{
- */
-
-#define TIM_OCMode_Timing ((uint16_t)0x0000)
-#define TIM_OCMode_Active ((uint16_t)0x0010)
-#define TIM_OCMode_Inactive ((uint16_t)0x0020)
-#define TIM_OCMode_Toggle ((uint16_t)0x0030)
-#define TIM_OCMode_PWM1 ((uint16_t)0x0060)
-#define TIM_OCMode_PWM2 ((uint16_t)0x0070)
-#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \
- ((MODE) == TIM_OCMode_Active) || \
- ((MODE) == TIM_OCMode_Inactive) || \
- ((MODE) == TIM_OCMode_Toggle)|| \
- ((MODE) == TIM_OCMode_PWM1) || \
- ((MODE) == TIM_OCMode_PWM2))
-#define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \
- ((MODE) == TIM_OCMode_Active) || \
- ((MODE) == TIM_OCMode_Inactive) || \
- ((MODE) == TIM_OCMode_Toggle)|| \
- ((MODE) == TIM_OCMode_PWM1) || \
- ((MODE) == TIM_OCMode_PWM2) || \
- ((MODE) == TIM_ForcedAction_Active) || \
- ((MODE) == TIM_ForcedAction_InActive))
-/**
- * @}
- */
-
-/** @defgroup TIM_One_Pulse_Mode
- * @{
- */
-
-#define TIM_OPMode_Single ((uint16_t)0x0008)
-#define TIM_OPMode_Repetitive ((uint16_t)0x0000)
-#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \
- ((MODE) == TIM_OPMode_Repetitive))
-/**
- * @}
- */
-
-/** @defgroup TIM_Channel
- * @{
- */
-
-#define TIM_Channel_1 ((uint16_t)0x0000)
-#define TIM_Channel_2 ((uint16_t)0x0004)
-#define TIM_Channel_3 ((uint16_t)0x0008)
-#define TIM_Channel_4 ((uint16_t)0x000C)
-
-#define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
- ((CHANNEL) == TIM_Channel_2) || \
- ((CHANNEL) == TIM_Channel_3) || \
- ((CHANNEL) == TIM_Channel_4))
-#define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
- ((CHANNEL) == TIM_Channel_2) || \
- ((CHANNEL) == TIM_Channel_3))
-#define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
- ((CHANNEL) == TIM_Channel_2))
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Clock_Division_CKD
- * @{
- */
-
-#define TIM_CKD_DIV1 ((uint16_t)0x0000)
-#define TIM_CKD_DIV2 ((uint16_t)0x0100)
-#define TIM_CKD_DIV4 ((uint16_t)0x0200)
-#define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \
- ((DIV) == TIM_CKD_DIV2) || \
- ((DIV) == TIM_CKD_DIV4))
-/**
- * @}
- */
-
-/** @defgroup TIM_Counter_Mode
- * @{
- */
-
-#define TIM_CounterMode_Up ((uint16_t)0x0000)
-#define TIM_CounterMode_Down ((uint16_t)0x0010)
-#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020)
-#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040)
-#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060)
-#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) || \
- ((MODE) == TIM_CounterMode_Down) || \
- ((MODE) == TIM_CounterMode_CenterAligned1) || \
- ((MODE) == TIM_CounterMode_CenterAligned2) || \
- ((MODE) == TIM_CounterMode_CenterAligned3))
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Compare_Polarity
- * @{
- */
-
-#define TIM_OCPolarity_High ((uint16_t)0x0000)
-#define TIM_OCPolarity_Low ((uint16_t)0x0002)
-#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \
- ((POLARITY) == TIM_OCPolarity_Low))
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Compare_N_Polarity
- * @{
- */
-
-#define TIM_OCNPolarity_High ((uint16_t)0x0000)
-#define TIM_OCNPolarity_Low ((uint16_t)0x0008)
-#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPolarity_High) || \
- ((POLARITY) == TIM_OCNPolarity_Low))
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Compare_state
- * @{
- */
-
-#define TIM_OutputState_Disable ((uint16_t)0x0000)
-#define TIM_OutputState_Enable ((uint16_t)0x0001)
-#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \
- ((STATE) == TIM_OutputState_Enable))
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Compare_N_state
- * @{
- */
-
-#define TIM_OutputNState_Disable ((uint16_t)0x0000)
-#define TIM_OutputNState_Enable ((uint16_t)0x0004)
-#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) || \
- ((STATE) == TIM_OutputNState_Enable))
-/**
- * @}
- */
-
-/** @defgroup TIM_Capture_Compare_state
- * @{
- */
-
-#define TIM_CCx_Enable ((uint16_t)0x0001)
-#define TIM_CCx_Disable ((uint16_t)0x0000)
-#define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \
- ((CCX) == TIM_CCx_Disable))
-/**
- * @}
- */
-
-/** @defgroup TIM_Capture_Compare_N_state
- * @{
- */
-
-#define TIM_CCxN_Enable ((uint16_t)0x0004)
-#define TIM_CCxN_Disable ((uint16_t)0x0000)
-#define IS_TIM_CCXN(CCXN) (((CCXN) == TIM_CCxN_Enable) || \
- ((CCXN) == TIM_CCxN_Disable))
-/**
- * @}
- */
-
-/** @defgroup TIM_Break_Input_enable_disable
- * @{
- */
-
-#define TIM_Break_Enable ((uint16_t)0x1000)
-#define TIM_Break_Disable ((uint16_t)0x0000)
-#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable) || \
- ((STATE) == TIM_Break_Disable))
-/**
- * @}
- */
-
-/** @defgroup TIM_Break_Polarity
- * @{
- */
-
-#define TIM_BreakPolarity_Low ((uint16_t)0x0000)
-#define TIM_BreakPolarity_High ((uint16_t)0x2000)
-#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low) || \
- ((POLARITY) == TIM_BreakPolarity_High))
-/**
- * @}
- */
-
-/** @defgroup TIM_AOE_Bit_Set_Reset
- * @{
- */
-
-#define TIM_AutomaticOutput_Enable ((uint16_t)0x4000)
-#define TIM_AutomaticOutput_Disable ((uint16_t)0x0000)
-#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AutomaticOutput_Enable) || \
- ((STATE) == TIM_AutomaticOutput_Disable))
-/**
- * @}
- */
-
-/** @defgroup TIM_Lock_level
- * @{
- */
-
-#define TIM_LOCKLevel_OFF ((uint16_t)0x0000)
-#define TIM_LOCKLevel_1 ((uint16_t)0x0100)
-#define TIM_LOCKLevel_2 ((uint16_t)0x0200)
-#define TIM_LOCKLevel_3 ((uint16_t)0x0300)
-#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF) || \
- ((LEVEL) == TIM_LOCKLevel_1) || \
- ((LEVEL) == TIM_LOCKLevel_2) || \
- ((LEVEL) == TIM_LOCKLevel_3))
-/**
- * @}
- */
-
-/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state
- * @{
- */
-
-#define TIM_OSSIState_Enable ((uint16_t)0x0400)
-#define TIM_OSSIState_Disable ((uint16_t)0x0000)
-#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) || \
- ((STATE) == TIM_OSSIState_Disable))
-/**
- * @}
- */
-
-/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state
- * @{
- */
-
-#define TIM_OSSRState_Enable ((uint16_t)0x0800)
-#define TIM_OSSRState_Disable ((uint16_t)0x0000)
-#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) || \
- ((STATE) == TIM_OSSRState_Disable))
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Compare_Idle_State
- * @{
- */
-
-#define TIM_OCIdleState_Set ((uint16_t)0x0100)
-#define TIM_OCIdleState_Reset ((uint16_t)0x0000)
-#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) || \
- ((STATE) == TIM_OCIdleState_Reset))
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Compare_N_Idle_State
- * @{
- */
-
-#define TIM_OCNIdleState_Set ((uint16_t)0x0200)
-#define TIM_OCNIdleState_Reset ((uint16_t)0x0000)
-#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set) || \
- ((STATE) == TIM_OCNIdleState_Reset))
-/**
- * @}
- */
-
-/** @defgroup TIM_Input_Capture_Polarity
- * @{
- */
-
-#define TIM_ICPolarity_Rising ((uint16_t)0x0000)
-#define TIM_ICPolarity_Falling ((uint16_t)0x0002)
-#define TIM_ICPolarity_BothEdge ((uint16_t)0x000A)
-#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \
- ((POLARITY) == TIM_ICPolarity_Falling)|| \
- ((POLARITY) == TIM_ICPolarity_BothEdge))
-/**
- * @}
- */
-
-/** @defgroup TIM_Input_Capture_Selection
- * @{
- */
-
-#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be
- connected to IC1, IC2, IC3 or IC4, respectively */
-#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be
- connected to IC2, IC1, IC4 or IC3, respectively. */
-#define TIM_ICSelection_TRC ((uint16_t)0x0003) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */
-#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \
- ((SELECTION) == TIM_ICSelection_IndirectTI) || \
- ((SELECTION) == TIM_ICSelection_TRC))
-/**
- * @}
- */
-
-/** @defgroup TIM_Input_Capture_Prescaler
- * @{
- */
-
-#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input. */
-#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /*!< Capture performed once every 2 events. */
-#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /*!< Capture performed once every 4 events. */
-#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /*!< Capture performed once every 8 events. */
-#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \
- ((PRESCALER) == TIM_ICPSC_DIV2) || \
- ((PRESCALER) == TIM_ICPSC_DIV4) || \
- ((PRESCALER) == TIM_ICPSC_DIV8))
-/**
- * @}
- */
-
-/** @defgroup TIM_interrupt_sources
- * @{
- */
-
-#define TIM_IT_Update ((uint16_t)0x0001)
-#define TIM_IT_CC1 ((uint16_t)0x0002)
-#define TIM_IT_CC2 ((uint16_t)0x0004)
-#define TIM_IT_CC3 ((uint16_t)0x0008)
-#define TIM_IT_CC4 ((uint16_t)0x0010)
-#define TIM_IT_COM ((uint16_t)0x0020)
-#define TIM_IT_Trigger ((uint16_t)0x0040)
-#define TIM_IT_Break ((uint16_t)0x0080)
-#define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000))
-
-#define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \
- ((IT) == TIM_IT_CC1) || \
- ((IT) == TIM_IT_CC2) || \
- ((IT) == TIM_IT_CC3) || \
- ((IT) == TIM_IT_CC4) || \
- ((IT) == TIM_IT_COM) || \
- ((IT) == TIM_IT_Trigger) || \
- ((IT) == TIM_IT_Break))
-/**
- * @}
- */
-
-/** @defgroup TIM_DMA_Base_address
- * @{
- */
-
-#define TIM_DMABase_CR1 ((uint16_t)0x0000)
-#define TIM_DMABase_CR2 ((uint16_t)0x0001)
-#define TIM_DMABase_SMCR ((uint16_t)0x0002)
-#define TIM_DMABase_DIER ((uint16_t)0x0003)
-#define TIM_DMABase_SR ((uint16_t)0x0004)
-#define TIM_DMABase_EGR ((uint16_t)0x0005)
-#define TIM_DMABase_CCMR1 ((uint16_t)0x0006)
-#define TIM_DMABase_CCMR2 ((uint16_t)0x0007)
-#define TIM_DMABase_CCER ((uint16_t)0x0008)
-#define TIM_DMABase_CNT ((uint16_t)0x0009)
-#define TIM_DMABase_PSC ((uint16_t)0x000A)
-#define TIM_DMABase_ARR ((uint16_t)0x000B)
-#define TIM_DMABase_RCR ((uint16_t)0x000C)
-#define TIM_DMABase_CCR1 ((uint16_t)0x000D)
-#define TIM_DMABase_CCR2 ((uint16_t)0x000E)
-#define TIM_DMABase_CCR3 ((uint16_t)0x000F)
-#define TIM_DMABase_CCR4 ((uint16_t)0x0010)
-#define TIM_DMABase_BDTR ((uint16_t)0x0011)
-#define TIM_DMABase_DCR ((uint16_t)0x0012)
-#define TIM_DMABase_OR ((uint16_t)0x0013)
-#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \
- ((BASE) == TIM_DMABase_CR2) || \
- ((BASE) == TIM_DMABase_SMCR) || \
- ((BASE) == TIM_DMABase_DIER) || \
- ((BASE) == TIM_DMABase_SR) || \
- ((BASE) == TIM_DMABase_EGR) || \
- ((BASE) == TIM_DMABase_CCMR1) || \
- ((BASE) == TIM_DMABase_CCMR2) || \
- ((BASE) == TIM_DMABase_CCER) || \
- ((BASE) == TIM_DMABase_CNT) || \
- ((BASE) == TIM_DMABase_PSC) || \
- ((BASE) == TIM_DMABase_ARR) || \
- ((BASE) == TIM_DMABase_RCR) || \
- ((BASE) == TIM_DMABase_CCR1) || \
- ((BASE) == TIM_DMABase_CCR2) || \
- ((BASE) == TIM_DMABase_CCR3) || \
- ((BASE) == TIM_DMABase_CCR4) || \
- ((BASE) == TIM_DMABase_BDTR) || \
- ((BASE) == TIM_DMABase_DCR) || \
- ((BASE) == TIM_DMABase_OR))
-/**
- * @}
- */
-
-
-/** @defgroup TIM_DMA_Burst_Length
- * @{
- */
-
-#define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000)
-#define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100)
-#define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200)
-#define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300)
-#define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400)
-#define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500)
-#define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600)
-#define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700)
-#define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800)
-#define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900)
-#define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00)
-#define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00)
-#define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00)
-#define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00)
-#define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00)
-#define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00)
-#define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000)
-#define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100)
-#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) || \
- ((LENGTH) == TIM_DMABurstLength_2Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_3Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_4Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_5Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_6Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_7Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_8Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_9Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_10Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_11Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_12Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_13Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_14Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_15Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_16Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_17Transfers) || \
- ((LENGTH) == TIM_DMABurstLength_18Transfers))
-/**
- * @}
- */
-
-/** @defgroup TIM_DMA_sources
- * @{
- */
-
-#define TIM_DMA_Update ((uint16_t)0x0100)
-#define TIM_DMA_CC1 ((uint16_t)0x0200)
-#define TIM_DMA_CC2 ((uint16_t)0x0400)
-#define TIM_DMA_CC3 ((uint16_t)0x0800)
-#define TIM_DMA_CC4 ((uint16_t)0x1000)
-#define TIM_DMA_COM ((uint16_t)0x2000)
-#define TIM_DMA_Trigger ((uint16_t)0x4000)
-#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000))
-
-/**
- * @}
- */
-
-/** @defgroup TIM_External_Trigger_Prescaler
- * @{
- */
-
-#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000)
-#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000)
-#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000)
-#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000)
-#define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \
- ((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \
- ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \
- ((PRESCALER) == TIM_ExtTRGPSC_DIV8))
-/**
- * @}
- */
-
-/** @defgroup TIM_Internal_Trigger_Selection
- * @{
- */
-
-#define TIM_TS_ITR0 ((uint16_t)0x0000)
-#define TIM_TS_ITR1 ((uint16_t)0x0010)
-#define TIM_TS_ITR2 ((uint16_t)0x0020)
-#define TIM_TS_ITR3 ((uint16_t)0x0030)
-#define TIM_TS_TI1F_ED ((uint16_t)0x0040)
-#define TIM_TS_TI1FP1 ((uint16_t)0x0050)
-#define TIM_TS_TI2FP2 ((uint16_t)0x0060)
-#define TIM_TS_ETRF ((uint16_t)0x0070)
-#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
- ((SELECTION) == TIM_TS_ITR1) || \
- ((SELECTION) == TIM_TS_ITR2) || \
- ((SELECTION) == TIM_TS_ITR3) || \
- ((SELECTION) == TIM_TS_TI1F_ED) || \
- ((SELECTION) == TIM_TS_TI1FP1) || \
- ((SELECTION) == TIM_TS_TI2FP2) || \
- ((SELECTION) == TIM_TS_ETRF))
-#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
- ((SELECTION) == TIM_TS_ITR1) || \
- ((SELECTION) == TIM_TS_ITR2) || \
- ((SELECTION) == TIM_TS_ITR3))
-/**
- * @}
- */
-
-/** @defgroup TIM_TIx_External_Clock_Source
- * @{
- */
-
-#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050)
-#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060)
-#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040)
-
-/**
- * @}
- */
-
-/** @defgroup TIM_External_Trigger_Polarity
- * @{
- */
-#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000)
-#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000)
-#define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \
- ((POLARITY) == TIM_ExtTRGPolarity_NonInverted))
-/**
- * @}
- */
-
-/** @defgroup TIM_Prescaler_Reload_Mode
- * @{
- */
-
-#define TIM_PSCReloadMode_Update ((uint16_t)0x0000)
-#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001)
-#define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \
- ((RELOAD) == TIM_PSCReloadMode_Immediate))
-/**
- * @}
- */
-
-/** @defgroup TIM_Forced_Action
- * @{
- */
-
-#define TIM_ForcedAction_Active ((uint16_t)0x0050)
-#define TIM_ForcedAction_InActive ((uint16_t)0x0040)
-#define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \
- ((ACTION) == TIM_ForcedAction_InActive))
-/**
- * @}
- */
-
-/** @defgroup TIM_Encoder_Mode
- * @{
- */
-
-#define TIM_EncoderMode_TI1 ((uint16_t)0x0001)
-#define TIM_EncoderMode_TI2 ((uint16_t)0x0002)
-#define TIM_EncoderMode_TI12 ((uint16_t)0x0003)
-#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \
- ((MODE) == TIM_EncoderMode_TI2) || \
- ((MODE) == TIM_EncoderMode_TI12))
-/**
- * @}
- */
-
-
-/** @defgroup TIM_Event_Source
- * @{
- */
-
-#define TIM_EventSource_Update ((uint16_t)0x0001)
-#define TIM_EventSource_CC1 ((uint16_t)0x0002)
-#define TIM_EventSource_CC2 ((uint16_t)0x0004)
-#define TIM_EventSource_CC3 ((uint16_t)0x0008)
-#define TIM_EventSource_CC4 ((uint16_t)0x0010)
-#define TIM_EventSource_COM ((uint16_t)0x0020)
-#define TIM_EventSource_Trigger ((uint16_t)0x0040)
-#define TIM_EventSource_Break ((uint16_t)0x0080)
-#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x0000))
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Update_Source
- * @{
- */
-
-#define TIM_UpdateSource_Global ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow
- or the setting of UG bit, or an update generation
- through the slave mode controller. */
-#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /*!< Source of update is counter overflow/underflow. */
-#define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \
- ((SOURCE) == TIM_UpdateSource_Regular))
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Compare_Preload_State
- * @{
- */
-
-#define TIM_OCPreload_Enable ((uint16_t)0x0008)
-#define TIM_OCPreload_Disable ((uint16_t)0x0000)
-#define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \
- ((STATE) == TIM_OCPreload_Disable))
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Compare_Fast_State
- * @{
- */
-
-#define TIM_OCFast_Enable ((uint16_t)0x0004)
-#define TIM_OCFast_Disable ((uint16_t)0x0000)
-#define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \
- ((STATE) == TIM_OCFast_Disable))
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Output_Compare_Clear_State
- * @{
- */
-
-#define TIM_OCClear_Enable ((uint16_t)0x0080)
-#define TIM_OCClear_Disable ((uint16_t)0x0000)
-#define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \
- ((STATE) == TIM_OCClear_Disable))
-/**
- * @}
- */
-
-/** @defgroup TIM_Trigger_Output_Source
- * @{
- */
-
-#define TIM_TRGOSource_Reset ((uint16_t)0x0000)
-#define TIM_TRGOSource_Enable ((uint16_t)0x0010)
-#define TIM_TRGOSource_Update ((uint16_t)0x0020)
-#define TIM_TRGOSource_OC1 ((uint16_t)0x0030)
-#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040)
-#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050)
-#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060)
-#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070)
-#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \
- ((SOURCE) == TIM_TRGOSource_Enable) || \
- ((SOURCE) == TIM_TRGOSource_Update) || \
- ((SOURCE) == TIM_TRGOSource_OC1) || \
- ((SOURCE) == TIM_TRGOSource_OC1Ref) || \
- ((SOURCE) == TIM_TRGOSource_OC2Ref) || \
- ((SOURCE) == TIM_TRGOSource_OC3Ref) || \
- ((SOURCE) == TIM_TRGOSource_OC4Ref))
-/**
- * @}
- */
-
-/** @defgroup TIM_Slave_Mode
- * @{
- */
-
-#define TIM_SlaveMode_Reset ((uint16_t)0x0004)
-#define TIM_SlaveMode_Gated ((uint16_t)0x0005)
-#define TIM_SlaveMode_Trigger ((uint16_t)0x0006)
-#define TIM_SlaveMode_External1 ((uint16_t)0x0007)
-#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \
- ((MODE) == TIM_SlaveMode_Gated) || \
- ((MODE) == TIM_SlaveMode_Trigger) || \
- ((MODE) == TIM_SlaveMode_External1))
-/**
- * @}
- */
-
-/** @defgroup TIM_Master_Slave_Mode
- * @{
- */
-
-#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080)
-#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000)
-#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \
- ((STATE) == TIM_MasterSlaveMode_Disable))
-/**
- * @}
- */
-
-/** @defgroup TIM_Flags
- * @{
- */
-
-#define TIM_FLAG_Update ((uint16_t)0x0001)
-#define TIM_FLAG_CC1 ((uint16_t)0x0002)
-#define TIM_FLAG_CC2 ((uint16_t)0x0004)
-#define TIM_FLAG_CC3 ((uint16_t)0x0008)
-#define TIM_FLAG_CC4 ((uint16_t)0x0010)
-#define TIM_FLAG_COM ((uint16_t)0x0020)
-#define TIM_FLAG_Trigger ((uint16_t)0x0040)
-#define TIM_FLAG_Break ((uint16_t)0x0080)
-#define TIM_FLAG_CC1OF ((uint16_t)0x0200)
-#define TIM_FLAG_CC2OF ((uint16_t)0x0400)
-#define TIM_FLAG_CC3OF ((uint16_t)0x0800)
-#define TIM_FLAG_CC4OF ((uint16_t)0x1000)
-#define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \
- ((FLAG) == TIM_FLAG_CC1) || \
- ((FLAG) == TIM_FLAG_CC2) || \
- ((FLAG) == TIM_FLAG_CC3) || \
- ((FLAG) == TIM_FLAG_CC4) || \
- ((FLAG) == TIM_FLAG_COM) || \
- ((FLAG) == TIM_FLAG_Trigger) || \
- ((FLAG) == TIM_FLAG_Break) || \
- ((FLAG) == TIM_FLAG_CC1OF) || \
- ((FLAG) == TIM_FLAG_CC2OF) || \
- ((FLAG) == TIM_FLAG_CC3OF) || \
- ((FLAG) == TIM_FLAG_CC4OF))
-
-
-#define IS_TIM_CLEAR_FLAG(TIM_FLAG) ((((TIM_FLAG) & (uint16_t)0xE100) == 0x0000) && ((TIM_FLAG) != 0x0000))
-/**
- * @}
- */
-
-
-/** @defgroup TIM_Input_Capture_Filer_Value
- * @{
- */
-
-#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
-/**
- * @}
- */
-
-/** @defgroup TIM_External_Trigger_Filter
- * @{
- */
-
-#define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF)
-/**
- * @}
- */
-
-/** @defgroup TIM_OCReferenceClear
- * @{
- */
-#define TIM_OCReferenceClear_ETRF ((uint16_t)0x0008)
-#define TIM_OCReferenceClear_OCREFCLR ((uint16_t)0x0000)
-#define TIM_OCREFERENCECECLEAR_SOURCE(SOURCE) (((SOURCE) == TIM_OCReferenceClear_ETRF) || \
- ((SOURCE) == TIM_OCReferenceClear_OCREFCLR))
-
-/**
- * @}
- */
-/** @defgroup TIM_Remap
- * @{
- */
-#define TIM14_GPIO ((uint16_t)0x0000)
-#define TIM14_RTC_CLK ((uint16_t)0x0001)
-#define TIM14_HSEDiv32 ((uint16_t)0x0002)
-#define TIM14_MCO ((uint16_t)0x0003)
-
-#define IS_TIM_REMAP(TIM_REMAP) (((TIM_REMAP) == TIM14_GPIO)|| \
- ((TIM_REMAP) == TIM14_RTC_CLK) || \
- ((TIM_REMAP) == TIM14_HSEDiv32) || \
- ((TIM_REMAP) == TIM14_MCO))
-/**
- * @}
- */
-
-/** @defgroup TIM_Legacy
- * @{
- */
-
-#define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer
-#define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers
-#define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers
-#define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers
-#define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers
-#define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers
-#define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers
-#define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers
-#define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers
-#define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers
-#define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers
-#define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers
-#define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers
-#define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers
-#define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers
-#define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers
-#define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers
-#define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-/* TimeBase management ********************************************************/
-void TIM_DeInit(TIM_TypeDef* TIMx);
-void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
-void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
-void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode);
-void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode);
-void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter);
-void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload);
-uint32_t TIM_GetCounter(TIM_TypeDef* TIMx);
-uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx);
-void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
-void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource);
-void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
-void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode);
-void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD);
-void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState);
-
-/* Advanced-control timers (TIM1) specific features*******************/
-void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct);
-void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct);
-void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState);
-
-/* Output Compare management **************************************************/
-void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
-void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
-void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
-void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
-void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct);
-void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode);
-void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1);
-void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2);
-void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3);
-void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4);
-void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
-void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
-void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
-void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
-void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState);
-void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
-void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
-void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
-void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
-void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
-void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
-void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
-void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
-void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
-void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
-void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
-void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
-void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
-void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
-void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
-void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
-void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
-void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
-void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
-void TIM_SelectOCREFClear(TIM_TypeDef* TIMx, uint16_t TIM_OCReferenceClear);
-void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx);
-void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN);
-void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState);
-
-/* Input Capture management ***************************************************/
-void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
-void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct);
-void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
-uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx);
-uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx);
-uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx);
-uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx);
-void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
-void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
-void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
-void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
-
-/* Interrupts, DMA and flags management ***************************************/
-void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState);
-void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource);
-FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);
-void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);
-ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT);
-void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT);
-void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength);
-void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState);
-void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState);
-
-/* Clocks management **********************************************************/
-void TIM_InternalClockConfig(TIM_TypeDef* TIMx);
-void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
-void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,
- uint16_t TIM_ICPolarity, uint16_t ICFilter);
-void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
- uint16_t ExtTRGFilter);
-void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
- uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter);
-
-
-/* Synchronization management *************************************************/
-void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
-void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource);
-void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode);
-void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode);
-void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
- uint16_t ExtTRGFilter);
-
-/* Specific interface management **********************************************/
-void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
- uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity);
-void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState);
-
-/* Specific remapping management **********************************************/
-void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap);
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F0XX_TIM_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_usart.h b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_usart.h
deleted file mode 100644
index c9d170a119c0b669c65c8bbc3bc0d1ddd48f58b1..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_usart.h
+++ /dev/null
@@ -1,599 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f0xx_usart.h
- * @author MCD Application Team
- * @version V1.3.0
- * @date 16-January-2014
- * @brief This file contains all the functions prototypes for the USART
- * firmware library.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F0XX_USART_H
-#define __STM32F0XX_USART_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup USART
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-
-
-/**
- * @brief USART Init Structure definition
- */
-
-typedef struct
-{
- uint32_t USART_BaudRate; /*!< This member configures the USART communication baud rate.
- The baud rate is computed using the following formula:
- - IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate)))
- - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 16) + 0.5 */
-
- uint32_t USART_WordLength; /*!< Specifies the number of data bits transmitted or received in a frame.
- This parameter can be a value of @ref USART_Word_Length */
-
- uint32_t USART_StopBits; /*!< Specifies the number of stop bits transmitted.
- This parameter can be a value of @ref USART_Stop_Bits */
-
- uint32_t USART_Parity; /*!< Specifies the parity mode.
- This parameter can be a value of @ref USART_Parity
- @note When parity is enabled, the computed parity is inserted
- at the MSB position of the transmitted data (9th bit when
- the word length is set to 9 data bits; 8th bit when the
- word length is set to 8 data bits). */
-
- uint32_t USART_Mode; /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
- This parameter can be a value of @ref USART_Mode */
-
- uint32_t USART_HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled
- or disabled.
- This parameter can be a value of @ref USART_Hardware_Flow_Control*/
-} USART_InitTypeDef;
-
-/**
- * @brief USART Clock Init Structure definition
- */
-
-typedef struct
-{
- uint32_t USART_Clock; /*!< Specifies whether the USART clock is enabled or disabled.
- This parameter can be a value of @ref USART_Clock */
-
- uint32_t USART_CPOL; /*!< Specifies the steady state of the serial clock.
- This parameter can be a value of @ref USART_Clock_Polarity */
-
- uint32_t USART_CPHA; /*!< Specifies the clock transition on which the bit capture is made.
- This parameter can be a value of @ref USART_Clock_Phase */
-
- uint32_t USART_LastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted
- data bit (MSB) has to be output on the SCLK pin in synchronous mode.
- This parameter can be a value of @ref USART_Last_Bit */
-} USART_ClockInitTypeDef;
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup USART_Exported_Constants
- * @{
- */
-
-#define IS_USART_ALL_PERIPH(PERIPH) (((PERIPH) == USART1) || \
- ((PERIPH) == USART2) || \
- ((PERIPH) == USART3) || \
- ((PERIPH) == USART4))
-
-#define IS_USART_12_PERIPH(PERIPH) (((PERIPH) == USART1) || \
- ((PERIPH) == USART2))
-
-/** @defgroup USART_Word_Length
- * @{
- */
-
-#define USART_WordLength_8b ((uint32_t)0x00000000)
-#define USART_WordLength_9b USART_CR1_M /* should be ((uint32_t)0x00001000) */
-#define USART_WordLength_7b ((uint32_t)0x10001000) /*!< only available for STM32F072 and STM32F030 devices */
-#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || \
- ((LENGTH) == USART_WordLength_9b) || \
- ((LENGTH) == USART_WordLength_7b))
-/**
- * @}
- */
-
-/** @defgroup USART_Stop_Bits
- * @{
- */
-
-#define USART_StopBits_1 ((uint32_t)0x00000000)
-#define USART_StopBits_2 USART_CR2_STOP_1
-#define USART_StopBits_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1)
-#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \
- ((STOPBITS) == USART_StopBits_2) || \
- ((STOPBITS) == USART_StopBits_1_5))
-/**
- * @}
- */
-
-/** @defgroup USART_Parity
- * @{
- */
-
-#define USART_Parity_No ((uint32_t)0x00000000)
-#define USART_Parity_Even USART_CR1_PCE
-#define USART_Parity_Odd (USART_CR1_PCE | USART_CR1_PS)
-#define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \
- ((PARITY) == USART_Parity_Even) || \
- ((PARITY) == USART_Parity_Odd))
-/**
- * @}
- */
-
-/** @defgroup USART_Mode
- * @{
- */
-
-#define USART_Mode_Rx USART_CR1_RE
-#define USART_Mode_Tx USART_CR1_TE
-#define IS_USART_MODE(MODE) ((((MODE) & (uint32_t)0xFFFFFFF3) == 0x00) && \
- ((MODE) != (uint32_t)0x00))
-/**
- * @}
- */
-
-/** @defgroup USART_Hardware_Flow_Control
- * @{
- */
-
-#define USART_HardwareFlowControl_None ((uint32_t)0x00000000)
-#define USART_HardwareFlowControl_RTS USART_CR3_RTSE
-#define USART_HardwareFlowControl_CTS USART_CR3_CTSE
-#define USART_HardwareFlowControl_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE)
-#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\
- (((CONTROL) == USART_HardwareFlowControl_None) || \
- ((CONTROL) == USART_HardwareFlowControl_RTS) || \
- ((CONTROL) == USART_HardwareFlowControl_CTS) || \
- ((CONTROL) == USART_HardwareFlowControl_RTS_CTS))
-/**
- * @}
- */
-
-/** @defgroup USART_Clock
- * @{
- */
-
-#define USART_Clock_Disable ((uint32_t)0x00000000)
-#define USART_Clock_Enable USART_CR2_CLKEN
-#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \
- ((CLOCK) == USART_Clock_Enable))
-/**
- * @}
- */
-
-/** @defgroup USART_Clock_Polarity
- * @{
- */
-
-#define USART_CPOL_Low ((uint32_t)0x00000000)
-#define USART_CPOL_High USART_CR2_CPOL
-#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High))
-
-/**
- * @}
- */
-
-/** @defgroup USART_Clock_Phase
- * @{
- */
-
-#define USART_CPHA_1Edge ((uint32_t)0x00000000)
-#define USART_CPHA_2Edge USART_CR2_CPHA
-#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge))
-
-/**
- * @}
- */
-
-/** @defgroup USART_Last_Bit
- * @{
- */
-
-#define USART_LastBit_Disable ((uint32_t)0x00000000)
-#define USART_LastBit_Enable USART_CR2_LBCL
-#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \
- ((LASTBIT) == USART_LastBit_Enable))
-/**
- * @}
- */
-
-/** @defgroup USART_DMA_Requests
- * @{
- */
-
-#define USART_DMAReq_Tx USART_CR3_DMAT
-#define USART_DMAReq_Rx USART_CR3_DMAR
-#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint32_t)0xFFFFFF3F) == 0x00) && \
- ((DMAREQ) != (uint32_t)0x00))
-
-/**
- * @}
- */
-
-/** @defgroup USART_DMA_Recception_Error
- * @{
- */
-
-#define USART_DMAOnError_Enable ((uint32_t)0x00000000)
-#define USART_DMAOnError_Disable USART_CR3_DDRE
-#define IS_USART_DMAONERROR(DMAERROR) (((DMAERROR) == USART_DMAOnError_Disable)|| \
- ((DMAERROR) == USART_DMAOnError_Enable))
-/**
- * @}
- */
-
-/** @defgroup USART_MuteMode_WakeUp_methods
- * @{
- */
-
-#define USART_WakeUp_IdleLine ((uint32_t)0x00000000)
-#define USART_WakeUp_AddressMark USART_CR1_WAKE
-#define IS_USART_MUTEMODE_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || \
- ((WAKEUP) == USART_WakeUp_AddressMark))
-/**
- * @}
- */
-
-/** @defgroup USART_Address_Detection
- * @{
- */
-
-#define USART_AddressLength_4b ((uint32_t)0x00000000)
-#define USART_AddressLength_7b USART_CR2_ADDM7
-#define IS_USART_ADDRESS_DETECTION(ADDRESS) (((ADDRESS) == USART_AddressLength_4b) || \
- ((ADDRESS) == USART_AddressLength_7b))
-/**
- * @}
- */
-
-/** @defgroup USART_StopMode_WakeUp_methods
- * @note These parameters are only available for STM32F051 and STM32F072 devices
- * @{
- */
-
-#define USART_WakeUpSource_AddressMatch ((uint32_t)0x00000000)
-#define USART_WakeUpSource_StartBit USART_CR3_WUS_1
-#define USART_WakeUpSource_RXNE (USART_CR3_WUS_0 | USART_CR3_WUS_1)
-#define IS_USART_STOPMODE_WAKEUPSOURCE(SOURCE) (((SOURCE) == USART_WakeUpSource_AddressMatch) || \
- ((SOURCE) == USART_WakeUpSource_StartBit) || \
- ((SOURCE) == USART_WakeUpSource_RXNE))
-/**
- * @}
- */
-
-/** @defgroup USART_LIN_Break_Detection_Length
- * @{
- */
-
-#define USART_LINBreakDetectLength_10b ((uint32_t)0x00000000)
-#define USART_LINBreakDetectLength_11b USART_CR2_LBDL
-#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \
- (((LENGTH) == USART_LINBreakDetectLength_10b) || \
- ((LENGTH) == USART_LINBreakDetectLength_11b))
-/**
- * @}
- */
-
-/** @defgroup USART_IrDA_Low_Power
- * @{
- */
-
-#define USART_IrDAMode_LowPower USART_CR3_IRLP
-#define USART_IrDAMode_Normal ((uint32_t)0x00000000)
-#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || \
- ((MODE) == USART_IrDAMode_Normal))
-/**
- * @}
- */
-
-/** @defgroup USART_DE_Polarity
- * @{
- */
-
-#define USART_DEPolarity_High ((uint32_t)0x00000000)
-#define USART_DEPolarity_Low USART_CR3_DEP
-#define IS_USART_DE_POLARITY(POLARITY) (((POLARITY) == USART_DEPolarity_Low) || \
- ((POLARITY) == USART_DEPolarity_High))
-/**
- * @}
- */
-
-/** @defgroup USART_Inversion_Pins
- * @{
- */
-
-#define USART_InvPin_Tx USART_CR2_TXINV
-#define USART_InvPin_Rx USART_CR2_RXINV
-#define IS_USART_INVERSTION_PIN(PIN) ((((PIN) & (uint32_t)0xFFFCFFFF) == 0x00) && \
- ((PIN) != (uint32_t)0x00))
-
-/**
- * @}
- */
-
-/** @defgroup USART_AutoBaudRate_Mode
- * @{
- */
-
-#define USART_AutoBaudRate_StartBit ((uint32_t)0x00000000)
-#define USART_AutoBaudRate_FallingEdge USART_CR2_ABRMODE_0
-#define IS_USART_AUTOBAUDRATE_MODE(MODE) (((MODE) == USART_AutoBaudRate_StartBit) || \
- ((MODE) == USART_AutoBaudRate_FallingEdge))
-/**
- * @}
- */
-
-/** @defgroup USART_OVR_DETECTION
- * @{
- */
-
-#define USART_OVRDetection_Enable ((uint32_t)0x00000000)
-#define USART_OVRDetection_Disable USART_CR3_OVRDIS
-#define IS_USART_OVRDETECTION(OVR) (((OVR) == USART_OVRDetection_Enable)|| \
- ((OVR) == USART_OVRDetection_Disable))
-/**
- * @}
- */
-/** @defgroup USART_Request
- * @{
- */
-
-#define USART_Request_ABRRQ USART_RQR_ABRRQ
-#define USART_Request_SBKRQ USART_RQR_SBKRQ
-#define USART_Request_MMRQ USART_RQR_MMRQ
-#define USART_Request_RXFRQ USART_RQR_RXFRQ
-#define USART_Request_TXFRQ USART_RQR_TXFRQ
-
-#define IS_USART_REQUEST(REQUEST) (((REQUEST) == USART_Request_TXFRQ) || \
- ((REQUEST) == USART_Request_RXFRQ) || \
- ((REQUEST) == USART_Request_MMRQ) || \
- ((REQUEST) == USART_Request_SBKRQ) || \
- ((REQUEST) == USART_Request_ABRRQ))
-/**
- * @}
- */
-
-/** @defgroup USART_Flags
- * @{
- */
-#define USART_FLAG_REACK USART_ISR_REACK
-#define USART_FLAG_TEACK USART_ISR_TEACK
-#define USART_FLAG_WU USART_ISR_WUF /*!< Not available for STM32F030 devices */
-#define USART_FLAG_RWU USART_ISR_RWU /*!< Not available for STM32F030 devices */
-#define USART_FLAG_SBK USART_ISR_SBKF
-#define USART_FLAG_CM USART_ISR_CMF
-#define USART_FLAG_BUSY USART_ISR_BUSY
-#define USART_FLAG_ABRF USART_ISR_ABRF
-#define USART_FLAG_ABRE USART_ISR_ABRE
-#define USART_FLAG_EOB USART_ISR_EOBF /*!< Not available for STM32F030 devices */
-#define USART_FLAG_RTO USART_ISR_RTOF
-#define USART_FLAG_nCTSS USART_ISR_CTS
-#define USART_FLAG_CTS USART_ISR_CTSIF
-#define USART_FLAG_LBD USART_ISR_LBD /*!< Not available for STM32F030 devices */
-#define USART_FLAG_TXE USART_ISR_TXE
-#define USART_FLAG_TC USART_ISR_TC
-#define USART_FLAG_RXNE USART_ISR_RXNE
-#define USART_FLAG_IDLE USART_ISR_IDLE
-#define USART_FLAG_ORE USART_ISR_ORE
-#define USART_FLAG_NE USART_ISR_NE
-#define USART_FLAG_FE USART_ISR_FE
-#define USART_FLAG_PE USART_ISR_PE
-#define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \
- ((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \
- ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \
- ((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \
- ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE) || \
- ((FLAG) == USART_FLAG_nCTSS) || ((FLAG) == USART_FLAG_RTO) || \
- ((FLAG) == USART_FLAG_EOB) || ((FLAG) == USART_FLAG_ABRE) || \
- ((FLAG) == USART_FLAG_ABRF) || ((FLAG) == USART_FLAG_BUSY) || \
- ((FLAG) == USART_FLAG_CM) || ((FLAG) == USART_FLAG_SBK) || \
- ((FLAG) == USART_FLAG_RWU) || ((FLAG) == USART_FLAG_WU) || \
- ((FLAG) == USART_FLAG_TEACK)|| ((FLAG) == USART_FLAG_REACK))
-
-#define IS_USART_CLEAR_FLAG(FLAG) (((FLAG) == USART_FLAG_WU) || ((FLAG) == USART_FLAG_TC) || \
- ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_ORE) || \
- ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE) || \
- ((FLAG) == USART_FLAG_LBD) || ((FLAG) == USART_FLAG_CTS) || \
- ((FLAG) == USART_FLAG_RTO) || ((FLAG) == USART_FLAG_EOB) || \
- ((FLAG) == USART_FLAG_CM) || ((FLAG) == USART_FLAG_PE))
-/**
- * @}
- */
-
-/** @defgroup USART_Interrupt_definition
- * @brief USART Interrupt definition
- * USART_IT possible values
- * Elements values convention: 0xZZZZYYXX
- * XX: Position of the corresponding Interrupt
- * YY: Register index
- * ZZZZ: Flag position
- * @{
- */
-
-#define USART_IT_WU ((uint32_t)0x00140316) /*!< Not available for STM32F030 devices */
-#define USART_IT_CM ((uint32_t)0x0011010E)
-#define USART_IT_EOB ((uint32_t)0x000C011B) /*!< Not available for STM32F030 devices */
-#define USART_IT_RTO ((uint32_t)0x000B011A)
-#define USART_IT_PE ((uint32_t)0x00000108)
-#define USART_IT_TXE ((uint32_t)0x00070107)
-#define USART_IT_TC ((uint32_t)0x00060106)
-#define USART_IT_RXNE ((uint32_t)0x00050105)
-#define USART_IT_IDLE ((uint32_t)0x00040104)
-#define USART_IT_LBD ((uint32_t)0x00080206) /*!< Not available for STM32F030 devices */
-#define USART_IT_CTS ((uint32_t)0x0009030A)
-#define USART_IT_ERR ((uint32_t)0x00000300)
-#define USART_IT_ORE ((uint32_t)0x00030300)
-#define USART_IT_NE ((uint32_t)0x00020300)
-#define USART_IT_FE ((uint32_t)0x00010300)
-
-#define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
- ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
- ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
- ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR) || \
- ((IT) == USART_IT_RTO) || ((IT) == USART_IT_EOB) || \
- ((IT) == USART_IT_CM) || ((IT) == USART_IT_WU))
-
-#define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
- ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
- ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
- ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE) || \
- ((IT) == USART_IT_NE) || ((IT) == USART_IT_FE) || \
- ((IT) == USART_IT_RTO) || ((IT) == USART_IT_EOB) || \
- ((IT) == USART_IT_CM) || ((IT) == USART_IT_WU))
-
-#define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_PE) || \
- ((IT) == USART_IT_FE) || ((IT) == USART_IT_NE) || \
- ((IT) == USART_IT_ORE) || ((IT) == USART_IT_IDLE) || \
- ((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS) || \
- ((IT) == USART_IT_RTO) || ((IT) == USART_IT_EOB) || \
- ((IT) == USART_IT_CM) || ((IT) == USART_IT_WU))
-/**
- * @}
- */
-
-/** @defgroup USART_Global_definition
- * @{
- */
-
-#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 0x005B8D81))
-#define IS_USART_DE_ASSERTION_DEASSERTION_TIME(TIME) ((TIME) <= 0x1F)
-#define IS_USART_AUTO_RETRY_COUNTER(COUNTER) ((COUNTER) <= 0x7)
-#define IS_USART_TIMEOUT(TIMEOUT) ((TIMEOUT) <= 0x00FFFFFF)
-#define IS_USART_DATA(DATA) ((DATA) <= 0x1FF)
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-/* Initialization and Configuration functions *********************************/
-void USART_DeInit(USART_TypeDef* USARTx);
-void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct);
-void USART_StructInit(USART_InitTypeDef* USART_InitStruct);
-void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct);
-void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct);
-void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
-void USART_DirectionModeCmd(USART_TypeDef* USARTx, uint32_t USART_DirectionMode, FunctionalState NewState);
-void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler); /* Not available for STM32F030 devices */
-void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
-void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState);
-void USART_MSBFirstCmd(USART_TypeDef* USARTx, FunctionalState NewState);
-void USART_DataInvCmd(USART_TypeDef* USARTx, FunctionalState NewState);
-void USART_InvPinCmd(USART_TypeDef* USARTx, uint32_t USART_InvPin, FunctionalState NewState);
-void USART_SWAPPinCmd(USART_TypeDef* USARTx, FunctionalState NewState);
-void USART_ReceiverTimeOutCmd(USART_TypeDef* USARTx, FunctionalState NewState);
-void USART_SetReceiverTimeOut(USART_TypeDef* USARTx, uint32_t USART_ReceiverTimeOut);
-
-/* STOP Mode functions ********************************************************/
-void USART_STOPModeCmd(USART_TypeDef* USARTx, FunctionalState NewState);
-void USART_StopModeWakeUpSourceConfig(USART_TypeDef* USARTx, uint32_t USART_WakeUpSource); /* Not available for STM32F030 devices */
-
-/* AutoBaudRate functions *****************************************************/
-void USART_AutoBaudRateCmd(USART_TypeDef* USARTx, FunctionalState NewState);
-void USART_AutoBaudRateConfig(USART_TypeDef* USARTx, uint32_t USART_AutoBaudRate);
-
-/* Data transfers functions ***************************************************/
-void USART_SendData(USART_TypeDef* USARTx, uint16_t Data);
-uint16_t USART_ReceiveData(USART_TypeDef* USARTx);
-
-/* Multi-Processor Communication functions ************************************/
-void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address);
-void USART_MuteModeWakeUpConfig(USART_TypeDef* USARTx, uint32_t USART_WakeUp);
-void USART_MuteModeCmd(USART_TypeDef* USARTx, FunctionalState NewState);
-void USART_AddressDetectionConfig(USART_TypeDef* USARTx, uint32_t USART_AddressLength);
-
-/* LIN mode functions *********************************************************/
-void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint32_t USART_LINBreakDetectLength); /* Not available for STM32F030 devices */
-void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState); /* Not available for STM32F030 devices */
-
-/* Half-duplex mode function **************************************************/
-void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState);
-
-/* Smartcard mode functions ***************************************************/
-void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState); /* Not available for STM32F030 devices */
-void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState); /* Not available for STM32F030 devices */
-void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime); /* Not available for STM32F030 devices */
-void USART_SetAutoRetryCount(USART_TypeDef* USARTx, uint8_t USART_AutoCount); /* Not available for STM32F030 devices */
-void USART_SetBlockLength(USART_TypeDef* USARTx, uint8_t USART_BlockLength); /* Not available for STM32F030 devices */
-
-/* IrDA mode functions ********************************************************/
-void USART_IrDAConfig(USART_TypeDef* USARTx, uint32_t USART_IrDAMode); /* Not available for STM32F030 devices */
-void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState); /* Not available for STM32F030 devices */
-
-/* RS485 mode functions *******************************************************/
-void USART_DECmd(USART_TypeDef* USARTx, FunctionalState NewState);
-void USART_DEPolarityConfig(USART_TypeDef* USARTx, uint32_t USART_DEPolarity);
-void USART_SetDEAssertionTime(USART_TypeDef* USARTx, uint32_t USART_DEAssertionTime);
-void USART_SetDEDeassertionTime(USART_TypeDef* USARTx, uint32_t USART_DEDeassertionTime);
-
-/* DMA transfers management functions *****************************************/
-void USART_DMACmd(USART_TypeDef* USARTx, uint32_t USART_DMAReq, FunctionalState NewState);
-void USART_DMAReceptionErrorConfig(USART_TypeDef* USARTx, uint32_t USART_DMAOnError);
-
-/* Interrupts and flags management functions **********************************/
-void USART_ITConfig(USART_TypeDef* USARTx, uint32_t USART_IT, FunctionalState NewState);
-void USART_RequestCmd(USART_TypeDef* USARTx, uint32_t USART_Request, FunctionalState NewState);
-void USART_OverrunDetectionConfig(USART_TypeDef* USARTx, uint32_t USART_OVRDetection);
-FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint32_t USART_FLAG);
-void USART_ClearFlag(USART_TypeDef* USARTx, uint32_t USART_FLAG);
-ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint32_t USART_IT);
-void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint32_t USART_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F0XX_USART_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_wwdg.h b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_wwdg.h
deleted file mode 100644
index 49defe551d18fa39b86d9d60dc11f79f0135fa78..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/inc/stm32f0xx_wwdg.h
+++ /dev/null
@@ -1,109 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f0xx_wwdg.h
- * @author MCD Application Team
- * @version V1.3.0
- * @date 16-January-2014
- * @brief This file contains all the functions prototypes for the WWDG
- * firmware library.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F0XX_WWDG_H
-#define __STM32F0XX_WWDG_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup WWDG
- * @{
- */
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup WWDG_Exported_Constants
- * @{
- */
-
-/** @defgroup WWDG_Prescaler
- * @{
- */
-
-#define WWDG_Prescaler_1 ((uint32_t)0x00000000)
-#define WWDG_Prescaler_2 ((uint32_t)0x00000080)
-#define WWDG_Prescaler_4 ((uint32_t)0x00000100)
-#define WWDG_Prescaler_8 ((uint32_t)0x00000180)
-#define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || \
- ((PRESCALER) == WWDG_Prescaler_2) || \
- ((PRESCALER) == WWDG_Prescaler_4) || \
- ((PRESCALER) == WWDG_Prescaler_8))
-#define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F)
-#define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F))
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-/* Function used to set the WWDG configuration to the default reset state ****/
-void WWDG_DeInit(void);
-
-/* Prescaler, Refresh window and Counter configuration functions **************/
-void WWDG_SetPrescaler(uint32_t WWDG_Prescaler);
-void WWDG_SetWindowValue(uint8_t WindowValue);
-void WWDG_EnableIT(void);
-void WWDG_SetCounter(uint8_t Counter);
-
-/* WWDG activation functions **************************************************/
-void WWDG_Enable(uint8_t Counter);
-
-/* Interrupts and flags management functions **********************************/
-FlagStatus WWDG_GetFlagStatus(void);
-void WWDG_ClearFlag(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32F0XX_WWDG_H */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_adc.c b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_adc.c
deleted file mode 100644
index 0a8c56d9e8d75e82ef97d50478f729f72c4a5bd6..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_adc.c
+++ /dev/null
@@ -1,1240 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f0xx_adc.c
- * @author MCD Application Team
- * @version V1.3.0
- * @date 16-January-2014
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Analog to Digital Convertor (ADC) peripheral:
- * + Initialization and Configuration
- * + Power saving
- * + Analog Watchdog configuration
- * + Temperature Sensor, Vrefint (Internal Reference Voltage) and
- * Vbat (Voltage battery) management
- * + ADC Channels Configuration
- * + ADC Channels DMA Configuration
- * + Interrupts and flags management
- *
- * @verbatim
-================================================================================
- ##### How to use this driver #####
-================================================================================
- [..]
- (#) Enable the ADC interface clock using
- RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC1, ENABLE);
- (#) ADC pins configuration
- (++) Enable the clock for the ADC GPIOs using the following function:
- RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOx, ENABLE);
- (++) Configure these ADC pins in analog mode using GPIO_Init();
- (#) Configure the ADC conversion resolution, data alignment, external
- trigger and edge, scan direction and Enable/Disable the continuous mode
- using the ADC_Init() function.
- (#) Activate the ADC peripheral using ADC_Cmd() function.
-
- *** ADC channels group configuration ***
- ============================================
- [..]
- (+) To configure the ADC channels features, use ADC_Init() and
- ADC_ChannelConfig() functions.
- (+) To activate the continuous mode, use the ADC_ContinuousModeCmd()
- function.
- (+) To activate the Discontinuous mode, use the ADC_DiscModeCmd() functions.
- (+) To activate the overrun mode, use the ADC_OverrunModeCmd() functions.
- (+) To activate the calibration mode, use the ADC_GetCalibrationFactor() functions.
- (+) To read the ADC converted values, use the ADC_GetConversionValue()
- function.
-
- *** DMA for ADC channels features configuration ***
- =============================================================
- [..]
- (+) To enable the DMA mode for ADC channels group, use the ADC_DMACmd() function.
- (+) To configure the DMA transfer request, use ADC_DMARequestModeConfig() function.
-
- * @endverbatim
- *
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx_adc.h"
-#include "stm32f0xx_rcc.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup ADC
- * @brief ADC driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* ADC CFGR mask */
-#define CFGR1_CLEAR_MASK ((uint32_t)0xFFFFD203)
-
-/* Calibration time out */
-#define CALIBRATION_TIMEOUT ((uint32_t)0x0000F000)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup ADC_Private_Functions
- * @{
- */
-
-/** @defgroup ADC_Group1 Initialization and Configuration functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and Configuration functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Initialize and configure the ADC Prescaler
- (+) ADC Conversion Resolution (12bit..6bit)
- (+) ADC Continuous Conversion Mode (Continuous or Single conversion)
- (+) External trigger Edge and source
- (+) Converted data alignment (left or right)
- (+) The direction in which the channels will be scanned in the sequence
- (+) Enable or disable the ADC peripheral
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitializes ADC1 peripheral registers to their default reset values.
- * @param ADCx: where x can be 1 to select the ADC peripheral.
- * @retval None
- */
-void ADC_DeInit(ADC_TypeDef* ADCx)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
-
- if(ADCx == ADC1)
- {
- /* Enable ADC1 reset state */
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, ENABLE);
-
- /* Release ADC1 from reset state */
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, DISABLE);
- }
-}
-
-/**
- * @brief Initializes the ADCx peripheral according to the specified parameters
- * in the ADC_InitStruct.
- * @note This function is used to configure the global features of the ADC (
- * Resolution, Data Alignment, continuous mode activation, External
- * trigger source and edge, Sequence Scan Direction).
- * @param ADCx: where x can be 1 to select the ADC peripheral.
- * @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure that contains
- * the configuration information for the specified ADC peripheral.
- * @retval None
- */
-void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_RESOLUTION(ADC_InitStruct->ADC_Resolution));
- assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ContinuousConvMode));
- assert_param(IS_ADC_EXT_TRIG_EDGE(ADC_InitStruct->ADC_ExternalTrigConvEdge));
- assert_param(IS_ADC_EXTERNAL_TRIG_CONV(ADC_InitStruct->ADC_ExternalTrigConv));
- assert_param(IS_ADC_DATA_ALIGN(ADC_InitStruct->ADC_DataAlign));
- assert_param(IS_ADC_SCAN_DIRECTION(ADC_InitStruct->ADC_ScanDirection));
-
- /* Get the ADCx CFGR value */
- tmpreg = ADCx->CFGR1;
-
- /* Clear SCANDIR, RES[1:0], ALIGN, EXTSEL[2:0], EXTEN[1:0] and CONT bits */
- tmpreg &= CFGR1_CLEAR_MASK;
-
- /*---------------------------- ADCx CFGR Configuration ---------------------*/
-
- /* Set RES[1:0] bits according to ADC_Resolution value */
- /* Set CONT bit according to ADC_ContinuousConvMode value */
- /* Set EXTEN[1:0] bits according to ADC_ExternalTrigConvEdge value */
- /* Set EXTSEL[2:0] bits according to ADC_ExternalTrigConv value */
- /* Set ALIGN bit according to ADC_DataAlign value */
- /* Set SCANDIR bit according to ADC_ScanDirection value */
-
- tmpreg |= (uint32_t)(ADC_InitStruct->ADC_Resolution | ((uint32_t)(ADC_InitStruct->ADC_ContinuousConvMode) << 13) |
- ADC_InitStruct->ADC_ExternalTrigConvEdge | ADC_InitStruct->ADC_ExternalTrigConv |
- ADC_InitStruct->ADC_DataAlign | ADC_InitStruct->ADC_ScanDirection);
-
- /* Write to ADCx CFGR */
- ADCx->CFGR1 = tmpreg;
-}
-
-/**
- * @brief Fills each ADC_InitStruct member with its default value.
- * @note This function is used to initialize the global features of the ADC (
- * Resolution, Data Alignment, continuous mode activation, External
- * trigger source and edge, Sequence Scan Direction).
- * @param ADC_InitStruct: pointer to an ADC_InitTypeDef structure which will
- * be initialized.
- * @retval None
- */
-void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct)
-{
- /* Reset ADC init structure parameters values */
- /* Initialize the ADC_Resolution member */
- ADC_InitStruct->ADC_Resolution = ADC_Resolution_12b;
-
- /* Initialize the ADC_ContinuousConvMode member */
- ADC_InitStruct->ADC_ContinuousConvMode = DISABLE;
-
- /* Initialize the ADC_ExternalTrigConvEdge member */
- ADC_InitStruct->ADC_ExternalTrigConvEdge = ADC_ExternalTrigConvEdge_None;
-
- /* Initialize the ADC_ExternalTrigConv member */
- ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_TRGO;
-
- /* Initialize the ADC_DataAlign member */
- ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right;
-
- /* Initialize the ADC_ScanDirection member */
- ADC_InitStruct->ADC_ScanDirection = ADC_ScanDirection_Upward;
-}
-
-/**
- * @brief Enables or disables the specified ADC peripheral.
- * @param ADCx: where x can be 1 to select the ADC1 peripheral.
- * @param NewState: new state of the ADCx peripheral.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Set the ADEN bit to Enable the ADC peripheral */
- ADCx->CR |= (uint32_t)ADC_CR_ADEN;
- }
- else
- {
- /* Set the ADDIS to Disable the ADC peripheral */
- ADCx->CR |= (uint32_t)ADC_CR_ADDIS;
- }
-}
-
-/**
- * @brief Configure the ADC to either be clocked by the asynchronous clock(which is
- * independent, the dedicated 14MHz clock) or the synchronous clock derived from
- * the APB clock of the ADC bus interface divided by 2 or 4
- * @note This function can be called only when ADC is disabled.
- * @param ADCx: where x can be 1 to select the ADC1 peripheral.
- * @param ADC_ClockMode: This parameter can be :
- * @arg ADC_ClockMode_AsynClk: ADC clocked by the dedicated 14MHz clock
- * @arg ADC_ClockMode_SynClkDiv2: ADC clocked by PCLK/2
- * @arg ADC_ClockMode_SynClkDiv4: ADC clocked by PCLK/4
- * @retval None
- */
-void ADC_ClockModeConfig(ADC_TypeDef* ADCx, uint32_t ADC_ClockMode)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_CLOCKMODE(ADC_ClockMode));
-
- /* Configure the ADC Clock mode according to ADC_ClockMode */
- ADCx->CFGR2 = (uint32_t)ADC_ClockMode;
-
-}
-
-/**
- * @brief Enables or disables the jitter when the ADC is clocked by PCLK div2
- * or div4
- * @note This function is obsolete and maintained for legacy purpose only. ADC_ClockModeConfig()
- * function should be used instead.
- * @param ADCx: where x can be 1 to select the ADC1 peripheral.
- * @param ADC_JitterOff: This parameter can be :
- * @arg ADC_JitterOff_PCLKDiv2: Remove jitter when ADC is clocked by PLCK divided by 2
- * @arg ADC_JitterOff_PCLKDiv4: Remove jitter when ADC is clocked by PLCK divided by 4
- * @param NewState: new state of the ADCx jitter.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_JitterCmd(ADC_TypeDef* ADCx, uint32_t ADC_JitterOff, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_JITTEROFF(ADC_JitterOff));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Disable Jitter */
- ADCx->CFGR2 |= (uint32_t)ADC_JitterOff;
- }
- else
- {
- /* Enable Jitter */
- ADCx->CFGR2 &= (uint32_t)(~ADC_JitterOff);
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup ADC_Group2 Power saving functions
- * @brief Power saving functions
- *
-@verbatim
- ===============================================================================
- ##### Power saving functions #####
- ===============================================================================
- [..] This section provides functions allowing to reduce power consumption.
- [..] The two function must be combined to get the maximal benefits:
- When the ADC frequency is higher than the CPU one, it is recommended to
- (#) Enable the Auto Delayed Conversion mode :
- ==> using ADC_WaitModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
- (#) Enable the power off in Delay phases :
- ==> using ADC_AutoPowerOffCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the ADC Power Off.
- * @note ADC power-on and power-off can be managed by hardware to cut the
- * consumption when the ADC is not converting.
- * @param ADCx: where x can be 1 to select the ADC1 peripheral.
- * @note The ADC can be powered down:
- * - During the Auto delay phase: The ADC is powered on again at the end
- * of the delay (until the previous data is read from the ADC data register).
- * - During the ADC is waiting for a trigger event: The ADC is powered up
- * at the next trigger event (when the conversion is started).
- * @param NewState: new state of the ADCx power Off.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_AutoPowerOffCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the ADC Automatic Power-Off */
- ADCx->CFGR1 |= ADC_CFGR1_AUTOFF;
- }
- else
- {
- /* Disable the ADC Automatic Power-Off */
- ADCx->CFGR1 &= (uint32_t)~ADC_CFGR1_AUTOFF;
- }
-}
-
-/**
- * @brief Enables or disables the Wait conversion mode.
- * @note When the CPU clock is not fast enough to manage the data rate, a
- * Hardware delay can be introduced between ADC conversions to reduce
- * this data rate.
- * @note The Hardware delay is inserted after each conversions and until the
- * previous data is read from the ADC data register
- * @note This is a way to automatically adapt the speed of the ADC to the speed
- * of the system which will read the data.
- * @note Any hardware triggers wich occur while a conversion is on going or
- * while the automatic Delay is applied are ignored
- * @param ADCx: where x can be 1 to select the ADC1 peripheral.
- * @param NewState: new state of the ADCx Auto-Delay.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_WaitModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the ADC Automatic Delayed conversion */
- ADCx->CFGR1 |= ADC_CFGR1_WAIT;
- }
- else
- {
- /* Disable the ADC Automatic Delayed conversion */
- ADCx->CFGR1 &= (uint32_t)~ADC_CFGR1_WAIT;
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup ADC_Group3 Analog Watchdog configuration functions
- * @brief Analog Watchdog configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Analog Watchdog configuration functions #####
- ===============================================================================
- [..] This section provides functions allowing to configure the Analog Watchdog
- (AWD) feature in the ADC.
- [..] A typical configuration Analog Watchdog is done following these steps :
- (#) the ADC guarded channel(s) is (are) selected using the
- ADC_AnalogWatchdogSingleChannelConfig() function.
- (#) The Analog watchdog lower and higher threshold are configured using the
- ADC_AnalogWatchdogThresholdsConfig() function.
- (#) The Analog watchdog is enabled and configured to enable the check, on one
- or more channels, using the ADC_AnalogWatchdogCmd() function.
- (#) Enable the analog watchdog on the selected channel using
- ADC_AnalogWatchdogSingleChannelCmd() function
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the analog watchdog
- * @param ADCx: where x can be 1 to select the ADC1 peripheral.
- * @param NewState: new state of the ADCx Analog Watchdog.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the ADC Analog Watchdog */
- ADCx->CFGR1 |= ADC_CFGR1_AWDEN;
- }
- else
- {
- /* Disable the ADC Analog Watchdog */
- ADCx->CFGR1 &= (uint32_t)~ADC_CFGR1_AWDEN;
- }
-}
-
-/**
- * @brief Configures the high and low thresholds of the analog watchdog.
- * @param ADCx: where x can be 1 to select the ADC1 peripheral.
- * @param HighThreshold: the ADC analog watchdog High threshold value.
- * This parameter must be a 12bit value.
- * @param LowThreshold: the ADC analog watchdog Low threshold value.
- * This parameter must be a 12bit value.
- * @retval None
- */
-void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,
- uint16_t LowThreshold)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_THRESHOLD(HighThreshold));
- assert_param(IS_ADC_THRESHOLD(LowThreshold));
-
- /* Set the ADCx high and low threshold */
- ADCx->TR = LowThreshold | ((uint32_t)HighThreshold << 16);
-
-}
-
-/**
- * @brief Configures the analog watchdog guarded single channel
- * @param ADCx: where x can be 1 to select the ADC1 peripheral.
- * @param ADC_AnalogWatchdog_Channel: the ADC channel to configure for the analog watchdog.
- * This parameter can be one of the following values:
- * @arg ADC_AnalogWatchdog_Channel_0: ADC Channel0 selected
- * @arg ADC_AnalogWatchdog_Channel_1: ADC Channel1 selected
- * @arg ADC_AnalogWatchdog_Channel_2: ADC Channel2 selected
- * @arg ADC_AnalogWatchdog_Channel_3: ADC Channel3 selected
- * @arg ADC_AnalogWatchdog_Channel_4: ADC Channel4 selected
- * @arg ADC_AnalogWatchdog_Channel_5: ADC Channel5 selected
- * @arg ADC_AnalogWatchdog_Channel_6: ADC Channel6 selected
- * @arg ADC_AnalogWatchdog_Channel_7: ADC Channel7 selected
- * @arg ADC_AnalogWatchdog_Channel_8: ADC Channel8 selected
- * @arg ADC_AnalogWatchdog_Channel_9: ADC Channel9 selected
- * @arg ADC_AnalogWatchdog_Channel_10: ADC Channel10 selected, not available for STM32F031 devices
- * @arg ADC_AnalogWatchdog_Channel_11: ADC Channel11 selected, not available for STM32F031 devices
- * @arg ADC_AnalogWatchdog_Channel_12: ADC Channel12 selected, not available for STM32F031 devices
- * @arg ADC_AnalogWatchdog_Channel_13: ADC Channel13 selected, not available for STM32F031 devices
- * @arg ADC_AnalogWatchdog_Channel_14: ADC Channel14 selected, not available for STM32F031 devices
- * @arg ADC_AnalogWatchdog_Channel_15: ADC Channel15 selected, not available for STM32F031 devices
- * @arg ADC_AnalogWatchdog_Channel_16: ADC Channel16 selected
- * @arg ADC_AnalogWatchdog_Channel_17: ADC Channel17 selected
- * @arg ADC_AnalogWatchdog_Channel_18: ADC Channel18 selected, not available for STM32F030 devices
- * @note The channel selected on the AWDCH must be also set into the CHSELR
- * register
- * @retval None
- */
-void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog_Channel)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_ANALOG_WATCHDOG_CHANNEL(ADC_AnalogWatchdog_Channel));
-
- /* Get the old register value */
- tmpreg = ADCx->CFGR1;
-
- /* Clear the Analog watchdog channel select bits */
- tmpreg &= ~ADC_CFGR1_AWDCH;
-
- /* Set the Analog watchdog channel */
- tmpreg |= ADC_AnalogWatchdog_Channel;
-
- /* Store the new register value */
- ADCx->CFGR1 = tmpreg;
-}
-
-/**
- * @brief Enables or disables the ADC Analog Watchdog Single Channel.
- * @param ADCx: where x can be 1 to select the ADC1 peripheral.
- * @param NewState: new state of the ADCx ADC Analog Watchdog Single Channel.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_AnalogWatchdogSingleChannelCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the ADC Analog Watchdog Single Channel */
- ADCx->CFGR1 |= ADC_CFGR1_AWDSGL;
- }
- else
- {
- /* Disable the ADC Analog Watchdog Single Channel */
- ADCx->CFGR1 &= (uint32_t)~ADC_CFGR1_AWDSGL;
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup ADC_Group4 Temperature Sensor, Vrefint and Vbat management functions
- * @brief Temperature Sensor, Vrefint and Vbat management functions
- *
-@verbatim
- ===============================================================================
- ##### Temperature Sensor, Vrefint and Vbat management function #####
- ===============================================================================
- [..] This section provides a function allowing to enable/disable the internal
- connections between the ADC and the Temperature Sensor, the Vrefint and
- Vbat source.
-
- [..] A typical configuration to get the Temperature sensor, Vrefint and Vbat channels
- voltages is done following these steps :
- (#) Enable the internal connection of Temperature sensor, Vrefint or Vbat sources
- with the ADC channels using ADC_TempSensorCmd(), ADC_VrefintCmd() or ADC_VbatCmd()
- functions.
- (#) select the ADC_Channel_16(Temperature sensor), ADC_Channel_17(Vrefint)
- or ADC_Channel_18(Voltage battery) using ADC_ChannelConfig() function
- (#) Get the voltage values, using ADC_GetConversionValue() function
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the temperature sensor channel.
- * @param NewState: new state of the temperature sensor input channel.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_TempSensorCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the temperature sensor channel*/
- ADC->CCR |= (uint32_t)ADC_CCR_TSEN;
- }
- else
- {
- /* Disable the temperature sensor channel*/
- ADC->CCR &= (uint32_t)(~ADC_CCR_TSEN);
- }
-}
-
-/**
- * @brief Enables or disables the Vrefint channel.
- * @param NewState: new state of the Vref input channel.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_VrefintCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the Vrefint channel*/
- ADC->CCR |= (uint32_t)ADC_CCR_VREFEN;
- }
- else
- {
- /* Disable the Vrefint channel*/
- ADC->CCR &= (uint32_t)(~ADC_CCR_VREFEN);
- }
-}
-
-/**
- * @brief Enables or disables the Vbat channel.
- * @note This feature is not applicable for STM32F030 devices.
- * @param NewState: new state of the Vbat input channel.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_VbatCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the Vbat channel*/
- ADC->CCR |= (uint32_t)ADC_CCR_VBATEN;
- }
- else
- {
- /* Disable the Vbat channel*/
- ADC->CCR &= (uint32_t)(~ADC_CCR_VBATEN);
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup ADC_Group5 Channels Configuration functions
- * @brief Channels Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Channels Configuration functions #####
- ===============================================================================
- [..] This section provides functions allowing to manage the ADC channels,
- it is composed of 3 sub sections :
- (#) Configuration and management functions for ADC channels: This subsection
- provides functions allowing to configure the ADC channels :
- (++) Select the ADC channels
- (++) Activate ADC Calibration
- (++) Activate the Overrun Mode.
- (++) Activate the Discontinuous Mode
- (++) Activate the Continuous Mode.
- (++) Configure the sampling time for each channel
- (++) Select the conversion Trigger and Edge for ADC channels
- (++) Select the scan direction.
- -@@- Please Note that the following features for ADC channels are configurated
- using the ADC_Init() function :
- (+@@) Activate the Continuous Mode (can be also activated by ADC_OverrunModeCmd().
- (+@@) Select the conversion Trigger and Edge for ADC channels
- (+@@) Select the scan direction.
- (#) Control the ADC peripheral : This subsection permits to command the ADC:
- (++) Stop or discard an on-going conversion (ADSTP command)
- (++) Start the ADC conversion .
- (#) Get the conversion data: This subsection provides an important function in
- the ADC peripheral since it returns the converted data of the current
- ADC channel. When the Conversion value is read, the EOC Flag is
- automatically cleared.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures for the selected ADC and its sampling time.
- * @param ADCx: where x can be 1 to select the ADC peripheral.
- * @param ADC_Channel: the ADC channel to configure.
- * This parameter can be any combination of the following values:
- * @arg ADC_Channel_0: ADC Channel0 selected
- * @arg ADC_Channel_1: ADC Channel1 selected
- * @arg ADC_Channel_2: ADC Channel2 selected
- * @arg ADC_Channel_3: ADC Channel3 selected
- * @arg ADC_Channel_4: ADC Channel4 selected
- * @arg ADC_Channel_5: ADC Channel5 selected
- * @arg ADC_Channel_6: ADC Channel6 selected
- * @arg ADC_Channel_7: ADC Channel7 selected
- * @arg ADC_Channel_8: ADC Channel8 selected
- * @arg ADC_Channel_9: ADC Channel9 selected
- * @arg ADC_Channel_10: ADC Channel10 selected, not available for STM32F031 devices
- * @arg ADC_Channel_11: ADC Channel11 selected, not available for STM32F031 devices
- * @arg ADC_Channel_12: ADC Channel12 selected, not available for STM32F031 devices
- * @arg ADC_Channel_13: ADC Channel13 selected, not available for STM32F031 devices
- * @arg ADC_Channel_14: ADC Channel14 selected, not available for STM32F031 devices
- * @arg ADC_Channel_15: ADC Channel15 selected, not available for STM32F031 devices
- * @arg ADC_Channel_16: ADC Channel16 selected
- * @arg ADC_Channel_17: ADC Channel17 selected
- * @arg ADC_Channel_18: ADC Channel18 selected, not available for STM32F030 devices
- * @param ADC_SampleTime: The sample time value to be set for the selected channel.
- * This parameter can be one of the following values:
- * @arg ADC_SampleTime_1_5Cycles: Sample time equal to 1.5 cycles
- * @arg ADC_SampleTime_7_5Cycles: Sample time equal to 7.5 cycles
- * @arg ADC_SampleTime_13_5Cycles: Sample time equal to 13.5 cycles
- * @arg ADC_SampleTime_28_5Cycles: Sample time equal to 28.5 cycles
- * @arg ADC_SampleTime_41_5Cycles: Sample time equal to 41.5 cycles
- * @arg ADC_SampleTime_55_5Cycles: Sample time equal to 55.5 cycles
- * @arg ADC_SampleTime_71_5Cycles: Sample time equal to 71.5 cycles
- * @arg ADC_SampleTime_239_5Cycles: Sample time equal to 239.5 cycles
- * @retval None
- */
-void ADC_ChannelConfig(ADC_TypeDef* ADCx, uint32_t ADC_Channel, uint32_t ADC_SampleTime)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_CHANNEL(ADC_Channel));
- assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime));
-
- /* Configure the ADC Channel */
- ADCx->CHSELR |= (uint32_t)ADC_Channel;
-
- /* Clear the Sampling time Selection bits */
- tmpreg &= ~ADC_SMPR1_SMPR;
-
- /* Set the ADC Sampling Time register */
- tmpreg |= (uint32_t)ADC_SampleTime;
-
- /* Configure the ADC Sample time register */
- ADCx->SMPR = tmpreg ;
-}
-
-/**
- * @brief Enable the Continuous mode for the selected ADCx channels.
- * @param ADCx: where x can be 1 to select the ADC1 peripheral.
- * @param NewState: new state of the Continuous mode.
- * This parameter can be: ENABLE or DISABLE.
- * @note It is not possible to have both discontinuous mode and continuous mode
- * enabled. In this case (If DISCEN and CONT are Set), the ADC behaves
- * as if continuous mode was disabled
- * @retval None
- */
-void ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the Continuous mode*/
- ADCx->CFGR1 |= (uint32_t)ADC_CFGR1_CONT;
- }
- else
- {
- /* Disable the Continuous mode */
- ADCx->CFGR1 &= (uint32_t)(~ADC_CFGR1_CONT);
- }
-}
-
-/**
- * @brief Enable the discontinuous mode for the selected ADC channels.
- * @param ADCx: where x can be 1 to select the ADC1 peripheral.
- * @param NewState: new state of the discontinuous mode.
- * This parameter can be: ENABLE or DISABLE.
- * @note It is not possible to have both discontinuous mode and continuous mode
- * enabled. In this case (If DISCEN and CONT are Set), the ADC behaves
- * as if continuous mode was disabled
- * @retval None
- */
-void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the Discontinuous mode */
- ADCx->CFGR1 |= (uint32_t)ADC_CFGR1_DISCEN;
- }
- else
- {
- /* Disable the Discontinuous mode */
- ADCx->CFGR1 &= (uint32_t)(~ADC_CFGR1_DISCEN);
- }
-}
-
-/**
- * @brief Enable the Overrun mode for the selected ADC channels.
- * @param ADCx: where x can be 1 to select the ADC1 peripheral.
- * @param NewState: new state of the Overrun mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_OverrunModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the Overrun mode */
- ADCx->CFGR1 |= (uint32_t)ADC_CFGR1_OVRMOD;
- }
- else
- {
- /* Disable the Overrun mode */
- ADCx->CFGR1 &= (uint32_t)(~ADC_CFGR1_OVRMOD);
- }
-}
-
-/**
- * @brief Active the Calibration operation for the selected ADC.
- * @note The Calibration can be initiated only when ADC is still in the
- * reset configuration (ADEN must be equal to 0).
- * @param ADCx: where x can be 1 to select the ADC1 peripheral.
- * @retval ADC Calibration factor
- */
-uint32_t ADC_GetCalibrationFactor(ADC_TypeDef* ADCx)
-{
- uint32_t tmpreg = 0, calibrationcounter = 0, calibrationstatus = 0;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
-
- /* Set the ADC calibartion */
- ADCx->CR |= (uint32_t)ADC_CR_ADCAL;
-
- /* Wait until no ADC calibration is completed */
- do
- {
- calibrationstatus = ADCx->CR & ADC_CR_ADCAL;
- calibrationcounter++;
- } while((calibrationcounter != CALIBRATION_TIMEOUT) && (calibrationstatus != 0x00));
-
- if((uint32_t)(ADCx->CR & ADC_CR_ADCAL) == RESET)
- {
- /*Get the calibration factor from the ADC data register */
- tmpreg = ADCx->DR;
- }
- else
- {
- /* Error factor */
- tmpreg = 0x00000000;
- }
- return tmpreg;
-}
-
-/**
- * @brief Stop the on going conversions for the selected ADC.
- * @note When ADSTP is set, any on going conversion is aborted, and the ADC
- * data register is not updated with current conversion.
- * @param ADCx: where x can be 1 to select the ADC1 peripheral.
- * @retval None
- */
-void ADC_StopOfConversion(ADC_TypeDef* ADCx)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
-
- ADCx->CR |= (uint32_t)ADC_CR_ADSTP;
-}
-
-/**
- * @brief Start Conversion for the selected ADC channels.
- * @note In continuous mode, ADSTART is not cleared by hardware with the
- * assertion of EOSEQ because the sequence is automatic relaunched
- * @param ADCx: where x can be 1 to select the ADC1 peripheral.
- * @retval None
- */
-void ADC_StartOfConversion(ADC_TypeDef* ADCx)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
-
- ADCx->CR |= (uint32_t)ADC_CR_ADSTART;
-}
-
-/**
- * @brief Returns the last ADCx conversion result data for ADC channel.
- * @param ADCx: where x can be 1 to select the ADC1 peripheral.
- * @retval The Data conversion value.
- */
-uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
-
- /* Return the selected ADC conversion value */
- return (uint16_t) ADCx->DR;
-}
-
-/**
- * @}
- */
-
-/** @defgroup ADC_Group6 DMA Configuration functions
- * @brief Regular Channels DMA Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### DMA Configuration functions #####
- ===============================================================================
- [..] This section provides functions allowing to configure the DMA for ADC hannels.
- Since converted channel values are stored into a unique data register,
- it is useful to use DMA for conversion of more than one channel. This
- avoids the loss of the data already stored in the ADC Data register.
- When the DMA mode is enabled (using the ADC_DMACmd() function), after each
- conversion of a channel, a DMA request is generated.
-
- [..] Depending on the "DMA disable selection" configuration (using the
- ADC_DMARequestModeConfig() function), at the end of the last DMA
- transfer, two possibilities are allowed:
- (+) No new DMA request is issued to the DMA controller (One Shot Mode)
- (+) Requests can continue to be generated (Circular Mode).
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the specified ADC DMA request.
- * @param ADCx: where x can be 1 to select the ADC1 peripheral.
- * @param NewState: new state of the selected ADC DMA transfer.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected ADC DMA request */
- ADCx->CFGR1 |= (uint32_t)ADC_CFGR1_DMAEN;
- }
- else
- {
- /* Disable the selected ADC DMA request */
- ADCx->CFGR1 &= (uint32_t)(~ADC_CFGR1_DMAEN);
- }
-}
-
-/**
- * @brief Enables or disables the ADC DMA request after last transfer (Single-ADC mode)
- * @param ADCx: where x can be 1 to select the ADC1 peripheral.
- * @param ADC_DMARequestMode: the ADC channel to configure.
- * This parameter can be one of the following values:
- * @arg ADC_DMAMode_OneShot: DMA One Shot Mode
- * @arg ADC_DMAMode_Circular: DMA Circular Mode
- * @retval None
- */
-void ADC_DMARequestModeConfig(ADC_TypeDef* ADCx, uint32_t ADC_DMARequestMode)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
-
- ADCx->CFGR1 &= (uint32_t)~ADC_CFGR1_DMACFG;
- ADCx->CFGR1 |= (uint32_t)ADC_DMARequestMode;
-}
-
-/**
- * @}
- */
-
-/** @defgroup ADC_Group7 Interrupts and flags management functions
- * @brief Interrupts and flags management functions.
- *
-@verbatim
- ===============================================================================
- ##### Interrupts and flags management functions #####
- ===============================================================================
- [..] This section provides functions allowing to configure the ADC Interrupts
- and get the status and clear flags and Interrupts pending bits.
-
- [..] The ADC provide 6 Interrupts sources and 11 Flags which can be divided into
- 3 groups:
-
- *** Flags for ADC status ***
- ======================================================
- [..]
- (+)Flags :
- (##) ADC_FLAG_ADRDY : This flag is set after the ADC has been enabled (bit ADEN=1)
- and when the ADC reaches a state where it is ready to accept conversion requests
- (##) ADC_FLAG_ADEN : This flag is set by software to enable the ADC.
- The ADC will be effectively ready to operate once the ADRDY flag has been set.
- (##) ADC_FLAG_ADDIS : This flag is cleared once the ADC is effectively
- disabled.
- (##) ADC_FLAG_ADSTART : This flag is cleared after the execution of
- ADC_StopOfConversion() function, at the same time as the ADSTP bit is
- cleared by hardware
- (##) ADC_FLAG_ADSTP : This flag is cleared by hardware when the conversion
- is effectively discarded and the ADC is ready to accept a new start conversion
- (##) ADC_FLAG_ADCAL : This flag is set once the calibration is complete.
-
- (+)Interrupts
- (##) ADC_IT_ADRDY : specifies the interrupt source for ADC ready event.
-
- *** Flags and Interrupts for ADC channel conversion ***
- =====================================================
- [..]
- (+)Flags :
- (##) ADC_FLAG_EOC : This flag is set by hardware at the end of each conversion
- of a channel when a new data result is available in the data register
- (##) ADC_FLAG_EOSEQ : This bit is set by hardware at the end of the conversion
- of a sequence of channels selected by ADC_ChannelConfig() function.
- (##) ADC_FLAG_EOSMP : This bit is set by hardware at the end of the sampling phase.
- (##) ADC_FLAG_OVR : This flag is set by hardware when an overrun occurs,
- meaning that a new conversion has complete while the EOC flag was already set.
-
- (+)Interrupts :
- (##) ADC_IT_EOC : specifies the interrupt source for end of conversion event.
- (##) ADC_IT_EOSEQ : specifies the interrupt source for end of sequence event.
- (##) ADC_IT_EOSMP : specifies the interrupt source for end of sampling event.
- (##) ADC_IT_OVR : specifies the interrupt source for Overrun detection
- event.
-
- *** Flags and Interrupts for the Analog Watchdog ***
- ================================================
- [..]
- (+)Flags :
- (##) ADC_FLAG_AWD: This flag is set by hardware when the converted
- voltage crosses the values programmed thrsholds
-
- (+)Interrupts :
- (##) ADC_IT_AWD : specifies the interrupt source for Analog watchdog
- event.
-
- [..] The user should identify which mode will be used in his application to
- manage the ADC controller events: Polling mode or Interrupt mode.
-
- [..] In the Polling Mode it is advised to use the following functions:
- (+) ADC_GetFlagStatus() : to check if flags events occur.
- (+) ADC_ClearFlag() : to clear the flags events.
-
- [..] In the Interrupt Mode it is advised to use the following functions:
- (+) ADC_ITConfig() : to enable or disable the interrupt source.
- (+) ADC_GetITStatus() : to check if Interrupt occurs.
- (+) ADC_ClearITPendingBit() : to clear the Interrupt pending Bit
- (corresponding Flag).
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the specified ADC interrupts.
- * @param ADCx: where x can be 1 to select the ADC peripheral.
- * @param ADC_IT: specifies the ADC interrupt sources to be enabled or disabled.
- * This parameter can be one of the following values:
- * @arg ADC_IT_ADRDY: ADC ready interrupt
- * @arg ADC_IT_EOSMP: End of sampling interrupt
- * @arg ADC_IT_EOC: End of conversion interrupt
- * @arg ADC_IT_EOSEQ: End of sequence of conversion interrupt
- * @arg ADC_IT_OVR: overrun interrupt
- * @arg ADC_IT_AWD: Analog watchdog interrupt
- * @param NewState: new state of the specified ADC interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void ADC_ITConfig(ADC_TypeDef* ADCx, uint32_t ADC_IT, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- assert_param(IS_ADC_CONFIG_IT(ADC_IT));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected ADC interrupts */
- ADCx->IER |= ADC_IT;
- }
- else
- {
- /* Disable the selected ADC interrupts */
- ADCx->IER &= (~(uint32_t)ADC_IT);
- }
-}
-
-/**
- * @brief Checks whether the specified ADC flag is set or not.
- * @param ADCx: where x can be 1 to select the ADC1 peripheral.
- * @param ADC_FLAG: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg ADC_FLAG_AWD: Analog watchdog flag
- * @arg ADC_FLAG_OVR: Overrun flag
- * @arg ADC_FLAG_EOSEQ: End of Sequence flag
- * @arg ADC_FLAG_EOC: End of conversion flag
- * @arg ADC_FLAG_EOSMP: End of sampling flag
- * @arg ADC_FLAG_ADRDY: ADC Ready flag
- * @arg ADC_FLAG_ADEN: ADC enable flag
- * @arg ADC_FLAG_ADDIS: ADC disable flag
- * @arg ADC_FLAG_ADSTART: ADC start flag
- * @arg ADC_FLAG_ADSTP: ADC stop flag
- * @arg ADC_FLAG_ADCAL: ADC Calibration flag
- * @retval The new state of ADC_FLAG (SET or RESET).
- */
-FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint32_t ADC_FLAG)
-{
- FlagStatus bitstatus = RESET;
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_GET_FLAG(ADC_FLAG));
-
- if((uint32_t)(ADC_FLAG & 0x01000000))
- {
- tmpreg = ADCx->CR & 0xFEFFFFFF;
- }
- else
- {
- tmpreg = ADCx->ISR;
- }
-
- /* Check the status of the specified ADC flag */
- if ((tmpreg & ADC_FLAG) != (uint32_t)RESET)
- {
- /* ADC_FLAG is set */
- bitstatus = SET;
- }
- else
- {
- /* ADC_FLAG is reset */
- bitstatus = RESET;
- }
- /* Return the ADC_FLAG status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the ADCx's pending flags.
- * @param ADCx: where x can be 1 to select the ADC1 peripheral.
- * @param ADC_FLAG: specifies the flag to clear.
- * This parameter can be any combination of the following values:
- * @arg ADC_FLAG_AWD: Analog watchdog flag
- * @arg ADC_FLAG_EOC: End of conversion flag
- * @arg ADC_FLAG_ADRDY: ADC Ready flag
- * @arg ADC_FLAG_EOSMP: End of sampling flag
- * @arg ADC_FLAG_EOSEQ: End of Sequence flag
- * @arg ADC_FLAG_OVR: Overrun flag
- * @retval None
- */
-void ADC_ClearFlag(ADC_TypeDef* ADCx, uint32_t ADC_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_CLEAR_FLAG(ADC_FLAG));
-
- /* Clear the selected ADC flags */
- ADCx->ISR = (uint32_t)ADC_FLAG;
-}
-
-/**
- * @brief Checks whether the specified ADC interrupt has occurred or not.
- * @param ADCx: where x can be 1 to select the ADC1 peripheral
- * @param ADC_IT: specifies the ADC interrupt source to check.
- * This parameter can be one of the following values:
- * @arg ADC_IT_ADRDY: ADC ready interrupt
- * @arg ADC_IT_EOSMP: End of sampling interrupt
- * @arg ADC_IT_EOC: End of conversion interrupt
- * @arg ADC_IT_EOSEQ: End of sequence of conversion interrupt
- * @arg ADC_IT_OVR: overrun interrupt
- * @arg ADC_IT_AWD: Analog watchdog interrupt
- * @retval The new state of ADC_IT (SET or RESET).
- */
-ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint32_t ADC_IT)
-{
- ITStatus bitstatus = RESET;
- uint32_t enablestatus = 0;
-
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_GET_IT(ADC_IT));
-
- /* Get the ADC_IT enable bit status */
- enablestatus = (uint32_t)(ADCx->IER & ADC_IT);
-
- /* Check the status of the specified ADC interrupt */
- if (((uint32_t)(ADCx->ISR & ADC_IT) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))
- {
- /* ADC_IT is set */
- bitstatus = SET;
- }
- else
- {
- /* ADC_IT is reset */
- bitstatus = RESET;
- }
- /* Return the ADC_IT status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the ADCx's interrupt pending bits.
- * @param ADCx: where x can be 1 to select the ADC1 peripheral.
- * @param ADC_IT: specifies the ADC interrupt pending bit to clear.
- * This parameter can be one of the following values:
- * @arg ADC_IT_ADRDY: ADC ready interrupt
- * @arg ADC_IT_EOSMP: End of sampling interrupt
- * @arg ADC_IT_EOC: End of conversion interrupt
- * @arg ADC_IT_EOSEQ: End of sequence of conversion interrupt
- * @arg ADC_IT_OVR: overrun interrupt
- * @arg ADC_IT_AWD: Analog watchdog interrupt
- * @retval None
- */
-void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint32_t ADC_IT)
-{
- /* Check the parameters */
- assert_param(IS_ADC_ALL_PERIPH(ADCx));
- assert_param(IS_ADC_CLEAR_IT(ADC_IT));
-
- /* Clear the selected ADC interrupt pending bits */
- ADCx->ISR = (uint32_t)ADC_IT;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_can.c b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_can.c
deleted file mode 100644
index 7dcae51e2acbfbdd01efb3a45810fb20377118b9..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_can.c
+++ /dev/null
@@ -1,1631 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f0xx_can.c
- * @author MCD Application Team
- * @version V1.3.0
- * @date 16-January-2014
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Controller area network (CAN) peripheral and
- * applicable only for STM32F072 devices :
- * + Initialization and Configuration
- * + CAN Frames Transmission
- * + CAN Frames Reception
- * + Operation modes switch
- * + Error management
- * + Interrupts and flags
- *
- @verbatim
-
- ===============================================================================
- ##### How to use this driver #####
- ===============================================================================
- [..]
- (#) Enable the CAN controller interface clock using
- RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN, ENABLE);
- (#) CAN pins configuration:
- (++) Enable the clock for the CAN GPIOs using the following function:
- RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOx, ENABLE);
- (++) Connect the involved CAN pins to AF0 using the following function
- GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_CANx);
- (++) Configure these CAN pins in alternate function mode by calling
- the function GPIO_Init();
- (#) Initialise and configure the CAN using CAN_Init() and
- CAN_FilterInit() functions.
- (#) Transmit the desired CAN frame using CAN_Transmit() function.
- (#) Check the transmission of a CAN frame using CAN_TransmitStatus() function.
- (#) Cancel the transmission of a CAN frame using CAN_CancelTransmit() function.
- (#) Receive a CAN frame using CAN_Recieve() function.
- (#) Release the receive FIFOs using CAN_FIFORelease() function.
- (#) Return the number of pending received frames using CAN_MessagePending() function.
- (#) To control CAN events you can use one of the following two methods:
- (++) Check on CAN flags using the CAN_GetFlagStatus() function.
- (++) Use CAN interrupts through the function CAN_ITConfig() at initialization
- phase and CAN_GetITStatus() function into interrupt routines to check
- if the event has occurred or not.
- After checking on a flag you should clear it using CAN_ClearFlag()
- function. And after checking on an interrupt event you should clear it
- using CAN_ClearITPendingBit() function.
-
- @endverbatim
- *
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx_can.h"
-#include "stm32f0xx_rcc.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup CAN
- * @brief CAN driver modules
- * @{
- */
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-/* CAN Master Control Register bits */
-#define MCR_DBF ((uint32_t)0x00010000) /* software master reset */
-
-/* CAN Mailbox Transmit Request */
-#define TMIDxR_TXRQ ((uint32_t)0x00000001) /* Transmit mailbox request */
-
-/* CAN Filter Master Register bits */
-#define FMR_FINIT ((uint32_t)0x00000001) /* Filter init mode */
-
-/* Time out for INAK bit */
-#define INAK_TIMEOUT ((uint32_t)0x00FFFFFF)
-/* Time out for SLAK bit */
-#define SLAK_TIMEOUT ((uint32_t)0x00FFFFFF)
-
-/* Flags in TSR register */
-#define CAN_FLAGS_TSR ((uint32_t)0x08000000)
-/* Flags in RF1R register */
-#define CAN_FLAGS_RF1R ((uint32_t)0x04000000)
-/* Flags in RF0R register */
-#define CAN_FLAGS_RF0R ((uint32_t)0x02000000)
-/* Flags in MSR register */
-#define CAN_FLAGS_MSR ((uint32_t)0x01000000)
-/* Flags in ESR register */
-#define CAN_FLAGS_ESR ((uint32_t)0x00F00000)
-
-/* Mailboxes definition */
-#define CAN_TXMAILBOX_0 ((uint8_t)0x00)
-#define CAN_TXMAILBOX_1 ((uint8_t)0x01)
-#define CAN_TXMAILBOX_2 ((uint8_t)0x02)
-
-#define CAN_MODE_MASK ((uint32_t) 0x00000003)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit);
-
-/** @defgroup CAN_Private_Functions
- * @{
- */
-
-/** @defgroup CAN_Group1 Initialization and Configuration functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and Configuration functions #####
- ===============================================================================
- [..] This section provides functions allowing to:
- (+) Initialize the CAN peripherals : Prescaler, operating mode, the maximum
- number of time quanta to perform resynchronization, the number of time
- quanta in Bit Segment 1 and 2 and many other modes.
- (+) Configure the CAN reception filter.
- (+) Select the start bank filter for slave CAN.
- (+) Enable or disable the Debug Freeze mode for CAN.
- (+) Enable or disable the CAN Time Trigger Operation communication mode.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitializes the CAN peripheral registers to their default reset values.
- * @param CANx: where x can be 1 to select the CAN peripheral.
- * @retval None.
- */
-void CAN_DeInit(CAN_TypeDef* CANx)
-{
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
-
- /* Enable CAN reset state */
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN, ENABLE);
- /* Release CAN from reset state */
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN, DISABLE);
-}
-
-/**
- * @brief Initializes the CAN peripheral according to the specified
- * parameters in the CAN_InitStruct.
- * @param CANx: where x can be 1 to select the CAN peripheral.
- * @param CAN_InitStruct: pointer to a CAN_InitTypeDef structure that contains
- * the configuration information for the CAN peripheral.
- * @retval Constant indicates initialization succeed which will be
- * CAN_InitStatus_Failed or CAN_InitStatus_Success.
- */
-uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct)
-{
- uint8_t InitStatus = CAN_InitStatus_Failed;
- uint32_t wait_ack = 0x00000000;
-
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
- assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TTCM));
- assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_ABOM));
- assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_AWUM));
- assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_NART));
- assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_RFLM));
- assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TXFP));
- assert_param(IS_CAN_MODE(CAN_InitStruct->CAN_Mode));
- assert_param(IS_CAN_SJW(CAN_InitStruct->CAN_SJW));
- assert_param(IS_CAN_BS1(CAN_InitStruct->CAN_BS1));
- assert_param(IS_CAN_BS2(CAN_InitStruct->CAN_BS2));
- assert_param(IS_CAN_PRESCALER(CAN_InitStruct->CAN_Prescaler));
-
- /* Exit from sleep mode */
- CANx->MCR &= (~(uint32_t)CAN_MCR_SLEEP);
-
- /* Request initialisation */
- CANx->MCR |= CAN_MCR_INRQ ;
-
- /* Wait the acknowledge */
- while (((CANx->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) && (wait_ack != INAK_TIMEOUT))
- {
- wait_ack++;
- }
-
- /* Check acknowledge */
- if ((CANx->MSR & CAN_MSR_INAK) != CAN_MSR_INAK)
- {
- InitStatus = CAN_InitStatus_Failed;
- }
- else
- {
- /* Set the time triggered communication mode */
- if (CAN_InitStruct->CAN_TTCM == ENABLE)
- {
- CANx->MCR |= CAN_MCR_TTCM;
- }
- else
- {
- CANx->MCR &= ~(uint32_t)CAN_MCR_TTCM;
- }
-
- /* Set the automatic bus-off management */
- if (CAN_InitStruct->CAN_ABOM == ENABLE)
- {
- CANx->MCR |= CAN_MCR_ABOM;
- }
- else
- {
- CANx->MCR &= ~(uint32_t)CAN_MCR_ABOM;
- }
-
- /* Set the automatic wake-up mode */
- if (CAN_InitStruct->CAN_AWUM == ENABLE)
- {
- CANx->MCR |= CAN_MCR_AWUM;
- }
- else
- {
- CANx->MCR &= ~(uint32_t)CAN_MCR_AWUM;
- }
-
- /* Set the no automatic retransmission */
- if (CAN_InitStruct->CAN_NART == ENABLE)
- {
- CANx->MCR |= CAN_MCR_NART;
- }
- else
- {
- CANx->MCR &= ~(uint32_t)CAN_MCR_NART;
- }
-
- /* Set the receive FIFO locked mode */
- if (CAN_InitStruct->CAN_RFLM == ENABLE)
- {
- CANx->MCR |= CAN_MCR_RFLM;
- }
- else
- {
- CANx->MCR &= ~(uint32_t)CAN_MCR_RFLM;
- }
-
- /* Set the transmit FIFO priority */
- if (CAN_InitStruct->CAN_TXFP == ENABLE)
- {
- CANx->MCR |= CAN_MCR_TXFP;
- }
- else
- {
- CANx->MCR &= ~(uint32_t)CAN_MCR_TXFP;
- }
-
- /* Set the bit timing register */
- CANx->BTR = (uint32_t)((uint32_t)CAN_InitStruct->CAN_Mode << 30) | \
- ((uint32_t)CAN_InitStruct->CAN_SJW << 24) | \
- ((uint32_t)CAN_InitStruct->CAN_BS1 << 16) | \
- ((uint32_t)CAN_InitStruct->CAN_BS2 << 20) | \
- ((uint32_t)CAN_InitStruct->CAN_Prescaler - 1);
-
- /* Request leave initialisation */
- CANx->MCR &= ~(uint32_t)CAN_MCR_INRQ;
-
- /* Wait the acknowledge */
- wait_ack = 0;
-
- while (((CANx->MSR & CAN_MSR_INAK) == (uint16_t)CAN_MSR_INAK) && (wait_ack != INAK_TIMEOUT))
- {
- wait_ack++;
- }
-
- /* ...and check acknowledged */
- if ((CANx->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)
- {
- InitStatus = CAN_InitStatus_Failed;
- }
- else
- {
- InitStatus = CAN_InitStatus_Success ;
- }
- }
-
- /* At this step, return the status of initialization */
- return InitStatus;
-}
-
-/**
- * @brief Configures the CAN reception filter according to the specified
- * parameters in the CAN_FilterInitStruct.
- * @param CAN_FilterInitStruct: pointer to a CAN_FilterInitTypeDef structure that
- * contains the configuration information.
- * @retval None
- */
-void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct)
-{
- uint32_t filter_number_bit_pos = 0;
- /* Check the parameters */
- assert_param(IS_CAN_FILTER_NUMBER(CAN_FilterInitStruct->CAN_FilterNumber));
- assert_param(IS_CAN_FILTER_MODE(CAN_FilterInitStruct->CAN_FilterMode));
- assert_param(IS_CAN_FILTER_SCALE(CAN_FilterInitStruct->CAN_FilterScale));
- assert_param(IS_CAN_FILTER_FIFO(CAN_FilterInitStruct->CAN_FilterFIFOAssignment));
- assert_param(IS_FUNCTIONAL_STATE(CAN_FilterInitStruct->CAN_FilterActivation));
-
- filter_number_bit_pos = ((uint32_t)1) << CAN_FilterInitStruct->CAN_FilterNumber;
-
- /* Initialisation mode for the filter */
- CAN->FMR |= FMR_FINIT;
-
- /* Filter Deactivation */
- CAN->FA1R &= ~(uint32_t)filter_number_bit_pos;
-
- /* Filter Scale */
- if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_16bit)
- {
- /* 16-bit scale for the filter */
- CAN->FS1R &= ~(uint32_t)filter_number_bit_pos;
-
- /* First 16-bit identifier and First 16-bit mask */
- /* Or First 16-bit identifier and Second 16-bit identifier */
- CAN->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 =
- ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow) << 16) |
- (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow);
-
- /* Second 16-bit identifier and Second 16-bit mask */
- /* Or Third 16-bit identifier and Fourth 16-bit identifier */
- CAN->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 =
- ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) |
- (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh);
- }
-
- if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_32bit)
- {
- /* 32-bit scale for the filter */
- CAN->FS1R |= filter_number_bit_pos;
- /* 32-bit identifier or First 32-bit identifier */
- CAN->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 =
- ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh) << 16) |
- (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow);
- /* 32-bit mask or Second 32-bit identifier */
- CAN->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 =
- ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) |
- (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow);
- }
-
- /* Filter Mode */
- if (CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdMask)
- {
- /*Id/Mask mode for the filter*/
- CAN->FM1R &= ~(uint32_t)filter_number_bit_pos;
- }
- else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */
- {
- /*Identifier list mode for the filter*/
- CAN->FM1R |= (uint32_t)filter_number_bit_pos;
- }
-
- /* Filter FIFO assignment */
- if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO0)
- {
- /* FIFO 0 assignation for the filter */
- CAN->FFA1R &= ~(uint32_t)filter_number_bit_pos;
- }
-
- if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO1)
- {
- /* FIFO 1 assignation for the filter */
- CAN->FFA1R |= (uint32_t)filter_number_bit_pos;
- }
-
- /* Filter activation */
- if (CAN_FilterInitStruct->CAN_FilterActivation == ENABLE)
- {
- CAN->FA1R |= filter_number_bit_pos;
- }
-
- /* Leave the initialisation mode for the filter */
- CAN->FMR &= ~FMR_FINIT;
-}
-
-/**
- * @brief Fills each CAN_InitStruct member with its default value.
- * @param CAN_InitStruct: pointer to a CAN_InitTypeDef structure which ill be initialized.
- * @retval None
- */
-void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct)
-{
- /* Reset CAN init structure parameters values */
-
- /* Initialize the time triggered communication mode */
- CAN_InitStruct->CAN_TTCM = DISABLE;
-
- /* Initialize the automatic bus-off management */
- CAN_InitStruct->CAN_ABOM = DISABLE;
-
- /* Initialize the automatic wake-up mode */
- CAN_InitStruct->CAN_AWUM = DISABLE;
-
- /* Initialize the no automatic retransmission */
- CAN_InitStruct->CAN_NART = DISABLE;
-
- /* Initialize the receive FIFO locked mode */
- CAN_InitStruct->CAN_RFLM = DISABLE;
-
- /* Initialize the transmit FIFO priority */
- CAN_InitStruct->CAN_TXFP = DISABLE;
-
- /* Initialize the CAN_Mode member */
- CAN_InitStruct->CAN_Mode = CAN_Mode_Normal;
-
- /* Initialize the CAN_SJW member */
- CAN_InitStruct->CAN_SJW = CAN_SJW_1tq;
-
- /* Initialize the CAN_BS1 member */
- CAN_InitStruct->CAN_BS1 = CAN_BS1_4tq;
-
- /* Initialize the CAN_BS2 member */
- CAN_InitStruct->CAN_BS2 = CAN_BS2_3tq;
-
- /* Initialize the CAN_Prescaler member */
- CAN_InitStruct->CAN_Prescaler = 1;
-}
-
-/**
- * @brief Select the start bank filter for slave CAN.
- * @param CAN_BankNumber: Select the start slave bank filter from 1..27.
- * @retval None
- */
-void CAN_SlaveStartBank(uint8_t CAN_BankNumber)
-{
- /* Check the parameters */
- assert_param(IS_CAN_BANKNUMBER(CAN_BankNumber));
-
- /* Enter Initialisation mode for the filter */
- CAN->FMR |= FMR_FINIT;
-
- /* Select the start slave bank */
- CAN->FMR &= (uint32_t)0xFFFFC0F1 ;
- CAN->FMR |= (uint32_t)(CAN_BankNumber)<<8;
-
- /* Leave Initialisation mode for the filter */
- CAN->FMR &= ~FMR_FINIT;
-}
-
-/**
- * @brief Enables or disables the DBG Freeze for CAN.
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
- * @param NewState: new state of the CAN peripheral.
- * This parameter can be: ENABLE (CAN reception/transmission is frozen
- * during debug. Reception FIFOs can still be accessed/controlled normally)
- * or DISABLE (CAN is working during debug).
- * @retval None
- */
-void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable Debug Freeze */
- CANx->MCR |= MCR_DBF;
- }
- else
- {
- /* Disable Debug Freeze */
- CANx->MCR &= ~MCR_DBF;
- }
-}
-
-/**
- * @brief Enables or disables the CAN Time TriggerOperation communication mode.
- * @note DLC must be programmed as 8 in order Time Stamp (2 bytes) to be
- * sent over the CAN bus.
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
- * @param NewState: Mode new state. This parameter can be: ENABLE or DISABLE.
- * When enabled, Time stamp (TIME[15:0]) value is sent in the last two
- * data bytes of the 8-byte message: TIME[7:0] in data byte 6 and TIME[15:8]
- * in data byte 7.
- * @retval None
- */
-void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the TTCM mode */
- CANx->MCR |= CAN_MCR_TTCM;
-
- /* Set TGT bits */
- CANx->sTxMailBox[0].TDTR |= ((uint32_t)CAN_TDT0R_TGT);
- CANx->sTxMailBox[1].TDTR |= ((uint32_t)CAN_TDT1R_TGT);
- CANx->sTxMailBox[2].TDTR |= ((uint32_t)CAN_TDT2R_TGT);
- }
- else
- {
- /* Disable the TTCM mode */
- CANx->MCR &= (uint32_t)(~(uint32_t)CAN_MCR_TTCM);
-
- /* Reset TGT bits */
- CANx->sTxMailBox[0].TDTR &= ((uint32_t)~CAN_TDT0R_TGT);
- CANx->sTxMailBox[1].TDTR &= ((uint32_t)~CAN_TDT1R_TGT);
- CANx->sTxMailBox[2].TDTR &= ((uint32_t)~CAN_TDT2R_TGT);
- }
-}
-/**
- * @}
- */
-
-
-/** @defgroup CAN_Group2 CAN Frames Transmission functions
- * @brief CAN Frames Transmission functions
- *
-@verbatim
- ===============================================================================
- ##### CAN Frames Transmission functions #####
- ===============================================================================
- [..] This section provides functions allowing to
- (+) Initiate and transmit a CAN frame message (if there is an empty mailbox).
- (+) Check the transmission status of a CAN Frame.
- (+) Cancel a transmit request.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initiates and transmits a CAN frame message.
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
- * @param TxMessage: pointer to a structure which contains CAN Id, CAN DLC and CAN data.
- * @retval The number of the mailbox that is used for transmission or
- * CAN_TxStatus_NoMailBox if there is no empty mailbox.
- */
-uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage)
-{
- uint8_t transmit_mailbox = 0;
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
- assert_param(IS_CAN_IDTYPE(TxMessage->IDE));
- assert_param(IS_CAN_RTR(TxMessage->RTR));
- assert_param(IS_CAN_DLC(TxMessage->DLC));
-
- /* Select one empty transmit mailbox */
- if ((CANx->TSR&CAN_TSR_TME0) == CAN_TSR_TME0)
- {
- transmit_mailbox = 0;
- }
- else if ((CANx->TSR&CAN_TSR_TME1) == CAN_TSR_TME1)
- {
- transmit_mailbox = 1;
- }
- else if ((CANx->TSR&CAN_TSR_TME2) == CAN_TSR_TME2)
- {
- transmit_mailbox = 2;
- }
- else
- {
- transmit_mailbox = CAN_TxStatus_NoMailBox;
- }
-
- if (transmit_mailbox != CAN_TxStatus_NoMailBox)
- {
- /* Set up the Id */
- CANx->sTxMailBox[transmit_mailbox].TIR &= TMIDxR_TXRQ;
- if (TxMessage->IDE == CAN_Id_Standard)
- {
- assert_param(IS_CAN_STDID(TxMessage->StdId));
- CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->StdId << 21) | \
- TxMessage->RTR);
- }
- else
- {
- assert_param(IS_CAN_EXTID(TxMessage->ExtId));
- CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->ExtId << 3) | \
- TxMessage->IDE | \
- TxMessage->RTR);
- }
-
- /* Set up the DLC */
- TxMessage->DLC &= (uint8_t)0x0000000F;
- CANx->sTxMailBox[transmit_mailbox].TDTR &= (uint32_t)0xFFFFFFF0;
- CANx->sTxMailBox[transmit_mailbox].TDTR |= TxMessage->DLC;
-
- /* Set up the data field */
- CANx->sTxMailBox[transmit_mailbox].TDLR = (((uint32_t)TxMessage->Data[3] << 24) |
- ((uint32_t)TxMessage->Data[2] << 16) |
- ((uint32_t)TxMessage->Data[1] << 8) |
- ((uint32_t)TxMessage->Data[0]));
- CANx->sTxMailBox[transmit_mailbox].TDHR = (((uint32_t)TxMessage->Data[7] << 24) |
- ((uint32_t)TxMessage->Data[6] << 16) |
- ((uint32_t)TxMessage->Data[5] << 8) |
- ((uint32_t)TxMessage->Data[4]));
- /* Request transmission */
- CANx->sTxMailBox[transmit_mailbox].TIR |= TMIDxR_TXRQ;
- }
- return transmit_mailbox;
-}
-
-/**
- * @brief Checks the transmission status of a CAN Frame.
- * @param CANx: where x can be 1 to select the CAN peripheral.
- * @param TransmitMailbox: the number of the mailbox that is used for transmission.
- * @retval CAN_TxStatus_Ok if the CAN driver transmits the message,
- * CAN_TxStatus_Failed in an other case.
- */
-uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox)
-{
- uint32_t state = 0;
-
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
- assert_param(IS_CAN_TRANSMITMAILBOX(TransmitMailbox));
-
- switch (TransmitMailbox)
- {
- case (CAN_TXMAILBOX_0):
- state = CANx->TSR & (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0);
- break;
- case (CAN_TXMAILBOX_1):
- state = CANx->TSR & (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1);
- break;
- case (CAN_TXMAILBOX_2):
- state = CANx->TSR & (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2);
- break;
- default:
- state = CAN_TxStatus_Failed;
- break;
- }
- switch (state)
- {
- /* transmit pending */
- case (0x0): state = CAN_TxStatus_Pending;
- break;
- /* transmit failed */
- case (CAN_TSR_RQCP0 | CAN_TSR_TME0): state = CAN_TxStatus_Failed;
- break;
- case (CAN_TSR_RQCP1 | CAN_TSR_TME1): state = CAN_TxStatus_Failed;
- break;
- case (CAN_TSR_RQCP2 | CAN_TSR_TME2): state = CAN_TxStatus_Failed;
- break;
- /* transmit succeeded */
- case (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0):state = CAN_TxStatus_Ok;
- break;
- case (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1):state = CAN_TxStatus_Ok;
- break;
- case (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2):state = CAN_TxStatus_Ok;
- break;
- default: state = CAN_TxStatus_Failed;
- break;
- }
- return (uint8_t) state;
-}
-
-/**
- * @brief Cancels a transmit request.
- * @param CANx: where x can be 1 to select the CAN peripheral.
- * @param Mailbox: Mailbox number.
- * @retval None
- */
-void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox)
-{
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
- assert_param(IS_CAN_TRANSMITMAILBOX(Mailbox));
- /* abort transmission */
- switch (Mailbox)
- {
- case (CAN_TXMAILBOX_0): CANx->TSR |= CAN_TSR_ABRQ0;
- break;
- case (CAN_TXMAILBOX_1): CANx->TSR |= CAN_TSR_ABRQ1;
- break;
- case (CAN_TXMAILBOX_2): CANx->TSR |= CAN_TSR_ABRQ2;
- break;
- default:
- break;
- }
-}
-/**
- * @}
- */
-
-
-/** @defgroup CAN_Group3 CAN Frames Reception functions
- * @brief CAN Frames Reception functions
- *
-@verbatim
- ===============================================================================
- ##### CAN Frames Reception functions #####
- ===============================================================================
- [..] This section provides functions allowing to
- (+) Receive a correct CAN frame.
- (+) Release a specified receive FIFO (2 FIFOs are available).
- (+) Return the number of the pending received CAN frames.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Receives a correct CAN frame.
- * @param CANx: where x can be 1 to select the CAN peripheral.
- * @param FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
- * @param RxMessage: pointer to a structure receive frame which contains CAN Id,
- * CAN DLC, CAN data and FMI number.
- * @retval None
- */
-void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage)
-{
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
- assert_param(IS_CAN_FIFO(FIFONumber));
- /* Get the Id */
- RxMessage->IDE = (uint8_t)0x04 & CANx->sFIFOMailBox[FIFONumber].RIR;
- if (RxMessage->IDE == CAN_Id_Standard)
- {
- RxMessage->StdId = (uint32_t)0x000007FF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 21);
- }
- else
- {
- RxMessage->ExtId = (uint32_t)0x1FFFFFFF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 3);
- }
-
- RxMessage->RTR = (uint8_t)0x02 & CANx->sFIFOMailBox[FIFONumber].RIR;
- /* Get the DLC */
- RxMessage->DLC = (uint8_t)0x0F & CANx->sFIFOMailBox[FIFONumber].RDTR;
- /* Get the FMI */
- RxMessage->FMI = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDTR >> 8);
- /* Get the data field */
- RxMessage->Data[0] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDLR;
- RxMessage->Data[1] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 8);
- RxMessage->Data[2] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 16);
- RxMessage->Data[3] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 24);
- RxMessage->Data[4] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDHR;
- RxMessage->Data[5] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 8);
- RxMessage->Data[6] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 16);
- RxMessage->Data[7] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 24);
- /* Release the FIFO */
- /* Release FIFO0 */
- if (FIFONumber == CAN_FIFO0)
- {
- CANx->RF0R |= CAN_RF0R_RFOM0;
- }
- /* Release FIFO1 */
- else /* FIFONumber == CAN_FIFO1 */
- {
- CANx->RF1R |= CAN_RF1R_RFOM1;
- }
-}
-
-/**
- * @brief Releases the specified receive FIFO.
- * @param CANx: where x can be 1 to select the CAN peripheral.
- * @param FIFONumber: FIFO to release, CAN_FIFO0 or CAN_FIFO1.
- * @retval None
- */
-void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber)
-{
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
- assert_param(IS_CAN_FIFO(FIFONumber));
- /* Release FIFO0 */
- if (FIFONumber == CAN_FIFO0)
- {
- CANx->RF0R |= CAN_RF0R_RFOM0;
- }
- /* Release FIFO1 */
- else /* FIFONumber == CAN_FIFO1 */
- {
- CANx->RF1R |= CAN_RF1R_RFOM1;
- }
-}
-
-/**
- * @brief Returns the number of pending received messages.
- * @param CANx: where x can be 1 to select the CAN peripheral.
- * @param FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
- * @retval NbMessage : which is the number of pending message.
- */
-uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber)
-{
- uint8_t message_pending=0;
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
- assert_param(IS_CAN_FIFO(FIFONumber));
- if (FIFONumber == CAN_FIFO0)
- {
- message_pending = (uint8_t)(CANx->RF0R&(uint32_t)0x03);
- }
- else if (FIFONumber == CAN_FIFO1)
- {
- message_pending = (uint8_t)(CANx->RF1R&(uint32_t)0x03);
- }
- else
- {
- message_pending = 0;
- }
- return message_pending;
-}
-/**
- * @}
- */
-
-
-/** @defgroup CAN_Group4 CAN Operation modes functions
- * @brief CAN Operation modes functions
- *
-@verbatim
- ===============================================================================
- ##### CAN Operation modes functions #####
- ===============================================================================
- [..] This section provides functions allowing to select the CAN Operation modes:
- (+) sleep mode.
- (+) normal mode.
- (+) initialization mode.
-
-@endverbatim
- * @{
- */
-
-
-/**
- * @brief Selects the CAN Operation mode.
- * @param CAN_OperatingMode: CAN Operating Mode.
- * This parameter can be one of @ref CAN_OperatingMode_TypeDef enumeration.
- * @retval status of the requested mode which can be:
- * - CAN_ModeStatus_Failed: CAN failed entering the specific mode
- * - CAN_ModeStatus_Success: CAN Succeed entering the specific mode
- */
-uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode)
-{
- uint8_t status = CAN_ModeStatus_Failed;
-
- /* Timeout for INAK or also for SLAK bits*/
- uint32_t timeout = INAK_TIMEOUT;
-
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
- assert_param(IS_CAN_OPERATING_MODE(CAN_OperatingMode));
-
- if (CAN_OperatingMode == CAN_OperatingMode_Initialization)
- {
- /* Request initialisation */
- CANx->MCR = (uint32_t)((CANx->MCR & (uint32_t)(~(uint32_t)CAN_MCR_SLEEP)) | CAN_MCR_INRQ);
-
- /* Wait the acknowledge */
- while (((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_INAK) && (timeout != 0))
- {
- timeout--;
- }
- if ((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_INAK)
- {
- status = CAN_ModeStatus_Failed;
- }
- else
- {
- status = CAN_ModeStatus_Success;
- }
- }
- else if (CAN_OperatingMode == CAN_OperatingMode_Normal)
- {
- /* Request leave initialisation and sleep mode and enter Normal mode */
- CANx->MCR &= (uint32_t)(~(CAN_MCR_SLEEP|CAN_MCR_INRQ));
-
- /* Wait the acknowledge */
- while (((CANx->MSR & CAN_MODE_MASK) != 0) && (timeout!=0))
- {
- timeout--;
- }
- if ((CANx->MSR & CAN_MODE_MASK) != 0)
- {
- status = CAN_ModeStatus_Failed;
- }
- else
- {
- status = CAN_ModeStatus_Success;
- }
- }
- else if (CAN_OperatingMode == CAN_OperatingMode_Sleep)
- {
- /* Request Sleep mode */
- CANx->MCR = (uint32_t)((CANx->MCR & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP);
-
- /* Wait the acknowledge */
- while (((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_SLAK) && (timeout!=0))
- {
- timeout--;
- }
- if ((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_SLAK)
- {
- status = CAN_ModeStatus_Failed;
- }
- else
- {
- status = CAN_ModeStatus_Success;
- }
- }
- else
- {
- status = CAN_ModeStatus_Failed;
- }
-
- return (uint8_t) status;
-}
-
-/**
- * @brief Enters the Sleep (low power) mode.
- * @param CANx: where x can be 1 to select the CAN peripheral.
- * @retval CAN_Sleep_Ok if sleep entered, CAN_Sleep_Failed otherwise.
- */
-uint8_t CAN_Sleep(CAN_TypeDef* CANx)
-{
- uint8_t sleepstatus = CAN_Sleep_Failed;
-
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
-
- /* Request Sleep mode */
- CANx->MCR = (((CANx->MCR) & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP);
-
- /* Sleep mode status */
- if ((CANx->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) == CAN_MSR_SLAK)
- {
- /* Sleep mode not entered */
- sleepstatus = CAN_Sleep_Ok;
- }
- /* return sleep mode status */
- return (uint8_t)sleepstatus;
-}
-
-/**
- * @brief Wakes up the CAN peripheral from sleep mode .
- * @param CANx: where x can be 1 to select the CAN peripheral.
- * @retval CAN_WakeUp_Ok if sleep mode left, CAN_WakeUp_Failed otherwise.
- */
-uint8_t CAN_WakeUp(CAN_TypeDef* CANx)
-{
- uint32_t wait_slak = SLAK_TIMEOUT;
- uint8_t wakeupstatus = CAN_WakeUp_Failed;
-
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
-
- /* Wake up request */
- CANx->MCR &= ~(uint32_t)CAN_MCR_SLEEP;
-
- /* Sleep mode status */
- while(((CANx->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)&&(wait_slak!=0x00))
- {
- wait_slak--;
- }
- if((CANx->MSR & CAN_MSR_SLAK) != CAN_MSR_SLAK)
- {
- /* wake up done : Sleep mode exited */
- wakeupstatus = CAN_WakeUp_Ok;
- }
- /* return wakeup status */
- return (uint8_t)wakeupstatus;
-}
-/**
- * @}
- */
-
-
-/** @defgroup CAN_Group5 CAN Bus Error management functions
- * @brief CAN Bus Error management functions
- *
-@verbatim
- ===============================================================================
- ##### CAN Bus Error management functions #####
- ===============================================================================
- [..] This section provides functions allowing to
- (+) Return the CANx's last error code (LEC).
- (+) Return the CANx Receive Error Counter (REC).
- (+) Return the LSB of the 9-bit CANx Transmit Error Counter(TEC).
- [..]
- (@) If TEC is greater than 255, The CAN is in bus-off state.
- (@) If REC or TEC are greater than 96, an Error warning flag occurs.
- (@) If REC or TEC are greater than 127, an Error Passive Flag occurs.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Returns the CANx's last error code (LEC).
- * @param CANx: where x can be 1 to select the CAN peripheral.
- * @retval Error code:
- * - CAN_ERRORCODE_NoErr: No Error
- * - CAN_ERRORCODE_StuffErr: Stuff Error
- * - CAN_ERRORCODE_FormErr: Form Error
- * - CAN_ERRORCODE_ACKErr : Acknowledgment Error
- * - CAN_ERRORCODE_BitRecessiveErr: Bit Recessive Error
- * - CAN_ERRORCODE_BitDominantErr: Bit Dominant Error
- * - CAN_ERRORCODE_CRCErr: CRC Error
- * - CAN_ERRORCODE_SoftwareSetErr: Software Set Error
- */
-uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx)
-{
- uint8_t errorcode=0;
-
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
-
- /* Get the error code*/
- errorcode = (((uint8_t)CANx->ESR) & (uint8_t)CAN_ESR_LEC);
-
- /* Return the error code*/
- return errorcode;
-}
-
-/**
- * @brief Returns the CANx Receive Error Counter (REC).
- * @note In case of an error during reception, this counter is incremented
- * by 1 or by 8 depending on the error condition as defined by the CAN
- * standard. After every successful reception, the counter is
- * decremented by 1 or reset to 120 if its value was higher than 128.
- * When the counter value exceeds 127, the CAN controller enters the
- * error passive state.
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
- * @retval CAN Receive Error Counter.
- */
-uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx)
-{
- uint8_t counter=0;
-
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
-
- /* Get the Receive Error Counter*/
- counter = (uint8_t)((CANx->ESR & CAN_ESR_REC)>> 24);
-
- /* Return the Receive Error Counter*/
- return counter;
-}
-
-
-/**
- * @brief Returns the LSB of the 9-bit CANx Transmit Error Counter(TEC).
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
- * @retval LSB of the 9-bit CAN Transmit Error Counter.
- */
-uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx)
-{
- uint8_t counter=0;
-
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
-
- /* Get the LSB of the 9-bit CANx Transmit Error Counter(TEC) */
- counter = (uint8_t)((CANx->ESR & CAN_ESR_TEC)>> 16);
-
- /* Return the LSB of the 9-bit CANx Transmit Error Counter(TEC) */
- return counter;
-}
-/**
- * @}
- */
-
-/** @defgroup CAN_Group6 Interrupts and flags management functions
- * @brief Interrupts and flags management functions
- *
-@verbatim
- ===============================================================================
- ##### Interrupts and flags management functions #####
- ===============================================================================
- [..] This section provides functions allowing to configure the CAN Interrupts
- and to get the status and clear flags and Interrupts pending bits.
- [..] The CAN provides 14 Interrupts sources and 15 Flags:
-
- *** Flags ***
- =============
- [..] The 15 flags can be divided on 4 groups:
- (+) Transmit Flags:
- (++) CAN_FLAG_RQCP0.
- (++) CAN_FLAG_RQCP1.
- (++) CAN_FLAG_RQCP2: Request completed MailBoxes 0, 1 and 2 Flags
- Set when when the last request (transmit or abort) has
- been performed.
- (+) Receive Flags:
- (++) CAN_FLAG_FMP0.
- (++) CAN_FLAG_FMP1: FIFO 0 and 1 Message Pending Flags;
- Set to signal that messages are pending in the receive FIFO.
- These Flags are cleared only by hardware.
- (++) CAN_FLAG_FF0.
- (++) CAN_FLAG_FF1: FIFO 0 and 1 Full Flags;
- Set when three messages are stored in the selected FIFO.
- (++) CAN_FLAG_FOV0.
- (++) CAN_FLAG_FOV1: FIFO 0 and 1 Overrun Flags;
- Set when a new message has been received and passed the filter
- while the FIFO was full.
- (+) Operating Mode Flags:
- (++) CAN_FLAG_WKU: Wake up Flag;
- Set to signal that a SOF bit has been detected while the CAN
- hardware was in Sleep mode.
- (++) CAN_FLAG_SLAK: Sleep acknowledge Flag;
- Set to signal that the CAN has entered Sleep Mode.
- (+) Error Flags:
- (++) CAN_FLAG_EWG: Error Warning Flag;
- Set when the warning limit has been reached (Receive Error Counter
- or Transmit Error Counter greater than 96).
- This Flag is cleared only by hardware.
- (++) CAN_FLAG_EPV: Error Passive Flag;
- Set when the Error Passive limit has been reached (Receive Error
- Counter or Transmit Error Counter greater than 127).
- This Flag is cleared only by hardware.
- (++) CAN_FLAG_BOF: Bus-Off Flag;
- Set when CAN enters the bus-off state. The bus-off state is
- entered on TEC overflow, greater than 255.
- This Flag is cleared only by hardware.
- (++) CAN_FLAG_LEC: Last error code Flag;
- Set If a message has been transferred (reception or transmission)
- with error, and the error code is hold.
-
- *** Interrupts ***
- ==================
- [..] The 14 interrupts can be divided on 4 groups:
- (+) Transmit interrupt:
- (++) CAN_IT_TME: Transmit mailbox empty Interrupt;
- If enabled, this interrupt source is pending when no transmit
- request are pending for Tx mailboxes.
- (+) Receive Interrupts:
- (++) CAN_IT_FMP0.
- (++) CAN_IT_FMP1: FIFO 0 and FIFO1 message pending Interrupts;
- If enabled, these interrupt sources are pending when messages
- are pending in the receive FIFO.
- The corresponding interrupt pending bits are cleared only by hardware.
- (++) CAN_IT_FF0.
- (++) CAN_IT_FF1: FIFO 0 and FIFO1 full Interrupts;
- If enabled, these interrupt sources are pending when three messages
- are stored in the selected FIFO.
- (++) CAN_IT_FOV0.
- (++) CAN_IT_FOV1: FIFO 0 and FIFO1 overrun Interrupts;
- If enabled, these interrupt sources are pending when a new message
- has been received and passed the filter while the FIFO was full.
- (+) Operating Mode Interrupts:
- (++) CAN_IT_WKU: Wake-up Interrupt;
- If enabled, this interrupt source is pending when a SOF bit has
- been detected while the CAN hardware was in Sleep mode.
- (++) CAN_IT_SLK: Sleep acknowledge Interrupt:
- If enabled, this interrupt source is pending when the CAN has
- entered Sleep Mode.
- (+) Error Interrupts:
- (++) CAN_IT_EWG: Error warning Interrupt;
- If enabled, this interrupt source is pending when the warning limit
- has been reached (Receive Error Counter or Transmit Error Counter=96).
- (++) CAN_IT_EPV: Error passive Interrupt;
- If enabled, this interrupt source is pending when the Error Passive
- limit has been reached (Receive Error Counter or Transmit Error Counter>127).
- (++) CAN_IT_BOF: Bus-off Interrupt;
- If enabled, this interrupt source is pending when CAN enters
- the bus-off state. The bus-off state is entered on TEC overflow,
- greater than 255.
- This Flag is cleared only by hardware.
- (++) CAN_IT_LEC: Last error code Interrupt;
- If enabled, this interrupt source is pending when a message has
- been transferred (reception or transmission) with error and the
- error code is hold.
- (++) CAN_IT_ERR: Error Interrupt;
- If enabled, this interrupt source is pending when an error condition
- is pending.
- [..] Managing the CAN controller events:
- The user should identify which mode will be used in his application to manage
- the CAN controller events: Polling mode or Interrupt mode.
- (+) In the Polling Mode it is advised to use the following functions:
- (++) CAN_GetFlagStatus() : to check if flags events occur.
- (++) CAN_ClearFlag() : to clear the flags events.
- (+) In the Interrupt Mode it is advised to use the following functions:
- (++) CAN_ITConfig() : to enable or disable the interrupt source.
- (++) CAN_GetITStatus() : to check if Interrupt occurs.
- (++) CAN_ClearITPendingBit() : to clear the Interrupt pending Bit
- (corresponding Flag).
- This function has no impact on CAN_IT_FMP0 and CAN_IT_FMP1 Interrupts
- pending bits since there are cleared only by hardware.
-
-@endverbatim
- * @{
- */
-/**
- * @brief Enables or disables the specified CANx interrupts.
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
- * @param CAN_IT: specifies the CAN interrupt sources to be enabled or disabled.
- * This parameter can be:
- * @arg CAN_IT_TME: Transmit mailbox empty Interrupt
- * @arg CAN_IT_FMP0: FIFO 0 message pending Interrupt
- * @arg CAN_IT_FF0: FIFO 0 full Interrupt
- * @arg CAN_IT_FOV0: FIFO 0 overrun Interrupt
- * @arg CAN_IT_FMP1: FIFO 1 message pending Interrupt
- * @arg CAN_IT_FF1: FIFO 1 full Interrupt
- * @arg CAN_IT_FOV1: FIFO 1 overrun Interrupt
- * @arg CAN_IT_WKU: Wake-up Interrupt
- * @arg CAN_IT_SLK: Sleep acknowledge Interrupt
- * @arg CAN_IT_EWG: Error warning Interrupt
- * @arg CAN_IT_EPV: Error passive Interrupt
- * @arg CAN_IT_BOF: Bus-off Interrupt
- * @arg CAN_IT_LEC: Last error code Interrupt
- * @arg CAN_IT_ERR: Error Interrupt
- * @param NewState: new state of the CAN interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
- assert_param(IS_CAN_IT(CAN_IT));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected CANx interrupt */
- CANx->IER |= CAN_IT;
- }
- else
- {
- /* Disable the selected CANx interrupt */
- CANx->IER &= ~CAN_IT;
- }
-}
-/**
- * @brief Checks whether the specified CAN flag is set or not.
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
- * @param CAN_FLAG: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg CAN_FLAG_RQCP0: Request MailBox0 Flag
- * @arg CAN_FLAG_RQCP1: Request MailBox1 Flag
- * @arg CAN_FLAG_RQCP2: Request MailBox2 Flag
- * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
- * @arg CAN_FLAG_FF0: FIFO 0 Full Flag
- * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
- * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
- * @arg CAN_FLAG_FF1: FIFO 1 Full Flag
- * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
- * @arg CAN_FLAG_WKU: Wake up Flag
- * @arg CAN_FLAG_SLAK: Sleep acknowledge Flag
- * @arg CAN_FLAG_EWG: Error Warning Flag
- * @arg CAN_FLAG_EPV: Error Passive Flag
- * @arg CAN_FLAG_BOF: Bus-Off Flag
- * @arg CAN_FLAG_LEC: Last error code Flag
- * @retval The new state of CAN_FLAG (SET or RESET).
- */
-FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG)
-{
- FlagStatus bitstatus = RESET;
-
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
- assert_param(IS_CAN_GET_FLAG(CAN_FLAG));
-
-
- if((CAN_FLAG & CAN_FLAGS_ESR) != (uint32_t)RESET)
- {
- /* Check the status of the specified CAN flag */
- if ((CANx->ESR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
- {
- /* CAN_FLAG is set */
- bitstatus = SET;
- }
- else
- {
- /* CAN_FLAG is reset */
- bitstatus = RESET;
- }
- }
- else if((CAN_FLAG & CAN_FLAGS_MSR) != (uint32_t)RESET)
- {
- /* Check the status of the specified CAN flag */
- if ((CANx->MSR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
- {
- /* CAN_FLAG is set */
- bitstatus = SET;
- }
- else
- {
- /* CAN_FLAG is reset */
- bitstatus = RESET;
- }
- }
- else if((CAN_FLAG & CAN_FLAGS_TSR) != (uint32_t)RESET)
- {
- /* Check the status of the specified CAN flag */
- if ((CANx->TSR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
- {
- /* CAN_FLAG is set */
- bitstatus = SET;
- }
- else
- {
- /* CAN_FLAG is reset */
- bitstatus = RESET;
- }
- }
- else if((CAN_FLAG & CAN_FLAGS_RF0R) != (uint32_t)RESET)
- {
- /* Check the status of the specified CAN flag */
- if ((CANx->RF0R & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
- {
- /* CAN_FLAG is set */
- bitstatus = SET;
- }
- else
- {
- /* CAN_FLAG is reset */
- bitstatus = RESET;
- }
- }
- else /* If(CAN_FLAG & CAN_FLAGS_RF1R != (uint32_t)RESET) */
- {
- /* Check the status of the specified CAN flag */
- if ((uint32_t)(CANx->RF1R & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
- {
- /* CAN_FLAG is set */
- bitstatus = SET;
- }
- else
- {
- /* CAN_FLAG is reset */
- bitstatus = RESET;
- }
- }
- /* Return the CAN_FLAG status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the CAN's pending flags.
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
- * @param CAN_FLAG: specifies the flag to clear.
- * This parameter can be one of the following values:
- * @arg CAN_FLAG_RQCP0: Request MailBox0 Flag
- * @arg CAN_FLAG_RQCP1: Request MailBox1 Flag
- * @arg CAN_FLAG_RQCP2: Request MailBox2 Flag
- * @arg CAN_FLAG_FF0: FIFO 0 Full Flag
- * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
- * @arg CAN_FLAG_FF1: FIFO 1 Full Flag
- * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
- * @arg CAN_FLAG_WKU: Wake up Flag
- * @arg CAN_FLAG_SLAK: Sleep acknowledge Flag
- * @arg CAN_FLAG_LEC: Last error code Flag
- * @retval None
- */
-void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG)
-{
- uint32_t flagtmp=0;
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
- assert_param(IS_CAN_CLEAR_FLAG(CAN_FLAG));
-
- if (CAN_FLAG == CAN_FLAG_LEC) /* ESR register */
- {
- /* Clear the selected CAN flags */
- CANx->ESR = (uint32_t)RESET;
- }
- else /* MSR or TSR or RF0R or RF1R */
- {
- flagtmp = CAN_FLAG & 0x000FFFFF;
-
- if ((CAN_FLAG & CAN_FLAGS_RF0R)!=(uint32_t)RESET)
- {
- /* Receive Flags */
- CANx->RF0R = (uint32_t)(flagtmp);
- }
- else if ((CAN_FLAG & CAN_FLAGS_RF1R)!=(uint32_t)RESET)
- {
- /* Receive Flags */
- CANx->RF1R = (uint32_t)(flagtmp);
- }
- else if ((CAN_FLAG & CAN_FLAGS_TSR)!=(uint32_t)RESET)
- {
- /* Transmit Flags */
- CANx->TSR = (uint32_t)(flagtmp);
- }
- else /* If((CAN_FLAG & CAN_FLAGS_MSR)!=(uint32_t)RESET) */
- {
- /* Operating mode Flags */
- CANx->MSR = (uint32_t)(flagtmp);
- }
- }
-}
-
-/**
- * @brief Checks whether the specified CANx interrupt has occurred or not.
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
- * @param CAN_IT: specifies the CAN interrupt source to check.
- * This parameter can be one of the following values:
- * @arg CAN_IT_TME: Transmit mailbox empty Interrupt
- * @arg CAN_IT_FMP0: FIFO 0 message pending Interrupt
- * @arg CAN_IT_FF0: FIFO 0 full Interrupt
- * @arg CAN_IT_FOV0: FIFO 0 overrun Interrupt
- * @arg CAN_IT_FMP1: FIFO 1 message pending Interrupt
- * @arg CAN_IT_FF1: FIFO 1 full Interrupt
- * @arg CAN_IT_FOV1: FIFO 1 overrun Interrupt
- * @arg CAN_IT_WKU: Wake-up Interrupt
- * @arg CAN_IT_SLK: Sleep acknowledge Interrupt
- * @arg CAN_IT_EWG: Error warning Interrupt
- * @arg CAN_IT_EPV: Error passive Interrupt
- * @arg CAN_IT_BOF: Bus-off Interrupt
- * @arg CAN_IT_LEC: Last error code Interrupt
- * @arg CAN_IT_ERR: Error Interrupt
- * @retval The current state of CAN_IT (SET or RESET).
- */
-ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT)
-{
- ITStatus itstatus = RESET;
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
- assert_param(IS_CAN_IT(CAN_IT));
-
- /* check the interrupt enable bit */
- if((CANx->IER & CAN_IT) != RESET)
- {
- /* in case the Interrupt is enabled, .... */
- switch (CAN_IT)
- {
- case CAN_IT_TME:
- /* Check CAN_TSR_RQCPx bits */
- itstatus = CheckITStatus(CANx->TSR, CAN_TSR_RQCP0|CAN_TSR_RQCP1|CAN_TSR_RQCP2);
- break;
- case CAN_IT_FMP0:
- /* Check CAN_RF0R_FMP0 bit */
- itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FMP0);
- break;
- case CAN_IT_FF0:
- /* Check CAN_RF0R_FULL0 bit */
- itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FULL0);
- break;
- case CAN_IT_FOV0:
- /* Check CAN_RF0R_FOVR0 bit */
- itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FOVR0);
- break;
- case CAN_IT_FMP1:
- /* Check CAN_RF1R_FMP1 bit */
- itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FMP1);
- break;
- case CAN_IT_FF1:
- /* Check CAN_RF1R_FULL1 bit */
- itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FULL1);
- break;
- case CAN_IT_FOV1:
- /* Check CAN_RF1R_FOVR1 bit */
- itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FOVR1);
- break;
- case CAN_IT_WKU:
- /* Check CAN_MSR_WKUI bit */
- itstatus = CheckITStatus(CANx->MSR, CAN_MSR_WKUI);
- break;
- case CAN_IT_SLK:
- /* Check CAN_MSR_SLAKI bit */
- itstatus = CheckITStatus(CANx->MSR, CAN_MSR_SLAKI);
- break;
- case CAN_IT_EWG:
- /* Check CAN_ESR_EWGF bit */
- itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EWGF);
- break;
- case CAN_IT_EPV:
- /* Check CAN_ESR_EPVF bit */
- itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EPVF);
- break;
- case CAN_IT_BOF:
- /* Check CAN_ESR_BOFF bit */
- itstatus = CheckITStatus(CANx->ESR, CAN_ESR_BOFF);
- break;
- case CAN_IT_LEC:
- /* Check CAN_ESR_LEC bit */
- itstatus = CheckITStatus(CANx->ESR, CAN_ESR_LEC);
- break;
- case CAN_IT_ERR:
- /* Check CAN_MSR_ERRI bit */
- itstatus = CheckITStatus(CANx->MSR, CAN_MSR_ERRI);
- break;
- default:
- /* in case of error, return RESET */
- itstatus = RESET;
- break;
- }
- }
- else
- {
- /* in case the Interrupt is not enabled, return RESET */
- itstatus = RESET;
- }
-
- /* Return the CAN_IT status */
- return itstatus;
-}
-
-/**
- * @brief Clears the CANx's interrupt pending bits.
- * @param CANx: where x can be 1 or 2 to to select the CAN peripheral.
- * @param CAN_IT: specifies the interrupt pending bit to clear.
- * This parameter can be one of the following values:
- * @arg CAN_IT_TME: Transmit mailbox empty Interrupt
- * @arg CAN_IT_FF0: FIFO 0 full Interrupt
- * @arg CAN_IT_FOV0: FIFO 0 overrun Interrupt
- * @arg CAN_IT_FF1: FIFO 1 full Interrupt
- * @arg CAN_IT_FOV1: FIFO 1 overrun Interrupt
- * @arg CAN_IT_WKU: Wake-up Interrupt
- * @arg CAN_IT_SLK: Sleep acknowledge Interrupt
- * @arg CAN_IT_EWG: Error warning Interrupt
- * @arg CAN_IT_EPV: Error passive Interrupt
- * @arg CAN_IT_BOF: Bus-off Interrupt
- * @arg CAN_IT_LEC: Last error code Interrupt
- * @arg CAN_IT_ERR: Error Interrupt
- * @retval None
- */
-void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT)
-{
- /* Check the parameters */
- assert_param(IS_CAN_ALL_PERIPH(CANx));
- assert_param(IS_CAN_CLEAR_IT(CAN_IT));
-
- switch (CAN_IT)
- {
- case CAN_IT_TME:
- /* Clear CAN_TSR_RQCPx (rc_w1)*/
- CANx->TSR = CAN_TSR_RQCP0|CAN_TSR_RQCP1|CAN_TSR_RQCP2;
- break;
- case CAN_IT_FF0:
- /* Clear CAN_RF0R_FULL0 (rc_w1)*/
- CANx->RF0R = CAN_RF0R_FULL0;
- break;
- case CAN_IT_FOV0:
- /* Clear CAN_RF0R_FOVR0 (rc_w1)*/
- CANx->RF0R = CAN_RF0R_FOVR0;
- break;
- case CAN_IT_FF1:
- /* Clear CAN_RF1R_FULL1 (rc_w1)*/
- CANx->RF1R = CAN_RF1R_FULL1;
- break;
- case CAN_IT_FOV1:
- /* Clear CAN_RF1R_FOVR1 (rc_w1)*/
- CANx->RF1R = CAN_RF1R_FOVR1;
- break;
- case CAN_IT_WKU:
- /* Clear CAN_MSR_WKUI (rc_w1)*/
- CANx->MSR = CAN_MSR_WKUI;
- break;
- case CAN_IT_SLK:
- /* Clear CAN_MSR_SLAKI (rc_w1)*/
- CANx->MSR = CAN_MSR_SLAKI;
- break;
- case CAN_IT_EWG:
- /* Clear CAN_MSR_ERRI (rc_w1) */
- CANx->MSR = CAN_MSR_ERRI;
- /* @note the corresponding Flag is cleared by hardware depending on the CAN Bus status*/
- break;
- case CAN_IT_EPV:
- /* Clear CAN_MSR_ERRI (rc_w1) */
- CANx->MSR = CAN_MSR_ERRI;
- /* @note the corresponding Flag is cleared by hardware depending on the CAN Bus status*/
- break;
- case CAN_IT_BOF:
- /* Clear CAN_MSR_ERRI (rc_w1) */
- CANx->MSR = CAN_MSR_ERRI;
- /* @note the corresponding Flag is cleared by hardware depending on the CAN Bus status*/
- break;
- case CAN_IT_LEC:
- /* Clear LEC bits */
- CANx->ESR = RESET;
- /* Clear CAN_MSR_ERRI (rc_w1) */
- CANx->MSR = CAN_MSR_ERRI;
- break;
- case CAN_IT_ERR:
- /*Clear LEC bits */
- CANx->ESR = RESET;
- /* Clear CAN_MSR_ERRI (rc_w1) */
- CANx->MSR = CAN_MSR_ERRI;
- /* @note BOFF, EPVF and EWGF Flags are cleared by hardware depending on the CAN Bus status*/
- break;
- default:
- break;
- }
-}
- /**
- * @}
- */
-
-/**
- * @brief Checks whether the CAN interrupt has occurred or not.
- * @param CAN_Reg: specifies the CAN interrupt register to check.
- * @param It_Bit: specifies the interrupt source bit to check.
- * @retval The new state of the CAN Interrupt (SET or RESET).
- */
-static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit)
-{
- ITStatus pendingbitstatus = RESET;
-
- if ((CAN_Reg & It_Bit) != (uint32_t)RESET)
- {
- /* CAN_IT is set */
- pendingbitstatus = SET;
- }
- else
- {
- /* CAN_IT is reset */
- pendingbitstatus = RESET;
- }
- return pendingbitstatus;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_cec.c b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_cec.c
deleted file mode 100644
index f6b4294a7e3e079a2769d05005dfe028f72c180a..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_cec.c
+++ /dev/null
@@ -1,607 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f0xx_cec.c
- * @author MCD Application Team
- * @version V1.3.0
- * @date 16-January-2014
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Consumer Electronics Control (CEC) peripheral
- * applicable only on STM32F051, STM32F042 and STM32F072 devices:
- * + Initialization and Configuration
- * + Data transfers functions
- * + Interrupts and flags management
- *
- * @verbatim
- ==============================================================================
- ##### CEC features #####
- ==============================================================================
- [..] This device provides some features:
- (#) Supports HDMI-CEC specification 1.4.
- (#) Supports two source clocks(HSI/244 or LSE).
- (#) Works in stop mode(without APB clock, but with CEC clock 32KHz).
- It can genarate an interrupt in the CEC clock domain that the CPU
- wakes up from the low power mode.
- (#) Configurable Signal Free Time before of transmission start. The
- number of nominal data bit periods waited before transmission can be
- ruled by Hardware or Software.
- (#) Configurable Peripheral Address (multi-addressing configuration).
- (#) Supports listen mode.The CEC Messages addressed to different destination
- can be received without interfering with CEC bus when Listen mode option is enabled.
- (#) Configurable Rx-Tolerance(Standard and Extended tolerance margin).
- (#) Error detection with configurable error bit generation.
- (#) Arbitration lost error in the case of two CEC devices starting at the same time.
-
- ##### How to use this driver #####
- ==============================================================================
- [..] This driver provides functions to configure and program the CEC device,
- follow steps below:
- (#) The source clock can be configured using:
- (++) RCC_CECCLKConfig(RCC_CECCLK_HSI_Div244) for HSI(Default)
- (++) RCC_CECCLKConfig(RCC_CECCLK_LSE) for LSE.
- (#) Enable CEC peripheral clock using RCC_APBPeriphClockCmd(RCC_APBPeriph_CEC, ENABLE).
- (#) Peripherals alternate function.
- (++) Connect the pin to the desired peripherals' Alternate Function (AF) using
- GPIO_PinAFConfig() function.
- (++) Configure the desired pin in alternate function by:
- GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF.
- (++) Select the type open-drain and output speed via GPIO_OType
- and GPIO_Speed members.
- (++) Call GPIO_Init() function.
- (#) Configure the Signal Free Time, Rx Tolerance, Stop reception generation
- and Bit error generation using the CEC_Init() function.
- The function CEC_Init() must be called when the CEC peripheral is disabled.
- (#) Configure the CEC own address by calling the fuction CEC_OwnAddressConfig().
- (#) Optionally, you can configure the Listen mode using the function CEC_ListenModeCmd().
- (#) Enable the NVIC and the corresponding interrupt using the function
- CEC_ITConfig() if you need to use interrupt mode.
- CEC_ITConfig() must be called before enabling the CEC peripheral.
- (#) Enable the CEC using the CEC_Cmd() function.
- (#) Charge the first data byte in the TXDR register using CEC_SendDataByte().
- (#) Enable the transmission of the Byte of a CEC message using CEC_StartOfMessage()
- (#) Transmit single data through the CEC peripheral using CEC_SendDataByte()
- and Receive the last transmitted byte using CEC_ReceiveDataByte().
- (#) Enable the CEC_EndOfMessage() in order to indicate the last byte of the message.
- [..]
- (@) If the listen mode is enabled, Stop reception generation and Bit error generation
- must be in reset state.
- (@) If the CEC message consists of only 1 byte, the function CEC_EndOfMessage()
- must be called before CEC_StartOfMessage().
-
- @endverbatim
- *
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx_cec.h"
-#include "stm32f0xx_rcc.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup CEC
- * @brief CEC driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-#define BROADCAST_ADDRESS ((uint32_t)0x0000F)
-#define CFGR_CLEAR_MASK ((uint32_t)0x7000FE00) /* CFGR register Mask */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup CEC_Private_Functions
- * @{
- */
-
-/** @defgroup CEC_Group1 Initialization and Configuration functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and Configuration functions #####
- ===============================================================================
- [..] This section provides functions allowing to initialize:
- (+) CEC own addresses
- (+) CEC Signal Free Time
- (+) CEC Rx Tolerance
- (+) CEC Stop Reception
- (+) CEC Bit Rising Error
- (+) CEC Long Bit Period Error
- [..] This section provides also a function to configure the CEC peripheral in Listen Mode.
- Messages addressed to different destination can be received when Listen mode is
- enabled without interfering with CEC bus.
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitializes the CEC peripheral registers to their default reset values.
- * @param None
- * @retval None
- */
-void CEC_DeInit(void)
-{
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_CEC, DISABLE);
-}
-
-/**
- * @brief Initializes the CEC peripheral according to the specified parameters
- * in the CEC_InitStruct.
- * @note The CEC parameters must be configured before enabling the CEC peripheral.
- * @param CEC_InitStruct: pointer to an CEC_InitTypeDef structure that contains
- * the configuration information for the specified CEC peripheral.
- * @retval None
- */
-void CEC_Init(CEC_InitTypeDef* CEC_InitStruct)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_CEC_SIGNAL_FREE_TIME(CEC_InitStruct->CEC_SignalFreeTime));
- assert_param(IS_CEC_RX_TOLERANCE(CEC_InitStruct->CEC_RxTolerance));
- assert_param(IS_CEC_STOP_RECEPTION(CEC_InitStruct->CEC_StopReception));
- assert_param(IS_CEC_BIT_RISING_ERROR(CEC_InitStruct->CEC_BitRisingError));
- assert_param(IS_CEC_LONG_BIT_PERIOD_ERROR(CEC_InitStruct->CEC_LongBitPeriodError));
- assert_param(IS_CEC_BDR_NO_GEN_ERROR(CEC_InitStruct->CEC_BRDNoGen));
- assert_param(IS_CEC_SFT_OPTION(CEC_InitStruct->CEC_SFTOption));
-
- /* Get the CEC CFGR value */
- tmpreg = CEC->CFGR;
-
- /* Clear CFGR bits */
- tmpreg &= CFGR_CLEAR_MASK;
-
- /* Configure the CEC peripheral */
- tmpreg |= (CEC_InitStruct->CEC_SignalFreeTime | CEC_InitStruct->CEC_RxTolerance |
- CEC_InitStruct->CEC_StopReception | CEC_InitStruct->CEC_BitRisingError |
- CEC_InitStruct->CEC_LongBitPeriodError| CEC_InitStruct->CEC_BRDNoGen |
- CEC_InitStruct->CEC_SFTOption);
-
- /* Write to CEC CFGR register */
- CEC->CFGR = tmpreg;
-}
-
-/**
- * @brief Fills each CEC_InitStruct member with its default value.
- * @param CEC_InitStruct: pointer to a CEC_InitTypeDef structure which will
- * be initialized.
- * @retval None
- */
-void CEC_StructInit(CEC_InitTypeDef* CEC_InitStruct)
-{
- CEC_InitStruct->CEC_SignalFreeTime = CEC_SignalFreeTime_Standard;
- CEC_InitStruct->CEC_RxTolerance = CEC_RxTolerance_Standard;
- CEC_InitStruct->CEC_StopReception = CEC_StopReception_Off;
- CEC_InitStruct->CEC_BitRisingError = CEC_BitRisingError_Off;
- CEC_InitStruct->CEC_LongBitPeriodError = CEC_LongBitPeriodError_Off;
- CEC_InitStruct->CEC_BRDNoGen = CEC_BRDNoGen_Off;
- CEC_InitStruct->CEC_SFTOption = CEC_SFTOption_Off;
-}
-
-/**
- * @brief Enables or disables the CEC peripheral.
- * @param NewState: new state of the CEC peripheral.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void CEC_Cmd(FunctionalState NewState)
-{
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the CEC peripheral */
- CEC->CR |= CEC_CR_CECEN;
- }
- else
- {
- /* Disable the CEC peripheral */
- CEC->CR &= ~CEC_CR_CECEN;
- }
-}
-
-/**
- * @brief Enables or disables the CEC Listen Mode.
- * @param NewState: new state of the Listen Mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void CEC_ListenModeCmd(FunctionalState NewState)
-{
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the Listen Mode */
- CEC->CFGR |= CEC_CFGR_LSTN;
- }
- else
- {
- /* Disable the Listen Mode */
- CEC->CFGR &= ~CEC_CFGR_LSTN;
- }
-}
-
-/**
- * @brief Defines the Own Address of the CEC device.
- * @param CEC_OwnAddress: The CEC own address.
- * @retval None
- */
-void CEC_OwnAddressConfig(uint8_t CEC_OwnAddress)
-{
- uint32_t tmp =0x00;
- /* Check the parameters */
- assert_param(IS_CEC_ADDRESS(CEC_OwnAddress));
- tmp = 1 <<(CEC_OwnAddress + 16);
- /* Set the CEC own address */
- CEC->CFGR |= tmp;
-}
-
-/**
- * @brief Clears the Own Address of the CEC device.
- * @param CEC_OwnAddress: The CEC own address.
- * @retval None
- */
-void CEC_OwnAddressClear(void)
-{
- /* Set the CEC own address */
- CEC->CFGR = 0x0;
-}
-
-/**
- * @}
- */
-
-/** @defgroup CEC_Group2 Data transfers functions
- * @brief Data transfers functions
- *
-@verbatim
- ===============================================================================
- ##### Data transfers functions #####
- ===============================================================================
- [..] This section provides functions allowing the CEC data transfers.The read
- access of the CEC_RXDR register can be done using the CEC_ReceiveData()function
- and returns the Rx buffered value. Whereas a write access to the CEC_TXDR can be
- done using CEC_SendData() function.
-@endverbatim
- * @{
- */
-
-/**
- * @brief Transmits single data through the CEC peripheral.
- * @param Data: the data to transmit.
- * @retval None
- */
-void CEC_SendData(uint8_t Data)
-{
- /* Transmit Data */
- CEC->TXDR = Data;
-}
-
-/**
- * @brief Returns the most recent received data by the CEC peripheral.
- * @param None
- * @retval The received data.
- */
-uint8_t CEC_ReceiveData(void)
-{
- /* Receive Data */
- return (uint8_t)(CEC->RXDR);
-}
-
-/**
- * @brief Starts a new message.
- * @param None
- * @retval None
- */
-void CEC_StartOfMessage(void)
-{
- /* Starts of new message */
- CEC->CR |= CEC_CR_TXSOM;
-}
-
-/**
- * @brief Transmits message with an EOM bit.
- * @param None
- * @retval None
- */
-void CEC_EndOfMessage(void)
-{
- /* The data byte will be transmitted with an EOM bit */
- CEC->CR |= CEC_CR_TXEOM;
-}
-
-/**
- * @}
- */
-
-/** @defgroup CEC_Group3 Interrupts and flags management functions
- * @brief Interrupts and flags management functions
-*
-@verbatim
- ===============================================================================
- ##### Interrupts and flags management functions #####
- ===============================================================================
- [..] This section provides functions allowing to configure the CEC Interrupts
- sources and check or clear the flags or pending bits status.
- [..] The user should identify which mode will be used in his application to manage
- the communication: Polling mode or Interrupt mode.
-
- [..] In polling mode, the CEC can be managed by the following flags:
- (+) CEC_FLAG_TXACKE : to indicate a missing acknowledge in transmission mode.
- (+) CEC_FLAG_TXERR : to indicate an error occurs during transmission mode.
- The initiator detects low impedance in the CEC line.
- (+) CEC_FLAG_TXUDR : to indicate if an underrun error occurs in transmission mode.
- The transmission is enabled while the software has not yet
- loaded any value into the TXDR register.
- (+) CEC_FLAG_TXEND : to indicate the end of successful transmission.
- (+) CEC_FLAG_TXBR : to indicate the next transmission data has to be written to TXDR.
- (+) CEC_FLAG_ARBLST : to indicate arbitration lost in the case of two CEC devices
- starting at the same time.
- (+) CEC_FLAG_RXACKE : to indicate a missing acknowledge in receive mode.
- (+) CEC_FLAG_LBPE : to indicate a long bit period error generated during receive mode.
- (+) CEC_FLAG_SBPE : to indicate a short bit period error generated during receive mode.
- (+) CEC_FLAG_BRE : to indicate a bit rising error generated during receive mode.
- (+) CEC_FLAG_RXOVR : to indicate if an overrun error occur while receiving a CEC message.
- A byte is not yet received while a new byte is stored in the RXDR register.
- (+) CEC_FLAG_RXEND : to indicate the end Of reception
- (+) CEC_FLAG_RXBR : to indicate a new byte has been received from the CEC line and
- stored into the RXDR buffer.
- [..]
- (@)In this Mode, it is advised to use the following functions:
- FlagStatus CEC_GetFlagStatus(uint16_t CEC_FLAG);
- void CEC_ClearFlag(uint16_t CEC_FLAG);
-
- [..] In Interrupt mode, the CEC can be managed by the following interrupt sources:
- (+) CEC_IT_TXACKE : to indicate a TX Missing acknowledge
- (+) CEC_IT_TXACKE : to indicate a missing acknowledge in transmission mode.
- (+) CEC_IT_TXERR : to indicate an error occurs during transmission mode.
- The initiator detects low impedance in the CEC line.
- (+) CEC_IT_TXUDR : to indicate if an underrun error occurs in transmission mode.
- The transmission is enabled while the software has not yet
- loaded any value into the TXDR register.
- (+) CEC_IT_TXEND : to indicate the end of successful transmission.
- (+) CEC_IT_TXBR : to indicate the next transmission data has to be written to TXDR register.
- (+) CEC_IT_ARBLST : to indicate arbitration lost in the case of two CEC devices
- starting at the same time.
- (+) CEC_IT_RXACKE : to indicate a missing acknowledge in receive mode.
- (+) CEC_IT_LBPE : to indicate a long bit period error generated during receive mode.
- (+) CEC_IT_SBPE : to indicate a short bit period error generated during receive mode.
- (+) CEC_IT_BRE : to indicate a bit rising error generated during receive mode.
- (+) CEC_IT_RXOVR : to indicate if an overrun error occur while receiving a CEC message.
- A byte is not yet received while a new byte is stored in the RXDR register.
- (+) CEC_IT_RXEND : to indicate the end Of reception
- (+) CEC_IT_RXBR : to indicate a new byte has been received from the CEC line and
- stored into the RXDR buffer.
- [..]
- (@)In this Mode it is advised to use the following functions:
- void CEC_ITConfig( uint16_t CEC_IT, FunctionalState NewState);
- ITStatus CEC_GetITStatus(uint16_t CEC_IT);
- void CEC_ClearITPendingBit(uint16_t CEC_IT);
-
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the selected CEC interrupts.
- * @param CEC_IT: specifies the CEC interrupt source to be enabled.
- * This parameter can be any combination of the following values:
- * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error
- * @arg CEC_IT_TXERR: Tx Error.
- * @arg CEC_IT_TXUDR: Tx-Buffer Underrun.
- * @arg CEC_IT_TXEND: End of Transmission (successful transmission of the last byte).
- * @arg CEC_IT_TXBR: Tx-Byte Request.
- * @arg CEC_IT_ARBLST: Arbitration Lost
- * @arg CEC_IT_RXACKE: Rx-Missing Acknowledge
- * @arg CEC_IT_LBPE: Rx Long period Error
- * @arg CEC_IT_SBPE: Rx Short period Error
- * @arg CEC_IT_BRE: Rx Bit Rising Error
- * @arg CEC_IT_RXOVR: Rx Overrun.
- * @arg CEC_IT_RXEND: End Of Reception
- * @arg CEC_IT_RXBR: Rx-Byte Received
- * @param NewState: new state of the selected CEC interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void CEC_ITConfig(uint16_t CEC_IT, FunctionalState NewState)
-{
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- assert_param(IS_CEC_IT(CEC_IT));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected CEC interrupt */
- CEC->IER |= CEC_IT;
- }
- else
- {
- CEC_IT =~CEC_IT;
- /* Disable the selected CEC interrupt */
- CEC->IER &= CEC_IT;
- }
-}
-
-/**
- * @brief Gets the CEC flag status.
- * @param CEC_FLAG: specifies the CEC flag to check.
- * This parameter can be one of the following values:
- * @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error
- * @arg CEC_FLAG_TXERR: Tx Error.
- * @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun.
- * @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte).
- * @arg CEC_FLAG_TXBR: Tx-Byte Request.
- * @arg CEC_FLAG_ARBLST: Arbitration Lost
- * @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge
- * @arg CEC_FLAG_LBPE: Rx Long period Error
- * @arg CEC_FLAG_SBPE: Rx Short period Error
- * @arg CEC_FLAG_BRE: Rx Bit Rissing Error
- * @arg CEC_FLAG_RXOVR: Rx Overrun.
- * @arg CEC_FLAG_RXEND: End Of Reception.
- * @arg CEC_FLAG_RXBR: Rx-Byte Received.
- * @retval The new state of CEC_FLAG (SET or RESET)
- */
-FlagStatus CEC_GetFlagStatus(uint16_t CEC_FLAG)
-{
- FlagStatus bitstatus = RESET;
-
- assert_param(IS_CEC_GET_FLAG(CEC_FLAG));
-
- /* Check the status of the specified CEC flag */
- if ((CEC->ISR & CEC_FLAG) != (uint16_t)RESET)
- {
- /* CEC flag is set */
- bitstatus = SET;
- }
- else
- {
- /* CEC flag is reset */
- bitstatus = RESET;
- }
-
- /* Return the CEC flag status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the CEC's pending flags.
- * @param CEC_FLAG: specifies the flag to clear.
- * This parameter can be any combination of the following values:
- * @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error
- * @arg CEC_FLAG_TXERR: Tx Error
- * @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun
- * @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte).
- * @arg CEC_FLAG_TXBR: Tx-Byte Request
- * @arg CEC_FLAG_ARBLST: Arbitration Lost
- * @arg CEC_FLAG_RXACKE: Rx Missing Acknowledge
- * @arg CEC_FLAG_LBPE: Rx Long period Error
- * @arg CEC_FLAG_SBPE: Rx Short period Error
- * @arg CEC_FLAG_BRE: Rx Bit Rising Error
- * @arg CEC_FLAG_RXOVR: Rx Overrun
- * @arg CEC_FLAG_RXEND: End Of Reception
- * @arg CEC_FLAG_RXBR: Rx-Byte Received
- * @retval None
- */
-void CEC_ClearFlag(uint32_t CEC_FLAG)
-{
- assert_param(IS_CEC_CLEAR_FLAG(CEC_FLAG));
-
- /* Clear the selected CEC flag */
- CEC->ISR = CEC_FLAG;
-}
-
-/**
- * @brief Checks whether the specified CEC interrupt has occurred or not.
- * @param CEC_IT: specifies the CEC interrupt source to check.
- * This parameter can be one of the following values:
- * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error
- * @arg CEC_IT_TXERR: Tx Error.
- * @arg CEC_IT_TXUDR: Tx-Buffer Underrun.
- * @arg CEC_IT_TXEND: End of transmission (successful transmission of the last byte).
- * @arg CEC_IT_TXBR: Tx-Byte Request.
- * @arg CEC_IT_ARBLST: Arbitration Lost.
- * @arg CEC_IT_RXACKE: Rx-Missing Acknowledge.
- * @arg CEC_IT_LBPE: Rx Long period Error.
- * @arg CEC_IT_SBPE: Rx Short period Error.
- * @arg CEC_IT_BRE: Rx Bit Rising Error.
- * @arg CEC_IT_RXOVR: Rx Overrun.
- * @arg CEC_IT_RXEND: End Of Reception.
- * @arg CEC_IT_RXBR: Rx-Byte Received
- * @retval The new state of CEC_IT (SET or RESET).
- */
-ITStatus CEC_GetITStatus(uint16_t CEC_IT)
-{
- ITStatus bitstatus = RESET;
- uint32_t enablestatus = 0;
-
- /* Check the parameters */
- assert_param(IS_CEC_GET_IT(CEC_IT));
-
- /* Get the CEC IT enable bit status */
- enablestatus = (CEC->IER & CEC_IT);
-
- /* Check the status of the specified CEC interrupt */
- if (((CEC->ISR & CEC_IT) != (uint32_t)RESET) && enablestatus)
- {
- /* CEC interrupt is set */
- bitstatus = SET;
- }
- else
- {
- /* CEC interrupt is reset */
- bitstatus = RESET;
- }
-
- /* Return the CEC interrupt status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the CEC's interrupt pending bits.
- * @param CEC_IT: specifies the CEC interrupt pending bit to clear.
- * This parameter can be any combination of the following values:
- * @arg CEC_IT_TXACKE: Tx Missing acknowledge Error
- * @arg CEC_IT_TXERR: Tx Error
- * @arg CEC_IT_TXUDR: Tx-Buffer Underrun
- * @arg CEC_IT_TXEND: End of Transmission
- * @arg CEC_IT_TXBR: Tx-Byte Request
- * @arg CEC_IT_ARBLST: Arbitration Lost
- * @arg CEC_IT_RXACKE: Rx-Missing Acknowledge
- * @arg CEC_IT_LBPE: Rx Long period Error
- * @arg CEC_IT_SBPE: Rx Short period Error
- * @arg CEC_IT_BRE: Rx Bit Rising Error
- * @arg CEC_IT_RXOVR: Rx Overrun
- * @arg CEC_IT_RXEND: End Of Reception
- * @arg CEC_IT_RXBR: Rx-Byte Received
- * @retval None
- */
-void CEC_ClearITPendingBit(uint16_t CEC_IT)
-{
- assert_param(IS_CEC_IT(CEC_IT));
-
- /* Clear the selected CEC interrupt pending bits */
- CEC->ISR = CEC_IT;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_comp.c b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_comp.c
deleted file mode 100644
index f4b279c045f7d964b399a74fc536bf0fc5e6a99f..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_comp.c
+++ /dev/null
@@ -1,408 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f0xx_comp.c
- * @author MCD Application Team
- * @version V1.3.0
- * @date 16-January-2014
- * @brief This file provides firmware functions to manage the following
- * functionalities of the comparators (COMP1 and COMP2) peripheral
- * applicable only on STM32F051 and STM32F072 devices:
- * + Comparators configuration
- * + Window mode control
- *
- * @verbatim
- *
- ===============================================================================
- ##### How to use this driver #####
- ===============================================================================
- [..]
-
- The device integrates two analog comparators COMP1 and COMP2:
- (+) The non inverting input is set to PA1 for COMP1 and to PA3
- for COMP2.
-
- (+) The inverting input can be selected among: DAC1_OUT, DAC2_OUT
- 1/4 VREFINT, 1/2 VERFINT, 3/4 VREFINT, VREFINT,
- I/O (PA0 for COMP1 and PA2 for COMP2)
-
- (+) The COMP output is internally is available using COMP_GetOutputLevel()
- and can be set on GPIO pins: PA0, PA6, PA11 for COMP1
- and PA2, PA7, PA12 for COMP2
-
- (+) The COMP output can be redirected to embedded timers (TIM1, TIM2
- and TIM3)
-
- (+) The two comparators COMP1 and COMP2 can be combined in window
- mode and only COMP1 non inverting (PA1) can be used as non-
- inverting input.
-
- (+) The two comparators COMP1 and COMP2 have interrupt capability
- with wake-up from Sleep and Stop modes (through the EXTI controller).
- COMP1 and COMP2 outputs are internally connected to EXTI Line 21
- and EXTI Line 22 respectively.
-
-
- ##### How to configure the comparator #####
- ===============================================================================
- [..]
- This driver provides functions to configure and program the Comparators
- of all STM32F0xx devices.
-
- [..] To use the comparator, perform the following steps:
-
- (#) Enable the SYSCFG APB clock to get write access to comparator
- register using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
-
- (#) Configure the comparator input in analog mode using GPIO_Init()
-
- (#) Configure the comparator output in alternate function mode
- using GPIO_Init() and use GPIO_PinAFConfig() function to map the
- comparator output to the GPIO pin
-
- (#) Configure the comparator using COMP_Init() function:
- (++) Select the inverting input
- (++) Select the output polarity
- (++) Select the output redirection
- (++) Select the hysteresis level
- (++) Select the power mode
-
- (#) Enable the comparator using COMP_Cmd() function
-
- (#) If required enable the COMP interrupt by configuring and enabling
- EXTI line in Interrupt mode and selecting the desired sensitivity
- level using EXTI_Init() function. After that enable the comparator
- interrupt vector using NVIC_Init() function.
-
- @endverbatim
- *
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx_comp.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup COMP
- * @brief COMP driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* CSR register Mask */
-#define COMP_CSR_CLEAR_MASK ((uint32_t)0x00003FFE)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup COMP_Private_Functions
- * @{
- */
-
-/** @defgroup COMP_Group1 Initialization and Configuration functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and Configuration functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitializes COMP peripheral registers to their default reset values.
- * @note Deinitialization can't be performed if the COMP configuration is locked.
- * To unlock the configuration, perform a system reset.
- * @param None
- * @retval None
- */
-void COMP_DeInit(void)
-{
- COMP->CSR = ((uint32_t)0x00000000); /*!< Set COMP_CSR register to reset value */
-}
-
-/**
- * @brief Initializes the COMP peripheral according to the specified parameters
- * in COMP_InitStruct
- * @note If the selected comparator is locked, initialization can't be performed.
- * To unlock the configuration, perform a system reset.
- * @note By default, PA1 is selected as COMP1 non inverting input.
- * To use PA4 as COMP1 non inverting input call COMP_SwitchCmd() after COMP_Init()
- * @param COMP_Selection: the selected comparator.
- * This parameter can be one of the following values:
- * @arg COMP_Selection_COMP1: COMP1 selected
- * @arg COMP_Selection_COMP2: COMP2 selected
- * @param COMP_InitStruct: pointer to an COMP_InitTypeDef structure that contains
- * the configuration information for the specified COMP peripheral.
- * @retval None
- */
-void COMP_Init(uint32_t COMP_Selection, COMP_InitTypeDef* COMP_InitStruct)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_COMP_ALL_PERIPH(COMP_Selection));
- assert_param(IS_COMP_INVERTING_INPUT(COMP_InitStruct->COMP_InvertingInput));
- assert_param(IS_COMP_OUTPUT(COMP_InitStruct->COMP_Output));
- assert_param(IS_COMP_OUTPUT_POL(COMP_InitStruct->COMP_OutputPol));
- assert_param(IS_COMP_HYSTERESIS(COMP_InitStruct->COMP_Hysteresis));
- assert_param(IS_COMP_MODE(COMP_InitStruct->COMP_Mode));
-
- /*!< Get the COMP_CSR register value */
- tmpreg = COMP->CSR;
-
- /*!< Clear the COMP1SW1, COMPx_IN_SEL, COMPx_OUT_TIM_SEL, COMPx_POL, COMPx_HYST and COMPx_PWR_MODE bits */
- tmpreg &= (uint32_t) ~(COMP_CSR_CLEAR_MASK<<COMP_Selection);
-
- /*!< Configure COMP: inverting input, output redirection, hysteresis value and power mode */
- /*!< Set COMPxINSEL bits according to COMP_InitStruct->COMP_InvertingInput value */
- /*!< Set COMPxOUTSEL bits according to COMP_InitStruct->COMP_Output value */
- /*!< Set COMPxPOL bit according to COMP_InitStruct->COMP_OutputPol value */
- /*!< Set COMPxHYST bits according to COMP_InitStruct->COMP_Hysteresis value */
- /*!< Set COMPxMODE bits according to COMP_InitStruct->COMP_Mode value */
- tmpreg |= (uint32_t)((COMP_InitStruct->COMP_InvertingInput | COMP_InitStruct->COMP_Output |
- COMP_InitStruct->COMP_OutputPol | COMP_InitStruct->COMP_Hysteresis |
- COMP_InitStruct->COMP_Mode)<<COMP_Selection);
-
- /*!< Write to COMP_CSR register */
- COMP->CSR = tmpreg;
-}
-
-/**
- * @brief Fills each COMP_InitStruct member with its default value.
- * @param COMP_InitStruct: pointer to an COMP_InitTypeDef structure which will
- * be initialized.
- * @retval None
- */
-void COMP_StructInit(COMP_InitTypeDef* COMP_InitStruct)
-{
- COMP_InitStruct->COMP_InvertingInput = COMP_InvertingInput_1_4VREFINT;
- COMP_InitStruct->COMP_Output = COMP_Output_None;
- COMP_InitStruct->COMP_OutputPol = COMP_OutputPol_NonInverted;
- COMP_InitStruct->COMP_Hysteresis = COMP_Hysteresis_No;
- COMP_InitStruct->COMP_Mode = COMP_Mode_UltraLowPower;
-}
-
-/**
- * @brief Enable or disable the COMP peripheral.
- * @note If the selected comparator is locked, enable/disable can't be performed.
- * To unlock the configuration, perform a system reset.
- * @param COMP_Selection: the selected comparator.
- * This parameter can be one of the following values:
- * @arg COMP_Selection_COMP1: COMP1 selected
- * @arg COMP_Selection_COMP2: COMP2 selected
- * @param NewState: new state of the COMP peripheral.
- * This parameter can be: ENABLE or DISABLE.
- * @note When enabled, the comparator compares the non inverting input with
- * the inverting input and the comparison result is available on comparator output.
- * @note When disabled, the comparator doesn't perform comparison and the
- * output level is low.
- * @retval None
- */
-void COMP_Cmd(uint32_t COMP_Selection, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_COMP_ALL_PERIPH(COMP_Selection));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected COMP peripheral */
- COMP->CSR |= (uint32_t) (1<<COMP_Selection);
- }
- else
- {
- /* Disable the selected COMP peripheral */
- COMP->CSR &= (uint32_t)(~((uint32_t)1<<COMP_Selection));
- }
-}
-
-/**
- * @brief Close or Open the SW1 switch.
- * @note This switch is solely intended to redirect signals onto high
- * impedance input, such as COMP1 non-inverting input (highly resistive switch)
- * @param NewState: New state of the analog switch.
- * This parameter can be: ENABLE or DISABLE.
- * @note When enabled, the SW1 is closed; PA1 is connected to PA4
- * @note When disabled, the SW1 switch is open; PA1 is disconnected from PA4
- * @retval None
- */
-void COMP_SwitchCmd(FunctionalState NewState)
-{
- /* Check the parameter */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Close SW1 switch */
- COMP->CSR |= (uint32_t) (COMP_CSR_COMP1SW1);
- }
- else
- {
- /* Open SW1 switch */
- COMP->CSR &= (uint32_t)(~COMP_CSR_COMP1SW1);
- }
-}
-
-/**
- * @brief Return the output level (high or low) of the selected comparator.
- * @note The output level depends on the selected polarity.
- * @note If the polarity is not inverted:
- * - Comparator output is low when the non-inverting input is at a lower
- * voltage than the inverting input
- * - Comparator output is high when the non-inverting input is at a higher
- * voltage than the inverting input
- * @note If the polarity is inverted:
- * - Comparator output is high when the non-inverting input is at a lower
- * voltage than the inverting input
- * - Comparator output is low when the non-inverting input is at a higher
- * voltage than the inverting input
- * @param COMP_Selection: the selected comparator.
- * This parameter can be one of the following values:
- * @arg COMP_Selection_COMP1: COMP1 selected
- * @arg COMP_Selection_COMP2: COMP2 selected
- * @retval Returns the selected comparator output level: low or high.
- *
- */
-uint32_t COMP_GetOutputLevel(uint32_t COMP_Selection)
-{
- uint32_t compout = 0x0;
-
- /* Check the parameters */
- assert_param(IS_COMP_ALL_PERIPH(COMP_Selection));
-
- /* Check if selected comparator output is high */
- if ((COMP->CSR & (COMP_CSR_COMP1OUT<<COMP_Selection)) != 0)
- {
- compout = COMP_OutputLevel_High;
- }
- else
- {
- compout = COMP_OutputLevel_Low;
- }
-
- /* Return the comparator output level */
- return (uint32_t)(compout);
-}
-
-/**
- * @}
- */
-
-/** @defgroup COMP_Group2 Window mode control function
- * @brief Window mode control function
- *
-@verbatim
- ===============================================================================
- ##### Window mode control function #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the window mode.
- * @note In window mode, COMP1 and COMP2 non inverting inputs are connected
- * together and only COMP1 non inverting input (PA1) can be used.
- * @param NewState: new state of the window mode.
- * This parameter can be :
- * @arg ENABLE: COMP1 and COMP2 non inverting inputs are connected together.
- * @arg DISABLE: OMP1 and COMP2 non inverting inputs are disconnected.
- * @retval None
- */
-void COMP_WindowCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the window mode */
- COMP->CSR |= (uint32_t) COMP_CSR_WNDWEN;
- }
- else
- {
- /* Disable the window mode */
- COMP->CSR &= (uint32_t)(~COMP_CSR_WNDWEN);
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup COMP_Group3 COMP configuration locking function
- * @brief COMP1 and COMP2 configuration locking function
- * COMP1 and COMP2 configuration can be locked each separately.
- * Unlocking is performed by system reset.
- *
-@verbatim
- ===============================================================================
- ##### Configuration Lock function #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Lock the selected comparator (COMP1/COMP2) configuration.
- * @note Locking the configuration means that all control bits are read-only.
- * To unlock the comparator configuration, perform a system reset.
- * @param COMP_Selection: selects the comparator to be locked
- * This parameter can be a value of the following values:
- * @arg COMP_Selection_COMP1: COMP1 configuration is locked.
- * @arg COMP_Selection_COMP2: COMP2 configuration is locked.
- * @retval None
- */
-void COMP_LockConfig(uint32_t COMP_Selection)
-{
- /* Check the parameter */
- assert_param(IS_COMP_ALL_PERIPH(COMP_Selection));
-
- /* Set the lock bit corresponding to selected comparator */
- COMP->CSR |= (uint32_t) (COMP_CSR_COMP1LOCK<<COMP_Selection);
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_crc.c b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_crc.c
deleted file mode 100644
index 05e1bf1f1eb74cea3cb04fb6d73a56d96a86142a..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_crc.c
+++ /dev/null
@@ -1,361 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f0xx_crc.c
- * @author MCD Application Team
- * @version V1.3.0
- * @date 16-January-2014
- * @brief This file provides firmware functions to manage the following
- * functionalities of CRC computation unit peripheral:
- * + Configuration of the CRC computation unit
- * + CRC computation of one/many 32-bit data
- * + CRC Independent register (IDR) access
- *
- * @verbatim
- ===============================================================================
- ##### How to use this driver #####
- ===============================================================================
- [..]
-
- (+) Enable CRC AHB clock using RCC_AHBPeriphClockCmd(RCC_AHBPeriph_CRC, ENABLE)
- function
- (+) If required, select the reverse operation on input data
- using CRC_ReverseInputDataSelect()
- (+) If required, enable the reverse operation on output data
- using CRC_ReverseOutputDataCmd(Enable)
- (+) use CRC_CalcCRC() function to compute the CRC of a 32-bit data
- or use CRC_CalcBlockCRC() function to compute the CRC if a 32-bit
- data buffer
- (@) To compute the CRC of a new data use CRC_ResetDR() to reset
- the CRC computation unit before starting the computation
- otherwise you can get wrong CRC values.
-
- @endverbatim
- *
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx_crc.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup CRC
- * @brief CRC driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup CRC_Private_Functions
- * @{
- */
-
-/** @defgroup CRC_Group1 Configuration of the CRC computation unit functions
- * @brief Configuration of the CRC computation unit functions
- *
-@verbatim
- ===============================================================================
- ##### CRC configuration functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitializes CRC peripheral registers to their default reset values.
- * @param None
- * @retval None
- */
-void CRC_DeInit(void)
-{
- /* Set DR register to reset value */
- CRC->DR = 0xFFFFFFFF;
-
- /* Set the POL register to the reset value: 0x04C11DB7 */
- CRC->POL = 0x04C11DB7;
-
- /* Reset IDR register */
- CRC->IDR = 0x00;
-
- /* Set INIT register to reset value */
- CRC->INIT = 0xFFFFFFFF;
-
- /* Reset the CRC calculation unit */
- CRC->CR = CRC_CR_RESET;
-}
-
-/**
- * @brief Resets the CRC calculation unit and sets INIT register content in DR register.
- * @param None
- * @retval None
- */
-void CRC_ResetDR(void)
-{
- /* Reset CRC generator */
- CRC->CR |= CRC_CR_RESET;
-}
-
-/**
- * @brief Selects the polynomial size. This function is only applicable for
- * STM32F072 devices.
- * @param CRC_PolSize: Specifies the polynomial size.
- * This parameter can be:
- * @arg CRC_PolSize_7: 7-bit polynomial for CRC calculation
- * @arg CRC_PolSize_8: 8-bit polynomial for CRC calculation
- * @arg CRC_PolSize_16: 16-bit polynomial for CRC calculation
- * @arg CRC_PolSize_32: 32-bit polynomial for CRC calculation
- * @retval None
- */
-void CRC_PolynomialSizeSelect(uint32_t CRC_PolSize)
-{
- uint32_t tmpcr = 0;
-
- /* Check the parameter */
- assert_param(IS_CRC_POL_SIZE(CRC_PolSize));
-
- /* Get CR register value */
- tmpcr = CRC->CR;
-
- /* Reset POL_SIZE bits */
- tmpcr &= (uint32_t)~((uint32_t)CRC_CR_POLSIZE);
- /* Set the polynomial size */
- tmpcr |= (uint32_t)CRC_PolSize;
-
- /* Write to CR register */
- CRC->CR = (uint32_t)tmpcr;
-}
-
-/**
- * @brief Selects the reverse operation to be performed on input data.
- * @param CRC_ReverseInputData: Specifies the reverse operation on input data.
- * This parameter can be:
- * @arg CRC_ReverseInputData_No: No reverse operation is performed
- * @arg CRC_ReverseInputData_8bits: reverse operation performed on 8 bits
- * @arg CRC_ReverseInputData_16bits: reverse operation performed on 16 bits
- * @arg CRC_ReverseInputData_32bits: reverse operation performed on 32 bits
- * @retval None
- */
-void CRC_ReverseInputDataSelect(uint32_t CRC_ReverseInputData)
-{
- uint32_t tmpcr = 0;
-
- /* Check the parameter */
- assert_param(IS_CRC_REVERSE_INPUT_DATA(CRC_ReverseInputData));
-
- /* Get CR register value */
- tmpcr = CRC->CR;
-
- /* Reset REV_IN bits */
- tmpcr &= (uint32_t)~((uint32_t)CRC_CR_REV_IN);
- /* Set the reverse operation */
- tmpcr |= (uint32_t)CRC_ReverseInputData;
-
- /* Write to CR register */
- CRC->CR = (uint32_t)tmpcr;
-}
-
-/**
- * @brief Enables or disable the reverse operation on output data.
- * The reverse operation on output data is performed on 32-bit.
- * @param NewState: new state of the reverse operation on output data.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void CRC_ReverseOutputDataCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable reverse operation on output data */
- CRC->CR |= CRC_CR_REV_OUT;
- }
- else
- {
- /* Disable reverse operation on output data */
- CRC->CR &= (uint32_t)~((uint32_t)CRC_CR_REV_OUT);
- }
-}
-
-/**
- * @brief Initializes the INIT register.
- * @note After resetting CRC calculation unit, CRC_InitValue is stored in DR register
- * @param CRC_InitValue: Programmable initial CRC value
- * @retval None
- */
-void CRC_SetInitRegister(uint32_t CRC_InitValue)
-{
- CRC->INIT = CRC_InitValue;
-}
-
-/**
- * @brief Initializes the polynomail coefficients. This function is only
- * applicable for STM32F072 devices.
- * @param CRC_Pol: Polynomial to be used for CRC calculation.
- * @retval None
- */
-void CRC_SetPolynomial(uint32_t CRC_Pol)
-{
- CRC->POL = CRC_Pol;
-}
-
-/**
- * @}
- */
-
-/** @defgroup CRC_Group2 CRC computation of one/many 32-bit data functions
- * @brief CRC computation of one/many 32-bit data functions
- *
-@verbatim
- ===============================================================================
- ##### CRC computation functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Computes the 32-bit CRC of a given data word(32-bit).
- * @param CRC_Data: data word(32-bit) to compute its CRC
- * @retval 32-bit CRC
- */
-uint32_t CRC_CalcCRC(uint32_t CRC_Data)
-{
- CRC->DR = CRC_Data;
-
- return (CRC->DR);
-}
-
-/**
- * @brief Computes the 16-bit CRC of a given 16-bit data. This function is only
- * applicable for STM32F072 devices.
- * @param CRC_Data: data half-word(16-bit) to compute its CRC
- * @retval 16-bit CRC
- */
-uint32_t CRC_CalcCRC16bits(uint16_t CRC_Data)
-{
- *(uint16_t*)(CRC_BASE) = (uint16_t) CRC_Data;
-
- return (CRC->DR);
-}
-
-/**
- * @brief Computes the 8-bit CRC of a given 8-bit data. This function is only
- * applicable for STM32F072 devices.
- * @param CRC_Data: 8-bit data to compute its CRC
- * @retval 8-bit CRC
- */
-uint32_t CRC_CalcCRC8bits(uint8_t CRC_Data)
-{
- *(uint8_t*)(CRC_BASE) = (uint8_t) CRC_Data;
-
- return (CRC->DR);
-}
-
-/**
- * @brief Computes the 32-bit CRC of a given buffer of data word(32-bit).
- * @param pBuffer: pointer to the buffer containing the data to be computed
- * @param BufferLength: length of the buffer to be computed
- * @retval 32-bit CRC
- */
-uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength)
-{
- uint32_t index = 0;
-
- for(index = 0; index < BufferLength; index++)
- {
- CRC->DR = pBuffer[index];
- }
- return (CRC->DR);
-}
-
-/**
- * @brief Returns the current CRC value.
- * @param None
- * @retval 32-bit CRC
- */
-uint32_t CRC_GetCRC(void)
-{
- return (CRC->DR);
-}
-
-/**
- * @}
- */
-
-/** @defgroup CRC_Group3 CRC Independent Register (IDR) access functions
- * @brief CRC Independent Register (IDR) access (write/read) functions
- *
-@verbatim
- ===============================================================================
- ##### CRC Independent Register (IDR) access functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Stores an 8-bit data in the Independent Data(ID) register.
- * @param CRC_IDValue: 8-bit value to be stored in the ID register
- * @retval None
- */
-void CRC_SetIDRegister(uint8_t CRC_IDValue)
-{
- CRC->IDR = CRC_IDValue;
-}
-
-/**
- * @brief Returns the 8-bit data stored in the Independent Data(ID) register
- * @param None
- * @retval 8-bit value of the ID register
- */
-uint8_t CRC_GetIDRegister(void)
-{
- return (CRC->IDR);
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_crs.c b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_crs.c
deleted file mode 100644
index 3d35149b4df3df98d7d221bdb514931db4e4f4ac..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_crs.c
+++ /dev/null
@@ -1,466 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f0xx_crs.c
- * @author MCD Application Team
- * @version V1.3.0
- * @date 16-January-2014
- * @brief This file provides firmware functions to manage the following
- * functionalities of CRS peripheral applicable only on STM32F042 and
- * STM32F072 devices:
- * + Configuration of the CRS peripheral
- * + Interrupts and flags management
- *
- *
- * @verbatim
- ===============================================================================
- ##### How to use this driver #####
- ===============================================================================
- [..]
-
- (+) Enable CRS AHB clock using RCC_APB1eriphClockCmd(RCC_APB1Periph_CRS, ENABLE)
- function
-
-
- @endverbatim
- *
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx_crs.h"
-#include "stm32f0xx_rcc.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup CRS
- * @brief CRS driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* CRS Flag Mask */
-#define FLAG_MASK ((uint32_t)0x700)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup CRS_Private_Functions
- * @{
- */
-
-/** @defgroup CRS_Group1 Configuration of the CRS functions
- * @brief Configuration of the CRS functions
- *
-@verbatim
- ===============================================================================
- ##### CRS configuration functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitializes CRS peripheral registers to their default reset values.
- * @param None
- * @retval None
- */
-void CRS_DeInit(void)
-{
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_CRS, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_CRS, DISABLE);
-}
-
-/**
- * @brief Adjusts the Internal High Speed 48 oscillator (HSI 48) calibration value.
- * @note The calibration is used to compensate for the variations in voltage
- * and temperature that influence the frequency of the internal HSI48 RC.
- * @note This function can be called only when the AUTOTRIMEN bit is reset.
- * @param CRS_HSI48CalibrationValue:
- * @retval None
- */
-void CRS_AdjustHSI48CalibrationValue(uint8_t CRS_HSI48CalibrationValue)
-{
- /* Clear TRIM[5:0] bits */
- CRS->CR &= ~CRS_CR_TRIM;
-
- /* Set the TRIM[5:0] bits according to CRS_HSI48CalibrationValue value */
- CRS->CR |= (uint32_t)((uint32_t)CRS_HSI48CalibrationValue << 8);
-
-}
-
-/**
- * @brief Enables or disables the oscillator clock for frequency error counter.
- * @note when the CEN bit is set the CRS_CFGR register becomes write-protected.
- * @param NewState: new state of the frequency error counter.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void CRS_FrequencyErrorCounterCmd(FunctionalState NewState)
-{
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- CRS->CR |= CRS_CR_CEN;
- }
- else
- {
- CRS->CR &= ~CRS_CR_CEN;
- }
-}
-
-/**
- * @brief Enables or disables the automatic hardware adjustement of TRIM bits.
- * @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected.
- * @param NewState: new state of the automatic trimming.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void CRS_AutomaticCalibrationCmd(FunctionalState NewState)
-{
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- CRS->CR |= CRS_CR_AUTOTRIMEN;
- }
-else
- {
- CRS->CR &= ~CRS_CR_AUTOTRIMEN;
- }
-}
-
-/**
- * @brief Generate the software synchronization event
- * @param None
- * @retval None
- */
-void CRS_SoftwareSynchronizationGenerate(void)
-{
- CRS->CR |= CRS_CR_SWSYNC;
-}
-
-/**
- * @brief Adjusts the Internal High Speed 48 oscillator (HSI 48) calibration value.
- * @note The calibration is used to compensate for the variations in voltage
- * and temperature that influence the frequency of the internal HSI48 RC.
- * @note This function can be called only when the CEN bit is reset.
- * @param CRS_ReloadValue: specifies the HSI calibration trimming value.
- * This parameter must be a number between 0 and .
- * @retval None
- */
-void CRS_FrequencyErrorCounterReload(uint32_t CRS_ReloadValue)
-{
-
- /* Clear RELOAD[15:0] bits */
- CRS->CFGR &= ~CRS_CFGR_RELOAD;
-
- /* Set the RELOAD[15:0] bits according to CRS_ReloadValue value */
- CRS->CFGR |= (uint32_t)CRS_ReloadValue;
-
-}
-
-/**
- * @brief
- * @note This function can be called only when the CEN bit is reset.
- * @param CRS_ErrorLimitValue: specifies the HSI calibration trimming value.
- * This parameter must be a number between 0 and .
- * @retval None
- */
-void CRS_FrequencyErrorLimitConfig(uint8_t CRS_ErrorLimitValue)
-{
- /* Clear FELIM[7:0] bits */
- CRS->CFGR &= ~CRS_CFGR_FELIM;
-
- /* Set the FELIM[7:0] bits according to CRS_ErrorLimitValue value */
- CRS->CFGR |= (uint32_t)CRS_ErrorLimitValue;
-}
-
-/**
- * @brief
- * @note This function can be called only when the CEN bit is reset.
- * @param CRS_Prescaler: specifies the HSI calibration trimming value.
- * This parameter can be one of the following values:
- * @arg CRS_SYNC_Div1:
- * @arg CRS_SYNC_Div2:
- * @arg CRS_SYNC_Div4:
- * @arg CRS_SYNC_Div8:
- * @arg CRS_SYNC_Div16:
- * @arg CRS_SYNC_Div32:
- * @arg CRS_SYNC_Div64:
- * @arg CRS_SYNC_Div128:
- * @retval None
- */
-void CRS_SynchronizationPrescalerConfig(uint32_t CRS_Prescaler)
-{
- /* Check the parameters */
- assert_param(IS_CRS_SYNC_DIV(CRS_Prescaler));
-
- /* Clear SYNCDIV[2:0] bits */
- CRS->CFGR &= ~CRS_CFGR_SYNCDIV;
-
- /* Set the CRS_CFGR_SYNCDIV[2:0] bits according to CRS_Prescaler value */
- CRS->CFGR |= CRS_Prescaler;
-}
-
-/**
- * @brief
- * @note This function can be called only when the CEN bit is reset.
- * @param CRS_Source: .
- * This parameter can be one of the following values:
- * @arg CRS_SYNCSource_GPIO:
- * @arg CRS_SYNCSource_LSE:
- * @arg CRS_SYNCSource_USB:
- * @retval None
- */
-void CRS_SynchronizationSourceConfig(uint32_t CRS_Source)
-{
- /* Check the parameters */
- assert_param(IS_CRS_SYNC_SOURCE(CRS_Source));
-
- /* Clear SYNCSRC[1:0] bits */
- CRS->CFGR &= ~CRS_CFGR_SYNCSRC;
-
- /* Set the SYNCSRC[1:0] bits according to CRS_Source value */
- CRS->CFGR |= CRS_Source;
-}
-
-/**
- * @brief
- * @note This function can be called only when the CEN bit is reset.
- * @param CRS_Polarity: .
- * This parameter can be one of the following values:
- * @arg CRS_SYNCPolarity_Rising:
- * @arg CRS_SYNCPolarity_Falling:
- * @retval None
- */
-void CRS_SynchronizationPolarityConfig(uint32_t CRS_Polarity)
-{
- /* Check the parameters */
- assert_param(IS_CRS_SYNC_POLARITY(CRS_Polarity));
-
- /* Clear SYNCSPOL bit */
- CRS->CFGR &= ~CRS_CFGR_SYNCPOL;
-
- /* Set the SYNCSPOL bits according to CRS_Polarity value */
- CRS->CFGR |= CRS_Polarity;
-}
-
-/**
- * @brief Returns the Relaod value.
- * @param None
- * @retval The reload value
- */
-uint32_t CRS_GetReloadValue(void)
-{
- return ((uint32_t)(CRS->CFGR & CRS_CFGR_RELOAD));
-}
-
-/**
- * @brief Returns the HSI48 Calibration value.
- * @param None
- * @retval The reload value
- */
-uint32_t CRS_GetHSI48CalibrationValue(void)
-{
- return (((uint32_t)(CRS->CR & CRS_CR_TRIM)) >> 8);
-}
-
-/**
- * @brief Returns the frequency error capture.
- * @param None
- * @retval The frequency error capture value
- */
-uint32_t CRS_GetFrequencyErrorValue(void)
-{
- return ((uint32_t)(CRS->ISR & CRS_ISR_FECAP));
-}
-
-/**
- * @brief Returns the frequency error direction.
- * @param None
- * @retval The frequency error direction. The returned value can be one
- * of the following values:
- * - 0x00: Up counting
- * - 0x8000: Down counting
- */
-uint32_t CRS_GetFrequencyErrorDirection(void)
-{
- return ((uint32_t)(CRS->ISR & CRS_ISR_FEDIR));
-}
-
-/** @defgroup CRS_Group2 Interrupts and flags management functions
- * @brief Interrupts and flags management functions
- *
-@verbatim
- ===============================================================================
- ##### Interrupts and flags management functions #####
- ===============================================================================
-@endverbatim
- * @{
- */
-/**
- * @brief Enables or disables the specified CRS interrupts.
- * @param CRS_IT: specifies the RCC interrupt sources to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg CRS_IT_SYNCOK:
- * @arg CRS_IT_SYNCWARN:
- * @arg CRS_IT_ERR:
- * @arg CRS_IT_ESYNC:
- * @param NewState: new state of the specified CRS interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void CRS_ITConfig(uint32_t CRS_IT, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_CRS_IT(CRS_IT));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- CRS->CR |= CRS_IT;
- }
- else
- {
- CRS->CR &= ~CRS_IT;
- }
-}
-
-/**
- * @brief Checks whether the specified CRS flag is set or not.
- * @param CRS_FLAG: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg CRS_FLAG_SYNCOK:
- * @arg CRS_FLAG_SYNCWARN:
- * @arg CRS_FLAG_ERR:
- * @arg CRS_FLAG_ESYNC:
- * @arg CRS_FLAG_TRIMOVF:
- * @arg CRS_FLAG_SYNCERR:
- * @arg CRS_FLAG_SYNCMISS:
- * @retval The new state of CRS_FLAG (SET or RESET).
- */
-FlagStatus CRS_GetFlagStatus(uint32_t CRS_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_CRS_FLAG(CRS_FLAG));
-
- return ((FlagStatus)(CRS->ISR & CRS_FLAG));
-}
-
-/**
- * @brief Clears the CRS specified FLAG.
- * @param CRS_FLAG: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg CRS_FLAG_SYNCOK:
- * @arg CRS_FLAG_SYNCWARN:
- * @arg CRS_FLAG_ERR:
- * @arg CRS_FLAG_ESYNC:
- * @arg CRS_FLAG_TRIMOVF:
- * @arg CRS_FLAG_SYNCERR:
- * @arg CRS_FLAG_SYNCMISS:
- * @retval None
- */
-void CRS_ClearFlag(uint32_t CRS_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_CRS_FLAG(CRS_FLAG));
-
- if ((CRS_FLAG & FLAG_MASK)!= 0)
- {
- CRS->ICR |= CRS_ICR_ERRC;
- }
- else
- {
- CRS->ICR |= CRS_FLAG;
- }
-}
-
-/**
- * @brief Checks whether the specified CRS IT pending bit is set or not.
- * @param CRS_IT: specifies the IT pending bit to check.
- * This parameter can be one of the following values:
- * @arg CRS_IT_SYNCOK:
- * @arg CRS_IT_SYNCWARN:
- * @arg CRS_IT_ERR:
- * @arg CRS_IT_ESYNC:
- * @arg CRS_IT_TRIMOVF:
- * @arg CRS_IT_SYNCERR:
- * @arg CRS_IT_SYNCMISS:
- * @retval The new state of CRS_IT (SET or RESET).
- */
-ITStatus CRS_GetITStatus(uint32_t CRS_IT)
-{
- /* Check the parameters */
- assert_param(IS_CRS_GET_IT(CRS_IT));
-
- return ((ITStatus)(CRS->ISR & CRS_IT));
-}
-
-/**
- * @brief Clears the CRS specified IT pending bi.
- * @param CRS_FLAG: specifies the IT pending bi to clear.
- * This parameter can be one of the following values:
- * @arg CRS_IT_SYNCOK:
- * @arg CRS_IT_SYNCWARN:
- * @arg CRS_IT_ERR:
- * @arg CRS_IT_ESYNC:
- * @arg CRS_IT_TRIMOVF:
- * @arg CRS_IT_SYNCERR:
- * @arg CRS_IT_SYNCMISS:
- * @retval None
- */
-void CRS_ClearITPendingBit(uint32_t CRS_IT)
-{
- /* Check the parameters */
- assert_param(IS_CRS_CLEAR_IT(CRS_IT));
-
- if ((CRS_IT & FLAG_MASK)!= 0)
- {
- CRS->ICR |= CRS_ICR_ERRC;
- }
- else
- {
- CRS->ICR |= CRS_IT;
- }
-}
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_dac.c b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_dac.c
deleted file mode 100644
index e6f34adf13f5b95265cb696a817f7fe9661f4dc9..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_dac.c
+++ /dev/null
@@ -1,692 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f0xx_dac.c
- * @author MCD Application Team
- * @version V1.3.0
- * @date 16-January-2014
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Digital-to-Analog Converter (DAC) peripheral
- * applicable only on STM32F051 and STM32F072 devices:
- * + DAC channel configuration: trigger, output buffer, data format
- * + DMA management
- * + Interrupts and flags management
- *
- * @verbatim
- *
- ===============================================================================
- ##### DAC Peripheral features #####
- ===============================================================================
- [..] The device integrates two 12-bit Digital Analog Converters refered as
- DAC channel1 with DAC_OUT1 (PA4) and DAC_OUT2 (PA5) as outputs.
-
- [..] Digital to Analog conversion can be non-triggered using DAC_Trigger_None
- and DAC_OUTx is available once writing to DHRx register using
- DAC_SetChannel1Data() or DAC_SetChannel2Data()
-
- [..] Digital to Analog conversion can be triggered by:
- (#) External event: EXTI Line 9 (any GPIOx_Pin9) using DAC_Trigger_Ext_IT9.
- The used pin (GPIOx_Pin9) must be configured in input mode.
-
- (#) Timers TRGO: TIM2, TIM3,TIM7, TIM6 and TIM15
- (DAC_Trigger_T2_TRGO, DAC_Trigger_T3_TRGO...)
- The timer TRGO event should be selected using TIM_SelectOutputTrigger()
-
- (#) Software using DAC_Trigger_Software
-
- [..] Each DAC integrates an output buffer that can be used to
- reduce the output impedance, and to drive external loads directly
- without having to add an external operational amplifier.
- To enable the output buffer use
- DAC_InitStructure.DAC_OutputBuffer = DAC_OutputBuffer_Enable;
-
- [..] Refer to the device datasheet for more details about output impedance
- value with and without output buffer.
-
- [..] DAC wave generation feature
- Both DAC channels can be used to generate
- 1- Noise wave using DAC_WaveGeneration_Noise
- 2- Triangle wave using DAC_WaveGeneration_Triangle
-
- [..] The DAC data format can be:
- (#) 8-bit right alignment using DAC_Align_8b_R
- (#) 12-bit left alignment using DAC_Align_12b_L
- (#) 12-bit right alignment using DAC_Align_12b_R
-
- [..] The analog output voltage on each DAC channel pin is determined
- by the following equation: DAC_OUTx = VREF+ * DOR / 4095
- with DOR is the Data Output Register
- VEF+ is the input voltage reference (refer to the device datasheet)
- e.g. To set DAC_OUT1 to 0.7V, use
- DAC_SetChannel1Data(DAC_Align_12b_R, 868);
- Assuming that VREF+ = 3.3, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V
-
- [..] A DMA1 request can be generated when an external trigger (but not
- a software trigger) occurs if DMA1 requests are enabled using
- DAC_DMACmd()
- DMA1 requests are mapped as following:
- (+) DAC channel1 is mapped on DMA1 channel3 which must be already
- configured
- (+) DAC channel2 is mapped on DMA1 channel4 which must be already
- configured
-
- ##### How to use this driver #####
- ===============================================================================
- [..]
- (+) Enable DAC APB1 clock to get write access to DAC registers
- using RCC_APB1PeriphClockCmd(RCC_APB1Periph_DAC, ENABLE)
-
- (+) Configure DAC_OUTx (DAC_OUT1: PA4, DAC_OUT2: PA5) in analog mode
- using GPIO_Init() function
-
- (+) Configure the DAC channel using DAC_Init()
-
- (+) Enable the DAC channel using DAC_Cmd()
-
- @endverbatim
- *
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx_dac.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup DAC
- * @brief DAC driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* CR register Mask */
-#define CR_CLEAR_MASK ((uint32_t)0x00000FFE) /* check the value of the mask */
-
-/* DAC Dual Channels SWTRIG masks */
-#define DUAL_SWTRIG_SET ((uint32_t)0x00000003) /*!< Only applicable for STM32F072 devices */
-#define DUAL_SWTRIG_RESET ((uint32_t)0xFFFFFFFC) /*!< Only applicable for STM32F072 devices */
-
-/* DHR registers offsets */
-#define DHR12R1_OFFSET ((uint32_t)0x00000008)
-#define DHR12R2_OFFSET ((uint32_t)0x00000014) /*!< Only applicable for STM32F072 devices */
-#define DHR12RD_OFFSET ((uint32_t)0x00000020) /*!< Only applicable for STM32F072 devices */
-
-/* DOR register offset */
-#define DOR_OFFSET ((uint32_t)0x0000002C)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup DAC_Private_Functions
- * @{
- */
-
-/** @defgroup DAC_Group1 DAC channels configuration
- * @brief DAC channels configuration: trigger, output buffer, data format
- *
-@verbatim
- ===============================================================================
- ##### DAC channels configuration: trigger, output buffer, data format #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitializes the DAC peripheral registers to their default reset values.
- * @param None
- * @retval None
- */
-void DAC_DeInit(void)
-{
- /* Enable DAC reset state */
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, ENABLE);
- /* Release DAC from reset state */
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, DISABLE);
-}
-
-/**
- * @brief Initializes the DAC peripheral according to the specified parameters
- * in the DAC_InitStruct.
- * @param DAC_Channel: the selected DAC channel.
- * This parameter can be:
- * @arg DAC_Channel_1: DAC Channel1 selected
- * @arg DAC_Channel_2: DAC Channel2 selected, applicable only for STM32F072 devices
- * @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure that contains
- * the configuration information for the specified DAC channel.
- * @retval None
- */
-void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct)
-{
- uint32_t tmpreg1 = 0, tmpreg2 = 0;
-
- /* Check the DAC parameters */
- assert_param(IS_DAC_TRIGGER(DAC_InitStruct->DAC_Trigger));
- assert_param(IS_DAC_GENERATE_WAVE(DAC_InitStruct->DAC_WaveGeneration));
- assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude));
- assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_InitStruct->DAC_OutputBuffer));
-
-/*---------------------------- DAC CR Configuration --------------------------*/
- /* Get the DAC CR value */
- tmpreg1 = DAC->CR;
- /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
- tmpreg1 &= ~(CR_CLEAR_MASK << DAC_Channel);
- /* Configure for the selected DAC channel: buffer output, trigger,
- wave generation, mask/amplitude for wave generation */
- /* Set TSELx and TENx bits according to DAC_Trigger value */
- /* Set WAVEx bits according to DAC_WaveGeneration value */
- /* Set MAMPx bits according to DAC_LFSRUnmask_TriangleAmplitude value */
- /* Set BOFFx bit according to DAC_OutputBuffer value */
- tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration |
- DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | \
- DAC_InitStruct->DAC_OutputBuffer);
- /* Calculate CR register value depending on DAC_Channel */
- tmpreg1 |= tmpreg2 << DAC_Channel;
- /* Write to DAC CR */
- DAC->CR = tmpreg1;
-}
-
-/**
- * @brief Fills each DAC_InitStruct member with its default value.
- * @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure which will
- * be initialized.
- * @retval None
- */
-void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct)
-{
-/*--------------- Reset DAC init structure parameters values -----------------*/
- /* Initialize the DAC_Trigger member */
- DAC_InitStruct->DAC_Trigger = DAC_Trigger_None;
-
- /* Initialize the DAC_WaveGeneration member */
- DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None;
-
- /* Initialize the DAC_LFSRUnmask_TriangleAmplitude member */
- DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0;
-
- /* Initialize the DAC_OutputBuffer member */
- DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable;
-}
-
-/**
- * @brief Enables or disables the specified DAC channel.
- * @param DAC_Channel: The selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_Channel_1: DAC Channel1 selected
- * @arg DAC_Channel_2: DAC Channel2 selected, applicable only for STM32F072 devices
- * @param NewState: new state of the DAC channel.
- * This parameter can be: ENABLE or DISABLE.
- * @note When the DAC channel is enabled the trigger source can no more be modified.
- * @retval None
- */
-void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_DAC_CHANNEL(DAC_Channel));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected DAC channel */
- DAC->CR |= (DAC_CR_EN1 << DAC_Channel);
- }
- else
- {
- /* Disable the selected DAC channel */
- DAC->CR &= (~(DAC_CR_EN1 << DAC_Channel));
- }
-}
-
-/**
- * @brief Enables or disables the selected DAC channel software trigger.
- * @param DAC_Channel: The selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_Channel_1: DAC Channel1 selected
- * @arg DAC_Channel_2: DAC Channel2 selected, applicable only for STM32F072 devices
- * @param NewState: new state of the selected DAC channel software trigger.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_DAC_CHANNEL(DAC_Channel));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable software trigger for the selected DAC channel */
- DAC->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4);
- }
- else
- {
- /* Disable software trigger for the selected DAC channel */
- DAC->SWTRIGR &= ~((uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4));
- }
-}
-
-/**
- * @brief Enables or disables simultaneously the two DAC channels software triggers.
- * This function is applicable only for STM32F072 devices.
- * @param NewState: new state of the DAC channels software triggers.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void DAC_DualSoftwareTriggerCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable software trigger for both DAC channels */
- DAC->SWTRIGR |= DUAL_SWTRIG_SET;
- }
- else
- {
- /* Disable software trigger for both DAC channels */
- DAC->SWTRIGR &= DUAL_SWTRIG_RESET;
- }
-}
-
-/**
- * @brief Enables or disables the selected DAC channel wave generation.
- * This function is applicable only for STM32F072 devices.
- * @param DAC_Channel: The selected DAC channel.
- * This parameter can be:
- * @arg DAC_Channel_1: DAC Channel1 selected
- * @arg DAC_Channel_2: DAC Channel2 selected
- * @param DAC_Wave: specifies the wave type to enable or disable.
- * This parameter can be:
- * @arg DAC_Wave_Noise: noise wave generation
- * @arg DAC_Wave_Triangle: triangle wave generation
- * @param NewState: new state of the selected DAC channel wave generation.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_DAC_CHANNEL(DAC_Channel));
- assert_param(IS_DAC_WAVE(DAC_Wave));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected wave generation for the selected DAC channel */
- DAC->CR |= DAC_Wave << DAC_Channel;
- }
- else
- {
- /* Disable the selected wave generation for the selected DAC channel */
- DAC->CR &= ~(DAC_Wave << DAC_Channel);
- }
-}
-
-/**
- * @brief Set the specified data holding register value for DAC channel1.
- * @param DAC_Align: Specifies the data alignment for DAC channel1.
- * This parameter can be one of the following values:
- * @arg DAC_Align_8b_R: 8bit right data alignment selected
- * @arg DAC_Align_12b_L: 12bit left data alignment selected
- * @arg DAC_Align_12b_R: 12bit right data alignment selected
- * @param Data: Data to be loaded in the selected data holding register.
- * @retval None
- */
-void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data)
-{
- __IO uint32_t tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_DAC_ALIGN(DAC_Align));
- assert_param(IS_DAC_DATA(Data));
-
- tmp = (uint32_t)DAC_BASE;
- tmp += DHR12R1_OFFSET + DAC_Align;
-
- /* Set the DAC channel1 selected data holding register */
- *(__IO uint32_t *) tmp = Data;
-}
-
-/**
- * @brief Sets the specified data holding register value for DAC channel2.
- * This function is applicable only for STM32F072 devices.
- * @param DAC_Align: Specifies the data alignment for DAC channel2.
- * This parameter can be:
- * @arg DAC_Align_8b_R: 8bit right data alignment selected
- * @arg DAC_Align_12b_L: 12bit left data alignment selected
- * @arg DAC_Align_12b_R: 12bit right data alignment selected
- * @param Data: Data to be loaded in the selected data holding register.
- * @retval None
- */
-void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data)
-{
- __IO uint32_t tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_DAC_ALIGN(DAC_Align));
- assert_param(IS_DAC_DATA(Data));
-
- tmp = (uint32_t)DAC_BASE;
- tmp += DHR12R2_OFFSET + DAC_Align;
-
- /* Set the DAC channel2 selected data holding register */
- *(__IO uint32_t *)tmp = Data;
-}
-
-/**
- * @brief Sets the specified data holding register value for dual channel DAC.
- * This function is applicable only for STM32F072 devices.
- * @param DAC_Align: Specifies the data alignment for dual channel DAC.
- * This parameter can be:
- * @arg DAC_Align_8b_R: 8bit right data alignment selected
- * @arg DAC_Align_12b_L: 12bit left data alignment selected
- * @arg DAC_Align_12b_R: 12bit right data alignment selected
- * @param Data2: Data for DAC Channel2 to be loaded in the selected data holding register.
- * @param Data1: Data for DAC Channel1 to be loaded in the selected data holding register.
- * @note In dual mode, a unique register access is required to write in both
- * DAC channels at the same time.
- * @retval None
- */
-void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1)
-{
- uint32_t data = 0, tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_DAC_ALIGN(DAC_Align));
- assert_param(IS_DAC_DATA(Data1));
- assert_param(IS_DAC_DATA(Data2));
-
- /* Calculate and set dual DAC data holding register value */
- if (DAC_Align == DAC_Align_8b_R)
- {
- data = ((uint32_t)Data2 << 8) | Data1;
- }
- else
- {
- data = ((uint32_t)Data2 << 16) | Data1;
- }
-
- tmp = (uint32_t)DAC_BASE;
- tmp += DHR12RD_OFFSET + DAC_Align;
-
- /* Set the dual DAC selected data holding register */
- *(__IO uint32_t *)tmp = data;
-}
-
-/**
- * @brief Returns the last data output value of the selected DAC channel.
- * @param DAC_Channel: The selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_Channel_1: DAC Channel1 selected
- * @arg DAC_Channel_2: DAC Channel2 selected, applicable only for STM32F072 devices
- * @retval The selected DAC channel data output value.
- */
-uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel)
-{
- __IO uint32_t tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_DAC_CHANNEL(DAC_Channel));
-
- tmp = (uint32_t) DAC_BASE ;
- tmp += DOR_OFFSET + ((uint32_t)DAC_Channel >> 2);
-
- /* Returns the DAC channel data output register value */
- return (uint16_t) (*(__IO uint32_t*) tmp);
-}
-
-/**
- * @}
- */
-
-/** @defgroup DAC_Group2 DMA management functions
- * @brief DMA management functions
- *
-@verbatim
- ===============================================================================
- ##### DMA management functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the specified DAC channel DMA request.
- * When enabled DMA1 is generated when an external trigger (EXTI Line9,
- * TIM2, TIM3, TIM6 or TIM15 but not a software trigger) occurs
- * @param DAC_Channel: the selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_Channel_1: DAC Channel1 selected
- * @arg DAC_Channel_2: DAC Channel2 selected, applicable only for STM32F072 devices
- * @param NewState: new state of the selected DAC channel DMA request.
- * This parameter can be: ENABLE or DISABLE.
- * @note The DAC channel1 is mapped on DMA1 channel3 which must be already configured.
- * @note The DAC channel2 is mapped on DMA1 channel4 which must be already configured.
- * @retval None
- */
-void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_DAC_CHANNEL(DAC_Channel));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected DAC channel DMA request */
- DAC->CR |= (DAC_CR_DMAEN1 << DAC_Channel);
- }
- else
- {
- /* Disable the selected DAC channel DMA request */
- DAC->CR &= (~(DAC_CR_DMAEN1 << DAC_Channel));
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup DAC_Group3 Interrupts and flags management functions
- * @brief Interrupts and flags management functions
- *
-@verbatim
- ===============================================================================
- ##### Interrupts and flags management functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the specified DAC interrupts.
- * @param DAC_Channel: The selected DAC channel.
- * This parameter can be:
- * @arg DAC_Channel_1: DAC Channel1 selected
- * @arg DAC_Channel_2: DAC Channel2 selected, applicable only for STM32F072 devices
- * @param DAC_IT: specifies the DAC interrupt sources to be enabled or disabled.
- * This parameter can be the following values:
- * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
- * @note The DMA underrun occurs when a second external trigger arrives before the
- * acknowledgement for the first external trigger is received (first request).
- * @param NewState: new state of the specified DAC interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_DAC_CHANNEL(DAC_Channel));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- assert_param(IS_DAC_IT(DAC_IT));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected DAC interrupts */
- DAC->CR |= (DAC_IT << DAC_Channel);
- }
- else
- {
- /* Disable the selected DAC interrupts */
- DAC->CR &= (~(uint32_t)(DAC_IT << DAC_Channel));
- }
-}
-
-/**
- * @brief Checks whether the specified DAC flag is set or not.
- * @param DAC_Channel: The selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_Channel_1: DAC Channel1 selected
- * @arg DAC_Channel_2: DAC Channel2 selected, applicable only for STM32F072 devices
- * @param DAC_FLAG: specifies the flag to check.
- * This parameter can be only of the following value:
- * @arg DAC_FLAG_DMAUDR: DMA underrun flag
- * @note The DMA underrun occurs when a second external trigger arrives before the
- * acknowledgement for the first external trigger is received (first request).
- * @retval The new state of DAC_FLAG (SET or RESET).
- */
-FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG)
-{
- FlagStatus bitstatus = RESET;
- /* Check the parameters */
- assert_param(IS_DAC_CHANNEL(DAC_Channel));
- assert_param(IS_DAC_FLAG(DAC_FLAG));
-
- /* Check the status of the specified DAC flag */
- if ((DAC->SR & (DAC_FLAG << DAC_Channel)) != (uint8_t)RESET)
- {
- /* DAC_FLAG is set */
- bitstatus = SET;
- }
- else
- {
- /* DAC_FLAG is reset */
- bitstatus = RESET;
- }
- /* Return the DAC_FLAG status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the DAC channel's pending flags.
- * @param DAC_Channel: The selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_Channel_1: DAC Channel1 selected
- * @arg DAC_Channel_2: DAC Channel2 selected, applicable only for STM32F072 devices
- * @param DAC_FLAG: specifies the flag to clear.
- * This parameter can be of the following value:
- * @arg DAC_FLAG_DMAUDR: DMA underrun flag
- * @retval None
- */
-void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_DAC_CHANNEL(DAC_Channel));
- assert_param(IS_DAC_FLAG(DAC_FLAG));
-
- /* Clear the selected DAC flags */
- DAC->SR = (DAC_FLAG << DAC_Channel);
-}
-
-/**
- * @brief Checks whether the specified DAC interrupt has occurred or not.
- * @param DAC_Channel: The selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_Channel_1: DAC Channel1 selected
- * @arg DAC_Channel_2: DAC Channel2 selected, applicable only for STM32F072 devices
- * @param DAC_IT: specifies the DAC interrupt source to check.
- * This parameter can be the following values:
- * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
- * @note The DMA underrun occurs when a second external trigger arrives before the
- * acknowledgement for the first external trigger is received (first request).
- * @retval The new state of DAC_IT (SET or RESET).
- */
-ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT)
-{
- ITStatus bitstatus = RESET;
- uint32_t enablestatus = 0;
-
- /* Check the parameters */
- assert_param(IS_DAC_CHANNEL(DAC_Channel));
- assert_param(IS_DAC_IT(DAC_IT));
-
- /* Get the DAC_IT enable bit status */
- enablestatus = (DAC->CR & (DAC_IT << DAC_Channel)) ;
-
- /* Check the status of the specified DAC interrupt */
- if (((DAC->SR & (DAC_IT << DAC_Channel)) != (uint32_t)RESET) && enablestatus)
- {
- /* DAC_IT is set */
- bitstatus = SET;
- }
- else
- {
- /* DAC_IT is reset */
- bitstatus = RESET;
- }
- /* Return the DAC_IT status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the DAC channel's interrupt pending bits.
- * @param DAC_Channel: The selected DAC channel.
- * This parameter can be one of the following values:
- * @arg DAC_Channel_1: DAC Channel1 selected
- * @arg DAC_Channel_2: DAC Channel2 selected, applicable only for STM32F072 devices
- * @param DAC_IT: specifies the DAC interrupt pending bit to clear.
- * This parameter can be the following values:
- * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
- * @retval None
- */
-void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT)
-{
- /* Check the parameters */
- assert_param(IS_DAC_CHANNEL(DAC_Channel));
- assert_param(IS_DAC_IT(DAC_IT));
-
- /* Clear the selected DAC interrupt pending bits */
- DAC->SR = (DAC_IT << DAC_Channel);
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_dbgmcu.c b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_dbgmcu.c
deleted file mode 100644
index 39657339968ceef87e4a61aa05f12867df89c164..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_dbgmcu.c
+++ /dev/null
@@ -1,218 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f0xx_dbgmcu.c
- * @author MCD Application Team
- * @version V1.3.0
- * @date 16-January-2014
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Debug MCU (DBGMCU) peripheral:
- * + Device and Revision ID management
- * + Peripherals Configuration
- * @verbatim
- * @endverbatim
- *
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx_dbgmcu.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup DBGMCU
- * @brief DBGMCU driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup DBGMCU_Private_Functions
- * @{
- */
-
-
-/** @defgroup DBGMCU_Group1 Device and Revision ID management functions
- * @brief Device and Revision ID management functions
- *
-@verbatim
- ==============================================================================
- ##### Device and Revision ID management functions #####
- ==============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Returns the device revision identifier.
- * @param None
- * @retval Device revision identifier
- */
-uint32_t DBGMCU_GetREVID(void)
-{
- return(DBGMCU->IDCODE >> 16);
-}
-
-/**
- * @brief Returns the device identifier.
- * @param None
- * @retval Device identifier
- */
-uint32_t DBGMCU_GetDEVID(void)
-{
- return(DBGMCU->IDCODE & IDCODE_DEVID_MASK);
-}
-
-/**
- * @}
- */
-
-/** @defgroup DBGMCU_Group2 Peripherals Configuration functions
- * @brief Peripherals Configuration
- *
-@verbatim
- ==============================================================================
- ##### Peripherals Configuration functions #####
- ==============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures low power mode behavior when the MCU is in Debug mode.
- * @param DBGMCU_Periph: specifies the low power mode.
- * This parameter can be any combination of the following values:
- * @arg DBGMCU_STOP: Keep debugger connection during STOP mode
- * @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode
- * @param NewState: new state of the specified low power mode in Debug mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- DBGMCU->CR |= DBGMCU_Periph;
- }
- else
- {
- DBGMCU->CR &= ~DBGMCU_Periph;
- }
-}
-
-
-/**
- * @brief Configures APB1 peripheral behavior when the MCU is in Debug mode.
- * @param DBGMCU_Periph: specifies the APB1 peripheral.
- * This parameter can be any combination of the following values:
- * @arg DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted,
- * not applicable for STM32F030 devices
- * @arg DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted
- * @arg DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted
- * @arg DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted,
- * applicable only for STM32F072 devices
- * @arg DBGMCU_TIM14_STOP: TIM14 counter stopped when Core is halted
- * @arg DBGMCU_RTC_STOP: RTC Calendar and Wakeup counter stopped
- * when Core is halted.
- * @arg DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted
- * @arg DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted
- * @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped
- * when Core is halted
- * @arg DBGMCU_CAN1_STOP: Debug CAN1 stopped when Core is halted,
- * applicable only for STM32F042 and STM32F072 devices
- * @param NewState: new state of the specified APB1 peripheral in Debug mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_DBGMCU_APB1PERIPH(DBGMCU_Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- DBGMCU->APB1FZ |= DBGMCU_Periph;
- }
- else
- {
- DBGMCU->APB1FZ &= ~DBGMCU_Periph;
- }
-}
-
-/**
- * @brief Configures APB2 peripheral behavior when the MCU is in Debug mode.
- * @param DBGMCU_Periph: specifies the APB2 peripheral.
- * This parameter can be any combination of the following values:
- * @arg DBGMCU_TIM1_STOP: TIM1 counter stopped when Core is halted
- * @arg DBGMCU_TIM15_STOP: TIM15 counter stopped when Core is halted
- * @arg DBGMCU_TIM16_STOP: TIM16 counter stopped when Core is halted
- * @arg DBGMCU_TIM17_STOP: TIM17 counter stopped when Core is halted
- * @param NewState: new state of the specified APB2 peripheral in Debug mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_DBGMCU_APB2PERIPH(DBGMCU_Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- DBGMCU->APB2FZ |= DBGMCU_Periph;
- }
- else
- {
- DBGMCU->APB2FZ &= ~DBGMCU_Periph;
- }
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_dma.c b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_dma.c
deleted file mode 100644
index 73492c5417953417553a9ed8fcc3f008f03ad756..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_dma.c
+++ /dev/null
@@ -1,705 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f0xx_dma.c
- * @author MCD Application Team
- * @version V1.3.0
- * @date 16-January-2014
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Direct Memory Access controller (DMA):
- * + Initialization and Configuration
- * + Data Counter
- * + Interrupts and flags management
- *
- * @verbatim
- ==============================================================================
- ##### How to use this driver #####
- ==============================================================================
- [..]
- (#) Enable The DMA controller clock using
- RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE) function for DMA1.
- (#) Enable and configure the peripheral to be connected to the DMA channel
- (except for internal SRAM / FLASH memories: no initialization is necessary).
- (#) For a given Channel, program the Source and Destination addresses,
- the transfer Direction, the Buffer Size, the Peripheral and Memory
- Incrementation mode and Data Size, the Circular or Normal mode,
- the channel transfer Priority and the Memory-to-Memory transfer
- mode (if needed) using the DMA_Init() function.
- (#) Enable the NVIC and the corresponding interrupt(s) using the function
- DMA_ITConfig() if you need to use DMA interrupts.
- (#) Enable the DMA channel using the DMA_Cmd() function.
- (#) Activate the needed channel Request using PPP_DMACmd() function for
- any PPP peripheral except internal SRAM and FLASH (ie. SPI, USART ...)
- The function allowing this operation is provided in each PPP peripheral
- driver (ie. SPI_DMACmd for SPI peripheral).
- (#) Optionally, you can configure the number of data to be transferred
- when the channel is disabled (ie. after each Transfer Complete event
- or when a Transfer Error occurs) using the function DMA_SetCurrDataCounter().
- And you can get the number of remaining data to be transferred using
- the function DMA_GetCurrDataCounter() at run time (when the DMA channel is
- enabled and running).
- (#) To control DMA events you can use one of the following two methods:
- (##) Check on DMA channel flags using the function DMA_GetFlagStatus().
- (##) Use DMA interrupts through the function DMA_ITConfig() at initialization
- phase and DMA_GetITStatus() function into interrupt routines in
- communication phase.
- After checking on a flag you should clear it using DMA_ClearFlag()
- function. And after checking on an interrupt event you should
- clear it using DMA_ClearITPendingBit() function.
- @endverbatim
- *
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx_dma.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup DMA
- * @brief DMA driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-#define CCR_CLEAR_MASK ((uint32_t)0xFFFF800F) /* DMA Channel config registers Masks */
-
-/* DMA1 Channelx interrupt pending bit masks */
-#define DMA1_CHANNEL1_IT_MASK ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))
-#define DMA1_CHANNEL2_IT_MASK ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2))
-#define DMA1_CHANNEL3_IT_MASK ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3))
-#define DMA1_CHANNEL4_IT_MASK ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4))
-#define DMA1_CHANNEL5_IT_MASK ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5))
-#define DMA1_CHANNEL6_IT_MASK ((uint32_t)(DMA_ISR_GIF6 | DMA_ISR_TCIF6 | DMA_ISR_HTIF6 | DMA_ISR_TEIF6)) /*!< Only applicable for STM32F072 devices */
-#define DMA1_CHANNEL7_IT_MASK ((uint32_t)(DMA_ISR_GIF7 | DMA_ISR_TCIF7 | DMA_ISR_HTIF7 | DMA_ISR_TEIF7)) /*!< Only applicable for STM32F072 devices */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup DMA_Private_Functions
- * @{
- */
-
-/** @defgroup DMA_Group1 Initialization and Configuration functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and Configuration functions #####
- ===============================================================================
- [..] This subsection provides functions allowing to initialize the DMA channel
- source and destination addresses, incrementation and data sizes, transfer
- direction, buffer size, circular/normal mode selection, memory-to-memory
- mode selection and channel priority value.
- [..] The DMA_Init() function follows the DMA configuration procedures as described
- in reference manual (RM0091).
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitializes the DMAy Channelx registers to their default reset
- * values.
- * @param DMAy_Channelx: where y can be 1 to select the DMA and
- * x can be 1 to 7 for DMA1 to select the DMA Channel.
- * @note Channel 6 and 7 are available only for STM32F072 devices.
- * @retval None
- */
-void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx)
-{
- /* Check the parameters */
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
-
- /* Disable the selected DMAy Channelx */
- DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR_EN);
-
- /* Reset DMAy Channelx control register */
- DMAy_Channelx->CCR = 0;
-
- /* Reset DMAy Channelx remaining bytes register */
- DMAy_Channelx->CNDTR = 0;
-
- /* Reset DMAy Channelx peripheral address register */
- DMAy_Channelx->CPAR = 0;
-
- /* Reset DMAy Channelx memory address register */
- DMAy_Channelx->CMAR = 0;
-
- if (DMAy_Channelx == DMA1_Channel1)
- {
- /* Reset interrupt pending bits for DMA1 Channel1 */
- DMA1->IFCR |= DMA1_CHANNEL1_IT_MASK;
- }
- else if (DMAy_Channelx == DMA1_Channel2)
- {
- /* Reset interrupt pending bits for DMA1 Channel2 */
- DMA1->IFCR |= DMA1_CHANNEL2_IT_MASK;
- }
- else if (DMAy_Channelx == DMA1_Channel3)
- {
- /* Reset interrupt pending bits for DMA1 Channel3 */
- DMA1->IFCR |= DMA1_CHANNEL3_IT_MASK;
- }
- else if (DMAy_Channelx == DMA1_Channel4)
- {
- /* Reset interrupt pending bits for DMA1 Channel4 */
- DMA1->IFCR |= DMA1_CHANNEL4_IT_MASK;
- }
- else if (DMAy_Channelx == DMA1_Channel5)
- {
- /* Reset interrupt pending bits for DMA1 Channel5 */
- DMA1->IFCR |= DMA1_CHANNEL5_IT_MASK;
- }
- else if (DMAy_Channelx == DMA1_Channel6)
- {
- /* Reset interrupt pending bits for DMA1 Channel6 */
- DMA1->IFCR |= DMA1_CHANNEL6_IT_MASK;
- }
- else
- {
- if (DMAy_Channelx == DMA1_Channel7)
- {
- /* Reset interrupt pending bits for DMA1 Channel7 */
- DMA1->IFCR |= DMA1_CHANNEL7_IT_MASK;
- }
- }
-}
-
-/**
- * @brief Initializes the DMAy Channelx according to the specified parameters
- * in the DMA_InitStruct.
- * @param DMAy_Channelx: where y can be 1 to select the DMA and x can be 1 to 7
- * for DMA1 to select the DMA Channel.
- * @note Channel 6 and 7 are available only for STM32F072 devices.
- * @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure that contains
- * the configuration information for the specified DMA Channel.
- * @retval None
- */
-void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
- assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_DIR));
- assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize));
- assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc));
- assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc));
- assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize));
- assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize));
- assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode));
- assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority));
- assert_param(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M));
-
-/*--------------------------- DMAy Channelx CCR Configuration ----------------*/
- /* Get the DMAy_Channelx CCR value */
- tmpreg = DMAy_Channelx->CCR;
-
- /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */
- tmpreg &= CCR_CLEAR_MASK;
-
- /* Configure DMAy Channelx: data transfer, data size, priority level and mode */
- /* Set DIR bit according to DMA_DIR value */
- /* Set CIRC bit according to DMA_Mode value */
- /* Set PINC bit according to DMA_PeripheralInc value */
- /* Set MINC bit according to DMA_MemoryInc value */
- /* Set PSIZE bits according to DMA_PeripheralDataSize value */
- /* Set MSIZE bits according to DMA_MemoryDataSize value */
- /* Set PL bits according to DMA_Priority value */
- /* Set the MEM2MEM bit according to DMA_M2M value */
- tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode |
- DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |
- DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |
- DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M;
-
- /* Write to DMAy Channelx CCR */
- DMAy_Channelx->CCR = tmpreg;
-
-/*--------------------------- DMAy Channelx CNDTR Configuration --------------*/
- /* Write to DMAy Channelx CNDTR */
- DMAy_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize;
-
-/*--------------------------- DMAy Channelx CPAR Configuration ---------------*/
- /* Write to DMAy Channelx CPAR */
- DMAy_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr;
-
-/*--------------------------- DMAy Channelx CMAR Configuration ---------------*/
- /* Write to DMAy Channelx CMAR */
- DMAy_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr;
-}
-
-/**
- * @brief Fills each DMA_InitStruct member with its default value.
- * @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure which will
- * be initialized.
- * @retval None
- */
-void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct)
-{
-/*-------------- Reset DMA init structure parameters values ------------------*/
- /* Initialize the DMA_PeripheralBaseAddr member */
- DMA_InitStruct->DMA_PeripheralBaseAddr = 0;
- /* Initialize the DMA_MemoryBaseAddr member */
- DMA_InitStruct->DMA_MemoryBaseAddr = 0;
- /* Initialize the DMA_DIR member */
- DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC;
- /* Initialize the DMA_BufferSize member */
- DMA_InitStruct->DMA_BufferSize = 0;
- /* Initialize the DMA_PeripheralInc member */
- DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable;
- /* Initialize the DMA_MemoryInc member */
- DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable;
- /* Initialize the DMA_PeripheralDataSize member */
- DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
- /* Initialize the DMA_MemoryDataSize member */
- DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
- /* Initialize the DMA_Mode member */
- DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;
- /* Initialize the DMA_Priority member */
- DMA_InitStruct->DMA_Priority = DMA_Priority_Low;
- /* Initialize the DMA_M2M member */
- DMA_InitStruct->DMA_M2M = DMA_M2M_Disable;
-}
-
-/**
- * @brief Enables or disables the specified DMAy Channelx.
- * @param DMAy_Channelx: where y can be 1 to select the DMA and
- * x can be 1 to 7 for DMA1 to select the DMA Channel.
- * @note Channel 6 and 7 are available only for STM32F072 devices.
- * @param NewState: new state of the DMAy Channelx.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected DMAy Channelx */
- DMAy_Channelx->CCR |= DMA_CCR_EN;
- }
- else
- {
- /* Disable the selected DMAy Channelx */
- DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR_EN);
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup DMA_Group2 Data Counter functions
- * @brief Data Counter functions
- *
-@verbatim
- ===============================================================================
- ##### Data Counter functions #####
- ===============================================================================
- [..] This subsection provides function allowing to configure and read the buffer
- size (number of data to be transferred).The DMA data counter can be written
- only when the DMA channel is disabled (ie. after transfer complete event).
- [..] The following function can be used to write the Channel data counter value:
- (+) void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t
- DataNumber).
- -@- It is advised to use this function rather than DMA_Init() in situations
- where only the Data buffer needs to be reloaded.
- [..] The DMA data counter can be read to indicate the number of remaining transfers
- for the relative DMA channel. This counter is decremented at the end of each
- data transfer and when the transfer is complete:
- (+) If Normal mode is selected: the counter is set to 0.
- (+) If Circular mode is selected: the counter is reloaded with the initial
- value(configured before enabling the DMA channel).
- [..] The following function can be used to read the Channel data counter value:
- (+) uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx).
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Sets the number of data units in the current DMAy Channelx transfer.
- * @param DMAy_Channelx: where y can be 1 to select the DMA and x can be
- * 1 to 7 for DMA1 to select the DMA Channel.
- * @note Channel 6 and 7 are available only for STM32F072 devices.
- * @param DataNumber: The number of data units in the current DMAy Channelx
- * transfer.
- * @note This function can only be used when the DMAy_Channelx is disabled.
- * @retval None.
- */
-void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber)
-{
- /* Check the parameters */
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
-
-/*--------------------------- DMAy Channelx CNDTR Configuration --------------*/
- /* Write to DMAy Channelx CNDTR */
- DMAy_Channelx->CNDTR = DataNumber;
-}
-
-/**
- * @brief Returns the number of remaining data units in the current
- * DMAy Channelx transfer.
- * @param DMAy_Channelx: where y can be 1 to select the DMA and
- * x can be 1 to 7 for DMA1 to select the DMA Channel.
- * @note Channel 6 and 7 are available only for STM32F072 devices.
- * @retval The number of remaining data units in the current DMAy Channelx
- * transfer.
- */
-uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx)
-{
- /* Check the parameters */
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
- /* Return the number of remaining data units for DMAy Channelx */
- return ((uint16_t)(DMAy_Channelx->CNDTR));
-}
-
-/**
- * @}
- */
-
-/** @defgroup DMA_Group3 Interrupts and flags management functions
- * @brief Interrupts and flags management functions
- *
-@verbatim
- ===============================================================================
- ##### Interrupts and flags management functions #####
- ===============================================================================
- [..] This subsection provides functions allowing to configure the DMA Interrupts
- sources and check or clear the flags or pending bits status.
- The user should identify which mode will be used in his application to manage
- the DMA controller events: Polling mode or Interrupt mode.
- *** Polling Mode ***
- ====================
- [..] Each DMA channel can be managed through 4 event Flags:(y : DMA Controller
- number x : DMA channel number ).
- (#) DMAy_FLAG_TCx : to indicate that a Transfer Complete event occurred.
- (#) DMAy_FLAG_HTx : to indicate that a Half-Transfer Complete event occurred.
- (#) DMAy_FLAG_TEx : to indicate that a Transfer Error occurred.
- (#) DMAy_FLAG_GLx : to indicate that at least one of the events described
- above occurred.
- -@- Clearing DMAy_FLAG_GLx results in clearing all other pending flags of the
- same channel (DMAy_FLAG_TCx, DMAy_FLAG_HTx and DMAy_FLAG_TEx).
- [..]In this Mode it is advised to use the following functions:
- (+) FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG);
- (+) void DMA_ClearFlag(uint32_t DMA_FLAG);
-
- *** Interrupt Mode ***
- ======================
- [..] Each DMA channel can be managed through 4 Interrupts:
- (+) Interrupt Source
- (##) DMA_IT_TC: specifies the interrupt source for the Transfer Complete
- event.
- (##) DMA_IT_HT : specifies the interrupt source for the Half-transfer Complete
- event.
- (##) DMA_IT_TE : specifies the interrupt source for the transfer errors event.
- (##) DMA_IT_GL : to indicate that at least one of the interrupts described
- above occurred.
- -@@- Clearing DMA_IT_GL interrupt results in clearing all other interrupts of
- the same channel (DMA_IT_TCx, DMA_IT_HT and DMA_IT_TE).
- [..]In this Mode it is advised to use the following functions:
- (+) void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT,
- FunctionalState NewState);
- (+) ITStatus DMA_GetITStatus(uint32_t DMA_IT);
- (+) void DMA_ClearITPendingBit(uint32_t DMA_IT);
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the specified DMAy Channelx interrupts.
- * @param DMAy_Channelx: where y can be 1 to select the DMA and
- * x can be 1 to 7 for DMA1 to select the DMA Channel.
- * @note Channel 6 and 7 are available only for STM32F072 devices.
- * @param DMA_IT: specifies the DMA interrupts sources to be enabled
- * or disabled.
- * This parameter can be any combination of the following values:
- * @arg DMA_IT_TC: Transfer complete interrupt mask
- * @arg DMA_IT_HT: Half transfer interrupt mask
- * @arg DMA_IT_TE: Transfer error interrupt mask
- * @param NewState: new state of the specified DMA interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
- assert_param(IS_DMA_CONFIG_IT(DMA_IT));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected DMA interrupts */
- DMAy_Channelx->CCR |= DMA_IT;
- }
- else
- {
- /* Disable the selected DMA interrupts */
- DMAy_Channelx->CCR &= ~DMA_IT;
- }
-}
-
-/**
- * @brief Checks whether the specified DMAy Channelx flag is set or not.
- * @param DMA_FLAG: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.
- * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
- * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
- * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
- * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.
- * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
- * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
- * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
- * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.
- * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
- * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
- * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
- * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.
- * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
- * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
- * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
- * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.
- * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
- * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
- * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
- * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag, applicable only for STM32F072 devices.
- * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag, applicable only for STM32F072 devices.
- * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag, applicable only for STM32F072 devices.
- * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag, applicable only for STM32F072 devices.
- * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag, applicable only for STM32F072 devices.
- * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag, applicable only for STM32F072 devices.
- * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag, applicable only for STM32F072 devices.
- * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag, applicable only for STM32F072 devices.
- * @note The Global flag (DMAy_FLAG_GLx) is set whenever any of the other flags
- * relative to the same channel is set (Transfer Complete, Half-transfer
- * Complete or Transfer Error flags: DMAy_FLAG_TCx, DMAy_FLAG_HTx or
- * DMAy_FLAG_TEx).
- *
- * @retval The new state of DMA_FLAG (SET or RESET).
- */
-FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG)
-{
- FlagStatus bitstatus = RESET;
-
- /* Check the parameters */
- assert_param(IS_DMA_GET_FLAG(DMA_FLAG));
-
- /* Check the status of the specified DMA flag */
- if ((DMA1->ISR & DMA_FLAG) != (uint32_t)RESET)
- {
- /* DMA_FLAG is set */
- bitstatus = SET;
- }
- else
- {
- /* DMA_FLAG is reset */
- bitstatus = RESET;
- }
-
- /* Return the DMA_FLAG status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the DMAy Channelx's pending flags.
- * @param DMA_FLAG: specifies the flag to clear.
- * This parameter can be any combination (for the same DMA) of the following values:
- * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.
- * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
- * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
- * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
- * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.
- * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
- * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
- * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
- * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.
- * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
- * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
- * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
- * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.
- * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
- * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
- * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
- * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.
- * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
- * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
- * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
- * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag, applicable only for STM32F072 devices.
- * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag, applicable only for STM32F072 devices.
- * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag, applicable only for STM32F072 devices.
- * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag, applicable only for STM32F072 devices.
- * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag, applicable only for STM32F072 devices.
- * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag, applicable only for STM32F072 devices.
- * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag, applicable only for STM32F072 devices.
- * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag, applicable only for STM32F072 devices.
- *
- * @note Clearing the Global flag (DMAy_FLAG_GLx) results in clearing all other flags
- * relative to the same channel (Transfer Complete, Half-transfer Complete and
- * Transfer Error flags: DMAy_FLAG_TCx, DMAy_FLAG_HTx and DMAy_FLAG_TEx).
- *
- * @retval None
- */
-void DMA_ClearFlag(uint32_t DMA_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_DMA_CLEAR_FLAG(DMA_FLAG));
-
- /* Clear the selected DMA flags */
- DMA1->IFCR = DMA_FLAG;
-}
-
-/**
- * @brief Checks whether the specified DMAy Channelx interrupt has occurred or not.
- * @param DMA_IT: specifies the DMA interrupt source to check.
- * This parameter can be one of the following values:
- * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.
- * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
- * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
- * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
- * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.
- * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
- * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
- * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
- * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.
- * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
- * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
- * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
- * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.
- * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
- * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
- * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
- * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.
- * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
- * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
- * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
- * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt, applicable only for STM32F072 devices.
- * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt, applicable only for STM32F072 devices.
- * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt, applicable only for STM32F072 devices.
- * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt, applicable only for STM32F072 devices.
- * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt, applicable only for STM32F072 devices.
- * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt, applicable only for STM32F072 devices.
- * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt, applicable only for STM32F072 devices.
- * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt, applicable only for STM32F072 devices.
- *
- * @note The Global interrupt (DMAy_FLAG_GLx) is set whenever any of the other
- * interrupts relative to the same channel is set (Transfer Complete,
- * Half-transfer Complete or Transfer Error interrupts: DMAy_IT_TCx,
- * DMAy_IT_HTx or DMAy_IT_TEx).
- *
- * @retval The new state of DMA_IT (SET or RESET).
- */
-ITStatus DMA_GetITStatus(uint32_t DMA_IT)
-{
- ITStatus bitstatus = RESET;
-
- /* Check the parameters */
- assert_param(IS_DMA_GET_IT(DMA_IT));
-
- /* Check the status of the specified DMA interrupt */
- if ((DMA1->ISR & DMA_IT) != (uint32_t)RESET)
- {
- /* DMA_IT is set */
- bitstatus = SET;
- }
- else
- {
- /* DMA_IT is reset */
- bitstatus = RESET;
- }
- /* Return the DMA_IT status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the DMAy Channelx's interrupt pending bits.
- * @param DMA_IT: specifies the DMA interrupt pending bit to clear.
- * This parameter can be any combination (for the same DMA) of the following values:
- * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.
- * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
- * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
- * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
- * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.
- * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
- * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
- * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
- * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.
- * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
- * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
- * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
- * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.
- * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
- * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
- * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
- * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.
- * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
- * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
- * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
- * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt, applicable only for STM32F072 devices.
- * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt, applicable only for STM32F072 devices.
- * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt, applicable only for STM32F072 devices.
- * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt, applicable only for STM32F072 devices.
- * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt, applicable only for STM32F072 devices.
- * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt, applicable only for STM32F072 devices.
- * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt, applicable only for STM32F072 devices.
- * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt, applicable only for STM32F072 devices.
- *
- * @note Clearing the Global interrupt (DMAy_IT_GLx) results in clearing all other
- * interrupts relative to the same channel (Transfer Complete, Half-transfer
- * Complete and Transfer Error interrupts: DMAy_IT_TCx, DMAy_IT_HTx and
- * DMAy_IT_TEx).
- *
- * @retval None
- */
-void DMA_ClearITPendingBit(uint32_t DMA_IT)
-{
- /* Check the parameters */
- assert_param(IS_DMA_CLEAR_IT(DMA_IT));
-
- /* Clear the selected DMA interrupt pending bits */
- DMA1->IFCR = DMA_IT;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_exti.c b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_exti.c
deleted file mode 100644
index 684a7deb9b72f7cb2118b443e98beb865617ef02..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_exti.c
+++ /dev/null
@@ -1,314 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f0xx_exti.c
- * @author MCD Application Team
- * @version V1.3.0
- * @date 16-January-2014
- * @brief This file provides firmware functions to manage the following
- * functionalities of the EXTI peripheral:
- * + Initialization and Configuration
- * + Interrupts and flags management
- *
- * @verbatim
- ==============================================================================
- ##### EXTI features #####
- ==============================================================================
- [..] External interrupt/event lines are mapped as following:
- (#) All available GPIO pins are connected to the 16 external
- interrupt/event lines from EXTI0 to EXTI15.
- (#) EXTI line 16 is connected to the PVD output, not applicable for STM32F030 devices.
- (#) EXTI line 17 is connected to the RTC Alarm event.
- (#) EXTI line 18 is connected to the RTC Alarm event, applicable only for STM32F072 devices.
- (#) EXTI line 19 is connected to the RTC Tamper and TimeStamp events.
- (#) EXTI line 20 is connected to the RTC wakeup event, applicable only for STM32F072 devices.
- (#) EXTI line 21 is connected to the Comparator 1 wakeup event, applicable only for STM32F051 and STM32F072 devices.
- (#) EXTI line 22 is connected to the Comparator 2 wakeup event, applicable only for STM32F051 and STM32F072 devices.
- (#) EXTI line 23 is connected to the I2C1 wakeup event, not applicable for STM32F030 devices.
- (#) EXTI line 25 is connected to the USART1 wakeup event, not applicable for STM32F030 devices.
- (#) EXTI line 26 is connected to the USART2 wakeup event, applicable only for STM32F072 devices.
- (#) EXTI line 27 is connected to the CEC wakeup event, applicable only for STM32F051 and STM32F072 devices.
- (#) EXTI line 31 is connected to the VDD USB monitor event, applicable only for STM32F072 devices.
-
- ##### How to use this driver #####
- ==============================================================================
- [..] In order to use an I/O pin as an external interrupt source, follow
- steps below:
- (#) Configure the I/O in input mode using GPIO_Init()
- (#) Select the input source pin for the EXTI line using
- SYSCFG_EXTILineConfig().
- (#) Select the mode(interrupt, event) and configure the trigger selection
- (Rising, falling or both) using EXTI_Init(). For the internal interrupt,
- the trigger selection is not needed( the active edge is always the rising one).
- (#) Configure NVIC IRQ channel mapped to the EXTI line using NVIC_Init().
- (#) Optionally, you can generate a software interrupt using the function EXTI_GenerateSWInterrupt().
- [..]
- (@) SYSCFG APB clock must be enabled to get write access to SYSCFG_EXTICRx
- registers using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
- @endverbatim
- *
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx_exti.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup EXTI
- * @brief EXTI driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-#define EXTI_LINENONE ((uint32_t)0x00000) /* No interrupt selected */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup EXTI_Private_Functions
- * @{
- */
-
-/** @defgroup EXTI_Group1 Initialization and Configuration functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ==============================================================================
- ##### Initialization and Configuration functions #####
- ==============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitializes the EXTI peripheral registers to their default reset
- * values.
- * @param None
- * @retval None
- */
-void EXTI_DeInit(void)
-{
- EXTI->IMR = 0x0F940000;
- EXTI->EMR = 0x00000000;
- EXTI->RTSR = 0x00000000;
- EXTI->FTSR = 0x00000000;
- EXTI->PR = 0x006BFFFF;
-}
-
-/**
- * @brief Initializes the EXTI peripheral according to the specified
- * parameters in the EXTI_InitStruct.
- * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure that
- * contains the configuration information for the EXTI peripheral.
- * @retval None
- */
-void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct)
-{
- uint32_t tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode));
- assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger));
- assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line));
- assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd));
-
- tmp = (uint32_t)EXTI_BASE;
-
- if (EXTI_InitStruct->EXTI_LineCmd != DISABLE)
- {
- /* Clear EXTI line configuration */
- EXTI->IMR &= ~EXTI_InitStruct->EXTI_Line;
- EXTI->EMR &= ~EXTI_InitStruct->EXTI_Line;
-
- tmp += EXTI_InitStruct->EXTI_Mode;
-
- *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;
-
- /* Clear Rising Falling edge configuration */
- EXTI->RTSR &= ~EXTI_InitStruct->EXTI_Line;
- EXTI->FTSR &= ~EXTI_InitStruct->EXTI_Line;
-
- /* Select the trigger for the selected interrupts */
- if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling)
- {
- /* Rising Falling edge */
- EXTI->RTSR |= EXTI_InitStruct->EXTI_Line;
- EXTI->FTSR |= EXTI_InitStruct->EXTI_Line;
- }
- else
- {
- tmp = (uint32_t)EXTI_BASE;
- tmp += EXTI_InitStruct->EXTI_Trigger;
-
- *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;
- }
- }
- else
- {
- tmp += EXTI_InitStruct->EXTI_Mode;
-
- /* Disable the selected external lines */
- *(__IO uint32_t *) tmp &= ~EXTI_InitStruct->EXTI_Line;
- }
-}
-
-/**
- * @brief Fills each EXTI_InitStruct member with its reset value.
- * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will
- * be initialized.
- * @retval None
- */
-void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct)
-{
- EXTI_InitStruct->EXTI_Line = EXTI_LINENONE;
- EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt;
- EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling;
- EXTI_InitStruct->EXTI_LineCmd = DISABLE;
-}
-
-/**
- * @brief Generates a Software interrupt on selected EXTI line.
- * @param EXTI_Line: specifies the EXTI line on which the software interrupt
- * will be generated.
- * This parameter can be any combination of EXTI_Linex where x can be (0..27).
- * @retval None
- */
-void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line)
-{
- /* Check the parameters */
- assert_param(IS_EXTI_LINE(EXTI_Line));
-
- EXTI->SWIER |= EXTI_Line;
-}
-
-/**
- * @}
- */
-
-/** @defgroup EXTI_Group2 Interrupts and flags management functions
- * @brief Interrupts and flags management functions
- *
-@verbatim
- ==============================================================================
- ##### Interrupts and flags management functions #####
- ==============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Checks whether the specified EXTI line flag is set or not.
- * @param EXTI_Line: specifies the EXTI line flag to check.
- * This parameter can be EXTI_Linex where x can be (0..27).
- * @retval The new state of EXTI_Line (SET or RESET).
- */
-FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line)
-{
- FlagStatus bitstatus = RESET;
- /* Check the parameters */
- assert_param(IS_GET_EXTI_LINE(EXTI_Line));
-
- if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Clears the EXTI's line pending flags.
- * @param EXTI_Line: specifies the EXTI lines flags to clear.
- * This parameter can be any combination of EXTI_Linex where x can be (0..27).
- * @retval None
- */
-void EXTI_ClearFlag(uint32_t EXTI_Line)
-{
- /* Check the parameters */
- assert_param(IS_EXTI_LINE(EXTI_Line));
-
- EXTI->PR = EXTI_Line;
-}
-
-/**
- * @brief Checks whether the specified EXTI line is asserted or not.
- * @param EXTI_Line: specifies the EXTI line to check.
- * This parameter can be EXTI_Linex where x can be (0..27).
- * @retval The new state of EXTI_Line (SET or RESET).
- */
-ITStatus EXTI_GetITStatus(uint32_t EXTI_Line)
-{
- ITStatus bitstatus = RESET;
-
- /* Check the parameters */
- assert_param(IS_GET_EXTI_LINE(EXTI_Line));
-
- if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Clears the EXTI's line pending bits.
- * @param EXTI_Line: specifies the EXTI lines to clear.
- * This parameter can be any combination of EXTI_Linex where x can be (0..27).
- * @retval None
- */
-void EXTI_ClearITPendingBit(uint32_t EXTI_Line)
-{
- /* Check the parameters */
- assert_param(IS_EXTI_LINE(EXTI_Line));
-
- EXTI->PR = EXTI_Line;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_flash.c b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_flash.c
deleted file mode 100644
index e548c4488bc703c9f40207f90df7f4da7009e00b..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_flash.c
+++ /dev/null
@@ -1,1256 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f0xx_flash.c
- * @author MCD Application Team
- * @version V1.3.0
- * @date 16-January-2014
- * @brief This file provides firmware functions to manage the following
- * functionalities of the FLASH peripheral:
- * - FLASH Interface configuration
- * - FLASH Memory Programming
- * - Option Bytes Programming
- * - Interrupts and flags management
- *
- * @verbatim
- ===============================================================================
- ##### How to use this driver #####
- ===============================================================================
- [..] This driver provides functions to configure and program the Flash
- memory of all STM32F0xx devices. These functions are split in 4 groups
- (#) FLASH Interface configuration functions: this group includes the
- management of following features:
- (++) Set the latency
- (++) Enable/Disable the prefetch buffer
-
- (#) FLASH Memory Programming functions: this group includes all needed
- functions to erase and program the main memory:
- (++) Lock and Unlock the Flash interface.
- (++) Erase function: Erase Page, erase all pages.
- (++) Program functions: Half Word and Word write.
-
- (#) FLASH Option Bytes Programming functions: this group includes all
- needed functions to:
- (++) Lock and Unlock the Flash Option bytes.
- (++) Launch the Option Bytes loader
- (++) Erase the Option Bytes
- (++)Set/Reset the write protection
- (++) Set the Read protection Level
- (++) Program the user option Bytes
- (++) Set/Reset the BOOT1 bit
- (++) Enable/Disable the VDDA Analog Monitoring
- (++) Get the user option bytes
- (++) Get the Write protection
- (++) Get the read protection status
-
- (#) FLASH Interrupts and flag management functions: this group includes
- all needed functions to:
- (++) Enable/Disable the flash interrupt sources
- (++) Get flags status
- (++) Clear flags
- (++) Get Flash operation status
- (++) Wait for last flash operation
-
- @endverbatim
-
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx_flash.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup FLASH
- * @brief FLASH driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup FLASH_Private_Functions
- * @{
- */
-
-/** @defgroup FLASH_Group1 FLASH Interface configuration functions
- * @brief FLASH Interface configuration functions
- *
-@verbatim
- ===============================================================================
- ##### FLASH Interface configuration functions #####
- ===============================================================================
-
- [..] FLASH_Interface configuration_Functions, includes the following functions:
- (+) void FLASH_SetLatency(uint32_t FLASH_Latency):
- [..] To correctly read data from Flash memory, the number of wait states (LATENCY)
- must be correctly programmed according to the frequency of the CPU clock (HCLK)
- [..]
- +--------------------------------------------- +
- | Wait states | HCLK clock frequency (MHz) |
- |---------------|------------------------------|
- |0WS(1CPU cycle)| 0 < HCLK <= 24 |
- |---------------|------------------------------|
- |1WS(2CPU cycle)| 24 < HCLK <= 48 |
- +----------------------------------------------+
- [..]
- (+) void FLASH_PrefetchBufferCmd(FunctionalState NewState);
- [..]
- All these functions don't need the unlock sequence.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Sets the code latency value.
- * @param FLASH_Latency: specifies the FLASH Latency value.
- * This parameter can be one of the following values:
- * @arg FLASH_Latency_0: FLASH Zero Latency cycle
- * @arg FLASH_Latency_1: FLASH One Latency cycle
- * @retval None
- */
-void FLASH_SetLatency(uint32_t FLASH_Latency)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_FLASH_LATENCY(FLASH_Latency));
-
- /* Read the ACR register */
- tmpreg = FLASH->ACR;
-
- /* Sets the Latency value */
- tmpreg &= (uint32_t) (~((uint32_t)FLASH_ACR_LATENCY));
- tmpreg |= FLASH_Latency;
-
- /* Write the ACR register */
- FLASH->ACR = tmpreg;
-}
-
-/**
- * @brief Enables or disables the Prefetch Buffer.
- * @param NewState: new state of the FLASH prefetch buffer.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void FLASH_PrefetchBufferCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if(NewState != DISABLE)
- {
- FLASH->ACR |= FLASH_ACR_PRFTBE;
- }
- else
- {
- FLASH->ACR &= (uint32_t)(~((uint32_t)FLASH_ACR_PRFTBE));
- }
-}
-
-/**
- * @brief Checks whether the FLASH Prefetch Buffer status is set or not.
- * @param None
- * @retval FLASH Prefetch Buffer Status (SET or RESET).
- */
-FlagStatus FLASH_GetPrefetchBufferStatus(void)
-{
- FlagStatus bitstatus = RESET;
-
- if ((FLASH->ACR & FLASH_ACR_PRFTBS) != (uint32_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- /* Return the new state of FLASH Prefetch Buffer Status (SET or RESET) */
- return bitstatus;
-}
-
-/**
- * @}
- */
-
-/** @defgroup FLASH_Group2 FLASH Memory Programming functions
- * @brief FLASH Memory Programming functions
- *
-@verbatim
- ===============================================================================
- ##### FLASH Memory Programming functions #####
- ===============================================================================
-
- [..] The FLASH Memory Programming functions, includes the following functions:
- (+) void FLASH_Unlock(void);
- (+) void FLASH_Lock(void);
- (+) FLASH_Status FLASH_ErasePage(uint32_t Page_Address);
- (+) FLASH_Status FLASH_EraseAllPages(void);
- (+) FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data);
- (+) FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data);
-
- [..] Any operation of erase or program should follow these steps:
-
- (#) Call the FLASH_Unlock() function to enable the flash control register and
- program memory access
- (#) Call the desired function to erase page or program data
- (#) Call the FLASH_Lock() to disable the flash program memory access
- (recommended to protect the FLASH memory against possible unwanted operation)
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Unlocks the FLASH control register and program memory access.
- * @param None
- * @retval None
- */
-void FLASH_Unlock(void)
-{
- if((FLASH->CR & FLASH_CR_LOCK) != RESET)
- {
- /* Unlocking the program memory access */
- FLASH->KEYR = FLASH_FKEY1;
- FLASH->KEYR = FLASH_FKEY2;
- }
-}
-
-/**
- * @brief Locks the Program memory access.
- * @param None
- * @retval None
- */
-void FLASH_Lock(void)
-{
- /* Set the LOCK Bit to lock the FLASH control register and program memory access */
- FLASH->CR |= FLASH_CR_LOCK;
-}
-
-/**
- * @brief Erases a specified page in program memory.
- * @note To correctly run this function, the FLASH_Unlock() function must be called before.
- * @note Call the FLASH_Lock() to disable the flash memory access (recommended
- * to protect the FLASH memory against possible unwanted operation)
- * @param Page_Address: The page address in program memory to be erased.
- * @note A Page is erased in the Program memory only if the address to load
- * is the start address of a page (multiple of 1024 bytes).
- * @retval FLASH Status: The returned value can be:
- * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
- */
-FLASH_Status FLASH_ErasePage(uint32_t Page_Address)
-{
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Check the parameters */
- assert_param(IS_FLASH_PROGRAM_ADDRESS(Page_Address));
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-
- if(status == FLASH_COMPLETE)
- {
- /* If the previous operation is completed, proceed to erase the page */
- FLASH->CR |= FLASH_CR_PER;
- FLASH->AR = Page_Address;
- FLASH->CR |= FLASH_CR_STRT;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-
- /* Disable the PER Bit */
- FLASH->CR &= ~FLASH_CR_PER;
- }
-
- /* Return the Erase Status */
- return status;
-}
-
-/**
- * @brief Erases all FLASH pages.
- * @note To correctly run this function, the FLASH_Unlock() function must be called before.
- * @note Call the FLASH_Lock() to disable the flash memory access (recommended
- * to protect the FLASH memory against possible unwanted operation)
- * @param None
- * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
- * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
- */
-FLASH_Status FLASH_EraseAllPages(void)
-{
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-
- if(status == FLASH_COMPLETE)
- {
- /* if the previous operation is completed, proceed to erase all pages */
- FLASH->CR |= FLASH_CR_MER;
- FLASH->CR |= FLASH_CR_STRT;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-
- /* Disable the MER Bit */
- FLASH->CR &= ~FLASH_CR_MER;
- }
-
- /* Return the Erase Status */
- return status;
-}
-
-/**
- * @brief Programs a word at a specified address.
- * @note To correctly run this function, the FLASH_Unlock() function must be called before.
- * @note Call the FLASH_Lock() to disable the flash memory access (recommended
- * to protect the FLASH memory against possible unwanted operation)
- * @param Address: specifies the address to be programmed.
- * @param Data: specifies the data to be programmed.
- * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
- * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
- */
-FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data)
-{
- FLASH_Status status = FLASH_COMPLETE;
- __IO uint32_t tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-
- if(status == FLASH_COMPLETE)
- {
- /* If the previous operation is completed, proceed to program the new first
- half word */
- FLASH->CR |= FLASH_CR_PG;
-
- *(__IO uint16_t*)Address = (uint16_t)Data;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-
- if(status == FLASH_COMPLETE)
- {
- /* If the previous operation is completed, proceed to program the new second
- half word */
- tmp = Address + 2;
-
- *(__IO uint16_t*) tmp = Data >> 16;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-
- /* Disable the PG Bit */
- FLASH->CR &= ~FLASH_CR_PG;
- }
- else
- {
- /* Disable the PG Bit */
- FLASH->CR &= ~FLASH_CR_PG;
- }
- }
-
- /* Return the Program Status */
- return status;
-}
-
-/**
- * @brief Programs a half word at a specified address.
- * @note To correctly run this function, the FLASH_Unlock() function must be called before.
- * @note Call the FLASH_Lock() to disable the flash memory access (recommended
- * to protect the FLASH memory against possible unwanted operation)
- * @param Address: specifies the address to be programmed.
- * @param Data: specifies the data to be programmed.
- * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
- * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
- */
-FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data)
-{
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Check the parameters */
- assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-
- if(status == FLASH_COMPLETE)
- {
- /* If the previous operation is completed, proceed to program the new data */
- FLASH->CR |= FLASH_CR_PG;
-
- *(__IO uint16_t*)Address = Data;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-
- /* Disable the PG Bit */
- FLASH->CR &= ~FLASH_CR_PG;
- }
-
- /* Return the Program Status */
- return status;
-}
-
-/**
- * @}
- */
-
-/** @defgroup FLASH_Group3 Option Bytes Programming functions
- * @brief Option Bytes Programming functions
- *
-@verbatim
- ===============================================================================
- ##### Option Bytes Programming functions #####
- ===============================================================================
-
- [..] The FLASH_Option Bytes Programming_functions, includes the following functions:
- (+) void FLASH_OB_Unlock(void);
- (+) void FLASH_OB_Lock(void);
- (+) void FLASH_OB_Launch(void);
- (+) FLASH_Status FLASH_OB_Erase(void);
- (+) FLASH_Status FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState);
- (+) FLASH_Status FLASH_OB_RDPConfig(uint8_t OB_RDP);
- (+) FLASH_Status FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY);
- (+) FLASH_Status FLASH_OB_BOOTConfig(uint8_t OB_BOOT1);
- (+) FLASH_Status FLASH_OB_VDDAConfig(uint8_t OB_VDDA_ANALOG);
- (+) FLASH_Status FLASH_OB_WriteUser(uint8_t OB_USER);
- (+) FLASH_OB_ProgramData(uint32_t Address, uint8_t Data);
- (+) uint8_t FLASH_OB_GetUser(void);
- (+) uint32_t FLASH_OB_GetWRP(void);
- (+) FlagStatus FLASH_OB_GetRDP(void);
-
- [..] Any operation of erase or program should follow these steps:
-
- (#) Call the FLASH_OB_Unlock() function to enable the Option Bytes registers access
-
- (#) Call one or several functions to program the desired option bytes
- (++) FLASH_Status FLASH_OB_RDPConfig(uint8_t OB_RDP) => to set the desired read Protection Level
- (++) FLASH_Status FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState)
- => to Enable/Disable the desired sector write protection
- (++) FLASH_Status FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY)
- => to configure the user option Bytes: IWDG, STOP and the Standby.
- (++) FLASH_Status FLASH_OB_BOOTConfig(uint8_t OB_BOOT1)
- => to set or reset BOOT1
- (++) FLASH_Status FLASH_OB_VDDAConfig(uint8_t OB_VDDA_ANALOG)
- => to enable or disable the VDDA Analog Monitoring
- (++) You can write all User Options bytes at once using a single function
- by calling FLASH_Status FLASH_OB_WriteUser(uint8_t OB_USER)
- (++) FLASH_OB_ProgramData(uint32_t Address, uint8_t Data) to program the
- two half word in the option bytes
-
- (#) Once all needed option bytes to be programmed are correctly written, call the
- FLASH_OB_Launch(void) function to launch the Option Bytes programming process.
-
- (#) Call the FLASH_OB_Lock() to disable the Option Bytes registers access (recommended
- to protect the option Bytes against possible unwanted operations)
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Unlocks the option bytes block access.
- * @param None
- * @retval None
- */
-void FLASH_OB_Unlock(void)
-{
- if((FLASH->CR & FLASH_CR_OPTWRE) == RESET)
- {
- /* Unlocking the option bytes block access */
- FLASH->OPTKEYR = FLASH_OPTKEY1;
- FLASH->OPTKEYR = FLASH_OPTKEY2;
- }
-}
-
-/**
- * @brief Locks the option bytes block access.
- * @param None
- * @retval None
- */
-void FLASH_OB_Lock(void)
-{
- /* Set the OPTWREN Bit to lock the option bytes block access */
- FLASH->CR &= ~FLASH_CR_OPTWRE;
-}
-
-/**
- * @brief Launch the option byte loading.
- * @param None
- * @retval None
- */
-void FLASH_OB_Launch(void)
-{
- /* Set the OBL_Launch bit to launch the option byte loading */
- FLASH->CR |= FLASH_CR_OBL_LAUNCH;
-}
-
-/**
- * @brief Erases the FLASH option bytes.
- * @note To correctly run this function, the FLASH_OB_Unlock() function must be called before.
- * @note Call the FLASH_OB_Lock() to disable the flash control register access and the option
- * bytes (recommended to protect the FLASH memory against possible unwanted operation)
- * @note This functions erases all option bytes except the Read protection (RDP).
- * @param None
- * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
- * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
- */
-FLASH_Status FLASH_OB_Erase(void)
-{
- uint16_t rdptmp = OB_RDP_Level_0;
-
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Get the actual read protection Option Byte value */
- if(FLASH_OB_GetRDP() != RESET)
- {
- rdptmp = 0x00;
- }
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-
- if(status == FLASH_COMPLETE)
- {
- /* If the previous operation is completed, proceed to erase the option bytes */
- FLASH->CR |= FLASH_CR_OPTER;
- FLASH->CR |= FLASH_CR_STRT;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-
- if(status == FLASH_COMPLETE)
- {
- /* If the erase operation is completed, disable the OPTER Bit */
- FLASH->CR &= ~FLASH_CR_OPTER;
-
- /* Enable the Option Bytes Programming operation */
- FLASH->CR |= FLASH_CR_OPTPG;
-
- /* Restore the last read protection Option Byte value */
- OB->RDP = (uint16_t)rdptmp;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-
- if(status != FLASH_TIMEOUT)
- {
- /* if the program operation is completed, disable the OPTPG Bit */
- FLASH->CR &= ~FLASH_CR_OPTPG;
- }
- }
- else
- {
- if (status != FLASH_TIMEOUT)
- {
- /* Disable the OPTPG Bit */
- FLASH->CR &= ~FLASH_CR_OPTPG;
- }
- }
- }
- /* Return the erase status */
- return status;
-}
-
-/**
- * @brief Write protects the desired pages
- * @note To correctly run this function, the FLASH_OB_Unlock() function must be called before.
- * @note Call the FLASH_OB_Lock() to disable the flash control register access and the option
- * bytes (recommended to protect the FLASH memory against possible unwanted operation)
- * @param OB_WRP: specifies the address of the pages to be write protected.
- * This parameter can be:
- * @arg OB_WRP_Pages0to3..OB_WRP_Pages60to63
- * @arg OB_WRP_AllPages
- * @retval FLASH Status: The returned value can be:
- * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
- */
-FLASH_Status FLASH_OB_EnableWRP(uint32_t OB_WRP)
-{
- uint16_t WRP0_Data = 0xFFFF, WRP1_Data = 0xFFFF, WRP2_Data = 0xFFFF, WRP3_Data = 0xFFFF;
-
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Check the parameters */
- assert_param(IS_OB_WRP(OB_WRP));
-
- OB_WRP = (uint32_t)(~OB_WRP);
- WRP0_Data = (uint16_t)(OB_WRP & OB_WRP0_WRP0);
- WRP1_Data = (uint16_t)((OB_WRP >> 8) & OB_WRP0_WRP0);
- WRP2_Data = (uint16_t)((OB_WRP >> 16) & OB_WRP0_WRP0) ;
- WRP3_Data = (uint16_t)((OB_WRP >> 24) & OB_WRP0_WRP0) ;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-
- if(status == FLASH_COMPLETE)
- {
- FLASH->CR |= FLASH_CR_OPTPG;
-
- if(WRP0_Data != 0xFF)
- {
- OB->WRP0 = WRP0_Data;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
- }
- if((status == FLASH_COMPLETE) && (WRP1_Data != 0xFF))
- {
- OB->WRP1 = WRP1_Data;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
- }
- if((status == FLASH_COMPLETE) && (WRP2_Data != 0xFF))
- {
- OB->WRP2 = WRP2_Data;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
- }
- if((status == FLASH_COMPLETE) && (WRP3_Data != 0xFF))
- {
- OB->WRP3 = WRP3_Data;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
- }
- if(status != FLASH_TIMEOUT)
- {
- /* if the program operation is completed, disable the OPTPG Bit */
- FLASH->CR &= ~FLASH_CR_OPTPG;
- }
- }
- /* Return the write protection operation Status */
- return status;
-}
-
-/**
- * @brief Enables or disables the read out protection.
- * @note To correctly run this function, the FLASH_OB_Unlock() function must be called before.
- * @note Call the FLASH_OB_Lock() to disable the flash control register access and the option
- * bytes (recommended to protect the FLASH memory against possible unwanted operation)
- * @param FLASH_ReadProtection_Level: specifies the read protection level.
- * This parameter can be:
- * @arg OB_RDP_Level_0: No protection
- * @arg OB_RDP_Level_1: Read protection of the memory
- * @arg OB_RDP_Level_2: Chip protection
- * @note When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0
- * @retval FLASH Status: The returned value can be:
- * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
- */
-FLASH_Status FLASH_OB_RDPConfig(uint8_t OB_RDP)
-{
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Check the parameters */
- assert_param(IS_OB_RDP(OB_RDP));
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-
- if(status == FLASH_COMPLETE)
- {
- FLASH->CR |= FLASH_CR_OPTER;
- FLASH->CR |= FLASH_CR_STRT;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-
- if(status == FLASH_COMPLETE)
- {
- /* If the erase operation is completed, disable the OPTER Bit */
- FLASH->CR &= ~FLASH_CR_OPTER;
-
- /* Enable the Option Bytes Programming operation */
- FLASH->CR |= FLASH_CR_OPTPG;
-
- OB->RDP = OB_RDP;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-
- if(status != FLASH_TIMEOUT)
- {
- /* if the program operation is completed, disable the OPTPG Bit */
- FLASH->CR &= ~FLASH_CR_OPTPG;
- }
- }
- else
- {
- if(status != FLASH_TIMEOUT)
- {
- /* Disable the OPTER Bit */
- FLASH->CR &= ~FLASH_CR_OPTER;
- }
- }
- }
- /* Return the protection operation Status */
- return status;
-}
-
-/**
- * @brief Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.
- * @note To correctly run this function, the FLASH_OB_Unlock() function must be called before.
- * @note Call the FLASH_OB_Lock() to disable the flash control register access and the option
- * bytes (recommended to protect the FLASH memory against possible unwanted operation)
- * @param OB_IWDG: Selects the WDG mode
- * This parameter can be one of the following values:
- * @arg OB_IWDG_SW: Software WDG selected
- * @arg OB_IWDG_HW: Hardware WDG selected
- * @param OB_STOP: Reset event when entering STOP mode.
- * This parameter can be one of the following values:
- * @arg OB_STOP_NoRST: No reset generated when entering in STOP
- * @arg OB_STOP_RST: Reset generated when entering in STOP
- * @param OB_STDBY: Reset event when entering Standby mode.
- * This parameter can be one of the following values:
- * @arg OB_STDBY_NoRST: No reset generated when entering in STANDBY
- * @arg OB_STDBY_RST: Reset generated when entering in STANDBY
- * @retval FLASH Status: The returned value can be:
- * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
- */
-FLASH_Status FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY)
-{
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Check the parameters */
- assert_param(IS_OB_IWDG_SOURCE(OB_IWDG));
- assert_param(IS_OB_STOP_SOURCE(OB_STOP));
- assert_param(IS_OB_STDBY_SOURCE(OB_STDBY));
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-
- if(status == FLASH_COMPLETE)
- {
- /* Enable the Option Bytes Programming operation */
- FLASH->CR |= FLASH_CR_OPTPG;
-
- OB->USER = (uint16_t)((uint16_t)(OB_IWDG | OB_STOP) | (uint16_t)(OB_STDBY | 0xF8));
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-
- if(status != FLASH_TIMEOUT)
- {
- /* If the program operation is completed, disable the OPTPG Bit */
- FLASH->CR &= ~FLASH_CR_OPTPG;
- }
- }
- /* Return the Option Byte program Status */
- return status;
-}
-
-/**
- * @brief Sets or resets the BOOT1 option bit.
- * @param OB_BOOT1: Set or Reset the BOOT1 option bit.
- * This parameter can be one of the following values:
- * @arg OB_BOOT1_RESET: BOOT1 option bit reset
- * @arg OB_BOOT1_SET: BOOT1 option bit set
- * @retval None
- */
-FLASH_Status FLASH_OB_BOOTConfig(uint8_t OB_BOOT1)
-{
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Check the parameters */
- assert_param(IS_OB_BOOT1(OB_BOOT1));
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-
- if(status == FLASH_COMPLETE)
- {
- /* Enable the Option Bytes Programming operation */
- FLASH->CR |= FLASH_CR_OPTPG;
-
- OB->USER = OB_BOOT1 | 0xEF;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-
- if(status != FLASH_TIMEOUT)
- {
- /* If the program operation is completed, disable the OPTPG Bit */
- FLASH->CR &= ~FLASH_CR_OPTPG;
- }
- }
- /* Return the Option Byte program Status */
- return status;
-}
-
-/**
- * @brief Sets or resets the BOOT0 option bit.
- * @note This function is applicable only for the STM32F042 devices.
- * @param OB_BOOT0: Set or Reset the BOOT0 option bit.
- * This parameter can be one of the following values:
- * @arg OB_BOOT0_RESET: BOOT0 option bit reset
- * @arg OB_BOOT0_SET: BOOT0 option bit set
- * @retval None
- */
-FLASH_Status FLASH_OB_BOOT0Config(uint8_t OB_BOOT0)
-{
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Check the parameters */
- assert_param(IS_OB_BOOT0(OB_BOOT0));
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-
- if(status == FLASH_COMPLETE)
- {
- /* Enable the Option Bytes Programming operation */
- FLASH->CR |= FLASH_CR_OPTPG;
-
- OB->USER = OB_BOOT0 | 0xF7;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-
- if(status != FLASH_TIMEOUT)
- {
- /* If the program operation is completed, disable the OPTPG Bit */
- FLASH->CR &= ~FLASH_CR_OPTPG;
- }
- }
- /* Return the Option Byte program Status */
- return status;
-}
-
-/**
- * @brief Sets or resets the BOOT0SW option bit.
- * @note This function is applicable only for the STM32F042 devices.
- * @param OB_BOOT0SW: Set or Reset the BOOT0_SW option bit.
- * This parameter can be one of the following values:
- * @arg OB_BOOT0_SW: BOOT0_SW option bit reset
- * @arg OB_BOOT0_HW: BOOT0_SW option bit set
- * @retval None
- */
-FLASH_Status FLASH_OB_BOOT0SWConfig(uint8_t OB_BOOT0SW)
-{
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Check the parameters */
- assert_param(IS_OB_BOOT0SW(OB_BOOT0SW));
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-
- if(status == FLASH_COMPLETE)
- {
- /* Enable the Option Bytes Programming operation */
- FLASH->CR |= FLASH_CR_OPTPG;
-
- OB->USER = OB_BOOT0SW | 0x7F;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-
- if(status != FLASH_TIMEOUT)
- {
- /* If the program operation is completed, disable the OPTPG Bit */
- FLASH->CR &= ~FLASH_CR_OPTPG;
- }
- }
- /* Return the Option Byte program Status */
- return status;
-}
-
-/**
- * @brief Sets or resets the analogue monitoring on VDDA Power source.
- * @param OB_VDDA_ANALOG: Selects the analog monitoring on VDDA Power source.
- * This parameter can be one of the following values:
- * @arg OB_VDDA_ANALOG_ON: Analog monitoring on VDDA Power source ON
- * @arg OB_VDDA_ANALOG_OFF: Analog monitoring on VDDA Power source OFF
- * @retval None
- */
-FLASH_Status FLASH_OB_VDDAConfig(uint8_t OB_VDDA_ANALOG)
-{
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Check the parameters */
- assert_param(IS_OB_VDDA_ANALOG(OB_VDDA_ANALOG));
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-
- if(status == FLASH_COMPLETE)
- {
- /* Enable the Option Bytes Programming operation */
- FLASH->CR |= FLASH_CR_OPTPG;
-
- OB->USER = OB_VDDA_ANALOG | 0xDF;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-
- if(status != FLASH_TIMEOUT)
- {
- /* if the program operation is completed, disable the OPTPG Bit */
- FLASH->CR &= ~FLASH_CR_OPTPG;
- }
- }
- /* Return the Option Byte program Status */
- return status;
-}
-
-/**
- * @brief Sets or resets the SRAM parity.
- * @param OB_SRAM_Parity: Set or Reset the SRAM parity enable bit.
- * This parameter can be one of the following values:
- * @arg OB_SRAM_PARITY_SET: Set SRAM parity.
- * @arg OB_SRAM_PARITY_RESET: Reset SRAM parity.
- * @retval None
- */
-FLASH_Status FLASH_OB_SRAMParityConfig(uint8_t OB_SRAM_Parity)
-{
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Check the parameters */
- assert_param(IS_OB_SRAM_PARITY(OB_SRAM_Parity));
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-
- if(status == FLASH_COMPLETE)
- {
- /* Enable the Option Bytes Programming operation */
- FLASH->CR |= FLASH_CR_OPTPG;
-
- OB->USER = OB_SRAM_Parity | 0xBF;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-
- if(status != FLASH_TIMEOUT)
- {
- /* if the program operation is completed, disable the OPTPG Bit */
- FLASH->CR &= ~FLASH_CR_OPTPG;
- }
- }
- /* Return the Option Byte program Status */
- return status;
-}
-
-/**
- * @brief Programs the FLASH User Option Byte: IWDG_SW, RST_STOP, RST_STDBY,
- * BOOT1 and VDDA ANALOG monitoring.
- * @note To correctly run this function, the FLASH_OB_Unlock() function must be called before.
- * @note Call the FLASH_OB_Lock() to disable the flash control register access and the option
- * bytes (recommended to protect the FLASH memory against possible unwanted operation)
- * @param OB_USER: Selects all user option bytes
- * This parameter is a combination of the following values:
- * @arg OB_IWDG_SW / OB_IWDG_HW: Software / Hardware WDG selected
- * @arg OB_STOP_NoRST / OB_STOP_RST: No reset / Reset generated when entering in STOP
- * @arg OB_STDBY_NoRST / OB_STDBY_RST: No reset / Reset generated when entering in STANDBY
- * @arg OB_BOOT1_RESET / OB_BOOT1_SET: BOOT1 Reset / Set
- * @arg OB_VDDA_ANALOG_ON / OB_VDDA_ANALOG_OFF: Analog monitoring on VDDA Power source ON / OFF
- * @arg OB_SRAM_PARITY_SET / OB_SRAM_PARITY_RESET: SRAM Parity SET / RESET
- * @arg OB_BOOT0_RESET / OB_BOOT0_SET: BOOT0 Reset / Set
- * @arg OB_BOOT0_SW / OB_BOOT0_SW: BOOT0 pin disabled / BOOT0 pin bonded with GPIO
- * @retval FLASH Status: The returned value can be:
- * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
- */
-FLASH_Status FLASH_OB_WriteUser(uint8_t OB_USER)
-{
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-
- if(status == FLASH_COMPLETE)
- {
- /* Enable the Option Bytes Programming operation */
- FLASH->CR |= FLASH_CR_OPTPG;
-
- OB->USER = OB_USER;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-
- if(status != FLASH_TIMEOUT)
- {
- /* If the program operation is completed, disable the OPTPG Bit */
- FLASH->CR &= ~FLASH_CR_OPTPG;
- }
- }
- /* Return the Option Byte program Status */
- return status;
-
-}
-
-/**
- * @brief Programs a half word at a specified Option Byte Data address.
- * @note To correctly run this function, the FLASH_OB_Unlock() function must be called before.
- * @note Call the FLASH_OB_Lock() to disable the flash control register access and the option
- * bytes (recommended to protect the FLASH memory against possible unwanted operation)
- * @param Address: specifies the address to be programmed.
- * This parameter can be 0x1FFFF804 or 0x1FFFF806.
- * @param Data: specifies the data to be programmed.
- * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
- * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
- */
-FLASH_Status FLASH_OB_ProgramData(uint32_t Address, uint8_t Data)
-{
- FLASH_Status status = FLASH_COMPLETE;
- /* Check the parameters */
- assert_param(IS_OB_DATA_ADDRESS(Address));
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-
- if(status == FLASH_COMPLETE)
- {
- /* Enables the Option Bytes Programming operation */
- FLASH->CR |= FLASH_CR_OPTPG;
- *(__IO uint16_t*)Address = Data;
-
- /* Wait for last operation to be completed */
- status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
-
- if(status != FLASH_TIMEOUT)
- {
- /* If the program operation is completed, disable the OPTPG Bit */
- FLASH->CR &= ~FLASH_CR_OPTPG;
- }
- }
- /* Return the Option Byte Data Program Status */
- return status;
-}
-
-/**
- * @brief Returns the FLASH User Option Bytes values.
- * @param None
- * @retval The FLASH User Option Bytes .
- */
-uint8_t FLASH_OB_GetUser(void)
-{
- /* Return the User Option Byte */
- return (uint8_t)(FLASH->OBR >> 8);
-}
-
-/**
- * @brief Returns the FLASH Write Protection Option Bytes value.
- * @param None
- * @retval The FLASH Write Protection Option Bytes value
- */
-uint32_t FLASH_OB_GetWRP(void)
-{
- /* Return the FLASH write protection Register value */
- return (uint32_t)(FLASH->WRPR);
-}
-
-/**
- * @brief Checks whether the FLASH Read out Protection Status is set or not.
- * @param None
- * @retval FLASH ReadOut Protection Status(SET or RESET)
- */
-FlagStatus FLASH_OB_GetRDP(void)
-{
- FlagStatus readstatus = RESET;
-
- if ((uint8_t)(FLASH->OBR & (FLASH_OBR_RDPRT1 | FLASH_OBR_RDPRT2)) != RESET)
- {
- readstatus = SET;
- }
- else
- {
- readstatus = RESET;
- }
- return readstatus;
-}
-
-/**
- * @}
- */
-
-/** @defgroup FLASH_Group4 Interrupts and flags management functions
- * @brief Interrupts and flags management functions
- *
-@verbatim
- ===============================================================================
- ##### Interrupts and flags management functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the specified FLASH interrupts.
- * @param FLASH_IT: specifies the FLASH interrupt sources to be enabled or
- * disabled.
- * This parameter can be any combination of the following values:
- * @arg FLASH_IT_EOP: FLASH end of programming Interrupt
- * @arg FLASH_IT_ERR: FLASH Error Interrupt
- * @retval None
- */
-void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FLASH_IT(FLASH_IT));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if(NewState != DISABLE)
- {
- /* Enable the interrupt sources */
- FLASH->CR |= FLASH_IT;
- }
- else
- {
- /* Disable the interrupt sources */
- FLASH->CR &= ~(uint32_t)FLASH_IT;
- }
-}
-
-/**
- * @brief Checks whether the specified FLASH flag is set or not.
- * @param FLASH_FLAG: specifies the FLASH flag to check.
- * This parameter can be one of the following values:
- * @arg FLASH_FLAG_BSY: FLASH write/erase operations in progress flag
- * @arg FLASH_FLAG_PGERR: FLASH Programming error flag flag
- * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag
- * @arg FLASH_FLAG_EOP: FLASH End of Programming flag
- * @retval The new state of FLASH_FLAG (SET or RESET).
- */
-FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG)
-{
- FlagStatus bitstatus = RESET;
-
- /* Check the parameters */
- assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG));
-
- if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- /* Return the new state of FLASH_FLAG (SET or RESET) */
- return bitstatus;
-}
-
-/**
- * @brief Clears the FLASH's pending flags.
- * @param FLASH_FLAG: specifies the FLASH flags to clear.
- * This parameter can be any combination of the following values:
- * @arg FLASH_FLAG_PGERR: FLASH Programming error flag flag
- * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag
- * @arg FLASH_FLAG_EOP: FLASH End of Programming flag
- * @retval None
- */
-void FLASH_ClearFlag(uint32_t FLASH_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG));
-
- /* Clear the flags */
- FLASH->SR = FLASH_FLAG;
-}
-
-/**
- * @brief Returns the FLASH Status.
- * @param None
- * @retval FLASH Status: The returned value can be:
- * FLASH_BUSY, FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP or FLASH_COMPLETE.
- */
-FLASH_Status FLASH_GetStatus(void)
-{
- FLASH_Status FLASHstatus = FLASH_COMPLETE;
-
- if((FLASH->SR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY)
- {
- FLASHstatus = FLASH_BUSY;
- }
- else
- {
- if((FLASH->SR & (uint32_t)FLASH_FLAG_WRPERR)!= (uint32_t)0x00)
- {
- FLASHstatus = FLASH_ERROR_WRP;
- }
- else
- {
- if((FLASH->SR & (uint32_t)(FLASH_SR_PGERR)) != (uint32_t)0x00)
- {
- FLASHstatus = FLASH_ERROR_PROGRAM;
- }
- else
- {
- FLASHstatus = FLASH_COMPLETE;
- }
- }
- }
- /* Return the FLASH Status */
- return FLASHstatus;
-}
-
-
-/**
- * @brief Waits for a FLASH operation to complete or a TIMEOUT to occur.
- * @param Timeout: FLASH programming Timeout
- * @retval FLASH Status: The returned value can be: FLASH_BUSY,
- * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
- */
-FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout)
-{
- FLASH_Status status = FLASH_COMPLETE;
-
- /* Check for the FLASH Status */
- status = FLASH_GetStatus();
-
- /* Wait for a FLASH operation to complete or a TIMEOUT to occur */
- while((status == FLASH_BUSY) && (Timeout != 0x00))
- {
- status = FLASH_GetStatus();
- Timeout--;
- }
-
- if(Timeout == 0x00 )
- {
- status = FLASH_TIMEOUT;
- }
- /* Return the operation status */
- return status;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
- /**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_gpio.c b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_gpio.c
deleted file mode 100644
index 880508c44cfc68e5c976452c57c0d00078a15903..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_gpio.c
+++ /dev/null
@@ -1,540 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f0xx_gpio.c
- * @author MCD Application Team
- * @version V1.3.0
- * @date 16-January-2014
- * @brief This file provides firmware functions to manage the following
- * functionalities of the GPIO peripheral:
- * + Initialization and Configuration functions
- * + GPIO Read and Write functions
- * + GPIO Alternate functions configuration functions
- *
- * @verbatim
- *
- *
- ===========================================================================
- ##### How to use this driver #####
- ===========================================================================
- [..]
- (#) Enable the GPIO AHB clock using RCC_AHBPeriphClockCmd()
- (#) Configure the GPIO pin(s) using GPIO_Init()
- Four possible configuration are available for each pin:
- (++) Input: Floating, Pull-up, Pull-down.
- (++) Output: Push-Pull (Pull-up, Pull-down or no Pull)
- Open Drain (Pull-up, Pull-down or no Pull).
- In output mode, the speed is configurable: Low, Medium, Fast or High.
- (++) Alternate Function: Push-Pull (Pull-up, Pull-down or no Pull)
- Open Drain (Pull-up, Pull-down or no Pull).
- (++) Analog: required mode when a pin is to be used as ADC channel,
- DAC output or comparator input.
- (#) Peripherals alternate function:
- (++) For ADC, DAC and comparators, configure the desired pin in analog
- mode using GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AN
- (++) For other peripherals (TIM, USART...):
- (+++) Connect the pin to the desired peripherals' Alternate
- Function (AF) using GPIO_PinAFConfig() function. For PortC,
- PortD and PortF, no configuration is needed.
- (+++) Configure the desired pin in alternate function mode using
- GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF
- (+++) Select the type, pull-up/pull-down and output speed via
- GPIO_PuPd, GPIO_OType and GPIO_Speed members
- (+++) Call GPIO_Init() function
- (#) To get the level of a pin configured in input mode use GPIO_ReadInputDataBit()
- (#) To set/reset the level of a pin configured in output mode use
- GPIO_SetBits()/GPIO_ResetBits()
- (#) During and just after reset, the alternate functions are not active and
- the GPIO pins are configured in input floating mode (except JTAG pins).
- (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as
- general-purpose (PC14 and PC15, respectively) when the LSE oscillator
- is off. The LSE has priority over the GPIO function.
- (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as general-purpose
- PD0 and PD1, respectively, when the HSE oscillator is off. The HSE has
- priority over the GPIO function.
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx_gpio.h"
-#include "stm32f0xx_rcc.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup GPIO
- * @brief GPIO driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup GPIO_Private_Functions
- * @{
- */
-
-/** @defgroup GPIO_Group1 Initialization and Configuration
- * @brief Initialization and Configuration
- *
-@verbatim
- ===============================================================================
- ##### Initialization and Configuration #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitializes the GPIOx peripheral registers to their default reset
- * values.
- * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
- * @note GPIOE is available only for STM32F072.
- * @note GPIOD is not available for STM32F031.
- * @retval None
- */
-void GPIO_DeInit(GPIO_TypeDef* GPIOx)
-{
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
-
- if(GPIOx == GPIOA)
- {
- RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOA, ENABLE);
- RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOA, DISABLE);
- }
- else if(GPIOx == GPIOB)
- {
- RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOB, ENABLE);
- RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOB, DISABLE);
- }
- else if(GPIOx == GPIOC)
- {
- RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOC, ENABLE);
- RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOC, DISABLE);
- }
- else if(GPIOx == GPIOD)
- {
- RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOD, ENABLE);
- RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOD, DISABLE);
- }
- else if(GPIOx == GPIOE)
- {
- RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOE, ENABLE);
- RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOE, DISABLE);
- }
- else
- {
- if(GPIOx == GPIOF)
- {
- RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOF, ENABLE);
- RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOF, DISABLE);
- }
- }
-}
-
-/**
- * @brief Initializes the GPIOx peripheral according to the specified
- * parameters in the GPIO_InitStruct.
- * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
- * @note GPIOE is available only for STM32F072.
- * @note GPIOD is not available for STM32F031.
- * @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that contains
- * the configuration information for the specified GPIO peripheral.
- * @retval None
- */
-void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)
-{
- uint32_t pinpos = 0x00, pos = 0x00 , currentpin = 0x00;
-
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
- assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin));
- assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode));
- assert_param(IS_GPIO_PUPD(GPIO_InitStruct->GPIO_PuPd));
-
- /*-------------------------- Configure the port pins -----------------------*/
- /*-- GPIO Mode Configuration --*/
- for (pinpos = 0x00; pinpos < 0x10; pinpos++)
- {
- pos = ((uint32_t)0x01) << pinpos;
-
- /* Get the port pins position */
- currentpin = (GPIO_InitStruct->GPIO_Pin) & pos;
-
- if (currentpin == pos)
- {
- if ((GPIO_InitStruct->GPIO_Mode == GPIO_Mode_OUT) || (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_AF))
- {
- /* Check Speed mode parameters */
- assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed));
-
- /* Speed mode configuration */
- GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (pinpos * 2));
- GPIOx->OSPEEDR |= ((uint32_t)(GPIO_InitStruct->GPIO_Speed) << (pinpos * 2));
-
- /* Check Output mode parameters */
- assert_param(IS_GPIO_OTYPE(GPIO_InitStruct->GPIO_OType));
-
- /* Output mode configuration */
- GPIOx->OTYPER &= ~((GPIO_OTYPER_OT_0) << ((uint16_t)pinpos));
- GPIOx->OTYPER |= (uint16_t)(((uint16_t)GPIO_InitStruct->GPIO_OType) << ((uint16_t)pinpos));
- }
-
- GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (pinpos * 2));
-
- GPIOx->MODER |= (((uint32_t)GPIO_InitStruct->GPIO_Mode) << (pinpos * 2));
-
- /* Pull-up Pull down resistor configuration */
- GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << ((uint16_t)pinpos * 2));
- GPIOx->PUPDR |= (((uint32_t)GPIO_InitStruct->GPIO_PuPd) << (pinpos * 2));
- }
- }
-}
-
-/**
- * @brief Fills each GPIO_InitStruct member with its default value.
- * @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure which will
- * be initialized.
- * @retval None
- */
-void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct)
-{
- /* Reset GPIO init structure parameters values */
- GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All;
- GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN;
- GPIO_InitStruct->GPIO_Speed = GPIO_Speed_Level_2;
- GPIO_InitStruct->GPIO_OType = GPIO_OType_PP;
- GPIO_InitStruct->GPIO_PuPd = GPIO_PuPd_NOPULL;
-}
-
-/**
- * @brief Locks GPIO Pins configuration registers.
- * @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
- * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
- * @note The configuration of the locked GPIO pins can no longer be modified
- * until the next device reset.
- * @param GPIOx: where x can be (A or B) to select the GPIO peripheral.
- * @param GPIO_Pin: specifies the port bit to be written.
- * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
- * @retval None
- */
-void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
- __IO uint32_t tmp = 0x00010000;
-
- /* Check the parameters */
- assert_param(IS_GPIO_LIST_PERIPH(GPIOx));
- assert_param(IS_GPIO_PIN(GPIO_Pin));
-
- tmp |= GPIO_Pin;
- /* Set LCKK bit */
- GPIOx->LCKR = tmp;
- /* Reset LCKK bit */
- GPIOx->LCKR = GPIO_Pin;
- /* Set LCKK bit */
- GPIOx->LCKR = tmp;
- /* Read LCKK bit */
- tmp = GPIOx->LCKR;
- /* Read LCKK bit */
- tmp = GPIOx->LCKR;
-}
-
-/**
- * @}
- */
-
-/** @defgroup GPIO_Group2 GPIO Read and Write
- * @brief GPIO Read and Write
- *
-@verbatim
- ===============================================================================
- ##### GPIO Read and Write #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Reads the specified input port pin.
- * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
- * @note GPIOE is available only for STM32F072.
- * @note GPIOD is not available for STM32F031.
- * @param GPIO_Pin: specifies the port bit to read.
- * @note This parameter can be GPIO_Pin_x where x can be:
- * For STM32F051 and STM32F030: (0..15) for GPIOA, GPIOB, GPIOC, (2) for GPIOD and (0..1, 4..7) for GIIOF.
- * For STM32F072: (0..15) for GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, (0..10) for GPIOF.
- * For STM32F031: (0..15) for GPIOA, GPIOB, (13..15) for GPIOC and (0..1, 6..7) for GPIOF.
- * @retval The input port pin value.
- */
-uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
- uint8_t bitstatus = 0x00;
-
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
- assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
-
- if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET)
- {
- bitstatus = (uint8_t)Bit_SET;
- }
- else
- {
- bitstatus = (uint8_t)Bit_RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Reads the specified input port pin.
- * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
- * @note GPIOE is available only for STM32F072.
- * @note GPIOD is not available for STM32F031.
- * @retval The input port pin value.
- */
-uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx)
-{
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
-
- return ((uint16_t)GPIOx->IDR);
-}
-
-/**
- * @brief Reads the specified output data port bit.
- * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
- * @note GPIOE is available only for STM32F072.
- * @note GPIOD is not available for STM32F031.
- * @param GPIO_Pin: Specifies the port bit to read.
- * @note This parameter can be GPIO_Pin_x where x can be:
- * For STM32F051 and STM32F030: (0..15) for GPIOA, GPIOB, GPIOC, (2) for GPIOD and (0..1, 4..7) for GIIOF.
- * For STM32F072: (0..15) for GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, (0..10) for GPIOF.
- * For STM32F031: (0..15) for GPIOA, GPIOB, (13..15) for GPIOC and (0..1, 6..7) for GPIOF.
- * @retval The output port pin value.
- */
-uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
- uint8_t bitstatus = 0x00;
-
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
- assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
-
- if ((GPIOx->ODR & GPIO_Pin) != (uint32_t)Bit_RESET)
- {
- bitstatus = (uint8_t)Bit_SET;
- }
- else
- {
- bitstatus = (uint8_t)Bit_RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Reads the specified GPIO output data port.
- * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
- * @note GPIOE is available only for STM32F072.
- * @note GPIOD is not available for STM32F031.
- * @retval GPIO output data port value.
- */
-uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx)
-{
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
-
- return ((uint16_t)GPIOx->ODR);
-}
-
-/**
- * @brief Sets the selected data port bits.
- * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
- * @note GPIOE is available only for STM32F072.
- * @note GPIOD is not available for STM32F031.
- * @param GPIO_Pin: specifies the port bits to be written.
- * @note This parameter can be GPIO_Pin_x where x can be:
- * For STM32F051 and STM32F030: (0..15) for GPIOA, GPIOB, GPIOC, (2) for GPIOD and (0..1, 4..7) for GIIOF.
- * For STM32F072: (0..15) for GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, (0..10) for GPIOF.
- * For STM32F031: (0..15) for GPIOA, GPIOB, (13..15) for GPIOC and (0..1, 6..7) for GPIOF.
- * @retval None
- */
-void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
- assert_param(IS_GPIO_PIN(GPIO_Pin));
-
- GPIOx->BSRR = GPIO_Pin;
-}
-
-/**
- * @brief Clears the selected data port bits.
- * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
- * @note GPIOE is available only for STM32F072.
- * @note GPIOD is not available for STM32F031.
- * @param GPIO_Pin: specifies the port bits to be written.
- * @note This parameter can be GPIO_Pin_x where x can be:
- * For STM32F051 and STM32F030: (0..15) for GPIOA, GPIOB, GPIOC, (2) for GPIOD and (0..1, 4..7) for GIIOF.
- * For STM32F072: (0..15) for GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, (0..10) for GPIOF.
- * For STM32F031: (0..15) for GPIOA, GPIOB, (13..15) for GPIOC and (0..1, 6..7) for GPIOF.
- * @retval None
- */
-void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
- assert_param(IS_GPIO_PIN(GPIO_Pin));
-
- GPIOx->BRR = GPIO_Pin;
-}
-
-/**
- * @brief Sets or clears the selected data port bit.
- * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
- * @note GPIOE is available only for STM32F072.
- * @note GPIOD is not available for STM32F031.
- * @param GPIO_Pin: specifies the port bit to be written.
- * @param BitVal: specifies the value to be written to the selected bit.
- * This parameter can be one of the BitAction enumeration values:
- * @arg Bit_RESET: to clear the port pin
- * @arg Bit_SET: to set the port pin
- * @note This parameter can be GPIO_Pin_x where x can be:
- * For STM32F051 and STM32F030: (0..15) for GPIOA, GPIOB, GPIOC, (2) for GPIOD and (0..1, 4..7) for GIIOF.
- * For STM32F072: (0..15) for GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, (0..10) for GPIOF.
- * For STM32F031: (0..15) for GPIOA, GPIOB, (13..15) for GPIOC and (0..1, 6..7) for GPIOF.
- * @retval None
- */
-void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal)
-{
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
- assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
- assert_param(IS_GPIO_BIT_ACTION(BitVal));
-
- if (BitVal != Bit_RESET)
- {
- GPIOx->BSRR = GPIO_Pin;
- }
- else
- {
- GPIOx->BRR = GPIO_Pin ;
- }
-}
-
-/**
- * @brief Writes data to the specified GPIO data port.
- * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
- * @note GPIOE is available only for STM32F072.
- * @note GPIOD is not available for STM32F031.
- * @param PortVal: specifies the value to be written to the port output data register.
- * @retval None
- */
-void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal)
-{
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
-
- GPIOx->ODR = PortVal;
-}
-
-/**
- * @}
- */
-
-/** @defgroup GPIO_Group3 GPIO Alternate functions configuration functions
- * @brief GPIO Alternate functions configuration functions
- *
-@verbatim
- ===============================================================================
- ##### GPIO Alternate functions configuration functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Writes data to the specified GPIO data port.
- * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
- * @note GPIOC, GPIOD, GPIOE and GPIOF are available only for STM32F072.
- * @param GPIO_PinSource: specifies the pin for the Alternate function.
- * This parameter can be GPIO_PinSourcex where x can be (0..15) for GPIOA, GPIOB, GPIOD, GPIOE
- * and (0..12) for GPIOC and (0, 2..5, 9..10) for GPIOF.
- * @param GPIO_AF: selects the pin to used as Alternate function.
- * This parameter can be one of the following value:
- * @arg GPIO_AF_0: WKUP, EVENTOUT, TIM15, SPI1, TIM17, MCO, SWDAT, SWCLK,
- * TIM14, BOOT, USART1, CEC, IR_OUT, SPI2, TIM3, USART4,
- * CAN, USART2, CRS, TIM16, TIM1, TS
- * @arg GPIO_AF_1: USART2, CEC, TIM3, USART1, USART2, EVENTOUT, I2C1,
- * I2C2, TIM15, SPI2, USART3, TS, SPI1
- * @arg GPIO_AF_2: TIM2, TIM1, EVENTOUT, TIM16, TIM17, USB
- * @arg GPIO_AF_3: TS, I2C1, TIM15, EVENTOUT
- * @arg GPIO_AF_4: TIM14, USART4, USART3, CRS, CAN
- * @arg GPIO_AF_5: TIM16, TIM17, TIM15, SPI2, I2C2
- * @arg GPIO_AF_6: EVENTOUT
- * @arg GPIO_AF_7: COMP1 OUT, COMP2 OUT
- * @note The pin should already been configured in Alternate Function mode(AF)
- * using GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF
- * @note Refer to the Alternate function mapping table in the device datasheet
- * for the detailed mapping of the system and peripherals'alternate
- * function I/O pins.
- * @retval None
- */
-void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF)
-{
- uint32_t temp = 0x00;
- uint32_t temp_2 = 0x00;
-
- /* Check the parameters */
- assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
- assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource));
- assert_param(IS_GPIO_AF(GPIO_AF));
-
- temp = ((uint32_t)(GPIO_AF) << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4));
- GPIOx->AFR[GPIO_PinSource >> 0x03] &= ~((uint32_t)0xF << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4));
- temp_2 = GPIOx->AFR[GPIO_PinSource >> 0x03] | temp;
- GPIOx->AFR[GPIO_PinSource >> 0x03] = temp_2;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_i2c.c b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_i2c.c
deleted file mode 100644
index 05a79662e3eb36516805305997856a7e3c1cab3d..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_i2c.c
+++ /dev/null
@@ -1,1585 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f0xx_i2c.c
- * @author MCD Application Team
- * @version V1.3.0
- * @date 16-January-2014
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Inter-Integrated circuit (I2C):
- * + Initialization and Configuration
- * + Communications handling
- * + SMBUS management
- * + I2C registers management
- * + Data transfers management
- * + DMA transfers management
- * + Interrupts and flags management
- *
- * @verbatim
- ============================================================================
- ##### How to use this driver #####
- ============================================================================
- [..]
- (#) Enable peripheral clock using RCC_APB1PeriphClockCmd(RCC_APB1Periph_I2Cx, ENABLE)
- function for I2C1 or I2C2.
- (#) Enable SDA, SCL and SMBA (when used) GPIO clocks using
- RCC_AHBPeriphClockCmd() function.
- (#) Peripherals alternate function:
- (++) Connect the pin to the desired peripherals' Alternate
- Function (AF) using GPIO_PinAFConfig() function.
- (++) Configure the desired pin in alternate function by:
- GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF
- (++) Select the type, OpenDrain and speed via
- GPIO_PuPd, GPIO_OType and GPIO_Speed members
- (++) Call GPIO_Init() function.
- (#) Program the Mode, Timing , Own address, Ack and Acknowledged Address
- using the I2C_Init() function.
- (#) Optionally you can enable/configure the following parameters without
- re-initialization (i.e there is no need to call again I2C_Init() function):
- (++) Enable the acknowledge feature using I2C_AcknowledgeConfig() function.
- (++) Enable the dual addressing mode using I2C_DualAddressCmd() function.
- (++) Enable the general call using the I2C_GeneralCallCmd() function.
- (++) Enable the clock stretching using I2C_StretchClockCmd() function.
- (++) Enable the PEC Calculation using I2C_CalculatePEC() function.
- (++) For SMBus Mode:
- (+++) Enable the SMBusAlert pin using I2C_SMBusAlertCmd() function.
- (#) Enable the NVIC and the corresponding interrupt using the function
- I2C_ITConfig() if you need to use interrupt mode.
- (#) When using the DMA mode
- (++) Configure the DMA using DMA_Init() function.
- (++) Active the needed channel Request using I2C_DMACmd() function.
- (#) Enable the I2C using the I2C_Cmd() function.
- (#) Enable the DMA using the DMA_Cmd() function when using DMA mode in the
- transfers.
- [..]
- (@) When using I2C in Fast Mode Plus, SCL and SDA pin 20mA current drive capability
- must be enabled by setting the driving capability control bit in SYSCFG.
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx_i2c.h"
-#include "stm32f0xx_rcc.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup I2C
- * @brief I2C driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-#define CR1_CLEAR_MASK ((uint32_t)0x00CFE0FF) /*<! I2C CR1 clear register Mask */
-#define CR2_CLEAR_MASK ((uint32_t)0x07FF7FFF) /*<! I2C CR2 clear register Mask */
-#define TIMING_CLEAR_MASK ((uint32_t)0xF0FFFFFF) /*<! I2C TIMING clear register Mask */
-#define ERROR_IT_MASK ((uint32_t)0x00003F00) /*<! I2C Error interrupt register Mask */
-#define TC_IT_MASK ((uint32_t)0x000000C0) /*<! I2C TC interrupt register Mask */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup I2C_Private_Functions
- * @{
- */
-
-
-/** @defgroup I2C_Group1 Initialization and Configuration functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and Configuration functions #####
- ===============================================================================
- [..] This section provides a set of functions allowing to initialize the I2C Mode,
- I2C Timing, I2C filters, I2C Addressing mode, I2C OwnAddress1.
-
- [..] The I2C_Init() function follows the I2C configuration procedures (these procedures
- are available in reference manual).
-
- [..] When the Software Reset is performed using I2C_SoftwareResetCmd() function, the internal
- states machines are reset and communication control bits, as well as status bits come
- back to their reset value.
-
- [..] Before enabling Stop mode using I2C_StopModeCmd() I2C Clock source must be set to
- HSI and Digital filters must be disabled.
-
- [..] Before enabling Own Address 2 via I2C_DualAddressCmd() function, OA2 and mask should be
- configured using I2C_OwnAddress2Config() function.
-
- [..] I2C_SlaveByteControlCmd() enable Slave byte control that allow user to get control of
- each byte in slave mode when NBYTES is set to 0x01.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitializes the I2Cx peripheral registers to their default reset values.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @retval None
- */
-void I2C_DeInit(I2C_TypeDef* I2Cx)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-
- if (I2Cx == I2C1)
- {
- /* Enable I2C1 reset state */
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, ENABLE);
- /* Release I2C1 from reset state */
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C1, DISABLE);
- }
- else
- {
- /* Enable I2C2 reset state */
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, ENABLE);
- /* Release I2C2 from reset state */
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_I2C2, DISABLE);
- }
-}
-
-/**
- * @brief Initializes the I2Cx peripheral according to the specified
- * parameters in the I2C_InitStruct.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param I2C_InitStruct: pointer to a I2C_InitTypeDef structure that
- * contains the configuration information for the specified I2C peripheral.
- * @retval None
- */
-void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_ANALOG_FILTER(I2C_InitStruct->I2C_AnalogFilter));
- assert_param(IS_I2C_DIGITAL_FILTER(I2C_InitStruct->I2C_DigitalFilter));
- assert_param(IS_I2C_MODE(I2C_InitStruct->I2C_Mode));
- assert_param(IS_I2C_OWN_ADDRESS1(I2C_InitStruct->I2C_OwnAddress1));
- assert_param(IS_I2C_ACK(I2C_InitStruct->I2C_Ack));
- assert_param(IS_I2C_ACKNOWLEDGE_ADDRESS(I2C_InitStruct->I2C_AcknowledgedAddress));
-
- /* Disable I2Cx Peripheral */
- I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_PE);
-
- /*---------------------------- I2Cx FILTERS Configuration ------------------*/
- /* Get the I2Cx CR1 value */
- tmpreg = I2Cx->CR1;
- /* Clear I2Cx CR1 register */
- tmpreg &= CR1_CLEAR_MASK;
- /* Configure I2Cx: analog and digital filter */
- /* Set ANFOFF bit according to I2C_AnalogFilter value */
- /* Set DFN bits according to I2C_DigitalFilter value */
- tmpreg |= (uint32_t)I2C_InitStruct->I2C_AnalogFilter |(I2C_InitStruct->I2C_DigitalFilter << 8);
-
- /* Write to I2Cx CR1 */
- I2Cx->CR1 = tmpreg;
-
- /*---------------------------- I2Cx TIMING Configuration -------------------*/
- /* Configure I2Cx: Timing */
- /* Set TIMINGR bits according to I2C_Timing */
- /* Write to I2Cx TIMING */
- I2Cx->TIMINGR = I2C_InitStruct->I2C_Timing & TIMING_CLEAR_MASK;
-
- /* Enable I2Cx Peripheral */
- I2Cx->CR1 |= I2C_CR1_PE;
-
- /*---------------------------- I2Cx OAR1 Configuration ---------------------*/
- /* Clear tmpreg local variable */
- tmpreg = 0;
- /* Clear OAR1 register */
- I2Cx->OAR1 = (uint32_t)tmpreg;
- /* Clear OAR2 register */
- I2Cx->OAR2 = (uint32_t)tmpreg;
- /* Configure I2Cx: Own Address1 and acknowledged address */
- /* Set OA1MODE bit according to I2C_AcknowledgedAddress value */
- /* Set OA1 bits according to I2C_OwnAddress1 value */
- tmpreg = (uint32_t)((uint32_t)I2C_InitStruct->I2C_AcknowledgedAddress | \
- (uint32_t)I2C_InitStruct->I2C_OwnAddress1);
- /* Write to I2Cx OAR1 */
- I2Cx->OAR1 = tmpreg;
- /* Enable Own Address1 acknowledgement */
- I2Cx->OAR1 |= I2C_OAR1_OA1EN;
-
- /*---------------------------- I2Cx MODE Configuration ---------------------*/
- /* Configure I2Cx: mode */
- /* Set SMBDEN and SMBHEN bits according to I2C_Mode value */
- tmpreg = I2C_InitStruct->I2C_Mode;
- /* Write to I2Cx CR1 */
- I2Cx->CR1 |= tmpreg;
-
- /*---------------------------- I2Cx ACK Configuration ----------------------*/
- /* Get the I2Cx CR2 value */
- tmpreg = I2Cx->CR2;
- /* Clear I2Cx CR2 register */
- tmpreg &= CR2_CLEAR_MASK;
- /* Configure I2Cx: acknowledgement */
- /* Set NACK bit according to I2C_Ack value */
- tmpreg |= I2C_InitStruct->I2C_Ack;
- /* Write to I2Cx CR2 */
- I2Cx->CR2 = tmpreg;
-}
-
-/**
- * @brief Fills each I2C_InitStruct member with its default value.
- * @param I2C_InitStruct: pointer to an I2C_InitTypeDef structure which will be initialized.
- * @retval None
- */
-void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct)
-{
- /*---------------- Reset I2C init structure parameters values --------------*/
- /* Initialize the I2C_Timing member */
- I2C_InitStruct->I2C_Timing = 0;
- /* Initialize the I2C_AnalogFilter member */
- I2C_InitStruct->I2C_AnalogFilter = I2C_AnalogFilter_Enable;
- /* Initialize the I2C_DigitalFilter member */
- I2C_InitStruct->I2C_DigitalFilter = 0;
- /* Initialize the I2C_Mode member */
- I2C_InitStruct->I2C_Mode = I2C_Mode_I2C;
- /* Initialize the I2C_OwnAddress1 member */
- I2C_InitStruct->I2C_OwnAddress1 = 0;
- /* Initialize the I2C_Ack member */
- I2C_InitStruct->I2C_Ack = I2C_Ack_Disable;
- /* Initialize the I2C_AcknowledgedAddress member */
- I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;
-}
-
-/**
- * @brief Enables or disables the specified I2C peripheral.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param NewState: new state of the I2Cx peripheral.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the selected I2C peripheral */
- I2Cx->CR1 |= I2C_CR1_PE;
- }
- else
- {
- /* Disable the selected I2C peripheral */
- I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_PE);
- }
-}
-
-/**
- * @brief Enables or disables the specified I2C software reset.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @retval None
- */
-void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-
- /* Disable peripheral */
- I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_PE);
-
- /* Perform a dummy read to delay the disable of peripheral for minimum
- 3 APB clock cycles to perform the software reset functionality */
- *(__IO uint32_t *)(uint32_t)I2Cx;
-
- /* Enable peripheral */
- I2Cx->CR1 |= I2C_CR1_PE;
-}
-
-/**
- * @brief Enables or disables the specified I2C interrupts.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param I2C_IT: specifies the I2C interrupts sources to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg I2C_IT_ERRI: Error interrupt mask
- * @arg I2C_IT_TCI: Transfer Complete interrupt mask
- * @arg I2C_IT_STOPI: Stop Detection interrupt mask
- * @arg I2C_IT_NACKI: Not Acknowledge received interrupt mask
- * @arg I2C_IT_ADDRI: Address Match interrupt mask
- * @arg I2C_IT_RXI: RX interrupt mask
- * @arg I2C_IT_TXI: TX interrupt mask
- * @param NewState: new state of the specified I2C interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_ITConfig(I2C_TypeDef* I2Cx, uint32_t I2C_IT, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- assert_param(IS_I2C_CONFIG_IT(I2C_IT));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected I2C interrupts */
- I2Cx->CR1 |= I2C_IT;
- }
- else
- {
- /* Disable the selected I2C interrupts */
- I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_IT);
- }
-}
-
-/**
- * @brief Enables or disables the I2C Clock stretching.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param NewState: new state of the I2Cx Clock stretching.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable clock stretching */
- I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_NOSTRETCH);
- }
- else
- {
- /* Disable clock stretching */
- I2Cx->CR1 |= I2C_CR1_NOSTRETCH;
- }
-}
-
-/**
- * @brief Enables or disables I2C wakeup from stop mode.
- * This function is not applicable for STM32F030 devices.
- * @param I2Cx: where x can be 1 to select the I2C peripheral.
- * @param NewState: new state of the I2Cx stop mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_StopModeCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_1_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable wakeup from stop mode */
- I2Cx->CR1 |= I2C_CR1_WUPEN;
- }
- else
- {
- /* Disable wakeup from stop mode */
- I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_WUPEN);
- }
-}
-
-/**
- * @brief Enables or disables the I2C own address 2.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param NewState: new state of the I2C own address 2.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable own address 2 */
- I2Cx->OAR2 |= I2C_OAR2_OA2EN;
- }
- else
- {
- /* Disable own address 2 */
- I2Cx->OAR2 &= (uint32_t)~((uint32_t)I2C_OAR2_OA2EN);
- }
-}
-
-/**
- * @brief Configures the I2C slave own address 2 and mask.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param Address: specifies the slave address to be programmed.
- * @param Mask: specifies own address 2 mask to be programmed.
- * This parameter can be one of the following values:
- * @arg I2C_OA2_NoMask: no mask.
- * @arg I2C_OA2_Mask01: OA2[1] is masked and don't care.
- * @arg I2C_OA2_Mask02: OA2[2:1] are masked and don't care.
- * @arg I2C_OA2_Mask03: OA2[3:1] are masked and don't care.
- * @arg I2C_OA2_Mask04: OA2[4:1] are masked and don't care.
- * @arg I2C_OA2_Mask05: OA2[5:1] are masked and don't care.
- * @arg I2C_OA2_Mask06: OA2[6:1] are masked and don't care.
- * @arg I2C_OA2_Mask07: OA2[7:1] are masked and don't care.
- * @retval None
- */
-void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint16_t Address, uint8_t Mask)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_OWN_ADDRESS2(Address));
- assert_param(IS_I2C_OWN_ADDRESS2_MASK(Mask));
-
- /* Get the old register value */
- tmpreg = I2Cx->OAR2;
-
- /* Reset I2Cx OA2 bit [7:1] and OA2MSK bit [1:0] */
- tmpreg &= (uint32_t)~((uint32_t)(I2C_OAR2_OA2 | I2C_OAR2_OA2MSK));
-
- /* Set I2Cx SADD */
- tmpreg |= (uint32_t)(((uint32_t)Address & I2C_OAR2_OA2) | \
- (((uint32_t)Mask << 8) & I2C_OAR2_OA2MSK)) ;
-
- /* Store the new register value */
- I2Cx->OAR2 = tmpreg;
-}
-
-/**
- * @brief Enables or disables the I2C general call mode.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param NewState: new state of the I2C general call mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable general call mode */
- I2Cx->CR1 |= I2C_CR1_GCEN;
- }
- else
- {
- /* Disable general call mode */
- I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_GCEN);
- }
-}
-
-/**
- * @brief Enables or disables the I2C slave byte control.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param NewState: new state of the I2C slave byte control.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_SlaveByteControlCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable slave byte control */
- I2Cx->CR1 |= I2C_CR1_SBC;
- }
- else
- {
- /* Disable slave byte control */
- I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_SBC);
- }
-}
-
-/**
- * @brief Configures the slave address to be transmitted after start generation.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param Address: specifies the slave address to be programmed.
- * @note This function should be called before generating start condition.
- * @retval None
- */
-void I2C_SlaveAddressConfig(I2C_TypeDef* I2Cx, uint16_t Address)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_SLAVE_ADDRESS(Address));
-
- /* Get the old register value */
- tmpreg = I2Cx->CR2;
-
- /* Reset I2Cx SADD bit [9:0] */
- tmpreg &= (uint32_t)~((uint32_t)I2C_CR2_SADD);
-
- /* Set I2Cx SADD */
- tmpreg |= (uint32_t)((uint32_t)Address & I2C_CR2_SADD);
-
- /* Store the new register value */
- I2Cx->CR2 = tmpreg;
-}
-
-/**
- * @brief Enables or disables the I2C 10-bit addressing mode for the master.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param NewState: new state of the I2C 10-bit addressing mode.
- * This parameter can be: ENABLE or DISABLE.
- * @note This function should be called before generating start condition.
- * @retval None
- */
-void I2C_10BitAddressingModeCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable 10-bit addressing mode */
- I2Cx->CR2 |= I2C_CR2_ADD10;
- }
- else
- {
- /* Disable 10-bit addressing mode */
- I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_ADD10);
- }
-}
-
-/**
- * @}
- */
-
-
-/** @defgroup I2C_Group2 Communications handling functions
- * @brief Communications handling functions
- *
-@verbatim
- ===============================================================================
- ##### Communications handling functions #####
- ===============================================================================
- [..] This section provides a set of functions that handles I2C communication.
-
- [..] Automatic End mode is enabled using I2C_AutoEndCmd() function. When Reload
- mode is enabled via I2C_ReloadCmd() AutoEnd bit has no effect.
-
- [..] I2C_NumberOfBytesConfig() function set the number of bytes to be transferred,
- this configuration should be done before generating start condition in master
- mode.
-
- [..] When switching from master write operation to read operation in 10Bit addressing
- mode, master can only sends the 1st 7 bits of the 10 bit address, followed by
- Read direction by enabling HEADR bit using I2C_10BitAddressHeader() function.
-
- [..] In master mode, when transferring more than 255 bytes Reload mode should be used
- to handle communication. In the first phase of transfer, Nbytes should be set to
- 255. After transferring these bytes TCR flag is set and I2C_TransferHandling()
- function should be called to handle remaining communication.
-
- [..] In master mode, when software end mode is selected when all data is transferred
- TC flag is set I2C_TransferHandling() function should be called to generate STOP
- or generate ReStart.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the I2C automatic end mode (stop condition is
- * automatically sent when nbytes data are transferred).
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param NewState: new state of the I2C automatic end mode.
- * This parameter can be: ENABLE or DISABLE.
- * @note This function has effect if Reload mode is disabled.
- * @retval None
- */
-void I2C_AutoEndCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable Auto end mode */
- I2Cx->CR2 |= I2C_CR2_AUTOEND;
- }
- else
- {
- /* Disable Auto end mode */
- I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_AUTOEND);
- }
-}
-
-/**
- * @brief Enables or disables the I2C nbytes reload mode.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param NewState: new state of the nbytes reload mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_ReloadCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable Auto Reload mode */
- I2Cx->CR2 |= I2C_CR2_RELOAD;
- }
- else
- {
- /* Disable Auto Reload mode */
- I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_RELOAD);
- }
-}
-
-/**
- * @brief Configures the number of bytes to be transmitted/received.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param Number_Bytes: specifies the number of bytes to be programmed.
- * @retval None
- */
-void I2C_NumberOfBytesConfig(I2C_TypeDef* I2Cx, uint8_t Number_Bytes)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-
- /* Get the old register value */
- tmpreg = I2Cx->CR2;
-
- /* Reset I2Cx Nbytes bit [7:0] */
- tmpreg &= (uint32_t)~((uint32_t)I2C_CR2_NBYTES);
-
- /* Set I2Cx Nbytes */
- tmpreg |= (uint32_t)(((uint32_t)Number_Bytes << 16 ) & I2C_CR2_NBYTES);
-
- /* Store the new register value */
- I2Cx->CR2 = tmpreg;
-}
-
-/**
- * @brief Configures the type of transfer request for the master.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param I2C_Direction: specifies the transfer request direction to be programmed.
- * This parameter can be one of the following values:
- * @arg I2C_Direction_Transmitter: Master request a write transfer
- * @arg I2C_Direction_Receiver: Master request a read transfer
- * @retval None
- */
-void I2C_MasterRequestConfig(I2C_TypeDef* I2Cx, uint16_t I2C_Direction)
-{
-/* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_DIRECTION(I2C_Direction));
-
- /* Test on the direction to set/reset the read/write bit */
- if (I2C_Direction == I2C_Direction_Transmitter)
- {
- /* Request a write Transfer */
- I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_RD_WRN);
- }
- else
- {
- /* Request a read Transfer */
- I2Cx->CR2 |= I2C_CR2_RD_WRN;
- }
-}
-
-/**
- * @brief Generates I2Cx communication START condition.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param NewState: new state of the I2C START condition generation.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Generate a START condition */
- I2Cx->CR2 |= I2C_CR2_START;
- }
- else
- {
- /* Disable the START condition generation */
- I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_START);
- }
-}
-
-/**
- * @brief Generates I2Cx communication STOP condition.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param NewState: new state of the I2C STOP condition generation.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Generate a STOP condition */
- I2Cx->CR2 |= I2C_CR2_STOP;
- }
- else
- {
- /* Disable the STOP condition generation */
- I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_STOP);
- }
-}
-
-/**
- * @brief Enables or disables the I2C 10-bit header only mode with read direction.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param NewState: new state of the I2C 10-bit header only mode.
- * This parameter can be: ENABLE or DISABLE.
- * @note This mode can be used only when switching from master transmitter mode
- * to master receiver mode.
- * @retval None
- */
-void I2C_10BitAddressHeaderCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable 10-bit header only mode */
- I2Cx->CR2 |= I2C_CR2_HEAD10R;
- }
- else
- {
- /* Disable 10-bit header only mode */
- I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_HEAD10R);
- }
-}
-
-/**
- * @brief Generates I2C communication Acknowledge.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param NewState: new state of the Acknowledge.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable ACK generation */
- I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_NACK);
- }
- else
- {
- /* Enable NACK generation */
- I2Cx->CR2 |= I2C_CR2_NACK;
- }
-}
-
-/**
- * @brief Returns the I2C slave matched address .
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @retval The value of the slave matched address .
- */
-uint8_t I2C_GetAddressMatched(I2C_TypeDef* I2Cx)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-
- /* Return the slave matched address in the SR1 register */
- return (uint8_t)(((uint32_t)I2Cx->ISR & I2C_ISR_ADDCODE) >> 16) ;
-}
-
-/**
- * @brief Returns the I2C slave received request.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @retval The value of the received request.
- */
-uint16_t I2C_GetTransferDirection(I2C_TypeDef* I2Cx)
-{
- uint32_t tmpreg = 0;
- uint16_t direction = 0;
-
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-
- /* Return the slave matched address in the SR1 register */
- tmpreg = (uint32_t)(I2Cx->ISR & I2C_ISR_DIR);
-
- /* If write transfer is requested */
- if (tmpreg == 0)
- {
- /* write transfer is requested */
- direction = I2C_Direction_Transmitter;
- }
- else
- {
- /* Read transfer is requested */
- direction = I2C_Direction_Receiver;
- }
- return direction;
-}
-
-/**
- * @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param Address: specifies the slave address to be programmed.
- * @param Number_Bytes: specifies the number of bytes to be programmed.
- * This parameter must be a value between 0 and 255.
- * @param ReloadEndMode: new state of the I2C START condition generation.
- * This parameter can be one of the following values:
- * @arg I2C_Reload_Mode: Enable Reload mode .
- * @arg I2C_AutoEnd_Mode: Enable Automatic end mode.
- * @arg I2C_SoftEnd_Mode: Enable Software end mode.
- * @param StartStopMode: new state of the I2C START condition generation.
- * This parameter can be one of the following values:
- * @arg I2C_No_StartStop: Don't Generate stop and start condition.
- * @arg I2C_Generate_Stop: Generate stop condition (Number_Bytes should be set to 0).
- * @arg I2C_Generate_Start_Read: Generate Restart for read request.
- * @arg I2C_Generate_Start_Write: Generate Restart for write request.
- * @retval None
- */
-void I2C_TransferHandling(I2C_TypeDef* I2Cx, uint16_t Address, uint8_t Number_Bytes, uint32_t ReloadEndMode, uint32_t StartStopMode)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_SLAVE_ADDRESS(Address));
- assert_param(IS_RELOAD_END_MODE(ReloadEndMode));
- assert_param(IS_START_STOP_MODE(StartStopMode));
-
- /* Get the CR2 register value */
- tmpreg = I2Cx->CR2;
-
- /* clear tmpreg specific bits */
- tmpreg &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP));
-
- /* update tmpreg */
- tmpreg |= (uint32_t)(((uint32_t)Address & I2C_CR2_SADD) | (((uint32_t)Number_Bytes << 16 ) & I2C_CR2_NBYTES) | \
- (uint32_t)ReloadEndMode | (uint32_t)StartStopMode);
-
- /* update CR2 register */
- I2Cx->CR2 = tmpreg;
-}
-
-/**
- * @}
- */
-
-
-/** @defgroup I2C_Group3 SMBUS management functions
- * @brief SMBUS management functions
- *
-@verbatim
- ===============================================================================
- ##### SMBUS management functions #####
- ===============================================================================
- [..] This section provides a set of functions that handles SMBus communication
- and timeouts detection.
-
- [..] The SMBus Device default address (0b1100 001) is enabled by calling I2C_Init()
- function and setting I2C_Mode member of I2C_InitTypeDef() structure to
- I2C_Mode_SMBusDevice.
-
- [..] The SMBus Host address (0b0001 000) is enabled by calling I2C_Init()
- function and setting I2C_Mode member of I2C_InitTypeDef() structure to
- I2C_Mode_SMBusHost.
-
- [..] The Alert Response Address (0b0001 100) is enabled using I2C_SMBusAlertCmd()
- function.
-
- [..] To detect cumulative SCL stretch in master and slave mode, TIMEOUTB should be
- configured (in accordance to SMBus specification) using I2C_TimeoutBConfig()
- function then I2C_ExtendedClockTimeoutCmd() function should be called to enable
- the detection.
-
- [..] SCL low timeout is detected by configuring TIMEOUTB using I2C_TimeoutBConfig()
- function followed by the call of I2C_ClockTimeoutCmd(). When adding to this
- procedure the call of I2C_IdleClockTimeoutCmd() function, Bus Idle condition
- (both SCL and SDA high) is detected also.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables I2C SMBus alert.
- * @param I2Cx: where x can be 1 to select the I2C peripheral.
- * @param NewState: new state of the I2Cx SMBus alert.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_SMBusAlertCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_1_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable SMBus alert */
- I2Cx->CR1 |= I2C_CR1_ALERTEN;
- }
- else
- {
- /* Disable SMBus alert */
- I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_ALERTEN);
- }
-}
-
-/**
- * @brief Enables or disables I2C Clock Timeout (SCL Timeout detection).
- * @param I2Cx: where x can be 1 to select the I2C peripheral.
- * @param NewState: new state of the I2Cx clock Timeout.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_ClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_1_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable Clock Timeout */
- I2Cx->TIMEOUTR |= I2C_TIMEOUTR_TIMOUTEN;
- }
- else
- {
- /* Disable Clock Timeout */
- I2Cx->TIMEOUTR &= (uint32_t)~((uint32_t)I2C_TIMEOUTR_TIMOUTEN);
- }
-}
-
-/**
- * @brief Enables or disables I2C Extended Clock Timeout (SCL cumulative Timeout detection).
- * @param I2Cx: where x can be 1 to select the I2C peripheral.
- * @param NewState: new state of the I2Cx Extended clock Timeout.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_ExtendedClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_1_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable Clock Timeout */
- I2Cx->TIMEOUTR |= I2C_TIMEOUTR_TEXTEN;
- }
- else
- {
- /* Disable Clock Timeout */
- I2Cx->TIMEOUTR &= (uint32_t)~((uint32_t)I2C_TIMEOUTR_TEXTEN);
- }
-}
-
-/**
- * @brief Enables or disables I2C Idle Clock Timeout (Bus idle SCL and SDA
- * high detection).
- * @param I2Cx: where x can be 1 to select the I2C peripheral.
- * @param NewState: new state of the I2Cx Idle clock Timeout.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_IdleClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_1_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable Clock Timeout */
- I2Cx->TIMEOUTR |= I2C_TIMEOUTR_TIDLE;
- }
- else
- {
- /* Disable Clock Timeout */
- I2Cx->TIMEOUTR &= (uint32_t)~((uint32_t)I2C_TIMEOUTR_TIDLE);
- }
-}
-
-/**
- * @brief Configures the I2C Bus Timeout A (SCL Timeout when TIDLE = 0 or Bus
- * idle SCL and SDA high when TIDLE = 1).
- * @param I2Cx: where x can be 1 to select the I2C peripheral.
- * @param Timeout: specifies the TimeoutA to be programmed.
- * @retval None
- */
-void I2C_TimeoutAConfig(I2C_TypeDef* I2Cx, uint16_t Timeout)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_I2C_1_PERIPH(I2Cx));
- assert_param(IS_I2C_TIMEOUT(Timeout));
-
- /* Get the old register value */
- tmpreg = I2Cx->TIMEOUTR;
-
- /* Reset I2Cx TIMEOUTA bit [11:0] */
- tmpreg &= (uint32_t)~((uint32_t)I2C_TIMEOUTR_TIMEOUTA);
-
- /* Set I2Cx TIMEOUTA */
- tmpreg |= (uint32_t)((uint32_t)Timeout & I2C_TIMEOUTR_TIMEOUTA) ;
-
- /* Store the new register value */
- I2Cx->TIMEOUTR = tmpreg;
-}
-
-/**
- * @brief Configures the I2C Bus Timeout B (SCL cumulative Timeout).
- * @param I2Cx: where x can be 1 to select the I2C peripheral.
- * @param Timeout: specifies the TimeoutB to be programmed.
- * @retval None
- */
-void I2C_TimeoutBConfig(I2C_TypeDef* I2Cx, uint16_t Timeout)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_I2C_1_PERIPH(I2Cx));
- assert_param(IS_I2C_TIMEOUT(Timeout));
-
- /* Get the old register value */
- tmpreg = I2Cx->TIMEOUTR;
-
- /* Reset I2Cx TIMEOUTB bit [11:0] */
- tmpreg &= (uint32_t)~((uint32_t)I2C_TIMEOUTR_TIMEOUTB);
-
- /* Set I2Cx TIMEOUTB */
- tmpreg |= (uint32_t)(((uint32_t)Timeout << 16) & I2C_TIMEOUTR_TIMEOUTB) ;
-
- /* Store the new register value */
- I2Cx->TIMEOUTR = tmpreg;
-}
-
-/**
- * @brief Enables or disables I2C PEC calculation.
- * @param I2Cx: where x can be 1 to select the I2C peripheral.
- * @param NewState: new state of the I2Cx PEC calculation.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_1_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable PEC calculation */
- I2Cx->CR1 |= I2C_CR1_PECEN;
- }
- else
- {
- /* Disable PEC calculation */
- I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_PECEN);
- }
-}
-
-/**
- * @brief Enables or disables I2C PEC transmission/reception request.
- * @param I2Cx: where x can be 1 to select the I2C peripheral.
- * @param NewState: new state of the I2Cx PEC request.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_PECRequestCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_1_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable PEC transmission/reception request */
- I2Cx->CR1 |= I2C_CR2_PECBYTE;
- }
- else
- {
- /* Disable PEC transmission/reception request */
- I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR2_PECBYTE);
- }
-}
-
-/**
- * @brief Returns the I2C PEC.
- * @param I2Cx: where x can be 1 to select the I2C peripheral.
- * @retval The value of the PEC .
- */
-uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx)
-{
- /* Check the parameters */
- assert_param(IS_I2C_1_PERIPH(I2Cx));
-
- /* Return the slave matched address in the SR1 register */
- return (uint8_t)((uint32_t)I2Cx->PECR & I2C_PECR_PEC);
-}
-
-/**
- * @}
- */
-
-
-/** @defgroup I2C_Group4 I2C registers management functions
- * @brief I2C registers management functions
- *
-@verbatim
- ===============================================================================
- ##### I2C registers management functions #####
- ===============================================================================
- [..] This section provides a functions that allow user the management of
- I2C registers.
-
-@endverbatim
- * @{
- */
-
- /**
- * @brief Reads the specified I2C register and returns its value.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param I2C_Register: specifies the register to read.
- * This parameter can be one of the following values:
- * @arg I2C_Register_CR1: CR1 register.
- * @arg I2C_Register_CR2: CR2 register.
- * @arg I2C_Register_OAR1: OAR1 register.
- * @arg I2C_Register_OAR2: OAR2 register.
- * @arg I2C_Register_TIMINGR: TIMING register.
- * @arg I2C_Register_TIMEOUTR: TIMEOUTR register.
- * @arg I2C_Register_ISR: ISR register.
- * @arg I2C_Register_ICR: ICR register.
- * @arg I2C_Register_PECR: PECR register.
- * @arg I2C_Register_RXDR: RXDR register.
- * @arg I2C_Register_TXDR: TXDR register.
- * @retval The value of the read register.
- */
-uint32_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register)
-{
- __IO uint32_t tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_REGISTER(I2C_Register));
-
- tmp = (uint32_t)I2Cx;
- tmp += I2C_Register;
-
- /* Return the selected register value */
- return (*(__IO uint32_t *) tmp);
-}
-
-/**
- * @}
- */
-
-/** @defgroup I2C_Group5 Data transfers management functions
- * @brief Data transfers management functions
- *
-@verbatim
- ===============================================================================
- ##### Data transfers management functions #####
- ===============================================================================
- [..] This subsection provides a set of functions allowing to manage
- the I2C data transfers.
-
- [..] The read access of the I2C_RXDR register can be done using
- the I2C_ReceiveData() function and returns the received value.
- Whereas a write access to the I2C_TXDR can be done using I2C_SendData()
- function and stores the written data into TXDR.
-@endverbatim
- * @{
- */
-
-/**
- * @brief Sends a data byte through the I2Cx peripheral.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param Data: Byte to be transmitted..
- * @retval None
- */
-void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-
- /* Write in the DR register the data to be sent */
- I2Cx->TXDR = (uint8_t)Data;
-}
-
-/**
- * @brief Returns the most recent received data by the I2Cx peripheral.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @retval The value of the received data.
- */
-uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
-
- /* Return the data in the DR register */
- return (uint8_t)I2Cx->RXDR;
-}
-
-/**
- * @}
- */
-
-
-/** @defgroup I2C_Group6 DMA transfers management functions
- * @brief DMA transfers management functions
- *
-@verbatim
- ===============================================================================
- ##### DMA transfers management functions #####
- ===============================================================================
- [..] This section provides two functions that can be used only in DMA mode.
- [..] In DMA Mode, the I2C communication can be managed by 2 DMA Channel
- requests:
- (#) I2C_DMAReq_Tx: specifies the Tx buffer DMA transfer request.
- (#) I2C_DMAReq_Rx: specifies the Rx buffer DMA transfer request.
- [..] In this Mode it is advised to use the following function:
- (+) I2C_DMACmd(I2C_TypeDef* I2Cx, uint32_t I2C_DMAReq, FunctionalState NewState);
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the I2C DMA interface.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param I2C_DMAReq: specifies the I2C DMA transfer request to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg I2C_DMAReq_Tx: Tx DMA transfer request
- * @arg I2C_DMAReq_Rx: Rx DMA transfer request
- * @param NewState: new state of the selected I2C DMA transfer request.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2C_DMACmd(I2C_TypeDef* I2Cx, uint32_t I2C_DMAReq, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- assert_param(IS_I2C_DMA_REQ(I2C_DMAReq));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected I2C DMA requests */
- I2Cx->CR1 |= I2C_DMAReq;
- }
- else
- {
- /* Disable the selected I2C DMA requests */
- I2Cx->CR1 &= (uint32_t)~I2C_DMAReq;
- }
-}
-/**
- * @}
- */
-
-
-/** @defgroup I2C_Group7 Interrupts and flags management functions
- * @brief Interrupts and flags management functions
- *
-@verbatim
- ===============================================================================
- ##### Interrupts and flags management functions #####
- ===============================================================================
- [..] This section provides functions allowing to configure the I2C Interrupts
- sources and check or clear the flags or pending bits status.
- The user should identify which mode will be used in his application to manage
- the communication: Polling mode, Interrupt mode or DMA mode(refer I2C_Group6).
-
- *** Polling Mode ***
- ====================
- [..] In Polling Mode, the I2C communication can be managed by 15 flags:
- (#) I2C_FLAG_TXE: to indicate the status of Transmit data register empty flag.
- (#) I2C_FLAG_TXIS: to indicate the status of Transmit interrupt status flag .
- (#) I2C_FLAG_RXNE: to indicate the status of Receive data register not empty flag.
- (#) I2C_FLAG_ADDR: to indicate the status of Address matched flag (slave mode).
- (#) I2C_FLAG_NACKF: to indicate the status of NACK received flag.
- (#) I2C_FLAG_STOPF: to indicate the status of STOP detection flag.
- (#) I2C_FLAG_TC: to indicate the status of Transfer complete flag(master mode).
- (#) I2C_FLAG_TCR: to indicate the status of Transfer complete reload flag.
- (#) I2C_FLAG_BERR: to indicate the status of Bus error flag.
- (#) I2C_FLAG_ARLO: to indicate the status of Arbitration lost flag.
- (#) I2C_FLAG_OVR: to indicate the status of Overrun/Underrun flag.
- (#) I2C_FLAG_PECERR: to indicate the status of PEC error in reception flag.
- (#) I2C_FLAG_TIMEOUT: to indicate the status of Timeout or Tlow detection flag.
- (#) I2C_FLAG_ALERT: to indicate the status of SMBus Alert flag.
- (#) I2C_FLAG_BUSY: to indicate the status of Bus busy flag.
-
- [..] In this Mode it is advised to use the following functions:
- (+) FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
- (+) void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
-
- [..]
- (@)Do not use the BUSY flag to handle each data transmission or reception.It is
- better to use the TXIS and RXNE flags instead.
-
- *** Interrupt Mode ***
- ======================
- [..] In Interrupt Mode, the I2C communication can be managed by 7 interrupt sources
- and 15 pending bits:
- [..] Interrupt Source:
- (#) I2C_IT_ERRI: specifies the interrupt source for the Error interrupt.
- (#) I2C_IT_TCI: specifies the interrupt source for the Transfer Complete interrupt.
- (#) I2C_IT_STOPI: specifies the interrupt source for the Stop Detection interrupt.
- (#) I2C_IT_NACKI: specifies the interrupt source for the Not Acknowledge received interrupt.
- (#) I2C_IT_ADDRI: specifies the interrupt source for the Address Match interrupt.
- (#) I2C_IT_RXI: specifies the interrupt source for the RX interrupt.
- (#) I2C_IT_TXI: specifies the interrupt source for the TX interrupt.
-
- [..] Pending Bits:
- (#) I2C_IT_TXIS: to indicate the status of Transmit interrupt status flag.
- (#) I2C_IT_RXNE: to indicate the status of Receive data register not empty flag.
- (#) I2C_IT_ADDR: to indicate the status of Address matched flag (slave mode).
- (#) I2C_IT_NACKF: to indicate the status of NACK received flag.
- (#) I2C_IT_STOPF: to indicate the status of STOP detection flag.
- (#) I2C_IT_TC: to indicate the status of Transfer complete flag (master mode).
- (#) I2C_IT_TCR: to indicate the status of Transfer complete reload flag.
- (#) I2C_IT_BERR: to indicate the status of Bus error flag.
- (#) I2C_IT_ARLO: to indicate the status of Arbitration lost flag.
- (#) I2C_IT_OVR: to indicate the status of Overrun/Underrun flag.
- (#) I2C_IT_PECERR: to indicate the status of PEC error in reception flag.
- (#) I2C_IT_TIMEOUT: to indicate the status of Timeout or Tlow detection flag.
- (#) I2C_IT_ALERT: to indicate the status of SMBus Alert flag.
-
- [..] In this Mode it is advised to use the following functions:
- (+) void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
- (+) ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Checks whether the specified I2C flag is set or not.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param I2C_FLAG: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg I2C_FLAG_TXE: Transmit data register empty
- * @arg I2C_FLAG_TXIS: Transmit interrupt status
- * @arg I2C_FLAG_RXNE: Receive data register not empty
- * @arg I2C_FLAG_ADDR: Address matched (slave mode)
- * @arg I2C_FLAG_NACKF: NACK received flag
- * @arg I2C_FLAG_STOPF: STOP detection flag
- * @arg I2C_FLAG_TC: Transfer complete (master mode)
- * @arg I2C_FLAG_TCR: Transfer complete reload
- * @arg I2C_FLAG_BERR: Bus error
- * @arg I2C_FLAG_ARLO: Arbitration lost
- * @arg I2C_FLAG_OVR: Overrun/Underrun
- * @arg I2C_FLAG_PECERR: PEC error in reception
- * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow detection flag
- * @arg I2C_FLAG_ALERT: SMBus Alert
- * @arg I2C_FLAG_BUSY: Bus busy
- * @retval The new state of I2C_FLAG (SET or RESET).
- */
-FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG)
-{
- uint32_t tmpreg = 0;
- FlagStatus bitstatus = RESET;
-
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_GET_FLAG(I2C_FLAG));
-
- /* Get the ISR register value */
- tmpreg = I2Cx->ISR;
-
- /* Get flag status */
- tmpreg &= I2C_FLAG;
-
- if(tmpreg != 0)
- {
- /* I2C_FLAG is set */
- bitstatus = SET;
- }
- else
- {
- /* I2C_FLAG is reset */
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Clears the I2Cx's pending flags.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param I2C_FLAG: specifies the flag to clear.
- * This parameter can be any combination of the following values:
- * @arg I2C_FLAG_ADDR: Address matched (slave mode)
- * @arg I2C_FLAG_NACKF: NACK received flag
- * @arg I2C_FLAG_STOPF: STOP detection flag
- * @arg I2C_FLAG_BERR: Bus error
- * @arg I2C_FLAG_ARLO: Arbitration lost
- * @arg I2C_FLAG_OVR: Overrun/Underrun
- * @arg I2C_FLAG_PECERR: PEC error in reception
- * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow detection flag
- * @arg I2C_FLAG_ALERT: SMBus Alert
- * @retval The new state of I2C_FLAG (SET or RESET).
- */
-void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_CLEAR_FLAG(I2C_FLAG));
-
- /* Clear the selected flag */
- I2Cx->ICR = I2C_FLAG;
- }
-
-/**
- * @brief Checks whether the specified I2C interrupt has occurred or not.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param I2C_IT: specifies the interrupt source to check.
- * This parameter can be one of the following values:
- * @arg I2C_IT_TXIS: Transmit interrupt status
- * @arg I2C_IT_RXNE: Receive data register not empty
- * @arg I2C_IT_ADDR: Address matched (slave mode)
- * @arg I2C_IT_NACKF: NACK received flag
- * @arg I2C_IT_STOPF: STOP detection flag
- * @arg I2C_IT_TC: Transfer complete (master mode)
- * @arg I2C_IT_TCR: Transfer complete reload
- * @arg I2C_IT_BERR: Bus error
- * @arg I2C_IT_ARLO: Arbitration lost
- * @arg I2C_IT_OVR: Overrun/Underrun
- * @arg I2C_IT_PECERR: PEC error in reception
- * @arg I2C_IT_TIMEOUT: Timeout or Tlow detection flag
- * @arg I2C_IT_ALERT: SMBus Alert
- * @retval The new state of I2C_IT (SET or RESET).
- */
-ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT)
-{
- uint32_t tmpreg = 0;
- ITStatus bitstatus = RESET;
- uint32_t enablestatus = 0;
-
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_GET_IT(I2C_IT));
-
- /* Check if the interrupt source is enabled or not */
- /* If Error interrupt */
- if ((uint32_t)(I2C_IT & ERROR_IT_MASK))
- {
- enablestatus = (uint32_t)((I2C_CR1_ERRIE) & (I2Cx->CR1));
- }
- /* If TC interrupt */
- else if ((uint32_t)(I2C_IT & TC_IT_MASK))
- {
- enablestatus = (uint32_t)((I2C_CR1_TCIE) & (I2Cx->CR1));
- }
- else
- {
- enablestatus = (uint32_t)((I2C_IT) & (I2Cx->CR1));
- }
-
- /* Get the ISR register value */
- tmpreg = I2Cx->ISR;
-
- /* Get flag status */
- tmpreg &= I2C_IT;
-
- /* Check the status of the specified I2C flag */
- if((tmpreg != RESET) && enablestatus)
- {
- /* I2C_IT is set */
- bitstatus = SET;
- }
- else
- {
- /* I2C_IT is reset */
- bitstatus = RESET;
- }
-
- /* Return the I2C_IT status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the I2Cx's interrupt pending bits.
- * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
- * @param I2C_IT: specifies the interrupt pending bit to clear.
- * This parameter can be any combination of the following values:
- * @arg I2C_IT_ADDR: Address matched (slave mode)
- * @arg I2C_IT_NACKF: NACK received flag
- * @arg I2C_IT_STOPF: STOP detection flag
- * @arg I2C_IT_BERR: Bus error
- * @arg I2C_IT_ARLO: Arbitration lost
- * @arg I2C_IT_OVR: Overrun/Underrun
- * @arg I2C_IT_PECERR: PEC error in reception
- * @arg I2C_IT_TIMEOUT: Timeout or Tlow detection flag
- * @arg I2C_IT_ALERT: SMBus Alert
- * @retval The new state of I2C_IT (SET or RESET).
- */
-void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT)
-{
- /* Check the parameters */
- assert_param(IS_I2C_ALL_PERIPH(I2Cx));
- assert_param(IS_I2C_CLEAR_IT(I2C_IT));
-
- /* Clear the selected flag */
- I2Cx->ICR = I2C_IT;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_iwdg.c b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_iwdg.c
deleted file mode 100644
index 2eca2c83c9e302e195aa7346e009cc9cee768119..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_iwdg.c
+++ /dev/null
@@ -1,293 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f0xx_iwdg.c
- * @author MCD Application Team
- * @version V1.3.0
- * @date 16-January-2014
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Independent watchdog (IWDG) peripheral:
- * + Prescaler and Counter configuration
- * + IWDG activation
- * + Flag management
- *
- * @verbatim
- *
- ==============================================================================
- ##### IWDG features #####
- ==============================================================================
- [..] The IWDG can be started by either software or hardware (configurable
- through option byte).
-
- [..] The IWDG is clocked by its own dedicated low-speed clock (LSI) and
- thus stays active even if the main clock fails.
- Once the IWDG is started, the LSI is forced ON and cannot be disabled
- (LSI cannot be disabled too), and the counter starts counting down from
- the reset value of 0xFFF. When it reaches the end of count value (0x000)
- a system reset is generated.
- The IWDG counter should be reloaded at regular intervals to prevent
- an MCU reset.
-
- [..] The IWDG is implemented in the VDD voltage domain that is still functional
- in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY).
-
- [..] IWDGRST flag in RCC_CSR register can be used to inform when a IWDG
- reset occurs.
-
- [..] Min-max timeout value @40KHz (LSI): ~0.1ms / ~28.3s
- The IWDG timeout may vary due to LSI frequency dispersion. STM32F0xx
- devices provide the capability to measure the LSI frequency (LSI clock
- should be seleted as RTC clock which is internally connected to TIM10 CH1
- input capture). The measured value can be used to have an IWDG timeout with
- an acceptable accuracy.
- For more information, please refer to the STM32F0xx Reference manual.
-
- ##### How to use this driver #####
- ==============================================================================
- [..] This driver allows to use IWDG peripheral with either window option enabled
- or disabled. To do so follow one of the two procedures below.
- (#) Window option is enabled:
- (++) Start the IWDG using IWDG_Enable() function, when the IWDG is used
- in software mode (no need to enable the LSI, it will be enabled
- by hardware).
- (++) Enable write access to IWDG_PR and IWDG_RLR registers using
- IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable) function.
- (++) Configure the IWDG prescaler using IWDG_SetPrescaler() function.
- (++) Configure the IWDG counter value using IWDG_SetReload() function.
- This value will be loaded in the IWDG counter each time the counter
- is reloaded, then the IWDG will start counting down from this value.
- (++) Wait for the IWDG registers to be updated using IWDG_GetFlagStatus() function.
- (++) Configure the IWDG refresh window using IWDG_SetWindowValue() function.
-
- (#) Window option is disabled:
- (++) Enable write access to IWDG_PR and IWDG_RLR registers using
- IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable) function.
- (++) Configure the IWDG prescaler using IWDG_SetPrescaler() function.
- (++) Configure the IWDG counter value using IWDG_SetReload() function.
- This value will be loaded in the IWDG counter each time the counter
- is reloaded, then the IWDG will start counting down from this value.
- (++) Wait for the IWDG registers to be updated using IWDG_GetFlagStatus() function.
- (++) reload the IWDG counter at regular intervals during normal operation
- to prevent an MCU reset, using IWDG_ReloadCounter() function.
- (++) Start the IWDG using IWDG_Enable() function, when the IWDG is used
- in software mode (no need to enable the LSI, it will be enabled
- by hardware).
-
- @endverbatim
- *
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx_iwdg.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup IWDG
- * @brief IWDG driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* ---------------------- IWDG registers bit mask ----------------------------*/
-/* KR register bit mask */
-#define KR_KEY_RELOAD ((uint16_t)0xAAAA)
-#define KR_KEY_ENABLE ((uint16_t)0xCCCC)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup IWDG_Private_Functions
- * @{
- */
-
-/** @defgroup IWDG_Group1 Prescaler and Counter configuration functions
- * @brief Prescaler and Counter configuration functions
- *
-@verbatim
- ==============================================================================
- ##### Prescaler and Counter configuration functions #####
- ==============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables write access to IWDG_PR and IWDG_RLR registers.
- * @param IWDG_WriteAccess: new state of write access to IWDG_PR and IWDG_RLR registers.
- * This parameter can be one of the following values:
- * @arg IWDG_WriteAccess_Enable: Enable write access to IWDG_PR and IWDG_RLR registers
- * @arg IWDG_WriteAccess_Disable: Disable write access to IWDG_PR and IWDG_RLR registers
- * @retval None
- */
-void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess)
-{
- /* Check the parameters */
- assert_param(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess));
- IWDG->KR = IWDG_WriteAccess;
-}
-
-/**
- * @brief Sets IWDG Prescaler value.
- * @param IWDG_Prescaler: specifies the IWDG Prescaler value.
- * This parameter can be one of the following values:
- * @arg IWDG_Prescaler_4: IWDG prescaler set to 4
- * @arg IWDG_Prescaler_8: IWDG prescaler set to 8
- * @arg IWDG_Prescaler_16: IWDG prescaler set to 16
- * @arg IWDG_Prescaler_32: IWDG prescaler set to 32
- * @arg IWDG_Prescaler_64: IWDG prescaler set to 64
- * @arg IWDG_Prescaler_128: IWDG prescaler set to 128
- * @arg IWDG_Prescaler_256: IWDG prescaler set to 256
- * @retval None
- */
-void IWDG_SetPrescaler(uint8_t IWDG_Prescaler)
-{
- /* Check the parameters */
- assert_param(IS_IWDG_PRESCALER(IWDG_Prescaler));
- IWDG->PR = IWDG_Prescaler;
-}
-
-/**
- * @brief Sets IWDG Reload value.
- * @param Reload: specifies the IWDG Reload value.
- * This parameter must be a number between 0 and 0x0FFF.
- * @retval None
- */
-void IWDG_SetReload(uint16_t Reload)
-{
- /* Check the parameters */
- assert_param(IS_IWDG_RELOAD(Reload));
- IWDG->RLR = Reload;
-}
-
-/**
- * @brief Reloads IWDG counter with value defined in the reload register
- * (write access to IWDG_PR and IWDG_RLR registers disabled).
- * @param None
- * @retval None
- */
-void IWDG_ReloadCounter(void)
-{
- IWDG->KR = KR_KEY_RELOAD;
-}
-
-
-/**
- * @brief Sets the IWDG window value.
- * @param WindowValue: specifies the window value to be compared to the downcounter.
- * @retval None
- */
-void IWDG_SetWindowValue(uint16_t WindowValue)
-{
- /* Check the parameters */
- assert_param(IS_IWDG_WINDOW_VALUE(WindowValue));
- IWDG->WINR = WindowValue;
-}
-
-/**
- * @}
- */
-
-/** @defgroup IWDG_Group2 IWDG activation function
- * @brief IWDG activation function
- *
-@verbatim
- ==============================================================================
- ##### IWDG activation function #####
- ==============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled).
- * @param None
- * @retval None
- */
-void IWDG_Enable(void)
-{
- IWDG->KR = KR_KEY_ENABLE;
-}
-
-/**
- * @}
- */
-
-/** @defgroup IWDG_Group3 Flag management function
- * @brief Flag management function
- *
-@verbatim
- ===============================================================================
- ##### Flag management function #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Checks whether the specified IWDG flag is set or not.
- * @param IWDG_FLAG: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg IWDG_FLAG_PVU: Prescaler Value Update on going
- * @arg IWDG_FLAG_RVU: Reload Value Update on going
- * @arg IWDG_FLAG_WVU: Counter Window Value Update on going
- * @retval The new state of IWDG_FLAG (SET or RESET).
- */
-FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG)
-{
- FlagStatus bitstatus = RESET;
- /* Check the parameters */
- assert_param(IS_IWDG_FLAG(IWDG_FLAG));
- if ((IWDG->SR & IWDG_FLAG) != (uint32_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- /* Return the flag status */
- return bitstatus;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_misc.c b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_misc.c
deleted file mode 100644
index 1ace673c89c9eb6ebb5d9aa28410dbb9dd762aa2..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_misc.c
+++ /dev/null
@@ -1,167 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f0xx_misc.c
- * @author MCD Application Team
- * @version V1.3.0
- * @date 16-January-2014
- * @brief This file provides all the miscellaneous firmware functions (add-on
- * to CMSIS functions).
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx_misc.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup MISC
- * @brief MISC driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup MISC_Private_Functions
- * @{
- */
-/**
- *
-@verbatim
- *******************************************************************************
- ##### Interrupts configuration functions #####
- *******************************************************************************
- [..] This section provide functions allowing to configure the NVIC interrupts
- (IRQ). The Cortex-M0 exceptions are managed by CMSIS functions.
- (#) Enable and Configure the priority of the selected IRQ Channels.
- The priority can be 0..3.
-
- -@- Lower priority values gives higher priority.
- -@- Priority Order:
- (#@) Lowest priority.
- (#@) Lowest hardware priority (IRQn position).
-
-@endverbatim
-*/
-
-/**
- * @brief Initializes the NVIC peripheral according to the specified
- * parameters in the NVIC_InitStruct.
- * @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains
- * the configuration information for the specified NVIC peripheral.
- * @retval None
- */
-void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct)
-{
- uint32_t tmppriority = 0x00;
-
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd));
- assert_param(IS_NVIC_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPriority));
-
- if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)
- {
- /* Compute the Corresponding IRQ Priority --------------------------------*/
- tmppriority = NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel >> 0x02];
- tmppriority &= (uint32_t)(~(((uint32_t)0xFF) << ((NVIC_InitStruct->NVIC_IRQChannel & 0x03) * 8)));
- tmppriority |= (uint32_t)((((uint32_t)NVIC_InitStruct->NVIC_IRQChannelPriority << 6) & 0xFF) << ((NVIC_InitStruct->NVIC_IRQChannel & 0x03) * 8));
-
- NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel >> 0x02] = tmppriority;
-
- /* Enable the Selected IRQ Channels --------------------------------------*/
- NVIC->ISER[0] = (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
- }
- else
- {
- /* Disable the Selected IRQ Channels -------------------------------------*/
- NVIC->ICER[0] = (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
- }
-}
-
-/**
- * @brief Selects the condition for the system to enter low power mode.
- * @param LowPowerMode: Specifies the new mode for the system to enter low power mode.
- * This parameter can be one of the following values:
- * @arg NVIC_LP_SEVONPEND: Low Power SEV on Pend.
- * @arg NVIC_LP_SLEEPDEEP: Low Power DEEPSLEEP request.
- * @arg NVIC_LP_SLEEPONEXIT: Low Power Sleep on Exit.
- * @param NewState: new state of LP condition.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_NVIC_LP(LowPowerMode));
-
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- SCB->SCR |= LowPowerMode;
- }
- else
- {
- SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode);
- }
-}
-
-/**
- * @brief Configures the SysTick clock source.
- * @param SysTick_CLKSource: specifies the SysTick clock source.
- * This parameter can be one of the following values:
- * @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source.
- * @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source.
- * @retval None
- */
-void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource)
-{
- /* Check the parameters */
- assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource));
-
- if (SysTick_CLKSource == SysTick_CLKSource_HCLK)
- {
- SysTick->CTRL |= SysTick_CLKSource_HCLK;
- }
- else
- {
- SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8;
- }
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_pwr.c b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_pwr.c
deleted file mode 100644
index 7c13ce4203566386d9ce33eb24a2860599534826..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_pwr.c
+++ /dev/null
@@ -1,566 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f0xx_pwr.c
- * @author MCD Application Team
- * @version V1.3.0
- * @date 16-January-2014
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Power Controller (PWR) peripheral:
- * + Backup Domain Access
- * + PVD configuration
- * + WakeUp pins configuration
- * + Low Power modes configuration
- * + Flags management
- *
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx_pwr.h"
-#include "stm32f0xx_rcc.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup PWR
- * @brief PWR driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-/* ------------------ PWR registers bit mask ------------------------ */
-
-/* CR register bit mask */
-#define CR_DS_MASK ((uint32_t)0xFFFFFFFC)
-#define CR_PLS_MASK ((uint32_t)0xFFFFFF1F)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup PWR_Private_Functions
- * @{
- */
-
-/** @defgroup PWR_Group1 Backup Domain Access function
- * @brief Backup Domain Access function
- *
-@verbatim
- ==============================================================================
- ##### Backup Domain Access function #####
- ==============================================================================
-
- [..] After reset, the Backup Domain Registers (RCC BDCR Register, RTC registers
- and RTC backup registers) are protected against possible stray write accesses.
- [..] To enable access to Backup domain use the PWR_BackupAccessCmd(ENABLE) function.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitializes the PWR peripheral registers to their default reset values.
- * @param None
- * @retval None
- */
-void PWR_DeInit(void)
-{
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE);
-}
-
-/**
- * @brief Enables or disables access to the Backup domain registers.
- * @note If the HSE divided by 32 is used as the RTC clock, the
- * Backup Domain Access should be kept enabled.
- * @param NewState: new state of the access to the Backup domain registers.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void PWR_BackupAccessCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the Backup Domain Access */
- PWR->CR |= PWR_CR_DBP;
- }
- else
- {
- /* Disable the Backup Domain Access */
- PWR->CR &= (uint32_t)~((uint32_t)PWR_CR_DBP);
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup PWR_Group2 PVD configuration functions
- * @brief PVD configuration functions
- *
-@verbatim
- ==============================================================================
- ##### PVD configuration functions #####
- ==============================================================================
- [..]
- (+) The PVD is used to monitor the VDD power supply by comparing it to a threshold
- selected by the PVD Level (PLS[2:0] bits in the PWR_CR).
- (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower than the
- PVD threshold. This event is internally connected to the EXTI line16
- and can generate an interrupt if enabled through the EXTI registers.
- (+) The PVD is stopped in Standby mode.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).
- * @note This function is not applicable for STM32F030 devices.
- * @param PWR_PVDLevel: specifies the PVD detection level
- * This parameter can be one of the following values:
- * @arg PWR_PVDLevel_0
- * @arg PWR_PVDLevel_1
- * @arg PWR_PVDLevel_2
- * @arg PWR_PVDLevel_3
- * @arg PWR_PVDLevel_4
- * @arg PWR_PVDLevel_5
- * @arg PWR_PVDLevel_6
- * @arg PWR_PVDLevel_7
- * @note Refer to the electrical characteristics of your device datasheet for
- * more details about the voltage threshold corresponding to each
- * detection level.
- * @retval None
- */
-void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel));
-
- tmpreg = PWR->CR;
-
- /* Clear PLS[7:5] bits */
- tmpreg &= CR_PLS_MASK;
-
- /* Set PLS[7:5] bits according to PWR_PVDLevel value */
- tmpreg |= PWR_PVDLevel;
-
- /* Store the new value */
- PWR->CR = tmpreg;
-}
-
-/**
- * @brief Enables or disables the Power Voltage Detector(PVD).
- * @note This function is not applicable for STM32F030 devices.
- * @param NewState: new state of the PVD.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void PWR_PVDCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the PVD */
- PWR->CR |= PWR_CR_PVDE;
- }
- else
- {
- /* Disable the PVD */
- PWR->CR &= (uint32_t)~((uint32_t)PWR_CR_PVDE);
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup PWR_Group3 WakeUp pins configuration functions
- * @brief WakeUp pins configuration functions
- *
-@verbatim
- ==============================================================================
- ##### WakeUp pin configuration functions #####
- ==============================================================================
-
- (+) WakeUp pins are used to wakeup the system from Standby mode. These pins are
- forced in input pull down configuration and are active on rising edges.
- (+) There are eight WakeUp pins: WakeUp Pin 1 on PA.00 and WakeUp Pin 2 on PC.13.
- The following WakeUp pins are only applicable for STM32F072 dvices:
- WakeUp Pin 3 on PE.06, WakeUp Pin 4 on PA.02, WakeUp Pin 5 on PC.05,
- WakeUp Pin 6 on PB.05, WakeUp Pin 7 on PB.15 and WakeUp Pin 8 on PF.02.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the WakeUp Pin functionality.
- * @param PWR_WakeUpPin: specifies the WakeUpPin.
- * This parameter can be one of the following values
- * @arg PWR_WakeUpPin_1
- * @arg PWR_WakeUpPin_2
- * @arg PWR_WakeUpPin_3, only applicable for STM32F072 devices
- * @arg PWR_WakeUpPin_4, only applicable for STM32F072 devices
- * @arg PWR_WakeUpPin_5, only applicable for STM32F072 devices
- * @arg PWR_WakeUpPin_6, only applicable for STM32F072 devices
- * @arg PWR_WakeUpPin_7, only applicable for STM32F072 devices
- * @arg PWR_WakeUpPin_8, only applicable for STM32F072 devices
- * @param NewState: new state of the WakeUp Pin functionality.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void PWR_WakeUpPinCmd(uint32_t PWR_WakeUpPin, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_PWR_WAKEUP_PIN(PWR_WakeUpPin));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the EWUPx pin */
- PWR->CSR |= PWR_WakeUpPin;
- }
- else
- {
- /* Disable the EWUPx pin */
- PWR->CSR &= ~PWR_WakeUpPin;
- }
-}
-
-/**
- * @}
- */
-
-
-/** @defgroup PWR_Group4 Low Power modes configuration functions
- * @brief Low Power modes configuration functions
- *
-@verbatim
- ==============================================================================
- ##### Low Power modes configuration functions #####
- ==============================================================================
-
- [..] The devices feature three low-power modes:
- (+) Sleep mode: Cortex-M0 core stopped, peripherals kept running.
- (+) Stop mode: all clocks are stopped, regulator running, regulator in low power mode
- (+) Standby mode: VCORE domain powered off
-
- *** Sleep mode ***
- ==================
- [..]
- (+) Entry:
- (++) The Sleep mode is entered by executing the WFE() or WFI() instructions.
- (+) Exit:
- (++) Any peripheral interrupt acknowledged by the nested vectored interrupt
- controller (NVIC) can wake up the device from Sleep mode.
-
- *** Stop mode ***
- =================
- [..] In Stop mode, all clocks in the VCORE domain are stopped, the PLL, the HSI,
- the HSI14 and the HSE RC oscillators are disabled. Internal SRAM and register
- contents are preserved.
- The voltage regulator can be configured either in normal or low-power mode.
-
- (+) Entry:
- (++) The Stop mode is entered using the PWR_EnterSTOPMode(PWR_Regulator_LowPower,)
- function with regulator in LowPower or with Regulator ON.
- (+) Exit:
- (++) Any EXTI Line (Internal or External) configured in Interrupt/Event mode
- or any internal IPs (I2C, UASRT or CEC) wakeup event.
-
- *** Standby mode ***
- ====================
- [..] The Standby mode allows to achieve the lowest power consumption. It is based
- on the Cortex-M0 deepsleep mode, with the voltage regulator disabled.
- The VCORE domain is consequently powered off. The PLL, the HSI, the HSI14
- oscillator and the HSE oscillator are also switched off. SRAM and register
- contents are lost except for the Backup domain (RTC registers, RTC backup
- registers and Standby circuitry).
-
- [..] The voltage regulator is OFF.
-
- (+) Entry:
- (++) The Standby mode is entered using the PWR_EnterSTANDBYMode() function.
- (+) Exit:
- (++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup,
- tamper event, time-stamp event, external reset in NRST pin, IWDG reset.
-
- *** Auto-wakeup (AWU) from low-power mode ***
- =============================================
- [..] The MCU can be woken up from low-power mode by an RTC Alarm event, a tamper
- event, a time-stamp event, or a comparator event, without depending on an
- external interrupt (Auto-wakeup mode).
-
- (+) RTC auto-wakeup (AWU) from the Stop mode
- (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to:
- (+++) Configure the EXTI Line 17 to be sensitive to rising edges (Interrupt
- or Event modes) using the EXTI_Init() function.
- (+++) Enable the RTC Alarm Interrupt using the RTC_ITConfig() function
- (+++) Configure the RTC to generate the RTC alarm using the RTC_SetAlarm()
- and RTC_AlarmCmd() functions.
- (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it
- is necessary to:
- (+++) Configure the EXTI Line 19 to be sensitive to rising edges (Interrupt
- or Event modes) using the EXTI_Init() function.
- (+++) Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig()
- function.
- (+++) Configure the RTC to detect the tamper or time stamp event using the
- RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd()
- functions.
-
- (+) RTC auto-wakeup (AWU) from the Standby mode
- (++) To wake up from the Standby mode with an RTC alarm event, it is necessary to:
- (+++) Enable the RTC Alarm Interrupt using the RTC_ITConfig() function.
- (+++) Configure the RTC to generate the RTC alarm using the RTC_SetAlarm()
- and RTC_AlarmCmd() functions.
- (++) To wake up from the Standby mode with an RTC Tamper or time stamp event, it
- is necessary to:
- (+++) Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig()
- function.
- (+++) Configure the RTC to detect the tamper or time stamp event using the
- RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd()
- functions.
-
- (+) Comparator auto-wakeup (AWU) from the Stop mode
- (++) To wake up from the Stop mode with an comparator 1 or comparator 2 wakeup
- event, it is necessary to:
- (+++) Configure the EXTI Line 21 for comparator 1 or EXTI Line 22 for comparator 2
- to be sensitive to to the selected edges (falling, rising or falling
- and rising) (Interrupt or Event modes) using the EXTI_Init() function.
- (+++) Configure the comparator to generate the event.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enters Sleep mode.
- * @note In Sleep mode, all I/O pins keep the same state as in Run mode.
- * @param PWR_SLEEPEntry: specifies if SLEEP mode in entered with WFI or WFE instruction.
- * This parameter can be one of the following values:
- * @arg PWR_SLEEPEntry_WFI: enter SLEEP mode with WFI instruction
- * @arg PWR_SLEEPEntry_WFE: enter SLEEP mode with WFE instruction
- * @retval None
- */
-void PWR_EnterSleepMode(uint8_t PWR_SLEEPEntry)
-{
- /* Check the parameters */
- assert_param(IS_PWR_SLEEP_ENTRY(PWR_SLEEPEntry));
-
- /* Clear SLEEPDEEP bit of Cortex-M0 System Control Register */
- SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
-
- /* Select SLEEP mode entry -------------------------------------------------*/
- if(PWR_SLEEPEntry == PWR_SLEEPEntry_WFI)
- {
- /* Request Wait For Interrupt */
- __WFI();
- }
- else
- {
- /* Request Wait For Event */
- __WFE();
- }
-}
-
-/**
- * @brief Enters STOP mode.
- * @note In Stop mode, all I/O pins keep the same state as in Run mode.
- * @note When exiting Stop mode by issuing an interrupt or a wakeup event,
- * the HSI RC oscillator is selected as system clock.
- * @note When the voltage regulator operates in low power mode, an additional
- * startup delay is incurred when waking up from Stop mode.
- * By keeping the internal regulator ON during Stop mode, the consumption
- * is higher although the startup time is reduced.
- * @param PWR_Regulator: specifies the regulator state in STOP mode.
- * This parameter can be one of the following values:
- * @arg PWR_Regulator_ON: STOP mode with regulator ON
- * @arg PWR_Regulator_LowPower: STOP mode with regulator in low power mode
- * @param PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction.
- * This parameter can be one of the following values:
- * @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction
- * @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction
- @arg PWR_STOPEntry_SLEEPONEXIT: enter STOP mode with SLEEPONEXIT instruction
- * @retval None
- */
-void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_PWR_REGULATOR(PWR_Regulator));
- assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry));
-
- /* Select the regulator state in STOP mode ---------------------------------*/
- tmpreg = PWR->CR;
- /* Clear PDDS and LPDSR bits */
- tmpreg &= CR_DS_MASK;
-
- /* Set LPDSR bit according to PWR_Regulator value */
- tmpreg |= PWR_Regulator;
-
- /* Store the new value */
- PWR->CR = tmpreg;
-
- /* Set SLEEPDEEP bit of Cortex-M0 System Control Register */
- SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
-
- /* Select STOP mode entry --------------------------------------------------*/
- if(PWR_STOPEntry == PWR_STOPEntry_WFI)
- {
- /* Request Wait For Interrupt */
- __WFI();
- /* Reset SLEEPDEEP bit of Cortex System Control Register */
- SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
- }
- else if (PWR_STOPEntry == PWR_STOPEntry_WFE)
- {
- /* Request Wait For Event */
- __WFE();
- /* Reset SLEEPDEEP bit of Cortex System Control Register */
- SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
- }
- else
- {
- /* Set SLEEP on exit bit of Cortex-M0 System Control Register */
- SCB->SCR |= SCB_SCR_SLEEPONEXIT_Msk;
- }
-}
-
-/**
- * @brief Enters STANDBY mode.
- * @note In Standby mode, all I/O pins are high impedance except for:
- * - Reset pad (still available)
- * - RTC_AF1 pin (PC13) if configured for Wakeup pin 2 (WKUP2), tamper,
- * time-stamp, RTC Alarm out, or RTC clock calibration out.
- * - WKUP pin 1 (PA0) if enabled.
- * @param None
- * @retval None
- */
-void PWR_EnterSTANDBYMode(void)
-{
- /* Clear Wakeup flag */
- PWR->CR |= PWR_CR_CWUF;
-
- /* Select STANDBY mode */
- PWR->CR |= PWR_CR_PDDS;
-
- /* Set SLEEPDEEP bit of Cortex-M0 System Control Register */
- SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
-
- /* Request Wait For Interrupt */
- __WFI();
-}
-
-/**
- * @}
- */
-
-/** @defgroup PWR_Group5 Flags management functions
- * @brief Flags management functions
- *
-@verbatim
- ==============================================================================
- ##### Flags management functions #####
- ==============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Checks whether the specified PWR flag is set or not.
- * @param PWR_FLAG: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup
- * event was received from the WKUP pin or from the RTC alarm
- * (Alarm A or Alarm B), RTC Tamper event or RTC TimeStamp event.
- * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the
- * system was resumed from StandBy mode.
- * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD
- * is enabled by the PWR_PVDCmd() function.
- * @arg PWR_FLAG_VREFINTRDY: Internal Voltage Reference Ready flag.
- * This flag indicates the state of the internal voltage
- * reference, VREFINT.
- * @retval The new state of PWR_FLAG (SET or RESET).
- */
-FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)
-{
- FlagStatus bitstatus = RESET;
- /* Check the parameters */
- assert_param(IS_PWR_GET_FLAG(PWR_FLAG));
-
- if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- /* Return the flag status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the PWR's pending flags.
- * @param PWR_FLAG: specifies the flag to clear.
- * This parameter can be one of the following values:
- * @arg PWR_FLAG_WU: Wake Up flag
- * @arg PWR_FLAG_SB: StandBy flag
- * @retval None
- */
-void PWR_ClearFlag(uint32_t PWR_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG));
-
- PWR->CR |= PWR_FLAG << 2;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_rcc.c b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_rcc.c
deleted file mode 100644
index ef8d5fda2b56c212ba69cd0e7d1e5c7026bf6980..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_rcc.c
+++ /dev/null
@@ -1,1741 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f0xx_rcc.c
- * @author MCD Application Team
- * @version V1.3.0
- * @date 16-January-2014
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Reset and clock control (RCC) peripheral:
- * + Internal/external clocks, PLL, CSS and MCO configuration
- * + System, AHB and APB busses clocks configuration
- * + Peripheral clocks configuration
- * + Interrupts and flags management
- *
- @verbatim
-
- ===============================================================================
- ##### RCC specific features #####
- ===============================================================================
- [..] After reset the device is running from HSI (8 MHz) with Flash 0 WS,
- all peripherals are off except internal SRAM, Flash and SWD.
- (#) There is no prescaler on High speed (AHB) and Low speed (APB) busses;
- all peripherals mapped on these busses are running at HSI speed.
- (#) The clock for all peripherals is switched off, except the SRAM and FLASH.
- (#) All GPIOs are in input floating state, except the SWD pins which
- are assigned to be used for debug purpose.
- [..] Once the device started from reset, the user application has to:
- (#) Configure the clock source to be used to drive the System clock
- (if the application needs higher frequency/performance)
- (#) Configure the System clock frequency and Flash settings
- (#) Configure the AHB and APB busses prescalers
- (#) Enable the clock for the peripheral(s) to be used
- (#) Configure the clock source(s) for peripherals which clocks are not
- derived from the System clock (ADC, CEC, I2C, USART, RTC and IWDG)
-
- @endverbatim
-
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx_rcc.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup RCC
- * @brief RCC driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-/* ---------------------- RCC registers mask -------------------------------- */
-/* RCC Flag Mask */
-#define FLAG_MASK ((uint8_t)0x1F)
-
-/* CR register byte 2 (Bits[23:16]) base address */
-#define CR_BYTE2_ADDRESS ((uint32_t)0x40021002)
-
-/* CFGR register byte 3 (Bits[31:23]) base address */
-#define CFGR_BYTE3_ADDRESS ((uint32_t)0x40021007)
-
-/* CIR register byte 1 (Bits[15:8]) base address */
-#define CIR_BYTE1_ADDRESS ((uint32_t)0x40021009)
-
-/* CIR register byte 2 (Bits[23:16]) base address */
-#define CIR_BYTE2_ADDRESS ((uint32_t)0x4002100A)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
-
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup RCC_Private_Functions
- * @{
- */
-
-/** @defgroup RCC_Group1 Internal and external clocks, PLL, CSS and MCO configuration functions
- * @brief Internal and external clocks, PLL, CSS and MCO configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Internal-external clocks, PLL, CSS and MCO configuration functions #####
- ===============================================================================
- [..] This section provides functions allowing to configure the internal/external clocks,
- PLL, CSS and MCO.
- (#) HSI (high-speed internal), 8 MHz factory-trimmed RC used directly
- or through the PLL as System clock source.
- The HSI clock can be used also to clock the USART, I2C and CEC peripherals.
- (#) HSI14 (high-speed internal for ADC), 14 MHz factory-trimmed RC used to clock
- the ADC peripheral.
- (#) LSI (low-speed internal), 40 KHz low consumption RC used as IWDG and/or RTC
- clock source.
- (#) HSE (high-speed external), 4 to 32 MHz crystal oscillator used directly or
- through the PLL as System clock source. Can be used also as RTC clock source.
- (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
- LSE can be used also to clock the USART and CEC peripherals.
- (#) PLL (clocked by HSI or HSE), for System clock.
- (#) CSS (Clock security system), once enabled and if a HSE clock failure occurs
- (HSE used directly or through PLL as System clock source), the System clock
- is automatically switched to HSI and an interrupt is generated if enabled.
- The interrupt is linked to the Cortex-M0 NMI (Non-Maskable Interrupt)
- exception vector.
- (#) MCO (microcontroller clock output), used to output SYSCLK, HSI, HSI14, LSI,
- HSE, LSE or PLL (divided by 2) clock on PA8 pin.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Resets the RCC clock configuration to the default reset state.
- * @note The default reset state of the clock configuration is given below:
- * @note HSI ON and used as system clock source
- * @note HSI14, HSE and PLL OFF
- * @note AHB, APB prescaler set to 1.
- * @note CSS and MCO OFF
- * @note All interrupts disabled
- * @note However, this function doesn't modify the configuration of the
- * @note Peripheral clocks
- * @note LSI, LSE and RTC clocks
- * @param None
- * @retval None
- */
-void RCC_DeInit(void)
-{
- /* Set HSION bit */
- RCC->CR |= (uint32_t)0x00000001;
-
-#if defined (STM32F051)
- /* Reset SW[1:0], HPRE[3:0], PPRE[2:0] and MCOSEL[2:0] bits */
- RCC->CFGR &= (uint32_t)0xF8FFB80C;
-#else
- /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, MCOSEL[2:0], MCOPRE[2:0] and PLLNODIV bits */
- RCC->CFGR &= (uint32_t)0x08FFB80C;
-#endif /* STM32F051 */
-
- /* Reset HSEON, CSSON and PLLON bits */
- RCC->CR &= (uint32_t)0xFEF6FFFF;
-
- /* Reset HSEBYP bit */
- RCC->CR &= (uint32_t)0xFFFBFFFF;
-
- /* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
- RCC->CFGR &= (uint32_t)0xFFC0FFFF;
-
- /* Reset PREDIV1[3:0] bits */
- RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
-
- /* Reset USARTSW[1:0], I2CSW, CECSW and ADCSW bits */
- RCC->CFGR3 &= (uint32_t)0xFFFFFEAC;
-
- /* Reset HSI14 bit */
- RCC->CR2 &= (uint32_t)0xFFFFFFFE;
-
- /* Disable all interrupts */
- RCC->CIR = 0x00000000;
-}
-
-/**
- * @brief Configures the External High Speed oscillator (HSE).
- * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
- * software should wait on HSERDY flag to be set indicating that HSE clock
- * is stable and can be used to clock the PLL and/or system clock.
- * @note HSE state can not be changed if it is used directly or through the
- * PLL as system clock. In this case, you have to select another source
- * of the system clock then change the HSE state (ex. disable it).
- * @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
- * @note This function resets the CSSON bit, so if the Clock security system(CSS)
- * was previously enabled you have to enable it again after calling this
- * function.
- * @param RCC_HSE: specifies the new state of the HSE.
- * This parameter can be one of the following values:
- * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
- * 6 HSE oscillator clock cycles.
- * @arg RCC_HSE_ON: turn ON the HSE oscillator
- * @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock
- * @retval None
- */
-void RCC_HSEConfig(uint8_t RCC_HSE)
-{
- /* Check the parameters */
- assert_param(IS_RCC_HSE(RCC_HSE));
-
- /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/
- *(__IO uint8_t *) CR_BYTE2_ADDRESS = RCC_HSE_OFF;
-
- /* Set the new HSE configuration -------------------------------------------*/
- *(__IO uint8_t *) CR_BYTE2_ADDRESS = RCC_HSE;
-
-}
-
-/**
- * @brief Waits for HSE start-up.
- * @note This function waits on HSERDY flag to be set and return SUCCESS if
- * this flag is set, otherwise returns ERROR if the timeout is reached
- * and this flag is not set. The timeout value is defined by the constant
- * HSE_STARTUP_TIMEOUT in stm32f0xx.h file. You can tailor it depending
- * on the HSE crystal used in your application.
- * @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
- * @param None
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: HSE oscillator is stable and ready to use
- * - ERROR: HSE oscillator not yet ready
- */
-ErrorStatus RCC_WaitForHSEStartUp(void)
-{
- __IO uint32_t StartUpCounter = 0;
- ErrorStatus status = ERROR;
- FlagStatus HSEStatus = RESET;
-
- /* Wait till HSE is ready and if timeout is reached exit */
- do
- {
- HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY);
- StartUpCounter++;
- } while((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET));
-
- if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET)
- {
- status = SUCCESS;
- }
- else
- {
- status = ERROR;
- }
- return (status);
-}
-
-/**
- * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value.
- * @note The calibration is used to compensate for the variations in voltage
- * and temperature that influence the frequency of the internal HSI RC.
- * Refer to the Application Note AN4067 for more details on how to
- * calibrate the HSI.
- * @param HSICalibrationValue: specifies the HSI calibration trimming value.
- * This parameter must be a number between 0 and 0x1F.
- * @retval None
- */
-void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_HSI_CALIBRATION_VALUE(HSICalibrationValue));
-
- tmpreg = RCC->CR;
-
- /* Clear HSITRIM[4:0] bits */
- tmpreg &= ~RCC_CR_HSITRIM;
-
- /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */
- tmpreg |= (uint32_t)HSICalibrationValue << 3;
-
- /* Store the new value */
- RCC->CR = tmpreg;
-}
-
-/**
- * @brief Enables or disables the Internal High Speed oscillator (HSI).
- * @note After enabling the HSI, the application software should wait on
- * HSIRDY flag to be set indicating that HSI clock is stable and can
- * be used to clock the PLL and/or system clock.
- * @note HSI can not be stopped if it is used directly or through the PLL
- * as system clock. In this case, you have to select another source
- * of the system clock then stop the HSI.
- * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
- * @param NewState: new state of the HSI.
- * This parameter can be: ENABLE or DISABLE.
- * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
- * clock cycles.
- * @retval None
- */
-void RCC_HSICmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- RCC->CR |= RCC_CR_HSION;
- }
- else
- {
- RCC->CR &= ~RCC_CR_HSION;
- }
-}
-
-/**
- * @brief Adjusts the Internal High Speed oscillator for ADC (HSI14)
- * calibration value.
- * @note The calibration is used to compensate for the variations in voltage
- * and temperature that influence the frequency of the internal HSI RC.
- * Refer to the Application Note AN4067 for more details on how to
- * calibrate the HSI14.
- * @param HSI14CalibrationValue: specifies the HSI14 calibration trimming value.
- * This parameter must be a number between 0 and 0x1F.
- * @retval None
- */
-void RCC_AdjustHSI14CalibrationValue(uint8_t HSI14CalibrationValue)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_HSI14_CALIBRATION_VALUE(HSI14CalibrationValue));
-
- tmpreg = RCC->CR2;
-
- /* Clear HSI14TRIM[4:0] bits */
- tmpreg &= ~RCC_CR2_HSI14TRIM;
-
- /* Set the HSITRIM14[4:0] bits according to HSI14CalibrationValue value */
- tmpreg |= (uint32_t)HSI14CalibrationValue << 3;
-
- /* Store the new value */
- RCC->CR2 = tmpreg;
-}
-
-/**
- * @brief Enables or disables the Internal High Speed oscillator for ADC (HSI14).
- * @note After enabling the HSI14, the application software should wait on
- * HSIRDY flag to be set indicating that HSI clock is stable and can
- * be used to clock the ADC.
- * @note The HSI14 is stopped by hardware when entering STOP and STANDBY modes.
- * @param NewState: new state of the HSI14.
- * This parameter can be: ENABLE or DISABLE.
- * @note When the HSI14 is stopped, HSI14RDY flag goes low after 6 HSI14 oscillator
- * clock cycles.
- * @retval None
- */
-void RCC_HSI14Cmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- RCC->CR2 |= RCC_CR2_HSI14ON;
- }
- else
- {
- RCC->CR2 &= ~RCC_CR2_HSI14ON;
- }
-}
-
-/**
- * @brief Enables or disables the Internal High Speed oscillator request from ADC.
- * @param NewState: new state of the HSI14 ADC request.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_HSI14ADCRequestCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- RCC->CR2 &= ~RCC_CR2_HSI14DIS;
- }
- else
- {
- RCC->CR2 |= RCC_CR2_HSI14DIS;
- }
-}
-
-/**
- * @brief Configures the External Low Speed oscillator (LSE).
- * @note As the LSE is in the Backup domain and write access is denied to this
- * domain after reset, you have to enable write access using
- * PWR_BackupAccessCmd(ENABLE) function before to configure the LSE
- * (to be done once after reset).
- * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_Bypass), the application
- * software should wait on LSERDY flag to be set indicating that LSE clock
- * is stable and can be used to clock the RTC.
- * @param RCC_LSE: specifies the new state of the LSE.
- * This parameter can be one of the following values:
- * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
- * 6 LSE oscillator clock cycles.
- * @arg RCC_LSE_ON: turn ON the LSE oscillator
- * @arg RCC_LSE_Bypass: LSE oscillator bypassed with external clock
- * @retval None
- */
-void RCC_LSEConfig(uint32_t RCC_LSE)
-{
- /* Check the parameters */
- assert_param(IS_RCC_LSE(RCC_LSE));
-
- /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/
- /* Reset LSEON bit */
- RCC->BDCR &= ~(RCC_BDCR_LSEON);
-
- /* Reset LSEBYP bit */
- RCC->BDCR &= ~(RCC_BDCR_LSEBYP);
-
- /* Configure LSE */
- RCC->BDCR |= RCC_LSE;
-}
-
-/**
- * @brief Configures the External Low Speed oscillator (LSE) drive capability.
- * @param RCC_LSEDrive: specifies the new state of the LSE drive capability.
- * This parameter can be one of the following values:
- * @arg RCC_LSEDrive_Low: LSE oscillator low drive capability.
- * @arg RCC_LSEDrive_MediumLow: LSE oscillator medium low drive capability.
- * @arg RCC_LSEDrive_MediumHigh: LSE oscillator medium high drive capability.
- * @arg RCC_LSEDrive_High: LSE oscillator high drive capability.
- * @retval None
- */
-void RCC_LSEDriveConfig(uint32_t RCC_LSEDrive)
-{
- /* Check the parameters */
- assert_param(IS_RCC_LSE_DRIVE(RCC_LSEDrive));
-
- /* Clear LSEDRV[1:0] bits */
- RCC->BDCR &= ~(RCC_BDCR_LSEDRV);
-
- /* Set the LSE Drive */
- RCC->BDCR |= RCC_LSEDrive;
-}
-
-/**
- * @brief Enables or disables the Internal Low Speed oscillator (LSI).
- * @note After enabling the LSI, the application software should wait on
- * LSIRDY flag to be set indicating that LSI clock is stable and can
- * be used to clock the IWDG and/or the RTC.
- * @note LSI can not be disabled if the IWDG is running.
- * @param NewState: new state of the LSI.
- * This parameter can be: ENABLE or DISABLE.
- * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
- * clock cycles.
- * @retval None
- */
-void RCC_LSICmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- RCC->CSR |= RCC_CSR_LSION;
- }
- else
- {
- RCC->CSR &= ~RCC_CSR_LSION;
- }
-}
-
-/**
- * @brief Configures the PLL clock source and multiplication factor.
- * @note This function must be used only when the PLL is disabled.
- *
- * @param RCC_PLLSource: specifies the PLL entry clock source.
- * This parameter can be one of the following values:
- * @arg RCC_PLLSource_HSI_Div2: HSI oscillator clock selected as PLL clock source
- * @arg RCC_PLLSource_PREDIV1: PREDIV1 clock selected as PLL clock entry
- * @arg RCC_PLLSource_HSI48 HSI48 oscillator clock selected as PLL clock source, applicable only for STM32F072 devices
- * @arg RCC_PLLSource_HSI: HSI clock selected as PLL clock entry, applicable only for STM32F072 devices
- * @note The minimum input clock frequency for PLL is 2 MHz (when using HSE as
- * PLL source).
- *
- * @param RCC_PLLMul: specifies the PLL multiplication factor, which drive the PLLVCO clock
- * This parameter can be RCC_PLLMul_x where x:[2,16]
- *
- * @retval None
- */
-void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul)
-{
- /* Check the parameters */
- assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource));
- assert_param(IS_RCC_PLL_MUL(RCC_PLLMul));
-
- /* Clear PLL Source [16] and Multiplier [21:18] bits */
- RCC->CFGR &= ~(RCC_CFGR_PLLMULL | RCC_CFGR_PLLSRC);
-
- /* Set the PLL Source and Multiplier */
- RCC->CFGR |= (uint32_t)(RCC_PLLSource | RCC_PLLMul);
-}
-
-/**
- * @brief Enables or disables the PLL.
- * @note After enabling the PLL, the application software should wait on
- * PLLRDY flag to be set indicating that PLL clock is stable and can
- * be used as system clock source.
- * @note The PLL can not be disabled if it is used as system clock source
- * @note The PLL is disabled by hardware when entering STOP and STANDBY modes.
- * @param NewState: new state of the PLL.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_PLLCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- RCC->CR |= RCC_CR_PLLON;
- }
- else
- {
- RCC->CR &= ~RCC_CR_PLLON;
- }
-}
-
-/**
- * @brief Enables or disables the Internal High Speed oscillator for USB (HSI48).
- * This function is only applicable for STM32F072 devices.
- * @note After enabling the HSI48, the application software should wait on
- * HSI48RDY flag to be set indicating that HSI48 clock is stable and can
- * be used to clock the USB.
- * @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes.
- * @param NewState: new state of the HSI48.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_HSI48Cmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- RCC->CR2 |= RCC_CR2_HSI48ON;
- }
- else
- {
- RCC->CR2 &= ~RCC_CR2_HSI48ON;
- }
-}
-
-/**
- * @brief Configures the PREDIV1 division factor.
- * @note This function must be used only when the PLL is disabled.
- * @param RCC_PREDIV1_Div: specifies the PREDIV1 clock division factor.
- * This parameter can be RCC_PREDIV1_Divx where x:[1,16]
- * @retval None
- */
-void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Div)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_PREDIV1(RCC_PREDIV1_Div));
-
- tmpreg = RCC->CFGR2;
- /* Clear PREDIV1[3:0] bits */
- tmpreg &= ~(RCC_CFGR2_PREDIV1);
- /* Set the PREDIV1 division factor */
- tmpreg |= RCC_PREDIV1_Div;
- /* Store the new value */
- RCC->CFGR2 = tmpreg;
-}
-
-/**
- * @brief Enables or disables the Clock Security System.
- * @note If a failure is detected on the HSE oscillator clock, this oscillator
- * is automatically disabled and an interrupt is generated to inform the
- * software about the failure (Clock Security System Interrupt, CSSI),
- * allowing the MCU to perform rescue operations. The CSSI is linked to
- * the Cortex-M0 NMI (Non-Maskable Interrupt) exception vector.
- * @param NewState: new state of the Clock Security System.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_ClockSecuritySystemCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- RCC->CR |= RCC_CR_CSSON;
- }
- else
- {
- RCC->CR &= ~RCC_CR_CSSON;
- }
-}
-
-#ifdef STM32F051
-/**
- * @brief Selects the clock source to output on MCO pin (PA8).
- * @note PA8 should be configured in alternate function mode.
- * @param RCC_MCOSource: specifies the clock source to output.
- * This parameter can be one of the following values:
- * @arg RCC_MCOSource_NoClock: No clock selected.
- * @arg RCC_MCOSource_HSI14: HSI14 oscillator clock selected.
- * @arg RCC_MCOSource_LSI: LSI oscillator clock selected.
- * @arg RCC_MCOSource_LSE: LSE oscillator clock selected.
- * @arg RCC_MCOSource_SYSCLK: System clock selected.
- * @arg RCC_MCOSource_HSI: HSI oscillator clock selected.
- * @arg RCC_MCOSource_HSE: HSE oscillator clock selected.
- * @arg RCC_MCOSource_PLLCLK_Div2: PLL clock divided by 2 selected.
- * @retval None
- */
-void RCC_MCOConfig(uint8_t RCC_MCOSource)
-{
- /* Check the parameters */
- assert_param(IS_RCC_MCO_SOURCE(RCC_MCOSource));
-
- /* Select MCO clock source and prescaler */
- *(__IO uint8_t *) CFGR_BYTE3_ADDRESS = RCC_MCOSource;
-}
-#else
-
-/**
- * @brief Selects the clock source to output on MCO pin (PA8) and the corresponding
- * prescsaler.
- * @note PA8 should be configured in alternate function mode.
- * @param RCC_MCOSource: specifies the clock source to output.
- * This parameter can be one of the following values:
- * @arg RCC_MCOSource_NoClock: No clock selected.
- * @arg RCC_MCOSource_HSI14: HSI14 oscillator clock selected.
- * @arg RCC_MCOSource_LSI: LSI oscillator clock selected.
- * @arg RCC_MCOSource_LSE: LSE oscillator clock selected.
- * @arg RCC_MCOSource_SYSCLK: System clock selected.
- * @arg RCC_MCOSource_HSI: HSI oscillator clock selected.
- * @arg RCC_MCOSource_HSE: HSE oscillator clock selected.
- * @arg RCC_MCOSource_PLLCLK_Div2: PLL clock divided by 2 selected.
- * @arg RCC_MCOSource_PLLCLK: PLL clock selected.
- * @arg RCC_MCOSource_HSI48: HSI48 clock selected.
- * @param RCC_MCOPrescaler: specifies the prescaler on MCO pin.
- * This parameter can be one of the following values:
- * @arg RCC_MCOPrescaler_1: MCO clock is divided by 1.
- * @arg RCC_MCOPrescaler_2: MCO clock is divided by 2.
- * @arg RCC_MCOPrescaler_4: MCO clock is divided by 4.
- * @arg RCC_MCOPrescaler_8: MCO clock is divided by 8.
- * @arg RCC_MCOPrescaler_16: MCO clock is divided by 16.
- * @arg RCC_MCOPrescaler_32: MCO clock is divided by 32.
- * @arg RCC_MCOPrescaler_64: MCO clock is divided by 64.
- * @arg RCC_MCOPrescaler_128: MCO clock is divided by 128.
- * @retval None
- */
-void RCC_MCOConfig(uint8_t RCC_MCOSource, uint32_t RCC_MCOPrescaler)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_MCO_SOURCE(RCC_MCOSource));
- assert_param(IS_RCC_MCO_PRESCALER(RCC_MCOPrescaler));
-
- /* Get CFGR value */
- tmpreg = RCC->CFGR;
- /* Clear MCOPRE[2:0] bits */
- tmpreg &= ~(RCC_CFGR_MCO_PRE | RCC_CFGR_MCO | RCC_CFGR_PLLNODIV);
- /* Set the RCC_MCOSource and RCC_MCOPrescaler */
- tmpreg |= (RCC_MCOPrescaler | ((uint32_t)RCC_MCOSource<<24));
- /* Store the new value */
- RCC->CFGR = tmpreg;
-}
-#endif /* STM32F072 */
-
-/**
- * @}
- */
-
-/** @defgroup RCC_Group2 System AHB and APB busses clocks configuration functions
- * @brief System, AHB and APB busses clocks configuration functions
- *
-@verbatim
- ===============================================================================
- ##### System, AHB and APB busses clocks configuration functions #####
- ===============================================================================
-
- [..] This section provide functions allowing to configure the System, AHB and
- APB busses clocks.
- (#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
- HSE and PLL.
- The AHB clock (HCLK) is derived from System clock through configurable prescaler
- and used to clock the CPU, memory and peripherals mapped on AHB bus (DMA and GPIO).
- and APB (PCLK) clocks are derived from AHB clock through
- configurable prescalers and used to clock the peripherals mapped on these busses.
- You can use "RCC_GetClocksFreq()" function to retrieve the frequencies of these clocks.
-
- -@- All the peripheral clocks are derived from the System clock (SYSCLK) except:
- (+@) The ADC clock which is derived from HSI14 or APB (APB divided by a
- programmable prescaler: 2 or 4).
- (+@) The CEC clock which is derived from LSE or HSI divided by 244.
- (+@) The I2C clock which is derived from HSI or system clock (SYSCLK).
- (+@) The USART clock which is derived from HSI, system clock (SYSCLK), APB or LSE.
- (+@) The RTC/LCD clock which is derived from the LSE, LSI or 2 MHz HSE_RTC (HSE
- divided by a programmable prescaler).
- The System clock (SYSCLK) frequency must be higher or equal to the RTC/LCD
- clock frequency.
- (+@) IWDG clock which is always the LSI clock.
-
- (#) The maximum frequency of the SYSCLK, HCLK and PCLK is 48 MHz.
- Depending on the maximum frequency, the FLASH wait states (WS) should be
- adapted accordingly:
- +--------------------------------------------- +
- | Wait states | HCLK clock frequency (MHz) |
- |---------------|------------------------------|
- |0WS(1CPU cycle)| 0 < HCLK <= 24 |
- |---------------|------------------------------|
- |1WS(2CPU cycle)| 24 < HCLK <= 48 |
- +----------------------------------------------+
-
- (#) After reset, the System clock source is the HSI (8 MHz) with 0 WS and
- prefetch is disabled.
-
- [..] It is recommended to use the following software sequences to tune the number
- of wait states needed to access the Flash memory with the CPU frequency (HCLK).
- (+) Increasing the CPU frequency
- (++) Program the Flash Prefetch buffer, using "FLASH_PrefetchBufferCmd(ENABLE)"
- function
- (++) Check that Flash Prefetch buffer activation is taken into account by
- reading FLASH_ACR using the FLASH_GetPrefetchBufferStatus() function
- (++) Program Flash WS to 1, using "FLASH_SetLatency(FLASH_Latency_1)" function
- (++) Check that the new number of WS is taken into account by reading FLASH_ACR
- (++) Modify the CPU clock source, using "RCC_SYSCLKConfig()" function
- (++) If needed, modify the CPU clock prescaler by using "RCC_HCLKConfig()" function
- (++) Check that the new CPU clock source is taken into account by reading
- the clock source status, using "RCC_GetSYSCLKSource()" function
- (+) Decreasing the CPU frequency
- (++) Modify the CPU clock source, using "RCC_SYSCLKConfig()" function
- (++) If needed, modify the CPU clock prescaler by using "RCC_HCLKConfig()" function
- (++) Check that the new CPU clock source is taken into account by reading
- the clock source status, using "RCC_GetSYSCLKSource()" function
- (++) Program the new number of WS, using "FLASH_SetLatency()" function
- (++) Check that the new number of WS is taken into account by reading FLASH_ACR
- (++) Disable the Flash Prefetch buffer using "FLASH_PrefetchBufferCmd(DISABLE)"
- function
- (++) Check that Flash Prefetch buffer deactivation is taken into account by reading FLASH_ACR
- using the FLASH_GetPrefetchBufferStatus() function.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures the system clock (SYSCLK).
- * @note The HSI is used (enabled by hardware) as system clock source after
- * startup from Reset, wake-up from STOP and STANDBY mode, or in case
- * of failure of the HSE used directly or indirectly as system clock
- * (if the Clock Security System CSS is enabled).
- * @note A switch from one clock source to another occurs only if the target
- * clock source is ready (clock stable after startup delay or PLL locked).
- * If a clock source which is not yet ready is selected, the switch will
- * occur when the clock source will be ready.
- * You can use RCC_GetSYSCLKSource() function to know which clock is
- * currently used as system clock source.
- * @param RCC_SYSCLKSource: specifies the clock source used as system clock source
- * This parameter can be one of the following values:
- * @arg RCC_SYSCLKSource_HSI: HSI selected as system clock source
- * @arg RCC_SYSCLKSource_HSE: HSE selected as system clock source
- * @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock source
- * @arg RCC_SYSCLKSource_HSI48: HSI48 selected as system clock source, applicable only for STM32F072 devices
- * @retval None
- */
-void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource));
-
- tmpreg = RCC->CFGR;
-
- /* Clear SW[1:0] bits */
- tmpreg &= ~RCC_CFGR_SW;
-
- /* Set SW[1:0] bits according to RCC_SYSCLKSource value */
- tmpreg |= RCC_SYSCLKSource;
-
- /* Store the new value */
- RCC->CFGR = tmpreg;
-}
-
-/**
- * @brief Returns the clock source used as system clock.
- * @param None
- * @retval The clock source used as system clock. The returned value can be one
- * of the following values:
- * - 0x00: HSI used as system clock
- * - 0x04: HSE used as system clock
- * - 0x08: PLL used as system clock
- * - 0x0C: HSI48 used as system clock, applicable only for STM32F072 devices
- */
-uint8_t RCC_GetSYSCLKSource(void)
-{
- return ((uint8_t)(RCC->CFGR & RCC_CFGR_SWS));
-}
-
-/**
- * @brief Configures the AHB clock (HCLK).
- * @param RCC_SYSCLK: defines the AHB clock divider. This clock is derived from
- * the system clock (SYSCLK).
- * This parameter can be one of the following values:
- * @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK
- * @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2
- * @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4
- * @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8
- * @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16
- * @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64
- * @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128
- * @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256
- * @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512
- * @retval None
- */
-void RCC_HCLKConfig(uint32_t RCC_SYSCLK)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_HCLK(RCC_SYSCLK));
-
- tmpreg = RCC->CFGR;
-
- /* Clear HPRE[3:0] bits */
- tmpreg &= ~RCC_CFGR_HPRE;
-
- /* Set HPRE[3:0] bits according to RCC_SYSCLK value */
- tmpreg |= RCC_SYSCLK;
-
- /* Store the new value */
- RCC->CFGR = tmpreg;
-}
-
-/**
- * @brief Configures the APB clock (PCLK).
- * @param RCC_HCLK: defines the APB clock divider. This clock is derived from
- * the AHB clock (HCLK).
- * This parameter can be one of the following values:
- * @arg RCC_HCLK_Div1: APB clock = HCLK
- * @arg RCC_HCLK_Div2: APB clock = HCLK/2
- * @arg RCC_HCLK_Div4: APB clock = HCLK/4
- * @arg RCC_HCLK_Div8: APB clock = HCLK/8
- * @arg RCC_HCLK_Div16: APB clock = HCLK/16
- * @retval None
- */
-void RCC_PCLKConfig(uint32_t RCC_HCLK)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_PCLK(RCC_HCLK));
-
- tmpreg = RCC->CFGR;
-
- /* Clear PPRE[2:0] bits */
- tmpreg &= ~RCC_CFGR_PPRE;
-
- /* Set PPRE[2:0] bits according to RCC_HCLK value */
- tmpreg |= RCC_HCLK;
-
- /* Store the new value */
- RCC->CFGR = tmpreg;
-}
-
-/**
- * @brief Configures the ADC clock (ADCCLK).
- * @note This function is obsolete.
- * For proper ADC clock selection, refer to ADC_ClockModeConfig() in the ADC driver
- * @param RCC_ADCCLK: defines the ADC clock source. This clock is derived
- * from the HSI14 or APB clock (PCLK).
- * This parameter can be one of the following values:
- * @arg RCC_ADCCLK_HSI14: ADC clock = HSI14 (14MHz)
- * @arg RCC_ADCCLK_PCLK_Div2: ADC clock = PCLK/2
- * @arg RCC_ADCCLK_PCLK_Div4: ADC clock = PCLK/4
- * @retval None
- */
-void RCC_ADCCLKConfig(uint32_t RCC_ADCCLK)
-{
- /* Check the parameters */
- assert_param(IS_RCC_ADCCLK(RCC_ADCCLK));
-
- /* Clear ADCPRE bit */
- RCC->CFGR &= ~RCC_CFGR_ADCPRE;
- /* Set ADCPRE bits according to RCC_PCLK value */
- RCC->CFGR |= RCC_ADCCLK & 0xFFFF;
-
- /* Clear ADCSW bit */
- RCC->CFGR3 &= ~RCC_CFGR3_ADCSW;
- /* Set ADCSW bits according to RCC_ADCCLK value */
- RCC->CFGR3 |= RCC_ADCCLK >> 16;
-}
-
-/**
- * @brief Configures the CEC clock (CECCLK).
- * @param RCC_CECCLK: defines the CEC clock source. This clock is derived
- * from the HSI or LSE clock.
- * This parameter can be one of the following values:
- * @arg RCC_CECCLK_HSI_Div244: CEC clock = HSI/244 (32768Hz)
- * @arg RCC_CECCLK_LSE: CEC clock = LSE
- * @retval None
- */
-void RCC_CECCLKConfig(uint32_t RCC_CECCLK)
-{
- /* Check the parameters */
- assert_param(IS_RCC_CECCLK(RCC_CECCLK));
-
- /* Clear CECSW bit */
- RCC->CFGR3 &= ~RCC_CFGR3_CECSW;
- /* Set CECSW bits according to RCC_CECCLK value */
- RCC->CFGR3 |= RCC_CECCLK;
-}
-
-/**
- * @brief Configures the I2C1 clock (I2C1CLK).
- * @param RCC_I2CCLK: defines the I2C1 clock source. This clock is derived
- * from the HSI or System clock.
- * This parameter can be one of the following values:
- * @arg RCC_I2C1CLK_HSI: I2C1 clock = HSI
- * @arg RCC_I2C1CLK_SYSCLK: I2C1 clock = System Clock
- * @retval None
- */
-void RCC_I2CCLKConfig(uint32_t RCC_I2CCLK)
-{
- /* Check the parameters */
- assert_param(IS_RCC_I2CCLK(RCC_I2CCLK));
-
- /* Clear I2CSW bit */
- RCC->CFGR3 &= ~RCC_CFGR3_I2C1SW;
- /* Set I2CSW bits according to RCC_I2CCLK value */
- RCC->CFGR3 |= RCC_I2CCLK;
-}
-
-/**
- * @brief Configures the USART1 clock (USART1CLK).
- * @param RCC_USARTCLK: defines the USART clock source. This clock is derived
- * from the HSI or System clock.
- * This parameter can be one of the following values:
- * @arg RCC_USART1CLK_PCLK: USART1 clock = APB Clock (PCLK)
- * @arg RCC_USART1CLK_SYSCLK: USART1 clock = System Clock
- * @arg RCC_USART1CLK_LSE: USART1 clock = LSE Clock
- * @arg RCC_USART1CLK_HSI: USART1 clock = HSI Clock
- * @arg RCC_USART2CLK_PCLK: USART2 clock = APB Clock (PCLK), applicable only for STM32F072 devices
- * @arg RCC_USART2CLK_SYSCLK: USART2 clock = System Clock, applicable only for STM32F072 devices
- * @arg RCC_USART2CLK_LSE: USART2 clock = LSE Clock, applicable only for STM32F072 devices
- * @arg RCC_USART2CLK_HSI: USART2 clock = HSI Clock, applicable only for STM32F072 devices
- * @retval None
- */
-void RCC_USARTCLKConfig(uint32_t RCC_USARTCLK)
-{
- uint32_t tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_RCC_USARTCLK(RCC_USARTCLK));
-
- /* Get USART index */
- tmp = (RCC_USARTCLK >> 28);
-
- /* Clear USARTSW[1:0] bit */
- if (tmp == (uint32_t)0x00000001)
- {
- /* Clear USART1SW[1:0] bit */
- RCC->CFGR3 &= ~RCC_CFGR3_USART1SW;
- }
- else
- {
- /* Clear USART2SW[1:0] bit */
- RCC->CFGR3 &= ~RCC_CFGR3_USART2SW;
- }
-
- /* Set USARTxSW bits according to RCC_USARTCLK value */
- RCC->CFGR3 |= RCC_USARTCLK;
-}
-
-/**
- * @brief Configures the USB clock (USBCLK).
- * This function is only applicable for STM32F072 devices.
- * @param RCC_USBCLK: defines the USB clock source. This clock is derived
- * from the HSI48 or system clock.
- * This parameter can be one of the following values:
- * @arg RCC_USBCLK_HSI48: USB clock = HSI48
- * @arg RCC_USBCLK_PLLCLK: USB clock = PLL clock
- * @retval None
- */
-void RCC_USBCLKConfig(uint32_t RCC_USBCLK)
-{
- /* Check the parameters */
- assert_param(IS_RCC_USBCLK(RCC_USBCLK));
-
- /* Clear USBSW bit */
- RCC->CFGR3 &= ~RCC_CFGR3_USBSW;
- /* Set USBSW bits according to RCC_USBCLK value */
- RCC->CFGR3 |= RCC_USBCLK;
-}
-
-/**
- * @brief Returns the frequencies of the System, AHB and APB busses clocks.
- * @note The frequency returned by this function is not the real frequency
- * in the chip. It is calculated based on the predefined constant and
- * the source selected by RCC_SYSCLKConfig():
- *
- * @note If SYSCLK source is HSI, function returns constant HSI_VALUE(*)
- *
- * @note If SYSCLK source is HSE, function returns constant HSE_VALUE(**)
- *
- * @note If SYSCLK source is PLL, function returns constant HSE_VALUE(**)
- * or HSI_VALUE(*) multiplied by the PLL factors.
- *
- * @note If SYSCLK source is HSI48, function returns constant HSI48_VALUE(***)
- *
- * @note (*) HSI_VALUE is a constant defined in stm32f0xx.h file (default value
- * 8 MHz) but the real value may vary depending on the variations
- * in voltage and temperature, refer to RCC_AdjustHSICalibrationValue().
- *
- * @note (**) HSE_VALUE is a constant defined in stm32f0xx.h file (default value
- * 8 MHz), user has to ensure that HSE_VALUE is same as the real
- * frequency of the crystal used. Otherwise, this function may
- * return wrong result.
- *
- * @note (***) HSI48_VALUE is a constant defined in stm32f0xx.h file (default value
- * 48 MHz) but the real value may vary depending on the variations
- * in voltage and temperature.
- *
- * @note The result of this function could be not correct when using fractional
- * value for HSE crystal.
- *
- * @param RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold
- * the clocks frequencies.
- *
- * @note This function can be used by the user application to compute the
- * baudrate for the communication peripherals or configure other parameters.
- * @note Each time SYSCLK, HCLK and/or PCLK clock changes, this function
- * must be called to update the structure's field. Otherwise, any
- * configuration based on this function will be incorrect.
- *
- * @retval None
- */
-void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
-{
- uint32_t tmp = 0, pllmull = 0, pllsource = 0, prediv1factor = 0, presc = 0, pllclk = 0;
-
- /* Get SYSCLK source -------------------------------------------------------*/
- tmp = RCC->CFGR & RCC_CFGR_SWS;
-
- switch (tmp)
- {
- case 0x00: /* HSI used as system clock */
- RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
- break;
- case 0x04: /* HSE used as system clock */
- RCC_Clocks->SYSCLK_Frequency = HSE_VALUE;
- break;
- case 0x08: /* PLL used as system clock */
- /* Get PLL clock source and multiplication factor ----------------------*/
- pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
- pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
- pllmull = ( pllmull >> 18) + 2;
-
- if (pllsource == 0x00)
- {
- /* HSI oscillator clock divided by 2 selected as PLL clock entry */
- pllclk = (HSI_VALUE >> 1) * pllmull;
- }
- else
- {
- prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
- /* HSE oscillator clock selected as PREDIV1 clock entry */
- pllclk = (HSE_VALUE / prediv1factor) * pllmull;
- }
- RCC_Clocks->SYSCLK_Frequency = pllclk;
- break;
- case 0x0C: /* HSI48 used as system clock */
- RCC_Clocks->SYSCLK_Frequency = HSI48_VALUE;
- break;
- default: /* HSI used as system clock */
- RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
- break;
- }
- /* Compute HCLK, PCLK clocks frequencies -----------------------------------*/
- /* Get HCLK prescaler */
- tmp = RCC->CFGR & RCC_CFGR_HPRE;
- tmp = tmp >> 4;
- presc = APBAHBPrescTable[tmp];
- /* HCLK clock frequency */
- RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;
-
- /* Get PCLK prescaler */
- tmp = RCC->CFGR & RCC_CFGR_PPRE;
- tmp = tmp >> 8;
- presc = APBAHBPrescTable[tmp];
- /* PCLK clock frequency */
- RCC_Clocks->PCLK_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
-
- /* ADCCLK clock frequency */
- if((RCC->CFGR3 & RCC_CFGR3_ADCSW) != RCC_CFGR3_ADCSW)
- {
- /* ADC Clock is HSI14 Osc. */
- RCC_Clocks->ADCCLK_Frequency = HSI14_VALUE;
- }
- else
- {
- if((RCC->CFGR & RCC_CFGR_ADCPRE) != RCC_CFGR_ADCPRE)
- {
- /* ADC Clock is derived from PCLK/2 */
- RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK_Frequency >> 1;
- }
- else
- {
- /* ADC Clock is derived from PCLK/4 */
- RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK_Frequency >> 2;
- }
-
- }
-
- /* CECCLK clock frequency */
- if((RCC->CFGR3 & RCC_CFGR3_CECSW) != RCC_CFGR3_CECSW)
- {
- /* CEC Clock is HSI/244 */
- RCC_Clocks->CECCLK_Frequency = HSI_VALUE / 244;
- }
- else
- {
- /* CECC Clock is LSE Osc. */
- RCC_Clocks->CECCLK_Frequency = LSE_VALUE;
- }
-
- /* I2C1CLK clock frequency */
- if((RCC->CFGR3 & RCC_CFGR3_I2C1SW) != RCC_CFGR3_I2C1SW)
- {
- /* I2C1 Clock is HSI Osc. */
- RCC_Clocks->I2C1CLK_Frequency = HSI_VALUE;
- }
- else
- {
- /* I2C1 Clock is System Clock */
- RCC_Clocks->I2C1CLK_Frequency = RCC_Clocks->SYSCLK_Frequency;
- }
-
- /* USART1CLK clock frequency */
- if((RCC->CFGR3 & RCC_CFGR3_USART1SW) == 0x0)
- {
- /* USART1 Clock is PCLK */
- RCC_Clocks->USART1CLK_Frequency = RCC_Clocks->PCLK_Frequency;
- }
- else if((RCC->CFGR3 & RCC_CFGR3_USART1SW) == RCC_CFGR3_USART1SW_0)
- {
- /* USART1 Clock is System Clock */
- RCC_Clocks->USART1CLK_Frequency = RCC_Clocks->SYSCLK_Frequency;
- }
- else if((RCC->CFGR3 & RCC_CFGR3_USART1SW) == RCC_CFGR3_USART1SW_1)
- {
- /* USART1 Clock is LSE Osc. */
- RCC_Clocks->USART1CLK_Frequency = LSE_VALUE;
- }
- else if((RCC->CFGR3 & RCC_CFGR3_USART1SW) == RCC_CFGR3_USART1SW)
- {
- /* USART1 Clock is HSI Osc. */
- RCC_Clocks->USART1CLK_Frequency = HSI_VALUE;
- }
-
- /* USART2CLK clock frequency */
- if((RCC->CFGR3 & RCC_CFGR3_USART2SW) == 0x0)
- {
- /* USART Clock is PCLK */
- RCC_Clocks->USART2CLK_Frequency = RCC_Clocks->PCLK_Frequency;
- }
- else if((RCC->CFGR3 & RCC_CFGR3_USART2SW) == RCC_CFGR3_USART2SW_0)
- {
- /* USART Clock is System Clock */
- RCC_Clocks->USART2CLK_Frequency = RCC_Clocks->SYSCLK_Frequency;
- }
- else if((RCC->CFGR3 & RCC_CFGR3_USART2SW) == RCC_CFGR3_USART2SW_1)
- {
- /* USART Clock is LSE Osc. */
- RCC_Clocks->USART2CLK_Frequency = LSE_VALUE;
- }
- else if((RCC->CFGR3 & RCC_CFGR3_USART2SW) == RCC_CFGR3_USART2SW)
- {
- /* USART Clock is HSI Osc. */
- RCC_Clocks->USART2CLK_Frequency = HSI_VALUE;
- }
-
- /* USBCLK clock frequency */
- if((RCC->CFGR3 & RCC_CFGR3_USBSW) != RCC_CFGR3_USBSW)
- {
- /* USB Clock is HSI48 */
- RCC_Clocks->USBCLK_Frequency = HSI48_VALUE;
- }
- else
- {
- /* USB Clock is PLL clock */
- RCC_Clocks->USBCLK_Frequency = pllclk;
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup RCC_Group3 Peripheral clocks configuration functions
- * @brief Peripheral clocks configuration functions
- *
-@verbatim
- ===============================================================================
- #####Peripheral clocks configuration functions #####
- ===============================================================================
-
- [..] This section provide functions allowing to configure the Peripheral clocks.
- (#) The RTC clock which is derived from the LSE, LSI or HSE_Div32 (HSE
- divided by 32).
- (#) After restart from Reset or wakeup from STANDBY, all peripherals are off
- except internal SRAM, Flash and SWD. Before to start using a peripheral you
- have to enable its interface clock. You can do this using RCC_AHBPeriphClockCmd(),
- RCC_APB2PeriphClockCmd() and RCC_APB1PeriphClockCmd() functions.
- (#) To reset the peripherals configuration (to the default state after device reset)
- you can use RCC_AHBPeriphResetCmd(), RCC_APB2PeriphResetCmd() and
- RCC_APB1PeriphResetCmd() functions.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures the RTC clock (RTCCLK).
- * @note As the RTC clock configuration bits are in the Backup domain and write
- * access is denied to this domain after reset, you have to enable write
- * access using PWR_BackupAccessCmd(ENABLE) function before to configure
- * the RTC clock source (to be done once after reset).
- * @note Once the RTC clock is configured it can't be changed unless the RTC
- * is reset using RCC_BackupResetCmd function, or by a Power On Reset (POR)
- *
- * @param RCC_RTCCLKSource: specifies the RTC clock source.
- * This parameter can be one of the following values:
- * @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock
- * @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock
- * @arg RCC_RTCCLKSource_HSE_Div32: HSE divided by 32 selected as RTC clock
- *
- * @note If the LSE or LSI is used as RTC clock source, the RTC continues to
- * work in STOP and STANDBY modes, and can be used as wakeup source.
- * However, when the HSE clock is used as RTC clock source, the RTC
- * cannot be used in STOP and STANDBY modes.
- *
- * @note The maximum input clock frequency for RTC is 2MHz (when using HSE as
- * RTC clock source).
- *
- * @retval None
- */
-void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource)
-{
- /* Check the parameters */
- assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource));
-
- /* Select the RTC clock source */
- RCC->BDCR |= RCC_RTCCLKSource;
-}
-
-/**
- * @brief Enables or disables the RTC clock.
- * @note This function must be used only after the RTC clock source was selected
- * using the RCC_RTCCLKConfig function.
- * @param NewState: new state of the RTC clock.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_RTCCLKCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- RCC->BDCR |= RCC_BDCR_RTCEN;
- }
- else
- {
- RCC->BDCR &= ~RCC_BDCR_RTCEN;
- }
-}
-
-/**
- * @brief Forces or releases the Backup domain reset.
- * @note This function resets the RTC peripheral (including the backup registers)
- * and the RTC clock source selection in RCC_BDCR register.
- * @param NewState: new state of the Backup domain reset.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_BackupResetCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- RCC->BDCR |= RCC_BDCR_BDRST;
- }
- else
- {
- RCC->BDCR &= ~RCC_BDCR_BDRST;
- }
-}
-
-/**
- * @brief Enables or disables the AHB peripheral clock.
- * @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
- * @param RCC_AHBPeriph: specifies the AHB peripheral to gates its clock.
- * This parameter can be any combination of the following values:
- * @arg RCC_AHBPeriph_GPIOA: GPIOA clock
- * @arg RCC_AHBPeriph_GPIOB: GPIOB clock
- * @arg RCC_AHBPeriph_GPIOC: GPIOC clock
- * @arg RCC_AHBPeriph_GPIOD: GPIOD clock
- * @arg RCC_AHBPeriph_GPIOE: GPIOE clock, applicable only for STM32F072 devices
- * @arg RCC_AHBPeriph_GPIOF: GPIOF clock
- * @arg RCC_AHBPeriph_TS: TS clock
- * @arg RCC_AHBPeriph_CRC: CRC clock
- * @arg RCC_AHBPeriph_FLITF: (has effect only when the Flash memory is in power down mode)
- * @arg RCC_AHBPeriph_SRAM: SRAM clock
- * @arg RCC_AHBPeriph_DMA1: DMA1 clock
- * @param NewState: new state of the specified peripheral clock.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_AHB_PERIPH(RCC_AHBPeriph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- RCC->AHBENR |= RCC_AHBPeriph;
- }
- else
- {
- RCC->AHBENR &= ~RCC_AHBPeriph;
- }
-}
-
-/**
- * @brief Enables or disables the High Speed APB (APB2) peripheral clock.
- * @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
- * @param RCC_APB2Periph: specifies the APB2 peripheral to gates its clock.
- * This parameter can be any combination of the following values:
- * @arg RCC_APB2Periph_SYSCFG: SYSCFG clock
- * @arg RCC_APB2Periph_ADC1: ADC1 clock
- * @arg RCC_APB2Periph_TIM1: TIM1 clock
- * @arg RCC_APB2Periph_SPI1: SPI1 clock
- * @arg RCC_APB2Periph_USART1: USART1 clock
- * @arg RCC_APB2Periph_TIM15: TIM15 clock
- * @arg RCC_APB2Periph_TIM16: TIM16 clock
- * @arg RCC_APB2Periph_TIM17: TIM17 clock
- * @arg RCC_APB2Periph_DBGMCU: DBGMCU clock
- * @param NewState: new state of the specified peripheral clock.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- RCC->APB2ENR |= RCC_APB2Periph;
- }
- else
- {
- RCC->APB2ENR &= ~RCC_APB2Periph;
- }
-}
-
-/**
- * @brief Enables or disables the Low Speed APB (APB1) peripheral clock.
- * @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
- * @param RCC_APB1Periph: specifies the APB1 peripheral to gates its clock.
- * This parameter can be any combination of the following values:
- * @arg RCC_APB1Periph_TIM2: TIM2 clock, applicable only for STM32F051 and STM32F072 devices
- * @arg RCC_APB1Periph_TIM3: TIM3 clock
- * @arg RCC_APB1Periph_TIM6: TIM6 clock
- * @arg RCC_APB1Periph_TIM7: TIM7 clock, applicable only for STM32F072 devices
- * @arg RCC_APB1Periph_TIM14: TIM14 clock
- * @arg RCC_APB1Periph_WWDG: WWDG clock
- * @arg RCC_APB1Periph_SPI2: SPI2 clock
- * @arg RCC_APB1Periph_USART2: USART2 clock
- * @arg RCC_APB1Periph_USART3: USART3 clock, applicable only for STM32F072 devices
- * @arg RCC_APB1Periph_USART4: USART4 clock, applicable only for STM32F072 devices
- * @arg RCC_APB1Periph_I2C1: I2C1 clock
- * @arg RCC_APB1Periph_I2C2: I2C2 clock
- * @arg RCC_APB1Periph_USB: USB clock, applicable only for STM32F042 and STM32F072 devices
- * @arg RCC_APB1Periph_CAN: CAN clock, applicable only for STM32F042 and STM32F072 devices
- * @arg RCC_APB1Periph_CRS: CRS clock , applicable only for STM32F042 and STM32F072 devices
- * @arg RCC_APB1Periph_PWR: PWR clock
- * @arg RCC_APB1Periph_DAC: DAC clock, applicable only for STM32F051 and STM32F072 devices
- * @arg RCC_APB1Periph_CEC: CEC clock, applicable only for STM32F051, STM32F042 and STM32F072 devices
- * @param NewState: new state of the specified peripheral clock.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- RCC->APB1ENR |= RCC_APB1Periph;
- }
- else
- {
- RCC->APB1ENR &= ~RCC_APB1Periph;
- }
-}
-
-/**
- * @brief Forces or releases AHB peripheral reset.
- * @param RCC_AHBPeriph: specifies the AHB peripheral to reset.
- * This parameter can be any combination of the following values:
- * @arg RCC_AHBPeriph_GPIOA: GPIOA clock
- * @arg RCC_AHBPeriph_GPIOB: GPIOB clock
- * @arg RCC_AHBPeriph_GPIOC: GPIOC clock
- * @arg RCC_AHBPeriph_GPIOD: GPIOD clock
- * @arg RCC_AHBPeriph_GPIOE: GPIOE clock, applicable only for STM32F072 devices
- * @arg RCC_AHBPeriph_GPIOF: GPIOF clock
- * @arg RCC_AHBPeriph_TS: TS clock
- * @param NewState: new state of the specified peripheral reset.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_AHB_RST_PERIPH(RCC_AHBPeriph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- RCC->AHBRSTR |= RCC_AHBPeriph;
- }
- else
- {
- RCC->AHBRSTR &= ~RCC_AHBPeriph;
- }
-}
-
-/**
- * @brief Forces or releases High Speed APB (APB2) peripheral reset.
- * @param RCC_APB2Periph: specifies the APB2 peripheral to reset.
- * This parameter can be any combination of the following values:
- * @arg RCC_APB2Periph_SYSCFG: SYSCFG clock
- * @arg RCC_APB2Periph_ADC1: ADC1 clock
- * @arg RCC_APB2Periph_TIM1: TIM1 clock
- * @arg RCC_APB2Periph_SPI1: SPI1 clock
- * @arg RCC_APB2Periph_USART1: USART1 clock
- * @arg RCC_APB2Periph_TIM15: TIM15 clock
- * @arg RCC_APB2Periph_TIM16: TIM16 clock
- * @arg RCC_APB2Periph_TIM17: TIM17 clock
- * @arg RCC_APB2Periph_DBGMCU: DBGMCU clock
- * @param NewState: new state of the specified peripheral reset.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- RCC->APB2RSTR |= RCC_APB2Periph;
- }
- else
- {
- RCC->APB2RSTR &= ~RCC_APB2Periph;
- }
-}
-
-/**
- * @brief Forces or releases Low Speed APB (APB1) peripheral reset.
- * @param RCC_APB1Periph: specifies the APB1 peripheral to reset.
- * This parameter can be any combination of the following values:
- * @arg RCC_APB1Periph_TIM2: TIM2 clock, applicable only for STM32F051 and STM32F072 devices
- * @arg RCC_APB1Periph_TIM3: TIM3 clock
- * @arg RCC_APB1Periph_TIM6: TIM6 clock
- * @arg RCC_APB1Periph_TIM7: TIM7 clock, applicable only for STM32F072 devices
- * @arg RCC_APB1Periph_TIM14: TIM14 clock
- * @arg RCC_APB1Periph_WWDG: WWDG clock
- * @arg RCC_APB1Periph_SPI2: SPI2 clock
- * @arg RCC_APB1Periph_USART2: USART2 clock
- * @arg RCC_APB1Periph_USART3: USART3 clock
- * @arg RCC_APB1Periph_USART4: USART4 clock
- * @arg RCC_APB1Periph_I2C1: I2C1 clock
- * @arg RCC_APB1Periph_I2C2: I2C2 clock
- * @arg RCC_APB1Periph_USB: USB clock, applicable only for STM32F072 devices
- * @arg RCC_APB1Periph_CAN: CAN clock, applicable only for STM32F072 devices
- * @arg RCC_APB1Periph_CRS: CRS clock, applicable only for STM32F072 devices
- * @arg RCC_APB1Periph_PWR: PWR clock
- * @arg RCC_APB1Periph_DAC: DAC clock, applicable only for STM32F051 and STM32F072 devices
- * @arg RCC_APB1Periph_CEC: CEC clock, applicable only for STM32F051 and STM32F072 devices
- * @param NewState: new state of the specified peripheral clock.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- RCC->APB1RSTR |= RCC_APB1Periph;
- }
- else
- {
- RCC->APB1RSTR &= ~RCC_APB1Periph;
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup RCC_Group4 Interrupts and flags management functions
- * @brief Interrupts and flags management functions
- *
-@verbatim
- ===============================================================================
- ##### Interrupts and flags management functions #####
- ===============================================================================
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the specified RCC interrupts.
- * @note The CSS interrupt doesn't have an enable bit; once the CSS is enabled
- * and if the HSE clock fails, the CSS interrupt occurs and an NMI is
- * automatically generated. The NMI will be executed indefinitely, and
- * since NMI has higher priority than any other IRQ (and main program)
- * the application will be stacked in the NMI ISR unless the CSS interrupt
- * pending bit is cleared.
- * @param RCC_IT: specifies the RCC interrupt sources to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg RCC_IT_LSIRDY: LSI ready interrupt
- * @arg RCC_IT_LSERDY: LSE ready interrupt
- * @arg RCC_IT_HSIRDY: HSI ready interrupt
- * @arg RCC_IT_HSERDY: HSE ready interrupt
- * @arg RCC_IT_PLLRDY: PLL ready interrupt
- * @arg RCC_IT_HSI14RDY: HSI14 ready interrupt
- * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt, applicable only for STM32F072 devices
- * @param NewState: new state of the specified RCC interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RCC_IT(RCC_IT));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Perform Byte access to RCC_CIR[13:8] bits to enable the selected interrupts */
- *(__IO uint8_t *) CIR_BYTE1_ADDRESS |= RCC_IT;
- }
- else
- {
- /* Perform Byte access to RCC_CIR[13:8] bits to disable the selected interrupts */
- *(__IO uint8_t *) CIR_BYTE1_ADDRESS &= (uint8_t)~RCC_IT;
- }
-}
-
-/**
- * @brief Checks whether the specified RCC flag is set or not.
- * @param RCC_FLAG: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
- * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
- * @arg RCC_FLAG_PLLRDY: PLL clock ready
- * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
- * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
- * @arg RCC_FLAG_OBLRST: Option Byte Loader (OBL) reset
- * @arg RCC_FLAG_PINRST: Pin reset
- * @arg RCC_FLAG_V18PWRRSTF: V1.8 power domain reset
- * @arg RCC_FLAG_PORRST: POR/PDR reset
- * @arg RCC_FLAG_SFTRST: Software reset
- * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
- * @arg RCC_FLAG_WWDGRST: Window Watchdog reset
- * @arg RCC_FLAG_LPWRRST: Low Power reset
- * @arg RCC_FLAG_HSI14RDY: HSI14 oscillator clock ready
- * @arg RCC_FLAG_HSI48RDY: HSI48 oscillator clock ready, applicable only for STM32F072 devices
- * @retval The new state of RCC_FLAG (SET or RESET).
- */
-FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG)
-{
- uint32_t tmp = 0;
- uint32_t statusreg = 0;
- FlagStatus bitstatus = RESET;
-
- /* Check the parameters */
- assert_param(IS_RCC_FLAG(RCC_FLAG));
-
- /* Get the RCC register index */
- tmp = RCC_FLAG >> 5;
-
- if (tmp == 0) /* The flag to check is in CR register */
- {
- statusreg = RCC->CR;
- }
- else if (tmp == 1) /* The flag to check is in BDCR register */
- {
- statusreg = RCC->BDCR;
- }
- else if (tmp == 2) /* The flag to check is in CSR register */
- {
- statusreg = RCC->CSR;
- }
- else /* The flag to check is in CR2 register */
- {
- statusreg = RCC->CR2;
- }
-
- /* Get the flag position */
- tmp = RCC_FLAG & FLAG_MASK;
-
- if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- /* Return the flag status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the RCC reset flags.
- * The reset flags are: RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_V18PWRRSTF,
- * RCC_FLAG_PORRST, RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST,
- * RCC_FLAG_LPWRRST.
- * @param None
- * @retval None
- */
-void RCC_ClearFlag(void)
-{
- /* Set RMVF bit to clear the reset flags */
- RCC->CSR |= RCC_CSR_RMVF;
-}
-
-/**
- * @brief Checks whether the specified RCC interrupt has occurred or not.
- * @param RCC_IT: specifies the RCC interrupt source to check.
- * This parameter can be one of the following values:
- * @arg RCC_IT_LSIRDY: LSI ready interrupt
- * @arg RCC_IT_LSERDY: LSE ready interrupt
- * @arg RCC_IT_HSIRDY: HSI ready interrupt
- * @arg RCC_IT_HSERDY: HSE ready interrupt
- * @arg RCC_IT_PLLRDY: PLL ready interrupt
- * @arg RCC_IT_HSI14RDY: HSI14 ready interrupt
- * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt, applicable only for STM32F072 devices
- * @arg RCC_IT_CSS: Clock Security System interrupt
- * @retval The new state of RCC_IT (SET or RESET).
- */
-ITStatus RCC_GetITStatus(uint8_t RCC_IT)
-{
- ITStatus bitstatus = RESET;
-
- /* Check the parameters */
- assert_param(IS_RCC_GET_IT(RCC_IT));
-
- /* Check the status of the specified RCC interrupt */
- if ((RCC->CIR & RCC_IT) != (uint32_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- /* Return the RCC_IT status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the RCC's interrupt pending bits.
- * @param RCC_IT: specifies the interrupt pending bit to clear.
- * This parameter can be any combination of the following values:
- * @arg RCC_IT_LSIRDY: LSI ready interrupt
- * @arg RCC_IT_LSERDY: LSE ready interrupt
- * @arg RCC_IT_HSIRDY: HSI ready interrupt
- * @arg RCC_IT_HSERDY: HSE ready interrupt
- * @arg RCC_IT_PLLRDY: PLL ready interrupt
- * @arg RCC_IT_HSI48RDY: HSI48 ready interrupt, applicable only for STM32F072 devices
- * @arg RCC_IT_HSI14RDY: HSI14 ready interrupt
- * @arg RCC_IT_CSS: Clock Security System interrupt
- * @retval None
- */
-void RCC_ClearITPendingBit(uint8_t RCC_IT)
-{
- /* Check the parameters */
- assert_param(IS_RCC_CLEAR_IT(RCC_IT));
-
- /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt
- pending bits */
- *(__IO uint8_t *) CIR_BYTE2_ADDRESS = RCC_IT;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_rtc.c b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_rtc.c
deleted file mode 100644
index 58b9978b21de65eff8f002e920e0546518be8955..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_rtc.c
+++ /dev/null
@@ -1,2518 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f0xx_rtc.c
- * @author MCD Application Team
- * @version V1.3.0
- * @date 16-January-2014
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Real-Time Clock (RTC) peripheral:
- * + Initialization
- * + Calendar (Time and Date) configuration
- * + Alarms (Alarm A) configuration
- * + Daylight Saving configuration
- * + Output pin Configuration
- * + Digital Calibration configuration
- * + TimeStamp configuration
- * + Tampers configuration
- * + Backup Data Registers configuration
- * + Output Type Config configuration
- * + Shift control synchronisation
- * + Interrupts and flags management
- *
- @verbatim
- ===============================================================================
- ##### Backup Domain Operating Condition #####
- ===============================================================================
- [..] The real-time clock (RTC) and the RTC backup registers can be powered
- from the VBAT voltage when the main VDD supply is powered off.
- To retain the content of the RTC backup registers and supply the RTC
- when VDD is turned off, VBAT pin can be connected to an optional
- standby voltage supplied by a battery or by another source.
-
- [..] To allow the RTC to operate even when the main digital supply (VDD)
- is turned off, the VBAT pin powers the following blocks:
- (#) The RTC
- (#) The LSE oscillator
- (#) PC13 to PC15 I/Os I/Os (when available)
-
- [..] When the backup domain is supplied by VDD (analog switch connected
- to VDD), the following functions are available:
- (#) PC14 and PC15 can be used as either GPIO or LSE pins
- (#) PC13 can be used as a GPIO or as the RTC_AF1 pin
-
- [..] When the backup domain is supplied by VBAT (analog switch connected
- to VBAT because VDD is not present), the following functions are available:
- (#) PC14 and PC15 can be used as LSE pins only
- (#) PC13 can be used as the RTC_AF1 pin
-
- ##### Backup Domain Reset #####
- ===============================================================================
- [..] The backup domain reset sets all RTC registers and the RCC_BDCR
- register to their reset values.
- A backup domain reset is generated when one of the following events
- occurs:
- (#) Software reset, triggered by setting the BDRST bit in the
- RCC Backup domain control register (RCC_BDCR). You can use the
- RCC_BackupResetCmd().
- (#) VDD or VBAT power on, if both supplies have previously been
- powered off.
-
- ##### Backup Domain Access #####
- ===============================================================================
- [..] After reset, the backup domain (RTC registers and RTC backup data
- registers) is protected against possible unwanted write accesses.
- [..] To enable access to the Backup Domain and RTC registers, proceed as follows:
- (#) Enable the Power Controller (PWR) APB1 interface clock using the
- RCC_APB1PeriphClockCmd() function.
- (#) Enable access to Backup domain using the PWR_BackupAccessCmd() function.
- (#) Select the RTC clock source using the RCC_RTCCLKConfig() function.
- (#) Enable RTC Clock using the RCC_RTCCLKCmd() function.
-
-
- ##### How to use this driver #####
- ===============================================================================
- [..]
- (+) Enable the backup domain access (see description in the section above)
- (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and
- RTC hour format using the RTC_Init() function.
-
- ***Time and Date configuration ***
- ==================================
- [..]
- (+) To configure the RTC Calendar (Time and Date) use the RTC_SetTime()
- and RTC_SetDate() functions.
- (+) To read the RTC Calendar, use the RTC_GetTime() and RTC_GetDate()
- functions.
- (+) To read the RTC subsecond, use the RTC_GetSubSecond() function.
- (+) Use the RTC_DayLightSavingConfig() function to add or sub one
- hour to the RTC Calendar.
-
- ***Alarm configuration ***
- ==========================
- [..]
- (+) To configure the RTC Alarm use the RTC_SetAlarm() function.
- (+) Enable the selected RTC Alarm using the RTC_AlarmCmd() function
- (+) To read the RTC Alarm, use the RTC_GetAlarm() function.
- (+) To read the RTC alarm SubSecond, use the RTC_GetAlarmSubSecond() function.
-
- ***RTC Wakeup configuration***
- ==========================
- [..]
- (+) Configure the RTC Wakeup Clock source use the RTC_WakeUpClockConfig()
- function.
- (+) Configure the RTC WakeUp Counter using the RTC_SetWakeUpCounter()
- function
- (+) Enable the RTC WakeUp using the RTC_WakeUpCmd() function
- (+) To read the RTC WakeUp Counter register, use the RTC_GetWakeUpCounter()
- function.
-
- ***Outputs configuration ***
- ============================
- [..] The RTC has 2 different outputs:
- (+) AFO_ALARM: this output is used to manage the RTC Alarm A.
- To output the selected RTC signal on RTC_AF1 pin, use the
- RTC_OutputConfig() function.
- (+) AFO_CALIB: this output is 512Hz signal or 1Hz .
- To output the RTC Clock on RTC_AF1 pin, use the RTC_CalibOutputCmd()
- function.
-
- ***Original Digital Calibration configuration ***
- =================================
- [..] Configure the RTC Original Digital Calibration Value and the corresponding
- calibration cycle period (32s,16s and 8s) using the RTC_SmoothCalibConfig()
- function.
-
- ***TimeStamp configuration ***
- ==============================
- [..]
- (+) Configure the RTC_AF1 trigger and enables the RTC TimeStamp
- using the RTC_TimeStampCmd() function.
- (+) To read the RTC TimeStamp Time and Date register, use the
- RTC_GetTimeStamp() function.
- (+) To read the RTC TimeStamp SubSecond register, use the
- RTC_GetTimeStampSubSecond() function.
-
- ***Tamper configuration ***
- ===========================
- [..]
- (+) Configure the Tamper filter count using RTC_TamperFilterConfig()
- function.
- (+) Configure the RTC Tamper trigger Edge or Level according to the Tamper
- filter (if equal to 0 Edge else Level) value using the RTC_TamperConfig() function
- (+) Configure the Tamper sampling frequency using RTC_TamperSamplingFreqConfig()
- function.
- (+) Configure the Tamper precharge or discharge duration using
- RTC_TamperPinsPrechargeDuration() function.
- (+) Enable the Tamper Pull-UP using RTC_TamperPullUpDisableCmd() function.
- (+) Enable the RTC Tamper using the RTC_TamperCmd() function.
- (+) Enable the Time stamp on Tamper detection event using
- RTC_TSOnTamperDetecCmd() function.
-
- ***Backup Data Registers configuration ***
- ==========================================
- [..]
- (+) To write to the RTC Backup Data registers, use the RTC_WriteBackupRegister()
- function.
- (+) To read the RTC Backup Data registers, use the RTC_ReadBackupRegister()
- function.
-
- ##### RTC and low power modes #####
- ===============================================================================
- [..] The MCU can be woken up from a low power mode by an RTC alternate
- function.
- [..] The RTC alternate functions are the RTC alarm (Alarm A), RTC tamper
- event detection and RTC time stamp event detection.
- These RTC alternate functions can wake up the system from the Stop
- and Standby lowpower modes.
- The system can also wake up from low power modes without depending
- on an external interrupt (Auto-wakeup mode), by using the RTC alarm events.
- [..] The RTC provides a programmable time base for waking up from the
- Stop or Standby mode at regular intervals.
- Wakeup from STOP and Standby modes is possible only when the RTC
- clock source is LSE or LSI.
-
- ##### Selection of RTC_AF1 alternate functions #####
- ===============================================================================
- [..] The RTC_AF1 pin (PC13) can be used for the following purposes:
- (+) AFO_ALARM output
- (+) AFO_CALIB output
- (+) AFI_TAMPER
- (+) AFI_TIMESTAMP
-
- +------------------------------------------------------------------------------------------+
- | Pin |AFO_ALARM |AFO_CALIB |AFI_TAMPER |AFI_TIMESTAMP | WKUP2 |ALARMOUTTYPE |
- | configuration | ENABLED | ENABLED | ENABLED | ENABLED |ENABLED | AFO_ALARM |
- | and function | | | | | |Configuration |
- |-----------------|----------|----------|-----------|--------------|--------|--------------|
- | Alarm out | | | | | Don't | |
- | output OD | 1 | 0 |Don't care | Don't care | care | 0 |
- |-----------------|----------|----------|-----------|--------------|--------|--------------|
- | Alarm out | | | | | Don't | |
- | output PP | 1 | 0 |Don't care | Don't care | care | 1 |
- |-----------------|----------|----------|-----------|--------------|--------|--------------|
- | Calibration out | | | | | Don't | |
- | output PP | 0 | 1 |Don't care | Don't care | care | Don't care |
- |-----------------|----------|----------|-----------|--------------|--------|--------------|
- | TAMPER input | | | | | Don't | |
- | floating | 0 | 0 | 1 | 0 | care | Don't care |
- |-----------------|----------|----------|-----------|--------------|--------|--------------|
- | TIMESTAMP and | | | | | Don't | |
- | TAMPER input | 0 | 0 | 1 | 1 | care | Don't care |
- | floating | | | | | | |
- |-----------------|----------|----------|-----------|--------------|--------|--------------|
- | TIMESTAMP input | | | | | Don't | |
- | floating | 0 | 0 | 0 | 1 | care | Don't care |
- |-----------------|----------|----------|-----------|--------------|--------|--------------|
- | Wakeup Pin 2 | 0 | 0 | 0 | 0 | 1 | Don't care |
- |-----------------|----------|----------|-----------|--------------|--------|--------------|
- | Standard GPIO | 0 | 0 | 0 | 0 | 0 | Don't care |
- +------------------------------------------------------------------------------------------+
-
- @endverbatim
-
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx_rtc.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup RTC
- * @brief RTC driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-/* Masks Definition */
-#define RTC_TR_RESERVED_MASK ((uint32_t)0x007F7F7F)
-#define RTC_DR_RESERVED_MASK ((uint32_t)0x00FFFF3F)
-#define RTC_INIT_MASK ((uint32_t)0xFFFFFFFF)
-#define RTC_RSF_MASK ((uint32_t)0xFFFFFF5F)
-#define RTC_FLAGS_MASK ((uint32_t)(RTC_FLAG_TSOVF | RTC_FLAG_TSF | RTC_FLAG_ALRAF | \
- RTC_FLAG_RSF | RTC_FLAG_INITS |RTC_FLAG_INITF | \
- RTC_FLAG_TAMP1F | RTC_FLAG_TAMP2F | RTC_FLAG_RECALPF | \
- RTC_FLAG_SHPF))
-
-#define INITMODE_TIMEOUT ((uint32_t) 0x00004000)
-#define SYNCHRO_TIMEOUT ((uint32_t) 0x00008000)
-#define RECALPF_TIMEOUT ((uint32_t) 0x00001000)
-#define SHPF_TIMEOUT ((uint32_t) 0x00001000)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-static uint8_t RTC_ByteToBcd2(uint8_t Value);
-static uint8_t RTC_Bcd2ToByte(uint8_t Value);
-
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup RTC_Private_Functions
- * @{
- */
-
-/** @defgroup RTC_Group1 Initialization and Configuration functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and Configuration functions #####
- ===============================================================================
-
- [..] This section provide functions allowing to initialize and configure the RTC
- Prescaler (Synchronous and Asynchronous), RTC Hour format, disable RTC registers
- Write protection, enter and exit the RTC initialization mode, RTC registers
- synchronization check and reference clock detection enable.
-
- (#) The RTC Prescaler is programmed to generate the RTC 1Hz time base.
- It is split into 2 programmable prescalers to minimize power consumption.
- (++) A 7-bit asynchronous prescaler and A 13-bit synchronous prescaler.
- (++) When both prescalers are used, it is recommended to configure the
- asynchronous prescaler to a high value to minimize consumption.
- (#) All RTC registers are Write protected. Writing to the RTC registers
- is enabled by writing a key into the Write Protection register, RTC_WPR.
- (#) To Configure the RTC Calendar, user application should enter
- initialization mode. In this mode, the calendar counter is stopped
- and its value can be updated. When the initialization sequence is
- complete, the calendar restarts counting after 4 RTCCLK cycles.
- (#) To read the calendar through the shadow registers after Calendar
- initialization, calendar update or after wakeup from low power modes
- the software must first clear the RSF flag. The software must then
- wait until it is set again before reading the calendar, which means
- that the calendar registers have been correctly copied into the
- RTC_TR and RTC_DR shadow registers.The RTC_WaitForSynchro() function
- implements the above software sequence (RSF clear and RSF check).
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitializes the RTC registers to their default reset values.
- * @note This function doesn't reset the RTC Clock source and RTC Backup Data
- * registers.
- * @param None
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: RTC registers are deinitialized
- * - ERROR: RTC registers are not deinitialized
- */
-ErrorStatus RTC_DeInit(void)
-{
- ErrorStatus status = ERROR;
-
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- /* Set Initialization mode */
- if (RTC_EnterInitMode() == ERROR)
- {
- status = ERROR;
- }
- else
- {
- /* Reset TR, DR and CR registers */
- RTC->TR = (uint32_t)0x00000000;
- RTC->WUTR = (uint32_t)0x0000FFFF;
- RTC->DR = (uint32_t)0x00002101;
- RTC->CR &= (uint32_t)0x00000000;
- RTC->PRER = (uint32_t)0x007F00FF;
- RTC->ALRMAR = (uint32_t)0x00000000;
- RTC->SHIFTR = (uint32_t)0x00000000;
- RTC->CALR = (uint32_t)0x00000000;
- RTC->ALRMASSR = (uint32_t)0x00000000;
-
- /* Reset ISR register and exit initialization mode */
- RTC->ISR = (uint32_t)0x00000000;
-
- /* Reset Tamper and alternate functions configuration register */
- RTC->TAFCR = 0x00000000;
-
- /* Wait till the RTC RSF flag is set */
- if (RTC_WaitForSynchro() == ERROR)
- {
- status = ERROR;
- }
- else
- {
- status = SUCCESS;
- }
-
- }
-
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
-
- return status;
-}
-
-/**
- * @brief Initializes the RTC registers according to the specified parameters
- * in RTC_InitStruct.
- * @param RTC_InitStruct: pointer to a RTC_InitTypeDef structure that contains
- * the configuration information for the RTC peripheral.
- * @note The RTC Prescaler register is write protected and can be written in
- * initialization mode only.
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: RTC registers are initialized
- * - ERROR: RTC registers are not initialized
- */
-ErrorStatus RTC_Init(RTC_InitTypeDef* RTC_InitStruct)
-{
- ErrorStatus status = ERROR;
-
- /* Check the parameters */
- assert_param(IS_RTC_HOUR_FORMAT(RTC_InitStruct->RTC_HourFormat));
- assert_param(IS_RTC_ASYNCH_PREDIV(RTC_InitStruct->RTC_AsynchPrediv));
- assert_param(IS_RTC_SYNCH_PREDIV(RTC_InitStruct->RTC_SynchPrediv));
-
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- /* Set Initialization mode */
- if (RTC_EnterInitMode() == ERROR)
- {
- status = ERROR;
- }
- else
- {
- /* Clear RTC CR FMT Bit */
- RTC->CR &= ((uint32_t)~(RTC_CR_FMT));
- /* Set RTC_CR register */
- RTC->CR |= ((uint32_t)(RTC_InitStruct->RTC_HourFormat));
-
- /* Configure the RTC PRER */
- RTC->PRER = (uint32_t)(RTC_InitStruct->RTC_SynchPrediv);
- RTC->PRER |= (uint32_t)(RTC_InitStruct->RTC_AsynchPrediv << 16);
-
- /* Exit Initialization mode */
- RTC_ExitInitMode();
-
- status = SUCCESS;
- }
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
-
- return status;
-}
-
-/**
- * @brief Fills each RTC_InitStruct member with its default value.
- * @param RTC_InitStruct: pointer to a RTC_InitTypeDef structure which will be
- * initialized.
- * @retval None
- */
-void RTC_StructInit(RTC_InitTypeDef* RTC_InitStruct)
-{
- /* Initialize the RTC_HourFormat member */
- RTC_InitStruct->RTC_HourFormat = RTC_HourFormat_24;
-
- /* Initialize the RTC_AsynchPrediv member */
- RTC_InitStruct->RTC_AsynchPrediv = (uint32_t)0x7F;
-
- /* Initialize the RTC_SynchPrediv member */
- RTC_InitStruct->RTC_SynchPrediv = (uint32_t)0xFF;
-}
-
-/**
- * @brief Enables or disables the RTC registers write protection.
- * @note All the RTC registers are write protected except for RTC_ISR[13:8],
- * RTC_TAFCR and RTC_BKPxR.
- * @note Writing a wrong key reactivates the write protection.
- * @note The protection mechanism is not affected by system reset.
- * @param NewState: new state of the write protection.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RTC_WriteProtectionCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
- }
- else
- {
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
- }
-}
-
-/**
- * @brief Enters the RTC Initialization mode.
- * @note The RTC Initialization mode is write protected, use the
- * RTC_WriteProtectionCmd(DISABLE) before calling this function.
- * @param None
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: RTC is in Init mode
- * - ERROR: RTC is not in Init mode
- */
-ErrorStatus RTC_EnterInitMode(void)
-{
- __IO uint32_t initcounter = 0x00;
- ErrorStatus status = ERROR;
- uint32_t initstatus = 0x00;
-
- /* Check if the Initialization mode is set */
- if ((RTC->ISR & RTC_ISR_INITF) == (uint32_t)RESET)
- {
- /* Set the Initialization mode */
- RTC->ISR = (uint32_t)RTC_INIT_MASK;
-
- /* Wait till RTC is in INIT state and if Time out is reached exit */
- do
- {
- initstatus = RTC->ISR & RTC_ISR_INITF;
- initcounter++;
- } while((initcounter != INITMODE_TIMEOUT) && (initstatus == 0x00));
-
- if ((RTC->ISR & RTC_ISR_INITF) != RESET)
- {
- status = SUCCESS;
- }
- else
- {
- status = ERROR;
- }
- }
- else
- {
- status = SUCCESS;
- }
-
- return (status);
-}
-
-/**
- * @brief Exits the RTC Initialization mode.
- * @note When the initialization sequence is complete, the calendar restarts
- * counting after 4 RTCCLK cycles.
- * @note The RTC Initialization mode is write protected, use the
- * RTC_WriteProtectionCmd(DISABLE) before calling this function.
- * @param None
- * @retval None
- */
-void RTC_ExitInitMode(void)
-{
- /* Exit Initialization mode */
- RTC->ISR &= (uint32_t)~RTC_ISR_INIT;
-}
-
-/**
- * @brief Waits until the RTC Time and Date registers (RTC_TR and RTC_DR) are
- * synchronized with RTC APB clock.
- * @note The RTC Resynchronization mode is write protected, use the
- * RTC_WriteProtectionCmd(DISABLE) before calling this function.
- * @note To read the calendar through the shadow registers after Calendar
- * initialization, calendar update or after wakeup from low power modes
- * the software must first clear the RSF flag.
- * The software must then wait until it is set again before reading
- * the calendar, which means that the calendar registers have been
- * correctly copied into the RTC_TR and RTC_DR shadow registers.
- * @param None
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: RTC registers are synchronised
- * - ERROR: RTC registers are not synchronised
- */
-ErrorStatus RTC_WaitForSynchro(void)
-{
- __IO uint32_t synchrocounter = 0;
- ErrorStatus status = ERROR;
- uint32_t synchrostatus = 0x00;
-
- if ((RTC->CR & RTC_CR_BYPSHAD) != RESET)
- {
- /* Bypass shadow mode */
- status = SUCCESS;
- }
- else
- {
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- /* Clear RSF flag */
- RTC->ISR &= (uint32_t)RTC_RSF_MASK;
-
- /* Wait the registers to be synchronised */
- do
- {
- synchrostatus = RTC->ISR & RTC_ISR_RSF;
- synchrocounter++;
- } while((synchrocounter != SYNCHRO_TIMEOUT) && (synchrostatus == 0x00));
-
- if ((RTC->ISR & RTC_ISR_RSF) != RESET)
- {
- status = SUCCESS;
- }
- else
- {
- status = ERROR;
- }
-
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
- }
-
- return (status);
-}
-
-/**
- * @brief Enables or disables the RTC reference clock detection.
- * @param NewState: new state of the RTC reference clock.
- * This parameter can be: ENABLE or DISABLE.
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: RTC reference clock detection is enabled
- * - ERROR: RTC reference clock detection is disabled
- */
-ErrorStatus RTC_RefClockCmd(FunctionalState NewState)
-{
- ErrorStatus status = ERROR;
-
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- /* Set Initialization mode */
- if (RTC_EnterInitMode() == ERROR)
- {
- status = ERROR;
- }
- else
- {
- if (NewState != DISABLE)
- {
- /* Enable the RTC reference clock detection */
- RTC->CR |= RTC_CR_REFCKON;
- }
- else
- {
- /* Disable the RTC reference clock detection */
- RTC->CR &= ~RTC_CR_REFCKON;
- }
- /* Exit Initialization mode */
- RTC_ExitInitMode();
-
- status = SUCCESS;
- }
-
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
-
- return status;
-}
-
-/**
- * @brief Enables or Disables the Bypass Shadow feature.
- * @note When the Bypass Shadow is enabled the calendar value are taken
- * directly from the Calendar counter.
- * @param NewState: new state of the Bypass Shadow feature.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
-*/
-void RTC_BypassShadowCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- if (NewState != DISABLE)
- {
- /* Set the BYPSHAD bit */
- RTC->CR |= (uint8_t)RTC_CR_BYPSHAD;
- }
- else
- {
- /* Reset the BYPSHAD bit */
- RTC->CR &= (uint8_t)~RTC_CR_BYPSHAD;
- }
-
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
-}
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Group2 Time and Date configuration functions
- * @brief Time and Date configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Time and Date configuration functions #####
- ===============================================================================
- [..] This section provide functions allowing to program and read the RTC
- Calendar (Time and Date).
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Set the RTC current time.
- * @param RTC_Format: specifies the format of the entered parameters.
- * This parameter can be one of the following values:
- * @arg RTC_Format_BIN: Binary data format
- * @arg RTC_Format_BCD: BCD data format
- * @param RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure that contains
- * the time configuration information for the RTC.
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: RTC Time register is configured
- * - ERROR: RTC Time register is not configured
- */
-ErrorStatus RTC_SetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct)
-{
- uint32_t tmpreg = 0;
- ErrorStatus status = ERROR;
-
- /* Check the parameters */
- assert_param(IS_RTC_FORMAT(RTC_Format));
-
- if (RTC_Format == RTC_Format_BIN)
- {
- if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET)
- {
- assert_param(IS_RTC_HOUR12(RTC_TimeStruct->RTC_Hours));
- assert_param(IS_RTC_H12(RTC_TimeStruct->RTC_H12));
- }
- else
- {
- RTC_TimeStruct->RTC_H12 = 0x00;
- assert_param(IS_RTC_HOUR24(RTC_TimeStruct->RTC_Hours));
- }
- assert_param(IS_RTC_MINUTES(RTC_TimeStruct->RTC_Minutes));
- assert_param(IS_RTC_SECONDS(RTC_TimeStruct->RTC_Seconds));
- }
- else
- {
- if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET)
- {
- tmpreg = RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours);
- assert_param(IS_RTC_HOUR12(tmpreg));
- assert_param(IS_RTC_H12(RTC_TimeStruct->RTC_H12));
- }
- else
- {
- RTC_TimeStruct->RTC_H12 = 0x00;
- assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours)));
- }
- assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Minutes)));
- assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Seconds)));
- }
-
- /* Check the input parameters format */
- if (RTC_Format != RTC_Format_BIN)
- {
- tmpreg = (((uint32_t)(RTC_TimeStruct->RTC_Hours) << 16) | \
- ((uint32_t)(RTC_TimeStruct->RTC_Minutes) << 8) | \
- ((uint32_t)RTC_TimeStruct->RTC_Seconds) | \
- ((uint32_t)(RTC_TimeStruct->RTC_H12) << 16));
- }
- else
- {
- tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Hours) << 16) | \
- ((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Minutes) << 8) | \
- ((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Seconds)) | \
- (((uint32_t)RTC_TimeStruct->RTC_H12) << 16));
- }
-
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- /* Set Initialization mode */
- if (RTC_EnterInitMode() == ERROR)
- {
- status = ERROR;
- }
- else
- {
- /* Set the RTC_TR register */
- RTC->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK);
-
- /* Exit Initialization mode */
- RTC_ExitInitMode();
-
- /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
- if ((RTC->CR & RTC_CR_BYPSHAD) == RESET)
- {
- if (RTC_WaitForSynchro() == ERROR)
- {
- status = ERROR;
- }
- else
- {
- status = SUCCESS;
- }
- }
- else
- {
- status = SUCCESS;
- }
-
- }
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
-
- return status;
-}
-
-/**
- * @brief Fills each RTC_TimeStruct member with its default value
- * (Time = 00h:00min:00sec).
- * @param RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure which will be
- * initialized.
- * @retval None
- */
-void RTC_TimeStructInit(RTC_TimeTypeDef* RTC_TimeStruct)
-{
- /* Time = 00h:00min:00sec */
- RTC_TimeStruct->RTC_H12 = RTC_H12_AM;
- RTC_TimeStruct->RTC_Hours = 0;
- RTC_TimeStruct->RTC_Minutes = 0;
- RTC_TimeStruct->RTC_Seconds = 0;
-}
-
-/**
- * @brief Get the RTC current Time.
- * @param RTC_Format: specifies the format of the returned parameters.
- * This parameter can be one of the following values:
- * @arg RTC_Format_BIN: Binary data format
- * @arg RTC_Format_BCD: BCD data format
- * @param RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure that will
- * contain the returned current time configuration.
- * @retval None
- */
-void RTC_GetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RTC_FORMAT(RTC_Format));
-
- /* Get the RTC_TR register */
- tmpreg = (uint32_t)(RTC->TR & RTC_TR_RESERVED_MASK);
-
- /* Fill the structure fields with the read parameters */
- RTC_TimeStruct->RTC_Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> 16);
- RTC_TimeStruct->RTC_Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >>8);
- RTC_TimeStruct->RTC_Seconds = (uint8_t)(tmpreg & (RTC_TR_ST | RTC_TR_SU));
- RTC_TimeStruct->RTC_H12 = (uint8_t)((tmpreg & (RTC_TR_PM)) >> 16);
-
- /* Check the input parameters format */
- if (RTC_Format == RTC_Format_BIN)
- {
- /* Convert the structure parameters to Binary format */
- RTC_TimeStruct->RTC_Hours = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours);
- RTC_TimeStruct->RTC_Minutes = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Minutes);
- RTC_TimeStruct->RTC_Seconds = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Seconds);
- }
-}
-
-/**
- * @brief Gets the RTC current Calendar Subseconds value.
- * @note This function freeze the Time and Date registers after reading the
- * SSR register.
- * @param None
- * @retval RTC current Calendar Subseconds value.
- */
-uint32_t RTC_GetSubSecond(void)
-{
- uint32_t tmpreg = 0;
-
- /* Get subseconds values from the correspondent registers*/
- tmpreg = (uint32_t)(RTC->SSR);
-
- /* Read DR register to unfroze calendar registers */
- (void) (RTC->DR);
-
- return (tmpreg);
-}
-
-/**
- * @brief Set the RTC current date.
- * @param RTC_Format: specifies the format of the entered parameters.
- * This parameter can be one of the following values:
- * @arg RTC_Format_BIN: Binary data format
- * @arg RTC_Format_BCD: BCD data format
- * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure that contains
- * the date configuration information for the RTC.
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: RTC Date register is configured
- * - ERROR: RTC Date register is not configured
- */
-ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct)
-{
- uint32_t tmpreg = 0;
- ErrorStatus status = ERROR;
-
- /* Check the parameters */
- assert_param(IS_RTC_FORMAT(RTC_Format));
-
- if ((RTC_Format == RTC_Format_BIN) && ((RTC_DateStruct->RTC_Month & 0x10) == 0x10))
- {
- RTC_DateStruct->RTC_Month = (RTC_DateStruct->RTC_Month & (uint32_t)~(0x10)) + 0x0A;
- }
- if (RTC_Format == RTC_Format_BIN)
- {
- assert_param(IS_RTC_YEAR(RTC_DateStruct->RTC_Year));
- assert_param(IS_RTC_MONTH(RTC_DateStruct->RTC_Month));
- assert_param(IS_RTC_DATE(RTC_DateStruct->RTC_Date));
- }
- else
- {
- assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(RTC_DateStruct->RTC_Year)));
- tmpreg = RTC_Bcd2ToByte(RTC_DateStruct->RTC_Month);
- assert_param(IS_RTC_MONTH(tmpreg));
- tmpreg = RTC_Bcd2ToByte(RTC_DateStruct->RTC_Date);
- assert_param(IS_RTC_DATE(tmpreg));
- }
- assert_param(IS_RTC_WEEKDAY(RTC_DateStruct->RTC_WeekDay));
-
- /* Check the input parameters format */
- if (RTC_Format != RTC_Format_BIN)
- {
- tmpreg = ((((uint32_t)RTC_DateStruct->RTC_Year) << 16) | \
- (((uint32_t)RTC_DateStruct->RTC_Month) << 8) | \
- ((uint32_t)RTC_DateStruct->RTC_Date) | \
- (((uint32_t)RTC_DateStruct->RTC_WeekDay) << 13));
- }
- else
- {
- tmpreg = (((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Year) << 16) | \
- ((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Month) << 8) | \
- ((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Date)) | \
- ((uint32_t)RTC_DateStruct->RTC_WeekDay << 13));
- }
-
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- /* Set Initialization mode */
- if (RTC_EnterInitMode() == ERROR)
- {
- status = ERROR;
- }
- else
- {
- /* Set the RTC_DR register */
- RTC->DR = (uint32_t)(tmpreg & RTC_DR_RESERVED_MASK);
-
- /* Exit Initialization mode */
- RTC_ExitInitMode();
-
- /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
- if ((RTC->CR & RTC_CR_BYPSHAD) == RESET)
- {
- if (RTC_WaitForSynchro() == ERROR)
- {
- status = ERROR;
- }
- else
- {
- status = SUCCESS;
- }
- }
- else
- {
- status = SUCCESS;
- }
- }
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
-
- return status;
-}
-
-/**
- * @brief Fills each RTC_DateStruct member with its default value
- * (Monday, January 01 xx00).
- * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure which will be
- * initialized.
- * @retval None
- */
-void RTC_DateStructInit(RTC_DateTypeDef* RTC_DateStruct)
-{
- /* Monday, January 01 xx00 */
- RTC_DateStruct->RTC_WeekDay = RTC_Weekday_Monday;
- RTC_DateStruct->RTC_Date = 1;
- RTC_DateStruct->RTC_Month = RTC_Month_January;
- RTC_DateStruct->RTC_Year = 0;
-}
-
-/**
- * @brief Get the RTC current date.
- * @param RTC_Format: specifies the format of the returned parameters.
- * This parameter can be one of the following values:
- * @arg RTC_Format_BIN: Binary data format
- * @arg RTC_Format_BCD: BCD data format
- * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure that will
- * contain the returned current date configuration.
- * @retval None
- */
-void RTC_GetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RTC_FORMAT(RTC_Format));
-
- /* Get the RTC_TR register */
- tmpreg = (uint32_t)(RTC->DR & RTC_DR_RESERVED_MASK);
-
- /* Fill the structure fields with the read parameters */
- RTC_DateStruct->RTC_Year = (uint8_t)((tmpreg & (RTC_DR_YT | RTC_DR_YU)) >> 16);
- RTC_DateStruct->RTC_Month = (uint8_t)((tmpreg & (RTC_DR_MT | RTC_DR_MU)) >> 8);
- RTC_DateStruct->RTC_Date = (uint8_t)(tmpreg & (RTC_DR_DT | RTC_DR_DU));
- RTC_DateStruct->RTC_WeekDay = (uint8_t)((tmpreg & (RTC_DR_WDU)) >> 13);
-
- /* Check the input parameters format */
- if (RTC_Format == RTC_Format_BIN)
- {
- /* Convert the structure parameters to Binary format */
- RTC_DateStruct->RTC_Year = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Year);
- RTC_DateStruct->RTC_Month = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Month);
- RTC_DateStruct->RTC_Date = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Date);
- RTC_DateStruct->RTC_WeekDay = (uint8_t)(RTC_DateStruct->RTC_WeekDay);
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Group3 Alarms configuration functions
- * @brief Alarms (Alarm A) configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Alarms (Alarm A and Alarm B) configuration functions #####
- ===============================================================================
- [..] This section provide functions allowing to program and read the RTC
- Alarms.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Set the specified RTC Alarm.
- * @note The Alarm register can only be written when the corresponding Alarm
- * is disabled (Use the RTC_AlarmCmd(DISABLE)).
- * @param RTC_Format: specifies the format of the returned parameters.
- * This parameter can be one of the following values:
- * @arg RTC_Format_BIN: Binary data format
- * @arg RTC_Format_BCD: BCD data format
- * @param RTC_Alarm: specifies the alarm to be configured.
- * This parameter can be one of the following values:
- * @arg RTC_Alarm_A: to select Alarm A
- * @param RTC_AlarmStruct: pointer to a RTC_AlarmTypeDef structure that
- * contains the alarm configuration parameters.
- * @retval None
- */
-void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RTC_FORMAT(RTC_Format));
- assert_param(IS_RTC_ALARM(RTC_Alarm));
- assert_param(IS_RTC_ALARM_MASK(RTC_AlarmStruct->RTC_AlarmMask));
- assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel));
-
- if (RTC_Format == RTC_Format_BIN)
- {
- if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET)
- {
- assert_param(IS_RTC_HOUR12(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours));
- assert_param(IS_RTC_H12(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12));
- }
- else
- {
- RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = 0x00;
- assert_param(IS_RTC_HOUR24(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours));
- }
- assert_param(IS_RTC_MINUTES(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes));
- assert_param(IS_RTC_SECONDS(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds));
-
- if(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel == RTC_AlarmDateWeekDaySel_Date)
- {
- assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(RTC_AlarmStruct->RTC_AlarmDateWeekDay));
- }
- else
- {
- assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_AlarmStruct->RTC_AlarmDateWeekDay));
- }
- }
- else
- {
- if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET)
- {
- tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours);
- assert_param(IS_RTC_HOUR12(tmpreg));
- assert_param(IS_RTC_H12(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12));
- }
- else
- {
- RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = 0x00;
- assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours)));
- }
-
- assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes)));
- assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds)));
-
- if(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel == RTC_AlarmDateWeekDaySel_Date)
- {
- tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay);
- assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg));
- }
- else
- {
- tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay);
- assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg));
- }
- }
-
- /* Check the input parameters format */
- if (RTC_Format != RTC_Format_BIN)
- {
- tmpreg = (((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours) << 16) | \
- ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes) << 8) | \
- ((uint32_t)RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds) | \
- ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12) << 16) | \
- ((uint32_t)(RTC_AlarmStruct->RTC_AlarmDateWeekDay) << 24) | \
- ((uint32_t)RTC_AlarmStruct->RTC_AlarmDateWeekDaySel) | \
- ((uint32_t)RTC_AlarmStruct->RTC_AlarmMask));
- }
- else
- {
- tmpreg = (((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours) << 16) | \
- ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes) << 8) | \
- ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds)) | \
- ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12) << 16) | \
- ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmDateWeekDay) << 24) | \
- ((uint32_t)RTC_AlarmStruct->RTC_AlarmDateWeekDaySel) | \
- ((uint32_t)RTC_AlarmStruct->RTC_AlarmMask));
- }
-
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- /* Configure the Alarm register */
- RTC->ALRMAR = (uint32_t)tmpreg;
-
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
-}
-
-/**
- * @brief Fills each RTC_AlarmStruct member with its default value
- * (Time = 00h:00mn:00sec / Date = 1st day of the month/Mask =
- * all fields are masked).
- * @param RTC_AlarmStruct: pointer to a @ref RTC_AlarmTypeDef structure which
- * will be initialized.
- * @retval None
- */
-void RTC_AlarmStructInit(RTC_AlarmTypeDef* RTC_AlarmStruct)
-{
- /* Alarm Time Settings : Time = 00h:00mn:00sec */
- RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = RTC_H12_AM;
- RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = 0;
- RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = 0;
- RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = 0;
-
- /* Alarm Date Settings : Date = 1st day of the month */
- RTC_AlarmStruct->RTC_AlarmDateWeekDaySel = RTC_AlarmDateWeekDaySel_Date;
- RTC_AlarmStruct->RTC_AlarmDateWeekDay = 1;
-
- /* Alarm Masks Settings : Mask = all fields are not masked */
- RTC_AlarmStruct->RTC_AlarmMask = RTC_AlarmMask_None;
-}
-
-/**
- * @brief Get the RTC Alarm value and masks.
- * @param RTC_Format: specifies the format of the output parameters.
- * This parameter can be one of the following values:
- * @arg RTC_Format_BIN: Binary data format
- * @arg RTC_Format_BCD: BCD data format
- * @param RTC_Alarm: specifies the alarm to be read.
- * This parameter can be one of the following values:
- * @arg RTC_Alarm_A: to select Alarm A
- * @param RTC_AlarmStruct: pointer to a RTC_AlarmTypeDef structure that will
- * contains the output alarm configuration values.
- * @retval None
- */
-void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RTC_FORMAT(RTC_Format));
- assert_param(IS_RTC_ALARM(RTC_Alarm));
-
- /* Get the RTC_ALRMAR register */
- tmpreg = (uint32_t)(RTC->ALRMAR);
-
- /* Fill the structure with the read parameters */
- RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = (uint32_t)((tmpreg & (RTC_ALRMAR_HT | \
- RTC_ALRMAR_HU)) >> 16);
- RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = (uint32_t)((tmpreg & (RTC_ALRMAR_MNT | \
- RTC_ALRMAR_MNU)) >> 8);
- RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = (uint32_t)(tmpreg & (RTC_ALRMAR_ST | \
- RTC_ALRMAR_SU));
- RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = (uint32_t)((tmpreg & RTC_ALRMAR_PM) >> 16);
- RTC_AlarmStruct->RTC_AlarmDateWeekDay = (uint32_t)((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> 24);
- RTC_AlarmStruct->RTC_AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMAR_WDSEL);
- RTC_AlarmStruct->RTC_AlarmMask = (uint32_t)(tmpreg & RTC_AlarmMask_All);
-
- if (RTC_Format == RTC_Format_BIN)
- {
- RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = RTC_Bcd2ToByte(RTC_AlarmStruct-> \
- RTC_AlarmTime.RTC_Hours);
- RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = RTC_Bcd2ToByte(RTC_AlarmStruct-> \
- RTC_AlarmTime.RTC_Minutes);
- RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = RTC_Bcd2ToByte(RTC_AlarmStruct-> \
- RTC_AlarmTime.RTC_Seconds);
- RTC_AlarmStruct->RTC_AlarmDateWeekDay = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay);
- }
-}
-
-/**
- * @brief Enables or disables the specified RTC Alarm.
- * @param RTC_Alarm: specifies the alarm to be configured.
- * This parameter can be any combination of the following values:
- * @arg RTC_Alarm_A: to select Alarm A
- * @param NewState: new state of the specified alarm.
- * This parameter can be: ENABLE or DISABLE.
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: RTC Alarm is enabled/disabled
- * - ERROR: RTC Alarm is not enabled/disabled
- */
-ErrorStatus RTC_AlarmCmd(uint32_t RTC_Alarm, FunctionalState NewState)
-{
- __IO uint32_t alarmcounter = 0x00;
- uint32_t alarmstatus = 0x00;
- ErrorStatus status = ERROR;
-
- /* Check the parameters */
- assert_param(IS_RTC_CMD_ALARM(RTC_Alarm));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- /* Configure the Alarm state */
- if (NewState != DISABLE)
- {
- RTC->CR |= (uint32_t)RTC_Alarm;
-
- status = SUCCESS;
- }
- else
- {
- /* Disable the Alarm in RTC_CR register */
- RTC->CR &= (uint32_t)~RTC_Alarm;
-
- /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */
- do
- {
- alarmstatus = RTC->ISR & (RTC_Alarm >> 8);
- alarmcounter++;
- } while((alarmcounter != INITMODE_TIMEOUT) && (alarmstatus == 0x00));
-
- if ((RTC->ISR & (RTC_Alarm >> 8)) == RESET)
- {
- status = ERROR;
- }
- else
- {
- status = SUCCESS;
- }
- }
-
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
-
- return status;
-}
-
-/**
- * @brief Configure the RTC AlarmA/B Subseconds value and mask.
- * @note This function is performed only when the Alarm is disabled.
- * @param RTC_Alarm: specifies the alarm to be configured.
- * This parameter can be one of the following values:
- * @arg RTC_Alarm_A: to select Alarm A
- * @param RTC_AlarmSubSecondValue: specifies the Subseconds value.
- * This parameter can be a value from 0 to 0x00007FFF.
- * @param RTC_AlarmSubSecondMask: specifies the Subseconds Mask.
- * This parameter can be any combination of the following values:
- * @arg RTC_AlarmSubSecondMask_All: All Alarm SS fields are masked.
- * There is no comparison on sub seconds for Alarm.
- * @arg RTC_AlarmSubSecondMask_SS14_1: SS[14:1] are don't care in Alarm comparison.
- * Only SS[0] is compared
- * @arg RTC_AlarmSubSecondMask_SS14_2: SS[14:2] are don't care in Alarm comparison.
- * Only SS[1:0] are compared
- * @arg RTC_AlarmSubSecondMask_SS14_3: SS[14:3] are don't care in Alarm comparison.
- * Only SS[2:0] are compared
- * @arg RTC_AlarmSubSecondMask_SS14_4: SS[14:4] are don't care in Alarm comparison.
- * Only SS[3:0] are compared
- * @arg RTC_AlarmSubSecondMask_SS14_5: SS[14:5] are don't care in Alarm comparison.
- * Only SS[4:0] are compared
- * @arg RTC_AlarmSubSecondMask_SS14_6: SS[14:6] are don't care in Alarm comparison.
- * Only SS[5:0] are compared
- * @arg RTC_AlarmSubSecondMask_SS14_7: SS[14:7] are don't care in Alarm comparison.
- * Only SS[6:0] are compared
- * @arg RTC_AlarmSubSecondMask_SS14_8: SS[14:8] are don't care in Alarm comparison.
- * Only SS[7:0] are compared
- * @arg RTC_AlarmSubSecondMask_SS14_9: SS[14:9] are don't care in Alarm comparison.
- * Only SS[8:0] are compared
- * @arg RTC_AlarmSubSecondMask_SS14_10: SS[14:10] are don't care in Alarm comparison.
- * Only SS[9:0] are compared
- * @arg RTC_AlarmSubSecondMask_SS14_11: SS[14:11] are don't care in Alarm comparison.
- * Only SS[10:0] are compared
- * @arg RTC_AlarmSubSecondMask_SS14_12: SS[14:12] are don't care in Alarm comparison.
- * Only SS[11:0] are compared
- * @arg RTC_AlarmSubSecondMask_SS14_13: SS[14:13] are don't care in Alarm comparison.
- * Only SS[12:0] are compared
- * @arg RTC_AlarmSubSecondMask_SS14: SS[14] is don't care in Alarm comparison.
- * Only SS[13:0] are compared
- * @arg RTC_AlarmSubSecondMask_None: SS[14:0] are compared and must match to activate alarm
- * @retval None
- */
-void RTC_AlarmSubSecondConfig(uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondValue, uint8_t RTC_AlarmSubSecondMask)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RTC_ALARM(RTC_Alarm));
- assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(RTC_AlarmSubSecondValue));
- assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(RTC_AlarmSubSecondMask));
-
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- /* Configure the Alarm A or Alarm B SubSecond registers */
- tmpreg = (uint32_t) (((uint32_t)(RTC_AlarmSubSecondValue)) | ((uint32_t)(RTC_AlarmSubSecondMask) << 24));
-
- /* Configure the AlarmA SubSecond register */
- RTC->ALRMASSR = tmpreg;
-
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
-
-}
-
-/**
- * @brief Gets the RTC Alarm Subseconds value.
- * @param RTC_Alarm: specifies the alarm to be read.
- * This parameter can be one of the following values:
- * @arg RTC_Alarm_A: to select Alarm A
- * @param None
- * @retval RTC Alarm Subseconds value.
- */
-uint32_t RTC_GetAlarmSubSecond(uint32_t RTC_Alarm)
-{
- uint32_t tmpreg = 0;
-
- /* Get the RTC_ALRMAR register */
- tmpreg = (uint32_t)((RTC->ALRMASSR) & RTC_ALRMASSR_SS);
-
- return (tmpreg);
-}
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Group4 WakeUp Timer configuration functions
- * @brief WakeUp Timer configuration functions
- *
-@verbatim
- ===============================================================================
- ##### WakeUp Timer configuration functions #####
- ===============================================================================
-
- [..] This section provide functions allowing to program and read the RTC WakeUp.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures the RTC Wakeup clock source.
- * This function is available for STM32F072 devices.
- * @note The WakeUp Clock source can only be changed when the RTC WakeUp
- * is disabled (Use the RTC_WakeUpCmd(DISABLE)).
- * @param RTC_WakeUpClock: Wakeup Clock source.
- * This parameter can be one of the following values:
- * @arg RTC_WakeUpClock_RTCCLK_Div16
- * @arg RTC_WakeUpClock_RTCCLK_Div8
- * @arg RTC_WakeUpClock_RTCCLK_Div4
- * @arg RTC_WakeUpClock_RTCCLK_Div2
- * @arg RTC_WakeUpClock_CK_SPRE_16bits
- * @arg RTC_WakeUpClock_CK_SPRE_17bits
- * @retval None
- */
-void RTC_WakeUpClockConfig(uint32_t RTC_WakeUpClock)
-{
- /* Check the parameters */
- assert_param(IS_RTC_WAKEUP_CLOCK(RTC_WakeUpClock));
-
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- /* Clear the Wakeup Timer clock source bits in CR register */
- RTC->CR &= (uint32_t)~RTC_CR_WUCKSEL;
-
- /* Configure the clock source */
- RTC->CR |= (uint32_t)RTC_WakeUpClock;
-
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
-}
-
-/**
- * @brief Configures the RTC Wakeup counter.
- * This function is available for STM32F072 devices.
- * @note The RTC WakeUp counter can only be written when the RTC WakeUp
- * is disabled (Use the RTC_WakeUpCmd(DISABLE)).
- * @param RTC_WakeUpCounter: specifies the WakeUp counter.
- * This parameter can be a value from 0x0000 to 0xFFFF.
- * @retval None
- */
-void RTC_SetWakeUpCounter(uint32_t RTC_WakeUpCounter)
-{
- /* Check the parameters */
- assert_param(IS_RTC_WAKEUP_COUNTER(RTC_WakeUpCounter));
-
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- /* Configure the Wakeup Timer counter */
- RTC->WUTR = (uint32_t)RTC_WakeUpCounter;
-
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
-}
-
-/**
- * @brief Returns the RTC WakeUp timer counter value.
- * This function is available for STM32F072 devices.
- * @param None
- * @retval The RTC WakeUp Counter value.
- */
-uint32_t RTC_GetWakeUpCounter(void)
-{
- /* Get the counter value */
- return ((uint32_t)(RTC->WUTR & RTC_WUTR_WUT));
-}
-
-/**
- * @brief Enables or Disables the RTC WakeUp timer.
- * This function is available for STM32F072 devices.
- * @param NewState: new state of the WakeUp timer.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-ErrorStatus RTC_WakeUpCmd(FunctionalState NewState)
-{
- __IO uint32_t wutcounter = 0x00;
- uint32_t wutwfstatus = 0x00;
- ErrorStatus status = ERROR;
-
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- if (NewState != DISABLE)
- {
- /* Enable the Wakeup Timer */
- RTC->CR |= (uint32_t)RTC_CR_WUTE;
- status = SUCCESS;
- }
- else
- {
- /* Disable the Wakeup Timer */
- RTC->CR &= (uint32_t)~RTC_CR_WUTE;
- /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
- do
- {
- wutwfstatus = RTC->ISR & RTC_ISR_WUTWF;
- wutcounter++;
- } while((wutcounter != INITMODE_TIMEOUT) && (wutwfstatus == 0x00));
-
- if ((RTC->ISR & RTC_ISR_WUTWF) == RESET)
- {
- status = ERROR;
- }
- else
- {
- status = SUCCESS;
- }
- }
-
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
-
- return status;
-}
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Group5 Daylight Saving configuration functions
- * @brief Daylight Saving configuration functions
- *
-@verbatim
- ===============================================================================
- ##### WakeUp Timer configuration functions #####
- ===============================================================================
- [..] This section provide functions allowing to program and read the RTC WakeUp.
-
- This section provide functions allowing to configure the RTC DayLight Saving.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Adds or substract one hour from the current time.
- * @param RTC_DayLightSaveOperation: the value of hour adjustment.
- * This parameter can be one of the following values:
- * @arg RTC_DayLightSaving_SUB1H: Substract one hour (winter time)
- * @arg RTC_DayLightSaving_ADD1H: Add one hour (summer time)
- * @param RTC_StoreOperation: Specifies the value to be written in the BCK bit
- * in CR register to store the operation.
- * This parameter can be one of the following values:
- * @arg RTC_StoreOperation_Reset: BCK Bit Reset
- * @arg RTC_StoreOperation_Set: BCK Bit Set
- * @retval None
- */
-void RTC_DayLightSavingConfig(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation)
-{
- /* Check the parameters */
- assert_param(IS_RTC_DAYLIGHT_SAVING(RTC_DayLightSaving));
- assert_param(IS_RTC_STORE_OPERATION(RTC_StoreOperation));
-
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- /* Clear the bits to be configured */
- RTC->CR &= (uint32_t)~(RTC_CR_BCK);
-
- /* Configure the RTC_CR register */
- RTC->CR |= (uint32_t)(RTC_DayLightSaving | RTC_StoreOperation);
-
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
-}
-
-/**
- * @brief Returns the RTC Day Light Saving stored operation.
- * @param None
- * @retval RTC Day Light Saving stored operation.
- * - RTC_StoreOperation_Reset
- * - RTC_StoreOperation_Set
- */
-uint32_t RTC_GetStoreOperation(void)
-{
- return (RTC->CR & RTC_CR_BCK);
-}
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Group6 Output pin Configuration function
- * @brief Output pin Configuration function
- *
-@verbatim
- ===============================================================================
- ##### Output pin Configuration function #####
- ===============================================================================
- [..] This section provide functions allowing to configure the RTC Output source.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures the RTC output source (AFO_ALARM).
- * @param RTC_Output: Specifies which signal will be routed to the RTC output.
- * This parameter can be one of the following values:
- * @arg RTC_Output_Disable: No output selected
- * @arg RTC_Output_AlarmA: signal of AlarmA mapped to output
- * @arg RTC_Output_WakeUp: signal of WakeUp mapped to output, available only for STM32F072 devices
- * @param RTC_OutputPolarity: Specifies the polarity of the output signal.
- * This parameter can be one of the following:
- * @arg RTC_OutputPolarity_High: The output pin is high when the
- * ALRAF is high (depending on OSEL)
- * @arg RTC_OutputPolarity_Low: The output pin is low when the
- * ALRAF is high (depending on OSEL)
- * @retval None
- */
-void RTC_OutputConfig(uint32_t RTC_Output, uint32_t RTC_OutputPolarity)
-{
- /* Check the parameters */
- assert_param(IS_RTC_OUTPUT(RTC_Output));
- assert_param(IS_RTC_OUTPUT_POL(RTC_OutputPolarity));
-
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- /* Clear the bits to be configured */
- RTC->CR &= (uint32_t)~(RTC_CR_OSEL | RTC_CR_POL);
-
- /* Configure the output selection and polarity */
- RTC->CR |= (uint32_t)(RTC_Output | RTC_OutputPolarity);
-
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
-}
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Group7 Digital Calibration configuration functions
- * @brief Digital Calibration configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Digital Calibration configuration functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the RTC clock to be output through the relative pin.
- * @param NewState: new state of the digital calibration Output.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RTC_CalibOutputCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- if (NewState != DISABLE)
- {
- /* Enable the RTC clock output */
- RTC->CR |= (uint32_t)RTC_CR_COE;
- }
- else
- {
- /* Disable the RTC clock output */
- RTC->CR &= (uint32_t)~RTC_CR_COE;
- }
-
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
-}
-
-/**
- * @brief Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
- * @param RTC_CalibOutput: Select the Calibration output Selection .
- * This parameter can be one of the following values:
- * @arg RTC_CalibOutput_512Hz: A signal has a regular waveform at 512Hz.
- * @arg RTC_CalibOutput_1Hz: A signal has a regular waveform at 1Hz.
- * @retval None
-*/
-void RTC_CalibOutputConfig(uint32_t RTC_CalibOutput)
-{
- /* Check the parameters */
- assert_param(IS_RTC_CALIB_OUTPUT(RTC_CalibOutput));
-
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- /*clear flags before config*/
- RTC->CR &= (uint32_t)~(RTC_CR_CALSEL);
-
- /* Configure the RTC_CR register */
- RTC->CR |= (uint32_t)RTC_CalibOutput;
-
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
-}
-
-/**
- * @brief Configures the Smooth Calibration Settings.
- * @param RTC_SmoothCalibPeriod: Select the Smooth Calibration Period.
- * This parameter can be can be one of the following values:
- * @arg RTC_SmoothCalibPeriod_32sec: The smooth calibration periode is 32s.
- * @arg RTC_SmoothCalibPeriod_16sec: The smooth calibration periode is 16s.
- * @arg RTC_SmoothCalibPeriod_8sec: The smooth calibartion periode is 8s.
- * @param RTC_SmoothCalibPlusPulses: Select to Set or reset the CALP bit.
- * This parameter can be one of the following values:
- * @arg RTC_SmoothCalibPlusPulses_Set: Add one RTCCLK puls every 2**11 pulses.
- * @arg RTC_SmoothCalibPlusPulses_Reset: No RTCCLK pulses are added.
- * @param RTC_SmouthCalibMinusPulsesValue: Select the value of CALM[8:0] bits.
- * This parameter can be one any value from 0 to 0x000001FF.
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: RTC Calib registers are configured
- * - ERROR: RTC Calib registers are not configured
-*/
-ErrorStatus RTC_SmoothCalibConfig(uint32_t RTC_SmoothCalibPeriod,
- uint32_t RTC_SmoothCalibPlusPulses,
- uint32_t RTC_SmouthCalibMinusPulsesValue)
-{
- ErrorStatus status = ERROR;
- uint32_t recalpfcount = 0;
-
- /* Check the parameters */
- assert_param(IS_RTC_SMOOTH_CALIB_PERIOD(RTC_SmoothCalibPeriod));
- assert_param(IS_RTC_SMOOTH_CALIB_PLUS(RTC_SmoothCalibPlusPulses));
- assert_param(IS_RTC_SMOOTH_CALIB_MINUS(RTC_SmouthCalibMinusPulsesValue));
-
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- /* check if a calibration is pending*/
- if ((RTC->ISR & RTC_ISR_RECALPF) != RESET)
- {
- /* wait until the Calibration is completed*/
- while (((RTC->ISR & RTC_ISR_RECALPF) != RESET) && (recalpfcount != RECALPF_TIMEOUT))
- {
- recalpfcount++;
- }
- }
-
- /* check if the calibration pending is completed or if there is no calibration operation at all*/
- if ((RTC->ISR & RTC_ISR_RECALPF) == RESET)
- {
- /* Configure the Smooth calibration settings */
- RTC->CALR = (uint32_t)((uint32_t)RTC_SmoothCalibPeriod | (uint32_t)RTC_SmoothCalibPlusPulses | (uint32_t)RTC_SmouthCalibMinusPulsesValue);
-
- status = SUCCESS;
- }
- else
- {
- status = ERROR;
- }
-
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
-
- return (ErrorStatus)(status);
-}
-
-/**
- * @}
- */
-
-
-/** @defgroup RTC_Group8 TimeStamp configuration functions
- * @brief TimeStamp configuration functions
- *
-@verbatim
- ===============================================================================
- ##### TimeStamp configuration functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or Disables the RTC TimeStamp functionality with the
- * specified time stamp pin stimulating edge.
- * @param RTC_TimeStampEdge: Specifies the pin edge on which the TimeStamp is
- * activated.
- * This parameter can be one of the following:
- * @arg RTC_TimeStampEdge_Rising: the Time stamp event occurs on the rising
- * edge of the related pin.
- * @arg RTC_TimeStampEdge_Falling: the Time stamp event occurs on the
- * falling edge of the related pin.
- * @param NewState: new state of the TimeStamp.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RTC_TimeStampCmd(uint32_t RTC_TimeStampEdge, FunctionalState NewState)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RTC_TIMESTAMP_EDGE(RTC_TimeStampEdge));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- /* Get the RTC_CR register and clear the bits to be configured */
- tmpreg = (uint32_t)(RTC->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));
-
- /* Get the new configuration */
- if (NewState != DISABLE)
- {
- tmpreg |= (uint32_t)(RTC_TimeStampEdge | RTC_CR_TSE);
- }
- else
- {
- tmpreg |= (uint32_t)(RTC_TimeStampEdge);
- }
-
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- /* Configure the Time Stamp TSEDGE and Enable bits */
- RTC->CR = (uint32_t)tmpreg;
-
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
-}
-
-/**
- * @brief Get the RTC TimeStamp value and masks.
- * @param RTC_Format: specifies the format of the output parameters.
- * This parameter can be one of the following values:
- * @arg RTC_Format_BIN: Binary data format
- * @arg RTC_Format_BCD: BCD data format
- * @param RTC_StampTimeStruct: pointer to a RTC_TimeTypeDef structure that will
- * contains the TimeStamp time values.
- * @param RTC_StampDateStruct: pointer to a RTC_DateTypeDef structure that will
- * contains the TimeStamp date values.
- * @retval None
- */
-void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_StampTimeStruct,
- RTC_DateTypeDef* RTC_StampDateStruct)
-{
- uint32_t tmptime = 0, tmpdate = 0;
-
- /* Check the parameters */
- assert_param(IS_RTC_FORMAT(RTC_Format));
-
- /* Get the TimeStamp time and date registers values */
- tmptime = (uint32_t)(RTC->TSTR & RTC_TR_RESERVED_MASK);
- tmpdate = (uint32_t)(RTC->TSDR & RTC_DR_RESERVED_MASK);
-
- /* Fill the Time structure fields with the read parameters */
- RTC_StampTimeStruct->RTC_Hours = (uint8_t)((tmptime & (RTC_TR_HT | RTC_TR_HU)) >> 16);
- RTC_StampTimeStruct->RTC_Minutes = (uint8_t)((tmptime & (RTC_TR_MNT | RTC_TR_MNU)) >> 8);
- RTC_StampTimeStruct->RTC_Seconds = (uint8_t)(tmptime & (RTC_TR_ST | RTC_TR_SU));
- RTC_StampTimeStruct->RTC_H12 = (uint8_t)((tmptime & (RTC_TR_PM)) >> 16);
-
- /* Fill the Date structure fields with the read parameters */
- RTC_StampDateStruct->RTC_Year = 0;
- RTC_StampDateStruct->RTC_Month = (uint8_t)((tmpdate & (RTC_DR_MT | RTC_DR_MU)) >> 8);
- RTC_StampDateStruct->RTC_Date = (uint8_t)(tmpdate & (RTC_DR_DT | RTC_DR_DU));
- RTC_StampDateStruct->RTC_WeekDay = (uint8_t)((tmpdate & (RTC_DR_WDU)) >> 13);
-
- /* Check the input parameters format */
- if (RTC_Format == RTC_Format_BIN)
- {
- /* Convert the Time structure parameters to Binary format */
- RTC_StampTimeStruct->RTC_Hours = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Hours);
- RTC_StampTimeStruct->RTC_Minutes = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Minutes);
- RTC_StampTimeStruct->RTC_Seconds = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Seconds);
-
- /* Convert the Date structure parameters to Binary format */
- RTC_StampDateStruct->RTC_Month = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_Month);
- RTC_StampDateStruct->RTC_Date = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_Date);
- RTC_StampDateStruct->RTC_WeekDay = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_WeekDay);
- }
-}
-
-/**
- * @brief Get the RTC timestamp Subseconds value.
- * @param None
- * @retval RTC current timestamp Subseconds value.
- */
-uint32_t RTC_GetTimeStampSubSecond(void)
-{
- /* Get timestamp subseconds values from the correspondent registers */
- return (uint32_t)(RTC->TSSSR);
-}
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Group9 Tampers configuration functions
- * @brief Tampers configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Tampers configuration functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures the select Tamper pin edge.
- * @param RTC_Tamper: Selected tamper pin.
- * This parameter can be any combination of the following values:
- * @arg RTC_Tamper_1: Select Tamper 1.
- * @arg RTC_Tamper_2: Select Tamper 2.
- * @param RTC_TamperTrigger: Specifies the trigger on the tamper pin that
- * stimulates tamper event.
- * This parameter can be one of the following values:
- * @arg RTC_TamperTrigger_RisingEdge: Rising Edge of the tamper pin causes tamper event.
- * @arg RTC_TamperTrigger_FallingEdge: Falling Edge of the tamper pin causes tamper event.
- * @arg RTC_TamperTrigger_LowLevel: Low Level of the tamper pin causes tamper event.
- * @arg RTC_TamperTrigger_HighLevel: High Level of the tamper pin causes tamper event.
- * @retval None
- */
-void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger)
-{
- /* Check the parameters */
- assert_param(IS_RTC_TAMPER(RTC_Tamper));
- assert_param(IS_RTC_TAMPER_TRIGGER(RTC_TamperTrigger));
-
- if (RTC_TamperTrigger == RTC_TamperTrigger_RisingEdge)
- {
- /* Configure the RTC_TAFCR register */
- RTC->TAFCR &= (uint32_t)((uint32_t)~(RTC_Tamper << 1));
- }
- else
- {
- /* Configure the RTC_TAFCR register */
- RTC->TAFCR |= (uint32_t)(RTC_Tamper << 1);
- }
-}
-
-/**
- * @brief Enables or Disables the Tamper detection.
- * @param RTC_Tamper: Selected tamper pin.
- * This parameter can be any combination of the following values:
- * @arg RTC_Tamper_1: Select Tamper 1.
- * @arg RTC_Tamper_2: Select Tamper 2.
- * @param NewState: new state of the tamper pin.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RTC_TAMPER(RTC_Tamper));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected Tamper pin */
- RTC->TAFCR |= (uint32_t)RTC_Tamper;
- }
- else
- {
- /* Disable the selected Tamper pin */
- RTC->TAFCR &= (uint32_t)~RTC_Tamper;
- }
-}
-
-/**
- * @brief Configures the Tampers Filter.
- * @param RTC_TamperFilter: Specifies the tampers filter.
- * This parameter can be one of the following values:
- * @arg RTC_TamperFilter_Disable: Tamper filter is disabled.
- * @arg RTC_TamperFilter_2Sample: Tamper is activated after 2 consecutive
- * samples at the active level
- * @arg RTC_TamperFilter_4Sample: Tamper is activated after 4 consecutive
- * samples at the active level
- * @arg RTC_TamperFilter_8Sample: Tamper is activated after 8 consecutive
- * samples at the active level
- * @retval None
- */
-void RTC_TamperFilterConfig(uint32_t RTC_TamperFilter)
-{
- /* Check the parameters */
- assert_param(IS_RTC_TAMPER_FILTER(RTC_TamperFilter));
-
- /* Clear TAMPFLT[1:0] bits in the RTC_TAFCR register */
- RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPFLT);
-
- /* Configure the RTC_TAFCR register */
- RTC->TAFCR |= (uint32_t)RTC_TamperFilter;
-}
-
-/**
- * @brief Configures the Tampers Sampling Frequency.
- * @param RTC_TamperSamplingFreq: Specifies the tampers Sampling Frequency.
- * This parameter can be one of the following values:
- * @arg RTC_TamperSamplingFreq_RTCCLK_Div32768: Each of the tamper inputs are sampled
- * with a frequency = RTCCLK / 32768
- * @arg RTC_TamperSamplingFreq_RTCCLK_Div16384: Each of the tamper inputs are sampled
- * with a frequency = RTCCLK / 16384
- * @arg RTC_TamperSamplingFreq_RTCCLK_Div8192: Each of the tamper inputs are sampled
- * with a frequency = RTCCLK / 8192
- * @arg RTC_TamperSamplingFreq_RTCCLK_Div4096: Each of the tamper inputs are sampled
- * with a frequency = RTCCLK / 4096
- * @arg RTC_TamperSamplingFreq_RTCCLK_Div2048: Each of the tamper inputs are sampled
- * with a frequency = RTCCLK / 2048
- * @arg RTC_TamperSamplingFreq_RTCCLK_Div1024: Each of the tamper inputs are sampled
- * with a frequency = RTCCLK / 1024
- * @arg RTC_TamperSamplingFreq_RTCCLK_Div512: Each of the tamper inputs are sampled
- * with a frequency = RTCCLK / 512
- * @arg RTC_TamperSamplingFreq_RTCCLK_Div256: Each of the tamper inputs are sampled
- * with a frequency = RTCCLK / 256
- * @retval None
- */
-void RTC_TamperSamplingFreqConfig(uint32_t RTC_TamperSamplingFreq)
-{
- /* Check the parameters */
- assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(RTC_TamperSamplingFreq));
-
- /* Clear TAMPFREQ[2:0] bits in the RTC_TAFCR register */
- RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPFREQ);
-
- /* Configure the RTC_TAFCR register */
- RTC->TAFCR |= (uint32_t)RTC_TamperSamplingFreq;
-}
-
-/**
- * @brief Configures the Tampers Pins input Precharge Duration.
- * @param RTC_TamperPrechargeDuration: Specifies the Tampers Pins input
- * Precharge Duration.
- * This parameter can be one of the following values:
- * @arg RTC_TamperPrechargeDuration_1RTCCLK: Tamper pins are pre-charged before sampling during 1 RTCCLK cycle
- * @arg RTC_TamperPrechargeDuration_2RTCCLK: Tamper pins are pre-charged before sampling during 2 RTCCLK cycle
- * @arg RTC_TamperPrechargeDuration_4RTCCLK: Tamper pins are pre-charged before sampling during 4 RTCCLK cycle
- * @arg RTC_TamperPrechargeDuration_8RTCCLK: Tamper pins are pre-charged before sampling during 8 RTCCLK cycle
- * @retval None
- */
-void RTC_TamperPinsPrechargeDuration(uint32_t RTC_TamperPrechargeDuration)
-{
- /* Check the parameters */
- assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(RTC_TamperPrechargeDuration));
-
- /* Clear TAMPPRCH[1:0] bits in the RTC_TAFCR register */
- RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPPRCH);
-
- /* Configure the RTC_TAFCR register */
- RTC->TAFCR |= (uint32_t)RTC_TamperPrechargeDuration;
-}
-
-/**
- * @brief Enables or Disables the TimeStamp on Tamper Detection Event.
- * @note The timestamp is valid even the TSE bit in tamper control register
- * is reset.
- * @param NewState: new state of the timestamp on tamper event.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RTC_TimeStampOnTamperDetectionCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Save timestamp on tamper detection event */
- RTC->TAFCR |= (uint32_t)RTC_TAFCR_TAMPTS;
- }
- else
- {
- /* Tamper detection does not cause a timestamp to be saved */
- RTC->TAFCR &= (uint32_t)~RTC_TAFCR_TAMPTS;
- }
-}
-
-/**
- * @brief Enables or Disables the Precharge of Tamper pin.
- * @param NewState: new state of tamper pull up.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RTC_TamperPullUpCmd(FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable precharge of the selected Tamper pin */
- RTC->TAFCR &= (uint32_t)~RTC_TAFCR_TAMPPUDIS;
- }
- else
- {
- /* Disable precharge of the selected Tamper pin */
- RTC->TAFCR |= (uint32_t)RTC_TAFCR_TAMPPUDIS;
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Group10 Backup Data Registers configuration functions
- * @brief Backup Data Registers configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Backup Data Registers configuration functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Writes a data in a specified RTC Backup data register.
- * @param RTC_BKP_DR: RTC Backup data Register number.
- * This parameter can be: RTC_BKP_DRx where x can be from 0 to 4 to
- * specify the register.
- * @param Data: Data to be written in the specified RTC Backup data register.
- * @retval None
- */
-void RTC_WriteBackupRegister(uint32_t RTC_BKP_DR, uint32_t Data)
-{
- __IO uint32_t tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_RTC_BKP(RTC_BKP_DR));
-
- tmp = RTC_BASE + 0x50;
- tmp += (RTC_BKP_DR * 4);
-
- /* Write the specified register */
- *(__IO uint32_t *)tmp = (uint32_t)Data;
-}
-
-/**
- * @brief Reads data from the specified RTC Backup data Register.
- * @param RTC_BKP_DR: RTC Backup data Register number.
- * This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to
- * specify the register.
- * @retval None
- */
-uint32_t RTC_ReadBackupRegister(uint32_t RTC_BKP_DR)
-{
- __IO uint32_t tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_RTC_BKP(RTC_BKP_DR));
-
- tmp = RTC_BASE + 0x50;
- tmp += (RTC_BKP_DR * 4);
-
- /* Read the specified register */
- return (*(__IO uint32_t *)tmp);
-}
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Group11 Output Type Config configuration functions
- * @brief Output Type Config configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Output Type Config configuration functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures the RTC Output Pin mode.
- * @param RTC_OutputType: specifies the RTC Output (PC13) pin mode.
- * This parameter can be one of the following values:
- * @arg RTC_OutputType_OpenDrain: RTC Output (PC13) is configured in
- * Open Drain mode.
- * @arg RTC_OutputType_PushPull: RTC Output (PC13) is configured in
- * Push Pull mode.
- * @retval None
- */
-void RTC_OutputTypeConfig(uint32_t RTC_OutputType)
-{
- /* Check the parameters */
- assert_param(IS_RTC_OUTPUT_TYPE(RTC_OutputType));
-
- RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_ALARMOUTTYPE);
- RTC->TAFCR |= (uint32_t)(RTC_OutputType);
-}
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Group12 Shift control synchronisation functions
- * @brief Shift control synchronisation functions
- *
-@verbatim
- ===============================================================================
- ##### Shift control synchronisation functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures the Synchronization Shift Control Settings.
- * @note When REFCKON is set, firmware must not write to Shift control register
- * @param RTC_ShiftAdd1S: Select to add or not 1 second to the time Calendar.
- * This parameter can be one of the following values :
- * @arg RTC_ShiftAdd1S_Set: Add one second to the clock calendar.
- * @arg RTC_ShiftAdd1S_Reset: No effect.
- * @param RTC_ShiftSubFS: Select the number of Second Fractions to Substitute.
- * This parameter can be one any value from 0 to 0x7FFF.
- * @retval An ErrorStatus enumeration value:
- * - SUCCESS: RTC Shift registers are configured
- * - ERROR: RTC Shift registers are not configured
-*/
-ErrorStatus RTC_SynchroShiftConfig(uint32_t RTC_ShiftAdd1S, uint32_t RTC_ShiftSubFS)
-{
- ErrorStatus status = ERROR;
- uint32_t shpfcount = 0;
-
- /* Check the parameters */
- assert_param(IS_RTC_SHIFT_ADD1S(RTC_ShiftAdd1S));
- assert_param(IS_RTC_SHIFT_SUBFS(RTC_ShiftSubFS));
-
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- /* Check if a Shift is pending*/
- if ((RTC->ISR & RTC_ISR_SHPF) != RESET)
- {
- /* Wait until the shift is completed*/
- while (((RTC->ISR & RTC_ISR_SHPF) != RESET) && (shpfcount != SHPF_TIMEOUT))
- {
- shpfcount++;
- }
- }
-
- /* Check if the Shift pending is completed or if there is no Shift operation at all*/
- if ((RTC->ISR & RTC_ISR_SHPF) == RESET)
- {
- /* check if the reference clock detection is disabled */
- if((RTC->CR & RTC_CR_REFCKON) == RESET)
- {
- /* Configure the Shift settings */
- RTC->SHIFTR = (uint32_t)(uint32_t)(RTC_ShiftSubFS) | (uint32_t)(RTC_ShiftAdd1S);
-
- if(RTC_WaitForSynchro() == ERROR)
- {
- status = ERROR;
- }
- else
- {
- status = SUCCESS;
- }
- }
- else
- {
- status = ERROR;
- }
- }
- else
- {
- status = ERROR;
- }
-
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
-
- return (ErrorStatus)(status);
-}
-
-/**
- * @}
- */
-
-/** @defgroup RTC_Group13 Interrupts and flags management functions
- * @brief Interrupts and flags management functions
- *
-@verbatim
- ===============================================================================
- ##### Interrupts and flags management functions #####
- ===============================================================================
- [..] All RTC interrupts are connected to the EXTI controller.
-
- (+) To enable the RTC Alarm interrupt, the following sequence is required:
- (++) Configure and enable the EXTI Line 17 in interrupt mode and select the rising
- edge sensitivity using the EXTI_Init() function.
- (++) Configure and enable the RTC_Alarm IRQ channel in the NVIC using the NVIC_Init()
- function.
- (++) Configure the RTC to generate RTC alarms (Alarm A) using
- the RTC_SetAlarm() and RTC_AlarmCmd() functions.
-
- (+) To enable the RTC Tamper interrupt, the following sequence is required:
- (++) Configure and enable the EXTI Line 19 in interrupt mode and select the rising
- edge sensitivity using the EXTI_Init() function.
- (++) Configure and enable the TAMP_STAMP IRQ channel in the NVIC using the NVIC_Init()
- function.
- (++) Configure the RTC to detect the RTC tamper event using the
- RTC_TamperTriggerConfig() and RTC_TamperCmd() functions.
-
- (+) To enable the RTC TimeStamp interrupt, the following sequence is required:
- (++) Configure and enable the EXTI Line 19 in interrupt mode and select the rising
- edge sensitivity using the EXTI_Init() function.
- (++) Configure and enable the TAMP_STAMP IRQ channel in the NVIC using the NVIC_Init()
- function.
- (++) Configure the RTC to detect the RTC time-stamp event using the
- RTC_TimeStampCmd() functions.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the specified RTC interrupts.
- * @param RTC_IT: specifies the RTC interrupt sources to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg RTC_IT_TS: Time Stamp interrupt mask
- * @arg RTC_IT_WUT: WakeUp Timer interrupt mask, available only for STM32F072 devices
- * @arg RTC_IT_ALRA: Alarm A interrupt mask
- * @arg RTC_IT_TAMP: Tamper event interrupt mask
- * @param NewState: new state of the specified RTC interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_RTC_CONFIG_IT(RTC_IT));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- /* Disable the write protection for RTC registers */
- RTC->WPR = 0xCA;
- RTC->WPR = 0x53;
-
- if (NewState != DISABLE)
- {
- /* Configure the Interrupts in the RTC_CR register */
- RTC->CR |= (uint32_t)(RTC_IT & ~RTC_TAFCR_TAMPIE);
- /* Configure the Tamper Interrupt in the RTC_TAFCR */
- RTC->TAFCR |= (uint32_t)(RTC_IT & RTC_TAFCR_TAMPIE);
- }
- else
- {
- /* Configure the Interrupts in the RTC_CR register */
- RTC->CR &= (uint32_t)~(RTC_IT & (uint32_t)~RTC_TAFCR_TAMPIE);
- /* Configure the Tamper Interrupt in the RTC_TAFCR */
- RTC->TAFCR &= (uint32_t)~(RTC_IT & RTC_TAFCR_TAMPIE);
- }
- /* Enable the write protection for RTC registers */
- RTC->WPR = 0xFF;
-}
-
-/**
- * @brief Checks whether the specified RTC flag is set or not.
- * @param RTC_FLAG: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg RTC_FLAG_RECALPF: RECALPF event flag
- * @arg RTC_FLAG_TAMP2F: Tamper 2 event flag
- * @arg RTC_FLAG_TAMP1F: Tamper 1 event flag
- * @arg RTC_FLAG_TSOVF: Time Stamp OverFlow flag
- * @arg RTC_FLAG_TSF: Time Stamp event flag
- * @arg RTC_FLAG_WUTF: WakeUp Timer flag, available only for STM32F072 devices
- * @arg RTC_FLAG_ALRAF: Alarm A flag
- * @arg RTC_FLAG_INITF: Initialization mode flag
- * @arg RTC_FLAG_RSF: Registers Synchronized flag
- * @arg RTC_FLAG_INITS: Registers Configured flag
- * @retval The new state of RTC_FLAG (SET or RESET).
- */
-FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG)
-{
- FlagStatus bitstatus = RESET;
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RTC_GET_FLAG(RTC_FLAG));
-
- /* Get all the flags */
- tmpreg = (uint32_t)(RTC->ISR & RTC_FLAGS_MASK);
-
- /* Return the status of the flag */
- if ((tmpreg & RTC_FLAG) != (uint32_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Clears the RTC's pending flags.
- * @param RTC_FLAG: specifies the RTC flag to clear.
- * This parameter can be any combination of the following values:
- * @arg RTC_FLAG_TAMP2F: Tamper 2 event flag
- * @arg RTC_FLAG_TAMP1F: Tamper 1 event flag
- * @arg RTC_FLAG_TSOVF: Time Stamp Overflow flag
- * @arg RTC_FLAG_TSF: Time Stamp event flag
- * @arg RTC_FLAG_WUTF: WakeUp Timer flag, available only for STM32F072 devices
- * @arg RTC_FLAG_ALRAF: Alarm A flag
- * @arg RTC_FLAG_RSF: Registers Synchronized flag
- * @retval None
- */
-void RTC_ClearFlag(uint32_t RTC_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_RTC_CLEAR_FLAG(RTC_FLAG));
-
- /* Clear the Flags in the RTC_ISR register */
- RTC->ISR = (uint32_t)((uint32_t)(~((RTC_FLAG | RTC_ISR_INIT)& 0x0001FFFF) | (uint32_t)(RTC->ISR & RTC_ISR_INIT)));
-}
-
-/**
- * @brief Checks whether the specified RTC interrupt has occurred or not.
- * @param RTC_IT: specifies the RTC interrupt source to check.
- * This parameter can be one of the following values:
- * @arg RTC_IT_TS: Time Stamp interrupt
- * @arg RTC_IT_WUT: WakeUp Timer interrupt, available only for STM32F072 devices
- * @arg RTC_IT_ALRA: Alarm A interrupt
- * @arg RTC_IT_TAMP1: Tamper1 event interrupt
- * @arg RTC_IT_TAMP2: Tamper2 event interrupt
- * @retval The new state of RTC_IT (SET or RESET).
- */
-ITStatus RTC_GetITStatus(uint32_t RTC_IT)
-{
- ITStatus bitstatus = RESET;
- uint32_t tmpreg = 0, enablestatus = 0;
-
- /* Check the parameters */
- assert_param(IS_RTC_GET_IT(RTC_IT));
-
- /* Get the TAMPER Interrupt enable bit and pending bit */
- tmpreg = (uint32_t)(RTC->TAFCR & (RTC_TAFCR_TAMPIE));
-
- /* Get the Interrupt enable Status */
- enablestatus = (uint32_t)((RTC->CR & RTC_IT) | (tmpreg & ((RTC_IT >> (RTC_IT >> 18)) >> 15)));
-
- /* Get the Interrupt pending bit */
- tmpreg = (uint32_t)((RTC->ISR & (uint32_t)(RTC_IT >> 4)));
-
- /* Get the status of the Interrupt */
- if ((enablestatus != (uint32_t)RESET) && ((tmpreg & 0x0000FFFF) != (uint32_t)RESET))
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Clears the RTC's interrupt pending bits.
- * @param RTC_IT: specifies the RTC interrupt pending bit to clear.
- * This parameter can be any combination of the following values:
- * @arg RTC_IT_TS: Time Stamp interrupt
- * @arg RTC_IT_WUT: WakeUp Timer interrupt, available only for STM32F072 devices
- * @arg RTC_IT_ALRA: Alarm A interrupt
- * @arg RTC_IT_TAMP1: Tamper1 event interrupt
- * @arg RTC_IT_TAMP2: Tamper2 event interrupt
- * @retval None
- */
-void RTC_ClearITPendingBit(uint32_t RTC_IT)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_RTC_CLEAR_IT(RTC_IT));
-
- /* Get the RTC_ISR Interrupt pending bits mask */
- tmpreg = (uint32_t)(RTC_IT >> 4);
-
- /* Clear the interrupt pending bits in the RTC_ISR register */
- RTC->ISR = (uint32_t)((uint32_t)(~((tmpreg | RTC_ISR_INIT)& 0x0000FFFF) | (uint32_t)(RTC->ISR & RTC_ISR_INIT)));
-}
-
-/**
- * @}
- */
-
-/**
- * @brief Converts a 2 digit decimal to BCD format.
- * @param Value: Byte to be converted.
- * @retval Converted byte
- */
-static uint8_t RTC_ByteToBcd2(uint8_t Value)
-{
- uint8_t bcdhigh = 0;
-
- while (Value >= 10)
- {
- bcdhigh++;
- Value -= 10;
- }
-
- return ((uint8_t)(bcdhigh << 4) | Value);
-}
-
-/**
- * @brief Convert from 2 digit BCD to Binary.
- * @param Value: BCD value to be converted.
- * @retval Converted word
- */
-static uint8_t RTC_Bcd2ToByte(uint8_t Value)
-{
- uint8_t tmp = 0;
- tmp = ((uint8_t)(Value & (uint8_t)0xF0) >> (uint8_t)0x4) * 10;
- return (tmp + (Value & (uint8_t)0x0F));
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_spi.c b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_spi.c
deleted file mode 100644
index e0c148b4f72bbd0164c5ad6f600d4f8eb87c0572..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_spi.c
+++ /dev/null
@@ -1,1334 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f0xx_spi.c
- * @author MCD Application Team
- * @version V1.3.0
- * @date 16-January-2014
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Serial peripheral interface (SPI):
- * + Initialization and Configuration
- * + Data transfers functions
- * + Hardware CRC Calculation
- * + DMA transfers management
- * + Interrupts and flags management
- *
- * @verbatim
-
- ===============================================================================
- ##### How to use this driver #####
- ===============================================================================
- [..]
- (#) Enable peripheral clock using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE)
- function for SPI1 or using RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE)
- function for SPI2.
-
- (#) Enable SCK, MOSI, MISO and NSS GPIO clocks using
- RCC_AHBPeriphClockCmd() function.
-
- (#) Peripherals alternate function:
- (++) Connect the pin to the desired peripherals' Alternate
- Function (AF) using GPIO_PinAFConfig() function.
- (++) Configure the desired pin in alternate function by:
- GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF.
- (++) Select the type, pull-up/pull-down and output speed via
- GPIO_PuPd, GPIO_OType and GPIO_Speed members.
- (++) Call GPIO_Init() function.
-
- (#) Program the Polarity, Phase, First Data, Baud Rate Prescaler, Slave
- Management, Peripheral Mode and CRC Polynomial values using the SPI_Init()
- function.In I2S mode, program the Mode, Standard, Data Format, MCLK
- Output, Audio frequency and Polarity using I2S_Init() function.
-
- (#) Configure the FIFO threshold using SPI_RxFIFOThresholdConfig() to select
- at which threshold the RXNE event is generated.
-
- (#) Enable the NVIC and the corresponding interrupt using the function
- SPI_ITConfig() if you need to use interrupt mode.
-
- (#) When using the DMA mode
- (++) Configure the DMA using DMA_Init() function.
- (++) Active the needed channel Request using SPI_I2S_DMACmd() function.
-
- (#) Enable the SPI using the SPI_Cmd() function or enable the I2S using
- I2S_Cmd().
-
- (#) Enable the DMA using the DMA_Cmd() function when using DMA mode.
-
- (#) Optionally, you can enable/configure the following parameters without
- re-initialization (i.e there is no need to call again SPI_Init() function):
- (++) When bidirectional mode (SPI_Direction_1Line_Rx or SPI_Direction_1Line_Tx)
- is programmed as Data direction parameter using the SPI_Init()
- function it can be possible to switch between SPI_Direction_Tx
- or SPI_Direction_Rx using the SPI_BiDirectionalLineConfig() function.
- (++) When SPI_NSS_Soft is selected as Slave Select Management parameter
- using the SPI_Init() function it can be possible to manage the
- NSS internal signal using the SPI_NSSInternalSoftwareConfig() function.
- (++) Reconfigure the data size using the SPI_DataSizeConfig() function.
- (++) Enable or disable the SS output using the SPI_SSOutputCmd() function.
-
- (#) To use the CRC Hardware calculation feature refer to the Peripheral
- CRC hardware Calculation subsection.
-
- @endverbatim
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx_spi.h"
-#include "stm32f0xx_rcc.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup SPI
- * @brief SPI driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* SPI registers Masks */
-#define CR1_CLEAR_MASK ((uint16_t)0x3040)
-#define CR1_CLEAR_MASK2 ((uint16_t)0xFFFB)
-#define CR2_LDMA_MASK ((uint16_t)0x9FFF)
-
-#define I2SCFGR_CLEAR_Mask ((uint16_t)0xF040)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup SPI_Private_Functions
- * @{
- */
-
-/** @defgroup SPI_Group1 Initialization and Configuration functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and Configuration functions #####
- ===============================================================================
- [..] This section provides a set of functions allowing to initialize the SPI Direction,
- SPI Mode, SPI Data Size, SPI Polarity, SPI Phase, SPI NSS Management, SPI Baud
- Rate Prescaler, SPI First Bit and SPI CRC Polynomial.
-
- [..] The SPI_Init() function follows the SPI configuration procedures for Master mode
- and Slave mode (details for these procedures are available in reference manual).
-
- [..] When the Software NSS management (SPI_InitStruct->SPI_NSS = SPI_NSS_Soft) is selected,
- use the following function to manage the NSS bit:
- void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft);
-
- [..] In Master mode, when the Hardware NSS management (SPI_InitStruct->SPI_NSS = SPI_NSS_Hard)
- is selected, use the follwoing function to enable the NSS output feature.
- void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
-
- [..] The NSS pulse mode can be managed by the SPI TI mode when enabling it using the following function:
- void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
- And it can be managed by software in the SPI Motorola mode using this function:
- void SPI_NSSPulseModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
-
- [..] This section provides also functions to initialize the I2S Mode, Standard,
- Data Format, MCLK Output, Audio frequency and Polarity.
-
- [..] The I2S_Init() function follows the I2S configuration procedures for Master mode
- and Slave mode.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitializes the SPIx peripheral registers to their default
- * reset values.
- * @param SPIx: where x can be 1 or 2 to select the SPI peripheral.
- * @note SPI2 is not available for STM32F031 devices.
- * I2S mode is not supported for STM32F030 devices.
- * @retval None
- */
-void SPI_I2S_DeInit(SPI_TypeDef* SPIx)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
-
- if (SPIx == SPI1)
- {
- /* Enable SPI1 reset state */
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE);
- /* Release SPI1 from reset state */
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE);
- }
- else
- {
- if (SPIx == SPI2)
- {
- /* Enable SPI2 reset state */
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE);
- /* Release SPI2 from reset state */
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE);
- }
- }
-}
-
-/**
- * @brief Fills each SPI_InitStruct member with its default value.
- * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure which will be initialized.
- * @retval None
- */
-void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct)
-{
-/*--------------- Reset SPI init structure parameters values -----------------*/
- /* Initialize the SPI_Direction member */
- SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex;
- /* Initialize the SPI_Mode member */
- SPI_InitStruct->SPI_Mode = SPI_Mode_Slave;
- /* Initialize the SPI_DataSize member */
- SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b;
- /* Initialize the SPI_CPOL member */
- SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low;
- /* Initialize the SPI_CPHA member */
- SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge;
- /* Initialize the SPI_NSS member */
- SPI_InitStruct->SPI_NSS = SPI_NSS_Hard;
- /* Initialize the SPI_BaudRatePrescaler member */
- SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
- /* Initialize the SPI_FirstBit member */
- SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB;
- /* Initialize the SPI_CRCPolynomial member */
- SPI_InitStruct->SPI_CRCPolynomial = 7;
-}
-
-/**
- * @brief Initializes the SPIx peripheral according to the specified
- * parameters in the SPI_InitStruct.
- * @param SPIx: where x can be 1 or 2 to select the SPI peripheral.
- * @note SPI2 is not available for STM32F031 devices.
- * @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure that
- * contains the configuration information for the specified SPI peripheral.
- * @retval None
- */
-void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct)
-{
- uint16_t tmpreg = 0;
-
- /* check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
-
- /* Check the SPI parameters */
- assert_param(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction));
- assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode));
- assert_param(IS_SPI_DATA_SIZE(SPI_InitStruct->SPI_DataSize));
- assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL));
- assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA));
- assert_param(IS_SPI_NSS(SPI_InitStruct->SPI_NSS));
- assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler));
- assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit));
- assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->SPI_CRCPolynomial));
-
- /*---------------------------- SPIx CR1 Configuration ------------------------*/
- /* Get the SPIx CR1 value */
- tmpreg = SPIx->CR1;
- /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, CPOL and CPHA bits */
- tmpreg &= CR1_CLEAR_MASK;
- /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler
- master/slave mode, CPOL and CPHA */
- /* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */
- /* Set SSM, SSI bit according to SPI_NSS values */
- /* Set LSBFirst bit according to SPI_FirstBit value */
- /* Set BR bits according to SPI_BaudRatePrescaler value */
- /* Set CPOL bit according to SPI_CPOL value */
- /* Set CPHA bit according to SPI_CPHA value */
- tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_FirstBit |
- SPI_InitStruct->SPI_CPOL | SPI_InitStruct->SPI_CPHA |
- SPI_InitStruct->SPI_NSS | SPI_InitStruct->SPI_BaudRatePrescaler);
- /* Write to SPIx CR1 */
- SPIx->CR1 = tmpreg;
- /*-------------------------Data Size Configuration -----------------------*/
- /* Get the SPIx CR2 value */
- tmpreg = SPIx->CR2;
- /* Clear DS[3:0] bits */
- tmpreg &=(uint16_t)~SPI_CR2_DS;
- /* Configure SPIx: Data Size */
- tmpreg |= (uint16_t)(SPI_InitStruct->SPI_DataSize);
- /* Write to SPIx CR2 */
- SPIx->CR2 = tmpreg;
-
- /*---------------------------- SPIx CRCPOLY Configuration --------------------*/
- /* Write to SPIx CRCPOLY */
- SPIx->CRCPR = SPI_InitStruct->SPI_CRCPolynomial;
-
- /*---------------------------- SPIx CR1 Configuration ------------------------*/
- /* Get the SPIx CR1 value */
- tmpreg = SPIx->CR1;
- /* Clear MSTR bit */
- tmpreg &= CR1_CLEAR_MASK2;
- /* Configure SPIx: master/slave mode */
- /* Set MSTR bit according to SPI_Mode */
- tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Mode);
- /* Write to SPIx CR1 */
- SPIx->CR1 = tmpreg;
-
- /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
- SPIx->I2SCFGR &= (uint16_t)~((uint16_t)SPI_I2SCFGR_I2SMOD);
-}
-
-/**
- * @brief Fills each I2S_InitStruct member with its default value.
- * @note This mode is not supported for STM32F030 devices.
- * @param I2S_InitStruct: pointer to a I2S_InitTypeDef structure which will be initialized.
- * @retval None
- */
-void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct)
-{
-/*--------------- Reset I2S init structure parameters values -----------------*/
- /* Initialize the I2S_Mode member */
- I2S_InitStruct->I2S_Mode = I2S_Mode_SlaveTx;
-
- /* Initialize the I2S_Standard member */
- I2S_InitStruct->I2S_Standard = I2S_Standard_Phillips;
-
- /* Initialize the I2S_DataFormat member */
- I2S_InitStruct->I2S_DataFormat = I2S_DataFormat_16b;
-
- /* Initialize the I2S_MCLKOutput member */
- I2S_InitStruct->I2S_MCLKOutput = I2S_MCLKOutput_Disable;
-
- /* Initialize the I2S_AudioFreq member */
- I2S_InitStruct->I2S_AudioFreq = I2S_AudioFreq_Default;
-
- /* Initialize the I2S_CPOL member */
- I2S_InitStruct->I2S_CPOL = I2S_CPOL_Low;
-}
-
-/**
- * @brief Initializes the SPIx peripheral according to the specified
- * parameters in the I2S_InitStruct.
- * @note This mode is not supported for STM32F030 devices.
- * @param SPIx: where x can be 1 to select the SPI peripheral (configured in I2S mode).
- * @param I2S_InitStruct: pointer to an I2S_InitTypeDef structure that
- * contains the configuration information for the specified SPI peripheral
- * configured in I2S mode.
- * @note This function calculates the optimal prescaler needed to obtain the most
- * accurate audio frequency (depending on the I2S clock source, the PLL values
- * and the product configuration). But in case the prescaler value is greater
- * than 511, the default value (0x02) will be configured instead.
- * @retval None
- */
-void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct)
-{
- uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1;
- uint32_t tmp = 0;
- RCC_ClocksTypeDef RCC_Clocks;
- uint32_t sourceclock = 0;
-
- /* Check the I2S parameters */
- assert_param(IS_SPI_1_PERIPH(SPIx));
- assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode));
- assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard));
- assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat));
- assert_param(IS_I2S_MCLK_OUTPUT(I2S_InitStruct->I2S_MCLKOutput));
- assert_param(IS_I2S_AUDIO_FREQ(I2S_InitStruct->I2S_AudioFreq));
- assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL));
-
-/*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/
- /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
- SPIx->I2SCFGR &= I2SCFGR_CLEAR_Mask;
- SPIx->I2SPR = 0x0002;
-
- /* Get the I2SCFGR register value */
- tmpreg = SPIx->I2SCFGR;
-
- /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/
- if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default)
- {
- i2sodd = (uint16_t)0;
- i2sdiv = (uint16_t)2;
- }
- /* If the requested audio frequency is not the default, compute the prescaler */
- else
- {
- /* Check the frame length (For the Prescaler computing) */
- if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b)
- {
- /* Packet length is 16 bits */
- packetlength = 1;
- }
- else
- {
- /* Packet length is 32 bits */
- packetlength = 2;
- }
-
- /* I2S Clock source is System clock: Get System Clock frequency */
- RCC_GetClocksFreq(&RCC_Clocks);
-
- /* Get the source clock value: based on System Clock value */
- sourceclock = RCC_Clocks.SYSCLK_Frequency;
-
- /* Compute the Real divider depending on the MCLK output state with a floating point */
- if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable)
- {
- /* MCLK output is enabled */
- tmp = (uint16_t)(((((sourceclock / 256) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5);
- }
- else
- {
- /* MCLK output is disabled */
- tmp = (uint16_t)(((((sourceclock / (32 * packetlength)) *10 ) / I2S_InitStruct->I2S_AudioFreq)) + 5);
- }
-
- /* Remove the floating point */
- tmp = tmp / 10;
-
- /* Check the parity of the divider */
- i2sodd = (uint16_t)(tmp & (uint16_t)0x0001);
-
- /* Compute the i2sdiv prescaler */
- i2sdiv = (uint16_t)((tmp - i2sodd) / 2);
-
- /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
- i2sodd = (uint16_t) (i2sodd << 8);
- }
-
- /* Test if the divider is 1 or 0 or greater than 0xFF */
- if ((i2sdiv < 2) || (i2sdiv > 0xFF))
- {
- /* Set the default values */
- i2sdiv = 2;
- i2sodd = 0;
- }
-
- /* Write to SPIx I2SPR register the computed value */
- SPIx->I2SPR = (uint16_t)(i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->I2S_MCLKOutput));
-
- /* Configure the I2S with the SPI_InitStruct values */
- tmpreg |= (uint16_t)(SPI_I2SCFGR_I2SMOD | (uint16_t)(I2S_InitStruct->I2S_Mode | \
- (uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | \
- (uint16_t)I2S_InitStruct->I2S_CPOL))));
-
- /* Write to SPIx I2SCFGR */
- SPIx->I2SCFGR = tmpreg;
-}
-
-/**
- * @brief Enables or disables the specified SPI peripheral.
- * @param SPIx: where x can be 1 or 2 to select the SPI peripheral.
- * @note SPI2 is not available for STM32F031 devices.
- * @param NewState: new state of the SPIx peripheral.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected SPI peripheral */
- SPIx->CR1 |= SPI_CR1_SPE;
- }
- else
- {
- /* Disable the selected SPI peripheral */
- SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_SPE);
- }
-}
-
-/**
- * @brief Enables or disables the TI Mode.
- *
- * @note This function can be called only after the SPI_Init() function has
- * been called.
- * @note When TI mode is selected, the control bits SSM, SSI, CPOL and CPHA
- * are not taken into consideration and are configured by hardware
- * respectively to the TI mode requirements.
- *
- * @param SPIx: where x can be 1 or 2 to select the SPI peripheral.
- * @note SPI2 is not available for STM32F031 devices.
- * @param NewState: new state of the selected SPI TI communication mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the TI mode for the selected SPI peripheral */
- SPIx->CR2 |= SPI_CR2_FRF;
- }
- else
- {
- /* Disable the TI mode for the selected SPI peripheral */
- SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_FRF);
- }
-}
-
-/**
- * @brief Enables or disables the specified SPI peripheral (in I2S mode).
- * @note This mode is not supported for STM32F030 devices.
- * @param SPIx: where x can be 1 to select the SPI peripheral.
- * @param NewState: new state of the SPIx peripheral.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_SPI_1_PERIPH(SPIx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the selected SPI peripheral in I2S mode */
- SPIx->I2SCFGR |= SPI_I2SCFGR_I2SE;
- }
- else
- {
- /* Disable the selected SPI peripheral in I2S mode */
- SPIx->I2SCFGR &= (uint16_t)~((uint16_t)SPI_I2SCFGR_I2SE);
- }
-}
-
-/**
- * @brief Configures the data size for the selected SPI.
- * @param SPIx: where x can be 1 or 2 to select the SPI peripheral.
- * @note SPI2 is not available for STM32F031 devices.
- * @param SPI_DataSize: specifies the SPI data size.
- * For the SPIx peripheral this parameter can be one of the following values:
- * @arg SPI_DataSize_4b: Set data size to 4 bits
- * @arg SPI_DataSize_5b: Set data size to 5 bits
- * @arg SPI_DataSize_6b: Set data size to 6 bits
- * @arg SPI_DataSize_7b: Set data size to 7 bits
- * @arg SPI_DataSize_8b: Set data size to 8 bits
- * @arg SPI_DataSize_9b: Set data size to 9 bits
- * @arg SPI_DataSize_10b: Set data size to 10 bits
- * @arg SPI_DataSize_11b: Set data size to 11 bits
- * @arg SPI_DataSize_12b: Set data size to 12 bits
- * @arg SPI_DataSize_13b: Set data size to 13 bits
- * @arg SPI_DataSize_14b: Set data size to 14 bits
- * @arg SPI_DataSize_15b: Set data size to 15 bits
- * @arg SPI_DataSize_16b: Set data size to 16 bits
- * @retval None
- */
-void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize)
-{
- uint16_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_SPI_DATA_SIZE(SPI_DataSize));
- /* Read the CR2 register */
- tmpreg = SPIx->CR2;
- /* Clear DS[3:0] bits */
- tmpreg &= (uint16_t)~SPI_CR2_DS;
- /* Set new DS[3:0] bits value */
- tmpreg |= SPI_DataSize;
- SPIx->CR2 = tmpreg;
-}
-
-/**
- * @brief Configures the FIFO reception threshold for the selected SPI.
- * @param SPIx: where x can be 1 or 2 to select the SPI peripheral.
- * @note SPI2 is not available for STM32F031 devices.
- * @param SPI_RxFIFOThreshold: specifies the FIFO reception threshold.
- * This parameter can be one of the following values:
- * @arg SPI_RxFIFOThreshold_HF: RXNE event is generated if the FIFO
- * level is greater or equal to 1/2.
- * @arg SPI_RxFIFOThreshold_QF: RXNE event is generated if the FIFO
- * level is greater or equal to 1/4.
- * @retval None
- */
-void SPI_RxFIFOThresholdConfig(SPI_TypeDef* SPIx, uint16_t SPI_RxFIFOThreshold)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_SPI_RX_FIFO_THRESHOLD(SPI_RxFIFOThreshold));
-
- /* Clear FRXTH bit */
- SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_FRXTH);
-
- /* Set new FRXTH bit value */
- SPIx->CR2 |= SPI_RxFIFOThreshold;
-}
-
-/**
- * @brief Selects the data transfer direction in bidirectional mode for the specified SPI.
- * @param SPIx: where x can be 1 or 2 to select the SPI peripheral.
- * @note SPI2 is not available for STM32F031 devices.
- * @param SPI_Direction: specifies the data transfer direction in bidirectional mode.
- * This parameter can be one of the following values:
- * @arg SPI_Direction_Tx: Selects Tx transmission direction
- * @arg SPI_Direction_Rx: Selects Rx receive direction
- * @retval None
- */
-void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_SPI_DIRECTION(SPI_Direction));
- if (SPI_Direction == SPI_Direction_Tx)
- {
- /* Set the Tx only mode */
- SPIx->CR1 |= SPI_Direction_Tx;
- }
- else
- {
- /* Set the Rx only mode */
- SPIx->CR1 &= SPI_Direction_Rx;
- }
-}
-
-/**
- * @brief Configures internally by software the NSS pin for the selected SPI.
- * @note This function can be called only after the SPI_Init() function has
- * been called.
- * @param SPIx: where x can be 1 or 2 to select the SPI peripheral.
- * @note SPI2 is not available for STM32F031 devices.
- * @param SPI_NSSInternalSoft: specifies the SPI NSS internal state.
- * This parameter can be one of the following values:
- * @arg SPI_NSSInternalSoft_Set: Set NSS pin internally
- * @arg SPI_NSSInternalSoft_Reset: Reset NSS pin internally
- * @retval None
- */
-void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_SPI_NSS_INTERNAL(SPI_NSSInternalSoft));
-
- if (SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset)
- {
- /* Set NSS pin internally by software */
- SPIx->CR1 |= SPI_NSSInternalSoft_Set;
- }
- else
- {
- /* Reset NSS pin internally by software */
- SPIx->CR1 &= SPI_NSSInternalSoft_Reset;
- }
-}
-
-/**
- * @brief Enables or disables the SS output for the selected SPI.
- * @note This function can be called only after the SPI_Init() function has
- * been called and the NSS hardware management mode is selected.
- * @param SPIx: where x can be 1 or 2 to select the SPI peripheral.
- * @note SPI2 is not available for STM32F031 devices.
- * @param NewState: new state of the SPIx SS output.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the selected SPI SS output */
- SPIx->CR2 |= SPI_CR2_SSOE;
- }
- else
- {
- /* Disable the selected SPI SS output */
- SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_SSOE);
- }
-}
-
-/**
- * @brief Enables or disables the NSS pulse management mode.
- * @note This function can be called only after the SPI_Init() function has
- * been called.
- * @note When TI mode is selected, the control bits NSSP is not taken into
- * consideration and are configured by hardware respectively to the
- * TI mode requirements.
- * @param SPIx: where x can be 1 or 2 to select the SPI peripheral.
- * @note SPI2 is not available for STM32F031 devices.
- * @param NewState: new state of the NSS pulse management mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SPI_NSSPulseModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the NSS pulse management mode */
- SPIx->CR2 |= SPI_CR2_NSSP;
- }
- else
- {
- /* Disable the NSS pulse management mode */
- SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_NSSP);
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup SPI_Group2 Data transfers functions
- * @brief Data transfers functions
- *
-@verbatim
- ===============================================================================
- ##### Data transfers functions #####
- ===============================================================================
- [..] This section provides a set of functions allowing to manage the SPI or I2S
- data transfers.
-
- [..] In reception, data are received and then stored into an internal Rx buffer while
- In transmission, data are first stored into an internal Tx buffer before being
- transmitted.
-
- [..] The read access of the SPI_DR register can be done using
- SPI_ReceiveData8() (when data size is equal or inferior than 8bits) and.
- SPI_I2S_ReceiveData16() (when data size is superior than 8bits)function
- and returns the Rx buffered value. Whereas a write access to the SPI_DR
- can be done using SPI_SendData8() (when data size is equal or inferior than 8bits)
- and SPI_I2S_SendData16() (when data size is superior than 8bits) function
- and stores the written data into Tx buffer.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Transmits a Data through the SPIx/I2Sx peripheral.
- * @param SPIx: where x can be 1 or 2 in SPI mode to select the SPI peripheral.
- * @note SPI2 is not available for STM32F031 devices.
- * @param Data: Data to be transmitted.
- * @retval None
- */
-void SPI_SendData8(SPI_TypeDef* SPIx, uint8_t Data)
-{
- uint32_t spixbase = 0x00;
-
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
-
- spixbase = (uint32_t)SPIx;
- spixbase += 0x0C;
-
- *(__IO uint8_t *) spixbase = Data;
-}
-
-/**
- * @brief Transmits a Data through the SPIx/I2Sx peripheral.
- * @param SPIx: where x can be 1 or 2 in SPI mode or 1 in I2S mode to select
- * the SPI peripheral.
- * @note SPI2 is not available for STM32F031 devices.
- * @param Data: Data to be transmitted.
- * @retval None
- */
-void SPI_I2S_SendData16(SPI_TypeDef* SPIx, uint16_t Data)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
-
- SPIx->DR = (uint16_t)Data;
-}
-
-/**
- * @brief Returns the most recent received data by the SPIx/I2Sx peripheral.
- * @param SPIx: where x can be 1 or 2 in SPI mode to select the SPI peripheral.
- * @note SPI2 is not available for STM32F031 devices.
- * @retval The value of the received data.
- */
-uint8_t SPI_ReceiveData8(SPI_TypeDef* SPIx)
-{
- uint32_t spixbase = 0x00;
-
- spixbase = (uint32_t)SPIx;
- spixbase += 0x0C;
-
- return *(__IO uint8_t *) spixbase;
-}
-
-/**
- * @brief Returns the most recent received data by the SPIx peripheral.
- * @param SPIx: where x can be 1 or 2 in SPI mode or 1 in I2S mode to select
- * @note SPI2 is not available for STM32F031 devices.
- * the SPI peripheral.
- * @retval The value of the received data.
- */
-uint16_t SPI_I2S_ReceiveData16(SPI_TypeDef* SPIx)
-{
- return SPIx->DR;
-}
-/**
- * @}
- */
-
-/** @defgroup SPI_Group3 Hardware CRC Calculation functions
- * @brief Hardware CRC Calculation functions
- *
-@verbatim
- ===============================================================================
- ##### Hardware CRC Calculation functions #####
- ===============================================================================
- [..] This section provides a set of functions allowing to manage the SPI CRC hardware
- calculation.SPI communication using CRC is possible through the following procedure:
-
- (#) Program the Data direction, Polarity, Phase, First Data, Baud Rate Prescaler,
- Slave Management, Peripheral Mode and CRC Polynomial values using the SPI_Init()
- function.
- (#) Enable the CRC calculation using the SPI_CalculateCRC() function.
- (#) Enable the SPI using the SPI_Cmd() function
- (#) Before writing the last data to the TX buffer, set the CRCNext bit using the
- SPI_TransmitCRC() function to indicate that after transmission of the last
- data, the CRC should be transmitted.
- (#) After transmitting the last data, the SPI transmits the CRC. The SPI_CR1_CRCNEXT
- bit is reset. The CRC is also received and compared against the SPI_RXCRCR
- value.
- If the value does not match, the SPI_FLAG_CRCERR flag is set and an interrupt
- can be generated when the SPI_I2S_IT_ERR interrupt is enabled.
-
- -@-
- (+@) It is advised to don't read the calculate CRC values during the communication.
- (+@) When the SPI is in slave mode, be careful to enable CRC calculation only
- when the clock is stable, that is, when the clock is in the steady state.
- If not, a wrong CRC calculation may be done. In fact, the CRC is sensitive
- to the SCK slave input clock as soon as CRCEN is set, and this, whatever
- the value of the SPE bit.
- (+@) With high bitrate frequencies, be careful when transmitting the CRC.
- As the number of used CPU cycles has to be as low as possible in the CRC
- transfer phase, it is forbidden to call software functions in the CRC
- transmission sequence to avoid errors in the last data and CRC reception.
- In fact, CRCNEXT bit has to be written before the end of the transmission/reception
- of the last data.
- (+@) For high bit rate frequencies, it is advised to use the DMA mode to avoid the
- degradation of the SPI speed performance due to CPU accesses impacting the
- SPI bandwidth.
- (+@) When the STM32F0xx are configured as slaves and the NSS hardware mode is
- used, the NSS pin needs to be kept low between the data phase and the CRC
- phase.
- (+@) When the SPI is configured in slave mode with the CRC feature enabled, CRC
- calculation takes place even if a high level is applied on the NSS pin.
- This may happen for example in case of a multislave environment where the
- communication master addresses slaves alternately.
- (+@) Between a slave deselection (high level on NSS) and a new slave selection
- (low level on NSS), the CRC value should be cleared on both master and slave
- sides in order to resynchronize the master and slave for their respective
- CRC calculation.
-
- -@- To clear the CRC, follow the procedure below:
- (#@) Disable SPI using the SPI_Cmd() function
- (#@) Disable the CRC calculation using the SPI_CalculateCRC() function.
- (#@) Enable the CRC calculation using the SPI_CalculateCRC() function.
- (#@) Enable SPI using the SPI_Cmd() function.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures the CRC calculation length for the selected SPI.
- * @note This function can be called only after the SPI_Init() function has
- * been called.
- * @param SPIx: where x can be 1 or 2 to select the SPI peripheral.
- * @note SPI2 is not available for STM32F031 devices.
- * @param SPI_CRCLength: specifies the SPI CRC calculation length.
- * This parameter can be one of the following values:
- * @arg SPI_CRCLength_8b: Set CRC Calculation to 8 bits
- * @arg SPI_CRCLength_16b: Set CRC Calculation to 16 bits
- * @retval None
- */
-void SPI_CRCLengthConfig(SPI_TypeDef* SPIx, uint16_t SPI_CRCLength)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_SPI_CRC_LENGTH(SPI_CRCLength));
-
- /* Clear CRCL bit */
- SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_CRCL);
-
- /* Set new CRCL bit value */
- SPIx->CR1 |= SPI_CRCLength;
-}
-
-/**
- * @brief Enables or disables the CRC value calculation of the transferred bytes.
- * @note This function can be called only after the SPI_Init() function has
- * been called.
- * @param SPIx: where x can be 1 or 2 to select the SPI peripheral.
- * @note SPI2 is not available for STM32F031 devices.
- * @param NewState: new state of the SPIx CRC value calculation.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected SPI CRC calculation */
- SPIx->CR1 |= SPI_CR1_CRCEN;
- }
- else
- {
- /* Disable the selected SPI CRC calculation */
- SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_CRCEN);
- }
-}
-
-/**
- * @brief Transmit the SPIx CRC value.
- * @param SPIx: where x can be 1 or 2 to select the SPI peripheral.
- * @note SPI2 is not available for STM32F031 devices.
- * @retval None
- */
-void SPI_TransmitCRC(SPI_TypeDef* SPIx)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
-
- /* Enable the selected SPI CRC transmission */
- SPIx->CR1 |= SPI_CR1_CRCNEXT;
-}
-
-/**
- * @brief Returns the transmit or the receive CRC register value for the specified SPI.
- * @param SPIx: where x can be 1 or 2 to select the SPI peripheral.
- * @note SPI2 is not available for STM32F031 devices.
- * @param SPI_CRC: specifies the CRC register to be read.
- * This parameter can be one of the following values:
- * @arg SPI_CRC_Tx: Selects Tx CRC register
- * @arg SPI_CRC_Rx: Selects Rx CRC register
- * @retval The selected CRC register value..
- */
-uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC)
-{
- uint16_t crcreg = 0;
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_SPI_CRC(SPI_CRC));
-
- if (SPI_CRC != SPI_CRC_Rx)
- {
- /* Get the Tx CRC register */
- crcreg = SPIx->TXCRCR;
- }
- else
- {
- /* Get the Rx CRC register */
- crcreg = SPIx->RXCRCR;
- }
- /* Return the selected CRC register */
- return crcreg;
-}
-
-/**
- * @brief Returns the CRC Polynomial register value for the specified SPI.
- * @param SPIx: where x can be 1 or 2 to select the SPI peripheral.
- * @note SPI2 is not available for STM32F031 devices.
- * @retval The CRC Polynomial register value.
- */
-uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
-
- /* Return the CRC polynomial register */
- return SPIx->CRCPR;
-}
-
-/**
- * @}
- */
-
-/** @defgroup SPI_Group4 DMA transfers management functions
- * @brief DMA transfers management functions
- *
-@verbatim
- ===============================================================================
- ##### DMA transfers management functions #####
- ===============================================================================
- [..] This section provides two functions that can be used only in DMA mode.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the SPIx/I2Sx DMA interface.
- * @param SPIx: where x can be 1 or 2 in SPI mode or 1 in I2S mode to select
- * the SPI peripheral.
- * @note SPI2 is not available for STM32F031 devices.
- * I2S mode is not supported for STM32F030 devices.
- * @param SPI_I2S_DMAReq: specifies the SPI DMA transfer request to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg SPI_I2S_DMAReq_Tx: Tx buffer DMA transfer request
- * @arg SPI_I2S_DMAReq_Rx: Rx buffer DMA transfer request
- * @param NewState: new state of the selected SPI DMA transfer request.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- assert_param(IS_SPI_I2S_DMA_REQ(SPI_I2S_DMAReq));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected SPI DMA requests */
- SPIx->CR2 |= SPI_I2S_DMAReq;
- }
- else
- {
- /* Disable the selected SPI DMA requests */
- SPIx->CR2 &= (uint16_t)~SPI_I2S_DMAReq;
- }
-}
-
-/**
- * @brief Configures the number of data to transfer type(Even/Odd) for the DMA
- * last transfers and for the selected SPI.
- * @note This function have a meaning only if DMA mode is selected and if
- * the packing mode is used (data length <= 8 and DMA transfer size halfword)
- * @param SPIx: where x can be 1 or 2 to select the SPI peripheral.
- * @note SPI2 is not available for STM32F031 devices.
- * @param SPI_LastDMATransfer: specifies the SPI last DMA transfers state.
- * This parameter can be one of the following values:
- * @arg SPI_LastDMATransfer_TxEvenRxEven: Number of data for transmission Even
- * and number of data for reception Even.
- * @arg SPI_LastDMATransfer_TxOddRxEven: Number of data for transmission Odd
- * and number of data for reception Even.
- * @arg SPI_LastDMATransfer_TxEvenRxOdd: Number of data for transmission Even
- * and number of data for reception Odd.
- * @arg SPI_LastDMATransfer_TxOddRxOdd: Number of data for transmission Odd
- * and number of data for reception Odd.
- * @retval None
- */
-void SPI_LastDMATransferCmd(SPI_TypeDef* SPIx, uint16_t SPI_LastDMATransfer)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_SPI_LAST_DMA_TRANSFER(SPI_LastDMATransfer));
-
- /* Clear LDMA_TX and LDMA_RX bits */
- SPIx->CR2 &= CR2_LDMA_MASK;
-
- /* Set new LDMA_TX and LDMA_RX bits value */
- SPIx->CR2 |= SPI_LastDMATransfer;
-}
-
-/**
- * @}
- */
-
-/** @defgroup SPI_Group5 Interrupts and flags management functions
- * @brief Interrupts and flags management functions
- *
-@verbatim
- ===============================================================================
- ##### Interrupts and flags management functions #####
- ===============================================================================
- [..] This section provides a set of functions allowing to configure the SPI/I2S Interrupts
- sources and check or clear the flags or pending bits status.
- The user should identify which mode will be used in his application to manage
- the communication: Polling mode, Interrupt mode or DMA mode.
-
- *** Polling Mode ***
- ====================
- [..] In Polling Mode, the SPI/I2S communication can be managed by 9 flags:
- (#) SPI_I2S_FLAG_TXE : to indicate the status of the transmit buffer register
- (#) SPI_I2S_FLAG_RXNE : to indicate the status of the receive buffer register
- (#) SPI_I2S_FLAG_BSY : to indicate the state of the communication layer of the SPI.
- (#) SPI_FLAG_CRCERR : to indicate if a CRC Calculation error occur
- (#) SPI_FLAG_MODF : to indicate if a Mode Fault error occur
- (#) SPI_I2S_FLAG_OVR : to indicate if an Overrun error occur
- (#) SPI_I2S_FLAG_FRE: to indicate a Frame Format error occurs.
- (#) I2S_FLAG_UDR: to indicate an Underrun error occurs.
- (#) I2S_FLAG_CHSIDE: to indicate Channel Side.
-
- [..]
- (@)Do not use the BSY flag to handle each data transmission or reception. It is better
- to use the TXE and RXNE flags instead.
-
- [..] In this Mode it is advised to use the following functions:
- (+) FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
- (+) void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
-
- *** Interrupt Mode ***
- ======================
- [..] In Interrupt Mode, the SPI/I2S communication can be managed by 3 interrupt sources
- and 5 pending bits:
- [..] Pending Bits:
- (#) SPI_I2S_IT_TXE : to indicate the status of the transmit buffer register
- (#) SPI_I2S_IT_RXNE : to indicate the status of the receive buffer register
- (#) SPI_I2S_IT_OVR : to indicate if an Overrun error occur
- (#) I2S_IT_UDR : to indicate an Underrun Error occurs.
- (#) SPI_I2S_FLAG_FRE : to indicate a Frame Format error occurs.
-
- [..] Interrupt Source:
- (#) SPI_I2S_IT_TXE: specifies the interrupt source for the Tx buffer empty
- interrupt.
- (#) SPI_I2S_IT_RXNE : specifies the interrupt source for the Rx buffer not
- empty interrupt.
- (#) SPI_I2S_IT_ERR : specifies the interrupt source for the errors interrupt.
-
- [..] In this Mode it is advised to use the following functions:
- (+) void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState);
- (+) ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
-
- *** FIFO Status ***
- ===================
- [..] It is possible to monitor the FIFO status when a transfer is ongoing using the
- following function:
- (+) uint32_t SPI_GetFIFOStatus(uint8_t SPI_FIFO_Direction);
-
- *** DMA Mode ***
- ================
- [..] In DMA Mode, the SPI communication can be managed by 2 DMA Channel
- requests:
- (#) SPI_I2S_DMAReq_Tx: specifies the Tx buffer DMA transfer request.
- (#) SPI_I2S_DMAReq_Rx: specifies the Rx buffer DMA transfer request.
-
- [..] In this Mode it is advised to use the following function:
- (+) void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState).
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the specified SPI/I2S interrupts.
- * @param SPIx: where x can be 1 or 2 in SPI mode or 1 in I2S mode to select
- * the SPI peripheral.
- * @note SPI2 is not available for STM32F031 devices.
- * I2S mode is not supported for STM32F030 devices.
- * @param SPI_I2S_IT: specifies the SPI interrupt source to be enabled or disabled.
- * This parameter can be one of the following values:
- * @arg SPI_I2S_IT_TXE: Tx buffer empty interrupt mask
- * @arg SPI_I2S_IT_RXNE: Rx buffer not empty interrupt mask
- * @arg SPI_I2S_IT_ERR: Error interrupt mask
- * @param NewState: new state of the specified SPI interrupt.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState)
-{
- uint16_t itpos = 0, itmask = 0 ;
-
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- assert_param(IS_SPI_I2S_CONFIG_IT(SPI_I2S_IT));
-
- /* Get the SPI IT index */
- itpos = SPI_I2S_IT >> 4;
-
- /* Set the IT mask */
- itmask = (uint16_t)1 << (uint16_t)itpos;
-
- if (NewState != DISABLE)
- {
- /* Enable the selected SPI interrupt */
- SPIx->CR2 |= itmask;
- }
- else
- {
- /* Disable the selected SPI interrupt */
- SPIx->CR2 &= (uint16_t)~itmask;
- }
-}
-
-/**
- * @brief Returns the current SPIx Transmission FIFO filled level.
- * @param SPIx: where x can be 1 or 2 to select the SPI peripheral.
- * @note SPI2 is not available for STM32F031 devices.
- * @retval The Transmission FIFO filling state.
- * - SPI_TransmissionFIFOStatus_Empty: when FIFO is empty
- * - SPI_TransmissionFIFOStatus_1QuarterFull: if more than 1 quarter-full.
- * - SPI_TransmissionFIFOStatus_HalfFull: if more than 1 half-full.
- * - SPI_TransmissionFIFOStatus_Full: when FIFO is full.
- */
-uint16_t SPI_GetTransmissionFIFOStatus(SPI_TypeDef* SPIx)
-{
- /* Get the SPIx Transmission FIFO level bits */
- return (uint16_t)((SPIx->SR & SPI_SR_FTLVL));
-}
-
-/**
- * @brief Returns the current SPIx Reception FIFO filled level.
- * @param SPIx: where x can be 1 or 2 to select the SPI peripheral.
- * @note SPI2 is not available for STM32F031 devices.
- * @retval The Reception FIFO filling state.
- * - SPI_ReceptionFIFOStatus_Empty: when FIFO is empty
- * - SPI_ReceptionFIFOStatus_1QuarterFull: if more than 1 quarter-full.
- * - SPI_ReceptionFIFOStatus_HalfFull: if more than 1 half-full.
- * - SPI_ReceptionFIFOStatus_Full: when FIFO is full.
- */
-uint16_t SPI_GetReceptionFIFOStatus(SPI_TypeDef* SPIx)
-{
- /* Get the SPIx Reception FIFO level bits */
- return (uint16_t)((SPIx->SR & SPI_SR_FRLVL));
-}
-
-/**
- * @brief Checks whether the specified SPI flag is set or not.
- * @param SPIx: where x can be 1 or 2 in SPI mode or 1 in I2S mode to select
- * the SPI peripheral.
- * @note SPI2 is not available for STM32F031 devices.
- * I2S mode is not supported for STM32F030 devices.
- * @param SPI_I2S_FLAG: specifies the SPI flag to check.
- * This parameter can be one of the following values:
- * @arg SPI_I2S_FLAG_TXE: Transmit buffer empty flag.
- * @arg SPI_I2S_FLAG_RXNE: Receive buffer not empty flag.
- * @arg SPI_I2S_FLAG_BSY: Busy flag.
- * @arg SPI_I2S_FLAG_OVR: Overrun flag.
- * @arg SPI_FLAG_MODF: Mode Fault flag.
- * @arg SPI_FLAG_CRCERR: CRC Error flag.
- * @arg SPI_I2S_FLAG_FRE: TI frame format error flag.
- * @arg I2S_FLAG_UDR: Underrun Error flag.
- * @arg I2S_FLAG_CHSIDE: Channel Side flag.
- * @retval The new state of SPI_I2S_FLAG (SET or RESET).
- */
-FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)
-{
- FlagStatus bitstatus = RESET;
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG));
-
- /* Check the status of the specified SPI flag */
- if ((SPIx->SR & SPI_I2S_FLAG) != (uint16_t)RESET)
- {
- /* SPI_I2S_FLAG is set */
- bitstatus = SET;
- }
- else
- {
- /* SPI_I2S_FLAG is reset */
- bitstatus = RESET;
- }
- /* Return the SPI_I2S_FLAG status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the SPIx CRC Error (CRCERR) flag.
- * @param SPIx: where x can be 1 or 2 to select the SPI peripheral.
- * @note SPI2 is not available for STM32F031 devices.
- * I2S mode is not supported for STM32F030 devices.
- * @param SPI_I2S_FLAG: specifies the SPI flag to clear.
- * This function clears only CRCERR flag.
- * @note OVR (OverRun error) flag is cleared by software sequence: a read
- * operation to SPI_DR register (SPI_I2S_ReceiveData()) followed by
- * a read operation to SPI_SR register (SPI_I2S_GetFlagStatus()).
- * @note MODF (Mode Fault) flag is cleared by software sequence: a read/write
- * operation to SPI_SR register (SPI_I2S_GetFlagStatus()) followed by
- * a write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI).
- * @retval None
- */
-void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_SPI_CLEAR_FLAG(SPI_I2S_FLAG));
-
- /* Clear the selected SPI CRC Error (CRCERR) flag */
- SPIx->SR = (uint16_t)~SPI_I2S_FLAG;
-}
-
-/**
- * @brief Checks whether the specified SPI/I2S interrupt has occurred or not.
- * @param SPIx: where x can be 1 or 2 in SPI mode or 1 in I2S mode to select
- * the SPI peripheral.
- * @param SPI_I2S_IT: specifies the SPI interrupt source to check.
- * This parameter can be one of the following values:
- * @arg SPI_I2S_IT_TXE: Transmit buffer empty interrupt.
- * @arg SPI_I2S_IT_RXNE: Receive buffer not empty interrupt.
- * @arg SPI_IT_MODF: Mode Fault interrupt.
- * @arg SPI_I2S_IT_OVR: Overrun interrupt.
- * @arg I2S_IT_UDR: Underrun interrupt.
- * @arg SPI_I2S_IT_FRE: Format Error interrupt.
- * @retval The new state of SPI_I2S_IT (SET or RESET).
- */
-ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT)
-{
- ITStatus bitstatus = RESET;
- uint16_t itpos = 0, itmask = 0, enablestatus = 0;
-
- /* Check the parameters */
- assert_param(IS_SPI_ALL_PERIPH(SPIx));
- assert_param(IS_SPI_I2S_GET_IT(SPI_I2S_IT));
-
- /* Get the SPI_I2S_IT index */
- itpos = 0x01 << (SPI_I2S_IT & 0x0F);
-
- /* Get the SPI_I2S_IT IT mask */
- itmask = SPI_I2S_IT >> 4;
-
- /* Set the IT mask */
- itmask = 0x01 << itmask;
-
- /* Get the SPI_I2S_IT enable bit status */
- enablestatus = (SPIx->CR2 & itmask) ;
-
- /* Check the status of the specified SPI interrupt */
- if (((SPIx->SR & itpos) != (uint16_t)RESET) && enablestatus)
- {
- /* SPI_I2S_IT is set */
- bitstatus = SET;
- }
- else
- {
- /* SPI_I2S_IT is reset */
- bitstatus = RESET;
- }
- /* Return the SPI_I2S_IT status */
- return bitstatus;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_syscfg.c b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_syscfg.c
deleted file mode 100644
index 518cf2ac8d62c5a965e3b4b082472df84cd1918c..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_syscfg.c
+++ /dev/null
@@ -1,320 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f0xx_syscfg.c
- * @author MCD Application Team
- * @version V1.3.0
- * @date 16-January-2014
- * @brief This file provides firmware functions to manage the following
- * functionalities of the SYSCFG peripheral:
- * + Remapping the memory mapped at 0x00000000
- * + Remapping the DMA channels
- * + Enabling I2C fast mode plus driving capability for I2C pins
- * + Configuring the EXTI lines connection to the GPIO port
- * + Configuring the CFGR2 features (Connecting some internal signal
- * to the break input of TIM1)
- *
- * @verbatim
- ===============================================================================
- ##### How to use this driver #####
- ===============================================================================
- [..]
- The SYSCFG registers can be accessed only when the SYSCFG
- interface APB clock is enabled.
- To enable SYSCFG APB clock use:
- RCC_APBPeriphClockCmd(RCC_APBPeriph_SYSCFG, ENABLE).
- * @endverbatim
- *
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx_syscfg.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup SYSCFG
- * @brief SYSCFG driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup SYSCFG_Private_Functions
- * @{
- */
-
-/** @defgroup SYSCFG_Group1 SYSCFG Initialization and Configuration functions
- * @brief SYSCFG Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### SYSCFG Initialization and Configuration functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitializes the SYSCFG registers to their default reset values.
- * @param None
- * @retval None
- * @note MEM_MODE bits are not affected by APB reset.
- * @note MEM_MODE bits took the value from the user option bytes.
- * @note CFGR2 register is not affected by APB reset.
- * @note CLABBB configuration bits are locked when set.
- * @note To unlock the configuration, perform a system reset.
- */
-void SYSCFG_DeInit(void)
-{
- /* Set SYSCFG_CFGR1 register to reset value without affecting MEM_MODE bits */
- SYSCFG->CFGR1 &= SYSCFG_CFGR1_MEM_MODE;
- /* Set EXTICRx registers to reset value */
- SYSCFG->EXTICR[0] = 0;
- SYSCFG->EXTICR[1] = 0;
- SYSCFG->EXTICR[2] = 0;
- SYSCFG->EXTICR[3] = 0;
- /* Set CFGR2 register to reset value: clear SRAM parity error flag */
- SYSCFG->CFGR2 |= (uint32_t) SYSCFG_CFGR2_SRAM_PE;
-}
-
-/**
- * @brief Configures the memory mapping at address 0x00000000.
- * @param SYSCFG_MemoryRemap: selects the memory remapping.
- * This parameter can be one of the following values:
- * @arg SYSCFG_MemoryRemap_Flash: Main Flash memory mapped at 0x00000000
- * @arg SYSCFG_MemoryRemap_SystemMemory: System Flash memory mapped at 0x00000000
- * @arg SYSCFG_MemoryRemap_SRAM: Embedded SRAM mapped at 0x00000000
- * @retval None
- */
-void SYSCFG_MemoryRemapConfig(uint32_t SYSCFG_MemoryRemap)
-{
- uint32_t tmpctrl = 0;
-
- /* Check the parameter */
- assert_param(IS_SYSCFG_MEMORY_REMAP(SYSCFG_MemoryRemap));
-
- /* Get CFGR1 register value */
- tmpctrl = SYSCFG->CFGR1;
-
- /* Clear MEM_MODE bits */
- tmpctrl &= (uint32_t) (~SYSCFG_CFGR1_MEM_MODE);
-
- /* Set the new MEM_MODE bits value */
- tmpctrl |= (uint32_t) SYSCFG_MemoryRemap;
-
- /* Set CFGR1 register with the new memory remap configuration */
- SYSCFG->CFGR1 = tmpctrl;
-}
-
-/**
- * @brief Configure the DMA channels remapping.
- * @param SYSCFG_DMARemap: selects the DMA channels remap.
- * This parameter can be one of the following values:
- * @arg SYSCFG_DMARemap_TIM17: Remap TIM17 DMA requests from channel1 to channel2
- * @arg SYSCFG_DMARemap_TIM16: Remap TIM16 DMA requests from channel3 to channel4
- * @arg SYSCFG_DMARemap_USART1Rx: Remap USART1 Rx DMA requests from channel3 to channel5
- * @arg SYSCFG_DMARemap_USART1Tx: Remap USART1 Tx DMA requests from channel2 to channel4
- * @arg SYSCFG_DMARemap_ADC1: Remap ADC1 DMA requests from channel1 to channel2
- * @param NewState: new state of the DMA channel remapping.
- * This parameter can be: ENABLE or DISABLE.
- * @note When enabled, DMA channel of the selected peripheral is remapped
- * @note When disabled, Default DMA channel is mapped to the selected peripheral
- * @note By default TIM17 DMA requests is mapped to channel 1,
- * use SYSCFG_DMAChannelRemapConfig(SYSCFG_DMARemap_TIM17, Enable) to remap
- * TIM17 DMA requests to channel 2 and use
- * SYSCFG_DMAChannelRemapConfig(SYSCFG_DMARemap_TIM17, Disable) to map
- * TIM17 DMA requests to channel 1 (default mapping)
- * @retval None
- */
-void SYSCFG_DMAChannelRemapConfig(uint32_t SYSCFG_DMARemap, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_SYSCFG_DMA_REMAP(SYSCFG_DMARemap));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Remap the DMA channel */
- SYSCFG->CFGR1 |= (uint32_t)SYSCFG_DMARemap;
- }
- else
- {
- /* use the default DMA channel mapping */
- SYSCFG->CFGR1 &= (uint32_t)(~SYSCFG_DMARemap);
- }
-}
-
-/**
- * @brief Configure the I2C fast mode plus driving capability.
- * @param SYSCFG_I2CFastModePlus: selects the pin.
- * This parameter can be one of the following values:
- * @arg SYSCFG_I2CFastModePlus_PB6: Configure fast mode plus driving capability for PB6
- * @arg SYSCFG_I2CFastModePlus_PB7: Configure fast mode plus driving capability for PB7
- * @arg SYSCFG_I2CFastModePlus_PB8: Configure fast mode plus driving capability for PB8
- * @arg SYSCFG_I2CFastModePlus_PB9: Configure fast mode plus driving capability for PB9
- * @arg SYSCFG_I2CFastModePlus_PA9: Configure fast mode plus driving capability for PA9 (only for STM32F031 and STM32F030 devices)
- * @arg SYSCFG_I2CFastModePlus_PA10: Configure fast mode plus driving capability for PA10 (only for STM32F031 and STM32F030 devices)
- * @arg SYSCFG_I2CFastModePlus_I2C1: Configure fast mode plus driving capability for PB10, PB11, PF6 and PF7(only for STM32F031 and STM32F030 devices)
- * @arg SYSCFG_I2CFastModePlus_I2C2: Configure fast mode plus driving capability for I2C2 pins, available only for STM32F072 devices
- *
- * @param NewState: new state of the DMA channel remapping.
- * This parameter can be: ENABLE or DISABLE.
- * @note ENABLE: Enable fast mode plus driving capability for selected I2C pin
- * @note DISABLE: Disable fast mode plus driving capability for selected I2C pin
- * @note For I2C1, fast mode plus driving capability can be enabled on all selected
- * I2C1 pins using SYSCFG_I2CFastModePlus_I2C1 parameter or independently
- * on each one of the following pins PB6, PB7, PB8 and PB9.
- * @note For remaing I2C1 pins (PA14, PA15...) fast mode plus driving capability
- * can be enabled only by using SYSCFG_I2CFastModePlus_I2C1 parameter.
- * @note For all I2C2 pins fast mode plus driving capability can be enabled
- * only by using SYSCFG_I2CFastModePlus_I2C2 parameter.
- * @retval None
- */
-void SYSCFG_I2CFastModePlusConfig(uint32_t SYSCFG_I2CFastModePlus, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_SYSCFG_I2C_FMP(SYSCFG_I2CFastModePlus));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable fast mode plus driving capability for selected pin */
- SYSCFG->CFGR1 |= (uint32_t)SYSCFG_I2CFastModePlus;
- }
- else
- {
- /* Disable fast mode plus driving capability for selected pin */
- SYSCFG->CFGR1 &= (uint32_t)(~SYSCFG_I2CFastModePlus);
- }
-}
-
-/**
- * @brief Selects the GPIO pin used as EXTI Line.
- * @param EXTI_PortSourceGPIOx: selects the GPIO port to be used as source
- * for EXTI lines where x can be (A, B, C, D, E or F).
- * @note GPIOE is available only for STM32F072.
- * @note GPIOD is not available for STM32F031.
- * @param EXTI_PinSourcex: specifies the EXTI line to be configured.
- * @note This parameter can be EXTI_PinSourcex where x can be:
- * For STM32F051 and STM32F030: (0..15) for GPIOA, GPIOB, GPIOC, (2) for GPIOD and (0..1, 4..7) for GIIOF.
- * For STM32F072: (0..15) for GPIOA, GPIOB, GPIOC, GPIOD, GPIOE, (0..10) for GPIOF.
- * For STM32F031: (0..15) for GPIOA, GPIOB, (13..15) for GPIOC and (0..1, 6..7) for GPIOF.
- * @retval None
- */
-void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex)
-{
- uint32_t tmp = 0x00;
-
- /* Check the parameters */
- assert_param(IS_EXTI_PORT_SOURCE(EXTI_PortSourceGPIOx));
- assert_param(IS_EXTI_PIN_SOURCE(EXTI_PinSourcex));
-
- tmp = ((uint32_t)0x0F) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03));
- SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] &= ~tmp;
- SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] |= (((uint32_t)EXTI_PortSourceGPIOx) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03)));
-}
-
-/**
- * @brief Connect the selected parameter to the break input of TIM1.
- * @note The selected configuration is locked and can be unlocked by system reset
- * @param SYSCFG_Break: selects the configuration to be connected to break
- * input of TIM1
- * This parameter can be any combination of the following values:
- * @arg SYSCFG_Break_PVD: Connects the PVD event to the Break Input of TIM1,, not avaailable for STM32F030 devices.
- * @arg SYSCFG_Break_SRAMParity: Connects the SRAM_PARITY error signal to the Break Input of TIM1 .
- * @arg SYSCFG_Break_Lockup: Connects Lockup output of CortexM0 to the break input of TIM1.
- * @retval None
- */
-void SYSCFG_BreakConfig(uint32_t SYSCFG_Break)
-{
- /* Check the parameter */
- assert_param(IS_SYSCFG_LOCK_CONFIG(SYSCFG_Break));
-
- SYSCFG->CFGR2 |= (uint32_t) SYSCFG_Break;
-}
-
-/**
- * @brief Checks whether the specified SYSCFG flag is set or not.
- * @param SYSCFG_Flag: specifies the SYSCFG flag to check.
- * This parameter can be one of the following values:
- * @arg SYSCFG_FLAG_PE: SRAM parity error flag.
- * @retval The new state of SYSCFG_Flag (SET or RESET).
- */
-FlagStatus SYSCFG_GetFlagStatus(uint32_t SYSCFG_Flag)
-{
- FlagStatus bitstatus = RESET;
-
- /* Check the parameter */
- assert_param(IS_SYSCFG_FLAG(SYSCFG_Flag));
-
- /* Check the status of the specified SPI flag */
- if ((SYSCFG->CFGR2 & SYSCFG_CFGR2_SRAM_PE) != (uint32_t)RESET)
- {
- /* SYSCFG_Flag is set */
- bitstatus = SET;
- }
- else
- {
- /* SYSCFG_Flag is reset */
- bitstatus = RESET;
- }
- /* Return the SYSCFG_Flag status */
- return bitstatus;
-}
-
-/**
- * @brief Clear the selected SYSCFG flag.
- * @param SYSCFG_Flag: selects the flag to be cleared.
- * This parameter can be any combination of the following values:
- * @arg SYSCFG_FLAG_PE: SRAM parity error flag.
- * @retval None
- */
-void SYSCFG_ClearFlag(uint32_t SYSCFG_Flag)
-{
- /* Check the parameter */
- assert_param(IS_SYSCFG_FLAG(SYSCFG_Flag));
-
- SYSCFG->CFGR2 |= (uint32_t) SYSCFG_Flag;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_tim.c b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_tim.c
deleted file mode 100644
index f7b428728abfd414763ea18a73711bc628a7c43d..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_tim.c
+++ /dev/null
@@ -1,3349 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f0xx_tim.c
- * @author MCD Application Team
- * @version V1.3.0
- * @date 16-January-2014
- * @brief This file provides firmware functions to manage the following
- * functionalities of the TIM peripheral:
- * + TimeBase management
- * + Output Compare management
- * + Input Capture management
- * + Interrupts, DMA and flags management
- * + Clocks management
- * + Synchronization management
- * + Specific interface management
- * + Specific remapping management
- *
- * @verbatim
-
- ===============================================================================
- ##### How to use this driver #####
- ===============================================================================
- [..] This driver provides functions to configure and program the TIM
- of all STM32F0xx devices These functions are split in 8 groups:
- (#) TIM TimeBase management: this group includes all needed functions
- to configure the TM Timebase unit:
- (++) Set/Get Prescaler.
- (++) Set/Get Autoreload.
- (++) Counter modes configuration.
- (++) Set Clock division.
- (++) Select the One Pulse mode.
- (++) Update Request Configuration.
- (++) Update Disable Configuration.
- (++) Auto-Preload Configuration.
- (++) Enable/Disable the counter.
-
- (#) TIM Output Compare management: this group includes all needed
- functions to configure the Capture/Compare unit used in Output
- compare mode:
- (++) Configure each channel, independently, in Output Compare mode.
- (++) Select the output compare modes.
- (++) Select the Polarities of each channel.
- (++) Set/Get the Capture/Compare register values.
- (++) Select the Output Compare Fast mode.
- (++) Select the Output Compare Forced mode.
- (++) Output Compare-Preload Configuration.
- (++) Clear Output Compare Reference.
- (++) Select the OCREF Clear signal.
- (++) Enable/Disable the Capture/Compare Channels.
-
- (#) TIM Input Capture management: this group includes all needed
- functions to configure the Capture/Compare unit used in
- Input Capture mode:
- (++) Configure each channel in input capture mode.
- (++) Configure Channel1/2 in PWM Input mode.
- (++) Set the Input Capture Prescaler.
- (++) Get the Capture/Compare values.
-
- (#) Advanced-control timers (TIM1) specific features
- (++) Configures the Break input, dead time, Lock level, the OSSI,
- the OSSR State and the AOE(automatic output enable)
- (++) Enable/Disable the TIM peripheral Main Outputs
- (++) Select the Commutation event
- (++) Set/Reset the Capture Compare Preload Control bit
-
- (#) TIM interrupts, DMA and flags management.
- (++) Enable/Disable interrupt sources.
- (++) Get flags status.
- (++) Clear flags/ Pending bits.
- (++) Enable/Disable DMA requests.
- (++) Configure DMA burst mode.
- (++) Select CaptureCompare DMA request.
-
- (#) TIM clocks management: this group includes all needed functions
- to configure the clock controller unit:
- (++) Select internal/External clock.
- (++) Select the external clock mode: ETR(Mode1/Mode2), TIx or ITRx.
-
- (#) TIM synchronization management: this group includes all needed.
- functions to configure the Synchronization unit:
- (++) Select Input Trigger.
- (++) Select Output Trigger.
- (++) Select Master Slave Mode.
- (++) ETR Configuration when used as external trigger.
-
- (#) TIM specific interface management, this group includes all
- needed functions to use the specific TIM interface:
- (++) Encoder Interface Configuration.
- (++) Select Hall Sensor.
-
- (#) TIM specific remapping management includes the Remapping
- configuration of specific timers
-
-@endverbatim
- *
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx_tim.h"
-#include "stm32f0xx_rcc.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup TIM
- * @brief TIM driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-/* ---------------------- TIM registers bit mask ------------------------ */
-#define SMCR_ETR_MASK ((uint16_t)0x00FF)
-#define CCMR_OFFSET ((uint16_t)0x0018)
-#define CCER_CCE_SET ((uint16_t)0x0001)
-#define CCER_CCNE_SET ((uint16_t)0x0004)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-
-static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
- uint16_t TIM_ICFilter);
-static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
- uint16_t TIM_ICFilter);
-static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
- uint16_t TIM_ICFilter);
-static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
- uint16_t TIM_ICFilter);
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup TIM_Private_Functions
- * @{
- */
-
-/** @defgroup TIM_Group1 TimeBase management functions
- * @brief TimeBase management functions
- *
-@verbatim
- ===============================================================================
- ##### TimeBase management functions #####
- ===============================================================================
-
- *** TIM Driver: how to use it in Timing(Time base) Mode ***
- ===============================================================================
- [..] To use the Timer in Timing(Time base) mode, the following steps are
- mandatory:
- (#) Enable TIM clock using
- RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function.
- (#) Fill the TIM_TimeBaseInitStruct with the desired parameters.
- (#) Call TIM_TimeBaseInit(TIMx, &TIM_TimeBaseInitStruct) to configure
- the Time Base unit with the corresponding configuration.
- (#) Enable the NVIC if you need to generate the update interrupt.
- (#) Enable the corresponding interrupt using the function
- TIM_ITConfig(TIMx, TIM_IT_Update).
- (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter.
- [..]
- (@) All other functions can be used seperatly to modify, if needed,
- a specific feature of the Timer.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitializes the TIMx peripheral registers to their default reset values.
- * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select the TIM peripheral.
- * @note TIM7 is applicable only for STM32F072 devices
- * @note TIM6 is not applivable for STM32F031 devices.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @retval None
- *
- */
-void TIM_DeInit(TIM_TypeDef* TIMx)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
-
- if (TIMx == TIM1)
- {
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE);
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE);
- }
- else if (TIMx == TIM2)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE);
- }
- else if (TIMx == TIM3)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE);
- }
- else if (TIMx == TIM6)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE);
- }
- else if (TIMx == TIM7)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE);
- }
- else if (TIMx == TIM14)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, DISABLE);
- }
- else if (TIMx == TIM15)
- {
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, ENABLE);
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM15, DISABLE);
- }
- else if (TIMx == TIM16)
- {
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, ENABLE);
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM16, DISABLE);
- }
- else
- {
- if (TIMx == TIM17)
- {
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, ENABLE);
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM17, DISABLE);
- }
- }
-
-}
-
-/**
- * @brief Initializes the TIMx Time Base Unit peripheral according to
- * the specified parameters in the TIM_TimeBaseInitStruct.
- * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select the TIM
- * peripheral.
- * @note TIM7 is applicable only for STM32F072 devices
- * @note TIM6 is not applivable for STM32F031 devices.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef
- * structure that contains the configuration information for
- * the specified TIM peripheral.
- * @retval None
- */
-void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
-{
- uint16_t tmpcr1 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode));
- assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision));
-
- tmpcr1 = TIMx->CR1;
-
- if((TIMx == TIM1) || (TIMx == TIM2) || (TIMx == TIM3))
- {
- /* Select the Counter Mode */
- tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS)));
- tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode;
- }
-
- if(TIMx != TIM6)
- {
- /* Set the clock division */
- tmpcr1 &= (uint16_t)(~((uint16_t)TIM_CR1_CKD));
- tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision;
- }
-
- TIMx->CR1 = tmpcr1;
-
- /* Set the Autoreload value */
- TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ;
-
- /* Set the Prescaler value */
- TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler;
-
- if ((TIMx == TIM1) || (TIMx == TIM15)|| (TIMx == TIM16) || (TIMx == TIM17))
- {
- /* Set the Repetition Counter value */
- TIMx->RCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter;
- }
-
- /* Generate an update event to reload the Prescaler and the Repetition counter
- values immediately */
- TIMx->EGR = TIM_PSCReloadMode_Immediate;
-}
-
-/**
- * @brief Fills each TIM_TimeBaseInitStruct member with its default value.
- * @param TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef structure
- * which will be initialized.
- * @retval None
- */
-void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
-{
- /* Set the default configuration */
- TIM_TimeBaseInitStruct->TIM_Period = 0xFFFFFFFF;
- TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000;
- TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1;
- TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up;
- TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000;
-}
-
-/**
- * @brief Configures the TIMx Prescaler.
- * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select the TIM peripheral.
- * @note TIM7 is applicable only for STM32F072 devices
- * @note TIM6 is not applivable for STM32F031 devices.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param Prescaler: specifies the Prescaler Register value
- * @param TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode
- * This parameter can be one of the following values:
- * @arg TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event.
- * @arg TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediatly.
- * @retval None
- */
-void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode));
-
- /* Set the Prescaler value */
- TIMx->PSC = Prescaler;
- /* Set or reset the UG Bit */
- TIMx->EGR = TIM_PSCReloadMode;
-}
-
-/**
- * @brief Specifies the TIMx Counter Mode to be used.
- * @param TIMx: where x can be 1, 2, or 3 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_CounterMode: specifies the Counter Mode to be used
- * This parameter can be one of the following values:
- * @arg TIM_CounterMode_Up: TIM Up Counting Mode
- * @arg TIM_CounterMode_Down: TIM Down Counting Mode
- * @arg TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1
- * @arg TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2
- * @arg TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3
- * @retval None
- */
-void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode)
-{
- uint16_t tmpcr1 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode));
-
- tmpcr1 = TIMx->CR1;
- /* Reset the CMS and DIR Bits */
- tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_CR1_DIR | TIM_CR1_CMS)));
- /* Set the Counter Mode */
- tmpcr1 |= TIM_CounterMode;
- /* Write to TIMx CR1 register */
- TIMx->CR1 = tmpcr1;
-}
-
-/**
- * @brief Sets the TIMx Counter Register value
- * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select the TIM
- * peripheral.
- * @note TIM7 is applicable only for STM32F072 devices
- * @note TIM6 is not applivable for STM32F031 devices.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param Counter: specifies the Counter register new value.
- * @retval None
- */
-void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
-
- /* Set the Counter Register value */
- TIMx->CNT = Counter;
-}
-
-/**
- * @brief Sets the TIMx Autoreload Register value
- * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select the TIM peripheral.
- * @note TIM7 is applicable only for STM32F072 devices
- * @note TIM6 is not applivable for STM32F031 devices.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param Autoreload: specifies the Autoreload register new value.
- * @retval None
- */
-void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
-
- /* Set the Autoreload Register value */
- TIMx->ARR = Autoreload;
-}
-
-/**
- * @brief Gets the TIMx Counter value.
- * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select the TIM
- * peripheral.
- * @note TIM7 is applicable only for STM32F072 devices
- * @note TIM6 is not applivable for STM32F031 devices.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @retval Counter Register value.
- */
-uint32_t TIM_GetCounter(TIM_TypeDef* TIMx)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
-
- /* Get the Counter Register value */
- return TIMx->CNT;
-}
-
-/**
- * @brief Gets the TIMx Prescaler value.
- * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select the TIM
- * peripheral.
- * @note TIM7 is applicable only for STM32F072 devices
- * @note TIM6 is not applivable for STM32F031 devices.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @retval Prescaler Register value.
- */
-uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
-
- /* Get the Prescaler Register value */
- return TIMx->PSC;
-}
-
-/**
- * @brief Enables or Disables the TIMx Update event.
- * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select the TIM
- * peripheral.
- * @note TIM7 is applicable only for STM32F072 devices
- * @note TIM6 is not applivable for STM32F031 devices.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param NewState: new state of the TIMx UDIS bit
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Set the Update Disable Bit */
- TIMx->CR1 |= TIM_CR1_UDIS;
- }
- else
- {
- /* Reset the Update Disable Bit */
- TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_UDIS);
- }
-}
-
-/**
- * @brief Configures the TIMx Update Request Interrupt source.
- * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select the TIM
- * peripheral.
- * @note TIM7 is applicable only for STM32F072 devices
- * @note TIM6 is not applivable for STM32F031 devices.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_UpdateSource: specifies the Update source.
- * This parameter can be one of the following values:
- * @arg TIM_UpdateSource_Regular: Source of update is the counter
- * overflow/underflow or the setting of UG bit, or an update
- * generation through the slave mode controller.
- * @arg TIM_UpdateSource_Global: Source of update is counter overflow/underflow.
- * @retval None
- */
-void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource));
-
- if (TIM_UpdateSource != TIM_UpdateSource_Global)
- {
- /* Set the URS Bit */
- TIMx->CR1 |= TIM_CR1_URS;
- }
- else
- {
- /* Reset the URS Bit */
- TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_URS);
- }
-}
-
-/**
- * @brief Enables or disables TIMx peripheral Preload register on ARR.
- * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select the TIM
- * peripheral.
- * @note TIM7 is applicable only for STM32F072 devices
- * @note TIM6 is not applivable for STM32F031 devices.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param NewState: new state of the TIMx peripheral Preload register
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Set the ARR Preload Bit */
- TIMx->CR1 |= TIM_CR1_ARPE;
- }
- else
- {
- /* Reset the ARR Preload Bit */
- TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_ARPE);
- }
-}
-
-/**
- * @brief Selects the TIMx's One Pulse Mode.
- * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 and 17 to select the TIM
- * peripheral.
- * @note TIM7 is applicable only for STM32F072 devices
- * @note TIM6 is not applivable for STM32F031 devices.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_OPMode: specifies the OPM Mode to be used.
- * This parameter can be one of the following values:
- * @arg TIM_OPMode_Single
- * @arg TIM_OPMode_Repetitive
- * @retval None
- */
-void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_TIM_OPM_MODE(TIM_OPMode));
-
- /* Reset the OPM Bit */
- TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_OPM);
- /* Configure the OPM Mode */
- TIMx->CR1 |= TIM_OPMode;
-}
-
-/**
- * @brief Sets the TIMx Clock Division value.
- * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 and 17 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_CKD: specifies the clock division value.
- * This parameter can be one of the following value:
- * @arg TIM_CKD_DIV1: TDTS = Tck_tim
- * @arg TIM_CKD_DIV2: TDTS = 2*Tck_tim
- * @arg TIM_CKD_DIV4: TDTS = 4*Tck_tim
- * @retval None
- */
-void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST4_PERIPH(TIMx));
- assert_param(IS_TIM_CKD_DIV(TIM_CKD));
-
- /* Reset the CKD Bits */
- TIMx->CR1 &= (uint16_t)~((uint16_t)TIM_CR1_CKD);
- /* Set the CKD value */
- TIMx->CR1 |= TIM_CKD;
-}
-
-/**
- * @brief Enables or disables the specified TIM peripheral.
- * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 and 17to select the TIMx
- * peripheral.
- * @note TIM7 is applicable only for STM32F072 devices
- * @note TIM6 is not applivable for STM32F031 devices.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param NewState: new state of the TIMx peripheral.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the TIM Counter */
- TIMx->CR1 |= TIM_CR1_CEN;
- }
- else
- {
- /* Disable the TIM Counter */
- TIMx->CR1 &= (uint16_t)(~((uint16_t)TIM_CR1_CEN));
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Group2 Advanced-control timers (TIM1) specific features
- * @brief Advanced-control timers (TIM1) specific features
- *
-@verbatim
- ===============================================================================
- ##### Advanced-control timers (TIM1) specific features #####
- ===============================================================================
-
- ===================================================================
- *** TIM Driver: how to use the Break feature ***
- ===================================================================
- [..] After configuring the Timer channel(s) in the appropriate Output Compare mode:
-
- (#) Fill the TIM_BDTRInitStruct with the desired parameters for the Timer
- Break Polarity, dead time, Lock level, the OSSI/OSSR State and the
- AOE(automatic output enable).
-
- (#) Call TIM_BDTRConfig(TIMx, &TIM_BDTRInitStruct) to configure the Timer
-
- (#) Enable the Main Output using TIM_CtrlPWMOutputs(TIM1, ENABLE)
-
- (#) Once the break even occurs, the Timer's output signals are put in reset
- state or in a known state (according to the configuration made in
- TIM_BDTRConfig() function).
-
-@endverbatim
- * @{
- */
-/**
- * @brief Configures the: Break feature, dead time, Lock level, OSSI/OSSR State
- * and the AOE(automatic output enable).
- * @param TIMx: where x can be 1, 15, 16 or 17 to select the TIM
- * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure that
- * contains the BDTR Register configuration information for the TIM peripheral.
- * @retval None
- */
-void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));
- assert_param(IS_TIM_OSSR_STATE(TIM_BDTRInitStruct->TIM_OSSRState));
- assert_param(IS_TIM_OSSI_STATE(TIM_BDTRInitStruct->TIM_OSSIState));
- assert_param(IS_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->TIM_LOCKLevel));
- assert_param(IS_TIM_BREAK_STATE(TIM_BDTRInitStruct->TIM_Break));
- assert_param(IS_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->TIM_BreakPolarity));
- assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->TIM_AutomaticOutput));
- /* Set the Lock level, the Break enable Bit and the Ploarity, the OSSR State,
- the OSSI State, the dead time value and the Automatic Output Enable Bit */
- TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState |
- TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime |
- TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity |
- TIM_BDTRInitStruct->TIM_AutomaticOutput;
-}
-
-/**
- * @brief Fills each TIM_BDTRInitStruct member with its default value.
- * @param TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure which
- * will be initialized.
- * @retval None
- */
-void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct)
-{
- /* Set the default configuration */
- TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable;
- TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable;
- TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF;
- TIM_BDTRInitStruct->TIM_DeadTime = 0x00;
- TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable;
- TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low;
- TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable;
-}
-
-/**
- * @brief Enables or disables the TIM peripheral Main Outputs.
- * @param TIMx: where x can be 1, 15, 16 or 17 to select the TIMx peripheral.
- * @param NewState: new state of the TIM peripheral Main Outputs.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the TIM Main Output */
- TIMx->BDTR |= TIM_BDTR_MOE;
- }
- else
- {
- /* Disable the TIM Main Output */
- TIMx->BDTR &= (uint16_t)(~((uint16_t)TIM_BDTR_MOE));
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Group3 Output Compare management functions
- * @brief Output Compare management functions
- *
-@verbatim
- ===============================================================================
- ##### Output Compare management functions #####
- ===============================================================================
- *** TIM Driver: how to use it in Output Compare Mode ***
- ===============================================================================
- [..] To use the Timer in Output Compare mode, the following steps are mandatory:
- (#) Enable TIM clock using
- RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function.
- (#) Configure the TIM pins by configuring the corresponding GPIO pins
- (#) Configure the Time base unit as described in the first part of this
- driver, if needed, else the Timer will run with the default
- configuration:
- (++) Autoreload value = 0xFFFF.
- (++) Prescaler value = 0x0000.
- (++) Counter mode = Up counting.
- (++) Clock Division = TIM_CKD_DIV1.
- (#) Fill the TIM_OCInitStruct with the desired parameters including:
- (++) The TIM Output Compare mode: TIM_OCMode.
- (++) TIM Output State: TIM_OutputState.
- (++) TIM Pulse value: TIM_Pulse.
- (++) TIM Output Compare Polarity : TIM_OCPolarity.
- (#) Call TIM_OCxInit(TIMx, &TIM_OCInitStruct) to configure the desired
- channel with the corresponding configuration.
- (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter.
- [..]
- (@) All other functions can be used separately to modify, if needed,
- a specific feature of the Timer.
- (@) In case of PWM mode, this function is mandatory:
- TIM_OCxPreloadConfig(TIMx, TIM_OCPreload_ENABLE).
- (@) If the corresponding interrupt or DMA request are needed, the user should:
- (#@) Enable the NVIC (or the DMA) to use the TIM interrupts (or DMA requests).
- (#@) Enable the corresponding interrupt (or DMA request) using the function
- TIM_ITConfig(TIMx, TIM_IT_CCx) (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx)).
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initializes the TIMx Channel1 according to the specified
- * parameters in the TIM_OCInitStruct.
- * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 and 17 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
- * that contains the configuration information for the specified TIM
- * peripheral.
- * @retval None
- */
-void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
-{
- uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST4_PERIPH(TIMx));
- assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
- assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
- assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
- /* Disable the Channel 1: Reset the CC1E Bit */
- TIMx->CCER &= (uint16_t)(~(uint16_t)TIM_CCER_CC1E);
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
- /* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
-
- /* Get the TIMx CCMR1 register value */
- tmpccmrx = TIMx->CCMR1;
-
- /* Reset the Output Compare Mode Bits */
- tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC1M));
- tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC1S));
-
- /* Select the Output Compare Mode */
- tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
-
- /* Reset the Output Polarity level */
- tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1P));
- /* Set the Output Compare Polarity */
- tmpccer |= TIM_OCInitStruct->TIM_OCPolarity;
-
- /* Set the Output State */
- tmpccer |= TIM_OCInitStruct->TIM_OutputState;
-
- if((TIMx == TIM1) || (TIMx == TIM15) || (TIMx == TIM16) || (TIMx == TIM17))
- {
- assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
- assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
- assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
- assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
-
- /* Reset the Output N Polarity level */
- tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1NP));
- /* Set the Output N Polarity */
- tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity;
-
- /* Reset the Output N State */
- tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC1NE));
- /* Set the Output N State */
- tmpccer |= TIM_OCInitStruct->TIM_OutputNState;
-
- /* Reset the Ouput Compare and Output Compare N IDLE State */
- tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS1));
- tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS1N));
-
- /* Set the Output Idle state */
- tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState;
- /* Set the Output N Idle state */
- tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState;
- }
- /* Write to TIMx CR2 */
- TIMx->CR2 = tmpcr2;
-
- /* Write to TIMx CCMR1 */
- TIMx->CCMR1 = tmpccmrx;
-
- /* Set the Capture Compare Register value */
- TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse;
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Initializes the TIMx Channel2 according to the specified
- * parameters in the TIM_OCInitStruct.
- * @param TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
- * that contains the configuration information for the specified TIM
- * peripheral.
- * @retval None
- */
-void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
-{
- uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));
- assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
- assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
- assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
- /* Disable the Channel 2: Reset the CC2E Bit */
- TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC2E));
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
- /* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
-
- /* Get the TIMx CCMR1 register value */
- tmpccmrx = TIMx->CCMR1;
-
- /* Reset the Output Compare mode and Capture/Compare selection Bits */
- tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_OC2M));
- tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S));
-
- /* Select the Output Compare Mode */
- tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);
-
- /* Reset the Output Polarity level */
- tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2P));
- /* Set the Output Compare Polarity */
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4);
-
- /* Set the Output State */
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4);
-
- if((TIMx == TIM1) || (TIMx == TIM15))
- {
- /* Check the parameters */
- assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
-
- /* Reset the Ouput Compare State */
- tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS2));
-
- /* Set the Output Idle state */
- tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2);
-
- if (TIMx == TIM1)
- {
- /* Check the parameters */
- assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
- assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
- assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
-
- /* Reset the Output N Polarity level */
- tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2NP));
- /* Set the Output N Polarity */
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4);
-
- /* Reset the Output N State */
- tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC2NE));
- /* Set the Output N State */
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4);
-
- /* Reset the Output Compare N IDLE State */
- tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS2N));
-
- /* Set the Output N Idle state */
- tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2);
- }
- }
- /* Write to TIMx CR2 */
- TIMx->CR2 = tmpcr2;
-
- /* Write to TIMx CCMR1 */
- TIMx->CCMR1 = tmpccmrx;
-
- /* Set the Capture Compare Register value */
- TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse;
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Initializes the TIMx Channel3 according to the specified
- * parameters in the TIM_OCInitStruct.
- * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
- * that contains the configuration information for the specified TIM
- * peripheral.
- * @retval None
- */
-void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
-{
- uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
- assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
- assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
- /* Disable the Channel 2: Reset the CC2E Bit */
- TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC3E));
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
- /* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
-
- /* Get the TIMx CCMR2 register value */
- tmpccmrx = TIMx->CCMR2;
-
- /* Reset the Output Compare mode and Capture/Compare selection Bits */
- tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC3M));
- tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_CC3S));
- /* Select the Output Compare Mode */
- tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
-
- /* Reset the Output Polarity level */
- tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3P));
- /* Set the Output Compare Polarity */
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8);
-
- /* Set the Output State */
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8);
-
- if(TIMx == TIM1)
- {
- assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
- assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
- assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
- assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
-
- /* Reset the Output N Polarity level */
- tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3NP));
- /* Set the Output N Polarity */
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8);
- /* Reset the Output N State */
- tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC3NE));
-
- /* Set the Output N State */
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8);
- /* Reset the Ouput Compare and Output Compare N IDLE State */
- tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS3));
- tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS3N));
- /* Set the Output Idle state */
- tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4);
- /* Set the Output N Idle state */
- tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4);
- }
- /* Write to TIMx CR2 */
- TIMx->CR2 = tmpcr2;
-
- /* Write to TIMx CCMR2 */
- TIMx->CCMR2 = tmpccmrx;
-
- /* Set the Capture Compare Register value */
- TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse;
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Initializes the TIMx Channel4 according to the specified
- * parameters in the TIM_OCInitStruct.
- * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure
- * that contains the configuration information for the specified TIM
- * peripheral.
- * @retval None
- */
-void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
-{
- uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
- assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
- assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));
- /* Disable the Channel 2: Reset the CC4E Bit */
- TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CCER_CC4E));
-
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
- /* Get the TIMx CR2 register value */
- tmpcr2 = TIMx->CR2;
-
- /* Get the TIMx CCMR2 register value */
- tmpccmrx = TIMx->CCMR2;
-
- /* Reset the Output Compare mode and Capture/Compare selection Bits */
- tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_OC4M));
- tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CCMR2_CC4S));
-
- /* Select the Output Compare Mode */
- tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);
-
- /* Reset the Output Polarity level */
- tmpccer &= (uint16_t)(~((uint16_t)TIM_CCER_CC4P));
- /* Set the Output Compare Polarity */
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12);
-
- /* Set the Output State */
- tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12);
-
- if(TIMx == TIM1)
- {
- assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
- /* Reset the Ouput Compare IDLE State */
- tmpcr2 &= (uint16_t)(~((uint16_t)TIM_CR2_OIS4));
- /* Set the Output Idle state */
- tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6);
- }
- /* Write to TIMx CR2 */
- TIMx->CR2 = tmpcr2;
-
- /* Write to TIMx CCMR2 */
- TIMx->CCMR2 = tmpccmrx;
-
- /* Set the Capture Compare Register value */
- TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse;
-
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Fills each TIM_OCInitStruct member with its default value.
- * @param TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure which will
- * be initialized.
- * @retval None
- */
-void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct)
-{
- /* Set the default configuration */
- TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing;
- TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable;
- TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable;
- TIM_OCInitStruct->TIM_Pulse = 0x0000000;
- TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High;
- TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High;
- TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset;
- TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset;
-}
-
-/**
- * @brief Selects the TIM Output Compare Mode.
- * @note This function disables the selected channel before changing the Output
- * Compare Mode.
- * User has to enable this channel using TIM_CCxCmd and TIM_CCxNCmd functions.
- * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_Channel: specifies the TIM Channel
- * This parameter can be one of the following values:
- * @arg TIM_Channel_1: TIM Channel 1
- * @arg TIM_Channel_2: TIM Channel 2
- * @arg TIM_Channel_3: TIM Channel 3
- * @arg TIM_Channel_4: TIM Channel 4
- * @param TIM_OCMode: specifies the TIM Output Compare Mode.
- * This parameter can be one of the following values:
- * @arg TIM_OCMode_Timing
- * @arg TIM_OCMode_Active
- * @arg TIM_OCMode_Toggle
- * @arg TIM_OCMode_PWM1
- * @arg TIM_OCMode_PWM2
- * @arg TIM_ForcedAction_Active
- * @arg TIM_ForcedAction_InActive
- * @retval None
- */
-void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode)
-{
- uint32_t tmp = 0;
- uint16_t tmp1 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST4_PERIPH(TIMx));
- assert_param(IS_TIM_OCM(TIM_OCMode));
-
- tmp = (uint32_t) TIMx;
- tmp += CCMR_OFFSET;
-
- tmp1 = CCER_CCE_SET << (uint16_t)TIM_Channel;
-
- /* Disable the Channel: Reset the CCxE Bit */
- TIMx->CCER &= (uint16_t) ~tmp1;
-
- if((TIM_Channel == TIM_Channel_1) ||(TIM_Channel == TIM_Channel_3))
- {
- tmp += (TIM_Channel>>1);
-
- /* Reset the OCxM bits in the CCMRx register */
- *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC1M);
-
- /* Configure the OCxM bits in the CCMRx register */
- *(__IO uint32_t *) tmp |= TIM_OCMode;
- }
- else
- {
- tmp += (uint16_t)(TIM_Channel - (uint16_t)4)>> (uint16_t)1;
-
- /* Reset the OCxM bits in the CCMRx register */
- *(__IO uint32_t *) tmp &= (uint32_t)~((uint32_t)TIM_CCMR1_OC2M);
-
- /* Configure the OCxM bits in the CCMRx register */
- *(__IO uint32_t *) tmp |= (uint16_t)(TIM_OCMode << 8);
- }
-}
-
-/**
- * @brief Sets the TIMx Capture Compare1 Register value
- * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param Compare1: specifies the Capture Compare1 register new value.
- * @retval None
- */
-void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST4_PERIPH(TIMx));
-
- /* Set the Capture Compare1 Register value */
- TIMx->CCR1 = Compare1;
-}
-
-/**
- * @brief Sets the TIMx Capture Compare2 Register value
- * @param TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param Compare2: specifies the Capture Compare2 register new value.
- * @retval None
- */
-void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));
-
- /* Set the Capture Compare2 Register value */
- TIMx->CCR2 = Compare2;
-}
-
-/**
- * @brief Sets the TIMx Capture Compare3 Register value
- * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
- * @param Compare3: specifies the Capture Compare3 register new value.
- * @retval None
- */
-void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
-
- /* Set the Capture Compare3 Register value */
- TIMx->CCR3 = Compare3;
-}
-
-/**
- * @brief Sets the TIMx Capture Compare4 Register value
- * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param Compare4: specifies the Capture Compare4 register new value.
- * @retval None
- */
-void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
-
- /* Set the Capture Compare4 Register value */
- TIMx->CCR4 = Compare4;
-}
-
-/**
- * @brief Forces the TIMx output 1 waveform to active or inactive level.
- * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
- * This parameter can be one of the following values:
- * @arg TIM_ForcedAction_Active: Force active level on OC1REF
- * @arg TIM_ForcedAction_InActive: Force inactive level on OC1REF.
- * @retval None
- */
-void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
-{
- uint16_t tmpccmr1 = 0;
- /* Check the parameters */
- assert_param(IS_TIM_LIST4_PERIPH(TIMx));
- assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
- tmpccmr1 = TIMx->CCMR1;
- /* Reset the OC1M Bits */
- tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1M);
- /* Configure The Forced output Mode */
- tmpccmr1 |= TIM_ForcedAction;
- /* Write to TIMx CCMR1 register */
- TIMx->CCMR1 = tmpccmr1;
-}
-
-/**
- * @brief Forces the TIMx output 2 waveform to active or inactive level.
- * @param TIMx: where x can be 1, 2, 3, or 15 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
- * This parameter can be one of the following values:
- * @arg TIM_ForcedAction_Active: Force active level on OC2REF
- * @arg TIM_ForcedAction_InActive: Force inactive level on OC2REF.
- * @retval None
- */
-void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
-{
- uint16_t tmpccmr1 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));
- assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
-
- tmpccmr1 = TIMx->CCMR1;
- /* Reset the OC2M Bits */
- tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2M);
- /* Configure The Forced output Mode */
- tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8);
- /* Write to TIMx CCMR1 register */
- TIMx->CCMR1 = tmpccmr1;
-}
-
-/**
- * @brief Forces the TIMx output 3 waveform to active or inactive level.
- * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
- * This parameter can be one of the following values:
- * @arg TIM_ForcedAction_Active: Force active level on OC3REF
- * @arg TIM_ForcedAction_InActive: Force inactive level on OC3REF.
- * @retval None
- */
-void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
-{
- uint16_t tmpccmr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
-
- tmpccmr2 = TIMx->CCMR2;
- /* Reset the OC1M Bits */
- tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3M);
- /* Configure The Forced output Mode */
- tmpccmr2 |= TIM_ForcedAction;
- /* Write to TIMx CCMR2 register */
- TIMx->CCMR2 = tmpccmr2;
-}
-
-/**
- * @brief Forces the TIMx output 4 waveform to active or inactive level.
- * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
- * This parameter can be one of the following values:
- * @arg TIM_ForcedAction_Active: Force active level on OC4REF
- * @arg TIM_ForcedAction_InActive: Force inactive level on OC4REF.
- * @retval None
- */
-void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
-{
- uint16_t tmpccmr2 = 0;
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
-
- tmpccmr2 = TIMx->CCMR2;
- /* Reset the OC2M Bits */
- tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4M);
- /* Configure The Forced output Mode */
- tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8);
- /* Write to TIMx CCMR2 register */
- TIMx->CCMR2 = tmpccmr2;
-}
-
-/**
- * @brief Sets or Resets the TIM peripheral Capture Compare Preload Control bit.
- * @param TIMx: where x can be 1, 2, 3 or 15 to select the TIMx peripheral
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param NewState: new state of the Capture Compare Preload Control bit
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Set the CCPC Bit */
- TIMx->CR2 |= TIM_CR2_CCPC;
- }
- else
- {
- /* Reset the CCPC Bit */
- TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCPC);
- }
-}
-
-
-/**
- * @brief Enables or disables the TIMx peripheral Preload register on CCR1.
- * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 and 17 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_OCPreload: new state of the TIMx peripheral Preload register
- * This parameter can be one of the following values:
- * @arg TIM_OCPreload_Enable
- * @arg TIM_OCPreload_Disable
- * @retval None
- */
-void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
-{
- uint16_t tmpccmr1 = 0;
- /* Check the parameters */
- assert_param(IS_TIM_LIST4_PERIPH(TIMx));
- assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
-
- tmpccmr1 = TIMx->CCMR1;
- /* Reset the OC1PE Bit */
- tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1PE);
- /* Enable or Disable the Output Compare Preload feature */
- tmpccmr1 |= TIM_OCPreload;
- /* Write to TIMx CCMR1 register */
- TIMx->CCMR1 = tmpccmr1;
-}
-
-/**
- * @brief Enables or disables the TIMx peripheral Preload register on CCR2.
- * @param TIMx: where x can be 1, 2, 3 and 15 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_OCPreload: new state of the TIMx peripheral Preload register
- * This parameter can be one of the following values:
- * @arg TIM_OCPreload_Enable
- * @arg TIM_OCPreload_Disable
- * @retval None
- */
-void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
-{
- uint16_t tmpccmr1 = 0;
- /* Check the parameters */
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));
- assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
-
- tmpccmr1 = TIMx->CCMR1;
- /* Reset the OC2PE Bit */
- tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2PE);
- /* Enable or Disable the Output Compare Preload feature */
- tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8);
- /* Write to TIMx CCMR1 register */
- TIMx->CCMR1 = tmpccmr1;
-}
-
-/**
- * @brief Enables or disables the TIMx peripheral Preload register on CCR3.
- * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_OCPreload: new state of the TIMx peripheral Preload register
- * This parameter can be one of the following values:
- * @arg TIM_OCPreload_Enable
- * @arg TIM_OCPreload_Disable
- * @retval None
- */
-void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
-{
- uint16_t tmpccmr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
-
- tmpccmr2 = TIMx->CCMR2;
- /* Reset the OC3PE Bit */
- tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3PE);
- /* Enable or Disable the Output Compare Preload feature */
- tmpccmr2 |= TIM_OCPreload;
- /* Write to TIMx CCMR2 register */
- TIMx->CCMR2 = tmpccmr2;
-}
-
-/**
- * @brief Enables or disables the TIMx peripheral Preload register on CCR4.
- * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_OCPreload: new state of the TIMx peripheral Preload register
- * This parameter can be one of the following values:
- * @arg TIM_OCPreload_Enable
- * @arg TIM_OCPreload_Disable
- * @retval None
- */
-void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
-{
- uint16_t tmpccmr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
-
- tmpccmr2 = TIMx->CCMR2;
- /* Reset the OC4PE Bit */
- tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4PE);
- /* Enable or Disable the Output Compare Preload feature */
- tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8);
- /* Write to TIMx CCMR2 register */
- TIMx->CCMR2 = tmpccmr2;
-}
-
-/**
- * @brief Configures the TIMx Output Compare 1 Fast feature.
- * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
- * This parameter can be one of the following values:
- * @arg TIM_OCFast_Enable: TIM output compare fast enable
- * @arg TIM_OCFast_Disable: TIM output compare fast disable
- * @retval None
- */
-void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
-{
- uint16_t tmpccmr1 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST4_PERIPH(TIMx));
- assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
-
- /* Get the TIMx CCMR1 register value */
- tmpccmr1 = TIMx->CCMR1;
- /* Reset the OC1FE Bit */
- tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1FE);
- /* Enable or Disable the Output Compare Fast Bit */
- tmpccmr1 |= TIM_OCFast;
- /* Write to TIMx CCMR1 */
- TIMx->CCMR1 = tmpccmr1;
-}
-
-/**
- * @brief Configures the TIMx Output Compare 2 Fast feature.
- * @param TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
- * This parameter can be one of the following values:
- * @arg TIM_OCFast_Enable: TIM output compare fast enable
- * @arg TIM_OCFast_Disable: TIM output compare fast disable
- * @retval None
- */
-void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
-{
- uint16_t tmpccmr1 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));
- assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
-
- /* Get the TIMx CCMR1 register value */
- tmpccmr1 = TIMx->CCMR1;
- /* Reset the OC2FE Bit */
- tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2FE);
- /* Enable or Disable the Output Compare Fast Bit */
- tmpccmr1 |= (uint16_t)(TIM_OCFast << 8);
- /* Write to TIMx CCMR1 */
- TIMx->CCMR1 = tmpccmr1;
-}
-
-/**
- * @brief Configures the TIMx Output Compare 3 Fast feature.
- * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
- * This parameter can be one of the following values:
- * @arg TIM_OCFast_Enable: TIM output compare fast enable
- * @arg TIM_OCFast_Disable: TIM output compare fast disable
- * @retval None
- */
-void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
-{
- uint16_t tmpccmr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
-
- /* Get the TIMx CCMR2 register value */
- tmpccmr2 = TIMx->CCMR2;
- /* Reset the OC3FE Bit */
- tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3FE);
- /* Enable or Disable the Output Compare Fast Bit */
- tmpccmr2 |= TIM_OCFast;
- /* Write to TIMx CCMR2 */
- TIMx->CCMR2 = tmpccmr2;
-}
-
-/**
- * @brief Configures the TIMx Output Compare 4 Fast feature.
- * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_OCFast: new state of the Output Compare Fast Enable Bit.
- * This parameter can be one of the following values:
- * @arg TIM_OCFast_Enable: TIM output compare fast enable
- * @arg TIM_OCFast_Disable: TIM output compare fast disable
- * @retval None
- */
-void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
-{
- uint16_t tmpccmr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
-
- /* Get the TIMx CCMR2 register value */
- tmpccmr2 = TIMx->CCMR2;
- /* Reset the OC4FE Bit */
- tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4FE);
- /* Enable or Disable the Output Compare Fast Bit */
- tmpccmr2 |= (uint16_t)(TIM_OCFast << 8);
- /* Write to TIMx CCMR2 */
- TIMx->CCMR2 = tmpccmr2;
-}
-
-/**
- * @brief Clears or safeguards the OCREF1 signal on an external event
- * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
- * This parameter can be one of the following values:
- * @arg TIM_OCClear_Enable: TIM Output clear enable
- * @arg TIM_OCClear_Disable: TIM Output clear disable
- * @retval None
- */
-void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
-{
- uint16_t tmpccmr1 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST4_PERIPH(TIMx));
- assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
-
- tmpccmr1 = TIMx->CCMR1;
- /* Reset the OC1CE Bit */
- tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC1CE);
- /* Enable or Disable the Output Compare Clear Bit */
- tmpccmr1 |= TIM_OCClear;
- /* Write to TIMx CCMR1 register */
- TIMx->CCMR1 = tmpccmr1;
-}
-
-/**
- * @brief Clears or safeguards the OCREF2 signal on an external event
- * @param TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
- * This parameter can be one of the following values:
- * @arg TIM_OCClear_Enable: TIM Output clear enable
- * @arg TIM_OCClear_Disable: TIM Output clear disable
- * @retval None
- */
-void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
-{
- uint16_t tmpccmr1 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));
- assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
-
- tmpccmr1 = TIMx->CCMR1;
- /* Reset the OC2CE Bit */
- tmpccmr1 &= (uint16_t)~((uint16_t)TIM_CCMR1_OC2CE);
- /* Enable or Disable the Output Compare Clear Bit */
- tmpccmr1 |= (uint16_t)(TIM_OCClear << 8);
- /* Write to TIMx CCMR1 register */
- TIMx->CCMR1 = tmpccmr1;
-}
-
-/**
- * @brief Clears or safeguards the OCREF3 signal on an external event
- * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
- * This parameter can be one of the following values:
- * @arg TIM_OCClear_Enable: TIM Output clear enable
- * @arg TIM_OCClear_Disable: TIM Output clear disable
- * @retval None
- */
-void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
-{
- uint16_t tmpccmr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
-
- tmpccmr2 = TIMx->CCMR2;
- /* Reset the OC3CE Bit */
- tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC3CE);
- /* Enable or Disable the Output Compare Clear Bit */
- tmpccmr2 |= TIM_OCClear;
- /* Write to TIMx CCMR2 register */
- TIMx->CCMR2 = tmpccmr2;
-}
-
-/**
- * @brief Clears or safeguards the OCREF4 signal on an external event
- * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_OCClear: new state of the Output Compare Clear Enable Bit.
- * This parameter can be one of the following values:
- * @arg TIM_OCClear_Enable: TIM Output clear enable
- * @arg TIM_OCClear_Disable: TIM Output clear disable
- * @retval None
- */
-void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
-{
- uint16_t tmpccmr2 = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
-
- tmpccmr2 = TIMx->CCMR2;
- /* Reset the OC4CE Bit */
- tmpccmr2 &= (uint16_t)~((uint16_t)TIM_CCMR2_OC4CE);
- /* Enable or Disable the Output Compare Clear Bit */
- tmpccmr2 |= (uint16_t)(TIM_OCClear << 8);
- /* Write to TIMx CCMR2 register */
- TIMx->CCMR2 = tmpccmr2;
-}
-
-/**
- * @brief Configures the TIMx channel 1 polarity.
- * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_OCPolarity: specifies the OC1 Polarity
- * This parmeter can be one of the following values:
- * @arg TIM_OCPolarity_High: Output Compare active high
- * @arg TIM_OCPolarity_Low: Output Compare active low
- * @retval None
- */
-void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
-{
- uint16_t tmpccer = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST4_PERIPH(TIMx));
- assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
-
- tmpccer = TIMx->CCER;
- /* Set or Reset the CC1P Bit */
- tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC1P);
- tmpccer |= TIM_OCPolarity;
- /* Write to TIMx CCER register */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configures the TIMx Channel 1N polarity.
- * @param TIMx: where x can be 1, 15, 16 or 17 to select the TIM peripheral.
- * @param TIM_OCNPolarity: specifies the OC1N Polarity
- * This parmeter can be one of the following values:
- * @arg TIM_OCNPolarity_High: Output Compare active high
- * @arg TIM_OCNPolarity_Low: Output Compare active low
- * @retval None
- */
-void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
-{
- uint16_t tmpccer = 0;
- /* Check the parameters */
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));
- assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
-
- tmpccer = TIMx->CCER;
- /* Set or Reset the CC1NP Bit */
- tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC1NP);
- tmpccer |= TIM_OCNPolarity;
- /* Write to TIMx CCER register */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configures the TIMx channel 2 polarity.
- * @param TIMx: where x can be 1, 2, 3, or 15 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_OCPolarity: specifies the OC2 Polarity
- * This parmeter can be one of the following values:
- * @arg TIM_OCPolarity_High: Output Compare active high
- * @arg TIM_OCPolarity_Low: Output Compare active low
- * @retval None
- */
-void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
-{
- uint16_t tmpccer = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));
- assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
-
- tmpccer = TIMx->CCER;
- /* Set or Reset the CC2P Bit */
- tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC2P);
- tmpccer |= (uint16_t)(TIM_OCPolarity << 4);
- /* Write to TIMx CCER register */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configures the TIMx Channel 2N polarity.
- * @param TIMx: where x can be 1 to select the TIM peripheral.
- * @param TIM_OCNPolarity: specifies the OC2N Polarity
- * This parmeter can be one of the following values:
- * @arg TIM_OCNPolarity_High: Output Compare active high
- * @arg TIM_OCNPolarity_Low: Output Compare active low
- * @retval None
- */
-void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
-{
- uint16_t tmpccer = 0;
- /* Check the parameters */
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));
- assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
-
- tmpccer = TIMx->CCER;
- /* Set or Reset the CC2NP Bit */
- tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC2NP);
- tmpccer |= (uint16_t)(TIM_OCNPolarity << 4);
- /* Write to TIMx CCER register */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configures the TIMx channel 3 polarity.
- * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_OCPolarity: specifies the OC3 Polarity
- * This parmeter can be one of the following values:
- * @arg TIM_OCPolarity_High: Output Compare active high
- * @arg TIM_OCPolarity_Low: Output Compare active low
- * @retval None
- */
-void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
-{
- uint16_t tmpccer = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
-
- tmpccer = TIMx->CCER;
- /* Set or Reset the CC3P Bit */
- tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC3P);
- tmpccer |= (uint16_t)(TIM_OCPolarity << 8);
- /* Write to TIMx CCER register */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configures the TIMx Channel 3N polarity.
- * @param TIMx: where x can be 1 to select the TIM peripheral.
- * @param TIM_OCNPolarity: specifies the OC3N Polarity
- * This parmeter can be one of the following values:
- * @arg TIM_OCNPolarity_High: Output Compare active high
- * @arg TIM_OCNPolarity_Low: Output Compare active low
- * @retval None
- */
-void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
-{
- uint16_t tmpccer = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST1_PERIPH(TIMx));
- assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
-
- tmpccer = TIMx->CCER;
- /* Set or Reset the CC3NP Bit */
- tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC3NP);
- tmpccer |= (uint16_t)(TIM_OCNPolarity << 8);
- /* Write to TIMx CCER register */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configures the TIMx channel 4 polarity.
- * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_OCPolarity: specifies the OC4 Polarity
- * This parmeter can be one of the following values:
- * @arg TIM_OCPolarity_High: Output Compare active high
- * @arg TIM_OCPolarity_Low: Output Compare active low
- * @retval None
- */
-void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
-{
- uint16_t tmpccer = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
-
- tmpccer = TIMx->CCER;
- /* Set or Reset the CC4P Bit */
- tmpccer &= (uint16_t)~((uint16_t)TIM_CCER_CC4P);
- tmpccer |= (uint16_t)(TIM_OCPolarity << 12);
- /* Write to TIMx CCER register */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Selects the OCReference Clear source.
- * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_OCReferenceClear: specifies the OCReference Clear source.
- * This parameter can be one of the following values:
- * @arg TIM_OCReferenceClear_ETRF: The internal OCreference clear input is connected to ETRF.
- * @arg TIM_OCReferenceClear_OCREFCLR: The internal OCreference clear input is connected to OCREF_CLR input.
- * @retval None
- */
-void TIM_SelectOCREFClear(TIM_TypeDef* TIMx, uint16_t TIM_OCReferenceClear)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(TIM_OCREFERENCECECLEAR_SOURCE(TIM_OCReferenceClear));
-
- /* Set the TIM_OCReferenceClear source */
- TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_OCCS);
- TIMx->SMCR |= TIM_OCReferenceClear;
-}
-
-/**
- * @brief Enables or disables the TIM Capture Compare Channel x.
- * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_Channel: specifies the TIM Channel
- * This parameter can be one of the following values:
- * @arg TIM_Channel_1: TIM Channel 1
- * @arg TIM_Channel_2: TIM Channel 2
- * @arg TIM_Channel_3: TIM Channel 3
- * @arg TIM_Channel_4: TIM Channel 4
- * @param TIM_CCx: specifies the TIM Channel CCxE bit new state.
- * This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable.
- * @retval None
- */
-void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx)
-{
- uint16_t tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST4_PERIPH(TIMx));
- assert_param(IS_TIM_CCX(TIM_CCx));
-
- tmp = CCER_CCE_SET << TIM_Channel;
-
- /* Reset the CCxE Bit */
- TIMx->CCER &= (uint16_t)~ tmp;
-
- /* Set or reset the CCxE Bit */
- TIMx->CCER |= (uint16_t)(TIM_CCx << TIM_Channel);
-}
-
-/**
- * @brief Enables or disables the TIM Capture Compare Channel xN.
- * @param TIMx: where x can be 1, 15, 16 or 17 to select the TIM peripheral.
- * @param TIM_Channel: specifies the TIM Channel
- * This parmeter can be one of the following values:
- * @arg TIM_Channel_1: TIM Channel 1
- * @arg TIM_Channel_2: TIM Channel 2
- * @arg TIM_Channel_3: TIM Channel 3
- * @param TIM_CCxN: specifies the TIM Channel CCxNE bit new state.
- * This parameter can be: TIM_CCxN_Enable or TIM_CCxN_Disable.
- * @retval None
- */
-void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN)
-{
- uint16_t tmp = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));
- assert_param(IS_TIM_COMPLEMENTARY_CHANNEL(TIM_Channel));
- assert_param(IS_TIM_CCXN(TIM_CCxN));
-
- tmp = CCER_CCNE_SET << TIM_Channel;
-
- /* Reset the CCxNE Bit */
- TIMx->CCER &= (uint16_t) ~tmp;
-
- /* Set or reset the CCxNE Bit */
- TIMx->CCER |= (uint16_t)(TIM_CCxN << TIM_Channel);
-}
-
-/**
- * @brief Selects the TIM peripheral Commutation event.
- * @param TIMx: where x can be 1, 15, 16 or 17 to select the TIMx peripheral
- * @param NewState: new state of the Commutation event.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST2_PERIPH(TIMx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Set the COM Bit */
- TIMx->CR2 |= TIM_CR2_CCUS;
- }
- else
- {
- /* Reset the COM Bit */
- TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCUS);
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Group4 Input Capture management functions
- * @brief Input Capture management functions
- *
-@verbatim
- ===============================================================================
- ##### Input Capture management functions #####
- ===============================================================================
-
- *** TIM Driver: how to use it in Input Capture Mode ***
- ===============================================================================
- [..] To use the Timer in Input Capture mode, the following steps are mandatory:
- (#) Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE)
- function.
- (#) Configure the TIM pins by configuring the corresponding GPIO pins.
- (#) Configure the Time base unit as described in the first part of this
- driver, if needed, else the Timer will run with the default configuration:
- (++) Autoreload value = 0xFFFF.
- (++) Prescaler value = 0x0000.
- (++) Counter mode = Up counting.
- (++) Clock Division = TIM_CKD_DIV1.
- (#) Fill the TIM_ICInitStruct with the desired parameters including:
- (++) TIM Channel: TIM_Channel.
- (++) TIM Input Capture polarity: TIM_ICPolarity.
- (++) TIM Input Capture selection: TIM_ICSelection.
- (++) TIM Input Capture Prescaler: TIM_ICPrescaler.
- (++) TIM Input CApture filter value: TIM_ICFilter.
- (#) Call TIM_ICInit(TIMx, &TIM_ICInitStruct) to configure the desired
- channel with the corresponding configuration and to measure only
- frequency or duty cycle of the input signal,or, Call
- TIM_PWMIConfig(TIMx, &TIM_ICInitStruct) to configure the desired
- channels with the corresponding configuration and to measure the
- frequency and the duty cycle of the input signal.
- (#) Enable the NVIC or the DMA to read the measured frequency.
- (#) Enable the corresponding interrupt (or DMA request) to read
- the Captured value, using the function TIM_ITConfig(TIMx, TIM_IT_CCx)
- (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx)).
- (#) Call the TIM_Cmd(ENABLE) function to enable the TIM counter.
- (#) Use TIM_GetCapturex(TIMx); to read the captured value.
- [..]
- (@) All other functions can be used separately to modify, if needed,
- a specific feature of the Timer.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Initializes the TIM peripheral according to the specified
- * parameters in the TIM_ICInitStruct.
- * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure
- * that contains the configuration information for the specified TIM
- * peripheral.
- * @retval None
- */
-void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST4_PERIPH(TIMx));
- assert_param(IS_TIM_CHANNEL(TIM_ICInitStruct->TIM_Channel));
- assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection));
- assert_param(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler));
- assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter));
- assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity));
-
- if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
- {
- assert_param(IS_TIM_LIST4_PERIPH(TIMx));
- /* TI1 Configuration */
- TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
- TIM_ICInitStruct->TIM_ICSelection,
- TIM_ICInitStruct->TIM_ICFilter);
- /* Set the Input Capture Prescaler value */
- TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
- }
- else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2)
- {
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));
- /* TI2 Configuration */
- TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
- TIM_ICInitStruct->TIM_ICSelection,
- TIM_ICInitStruct->TIM_ICFilter);
- /* Set the Input Capture Prescaler value */
- TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
- }
- else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3)
- {
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- /* TI3 Configuration */
- TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
- TIM_ICInitStruct->TIM_ICSelection,
- TIM_ICInitStruct->TIM_ICFilter);
- /* Set the Input Capture Prescaler value */
- TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
- }
- else
- {
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- /* TI4 Configuration */
- TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
- TIM_ICInitStruct->TIM_ICSelection,
- TIM_ICInitStruct->TIM_ICFilter);
- /* Set the Input Capture Prescaler value */
- TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
- }
-}
-
-/**
- * @brief Fills each TIM_ICInitStruct member with its default value.
- * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure which will
- * be initialized.
- * @retval None
- */
-void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct)
-{
- /* Set the default configuration */
- TIM_ICInitStruct->TIM_Channel = TIM_Channel_1;
- TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising;
- TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI;
- TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1;
- TIM_ICInitStruct->TIM_ICFilter = 0x00;
-}
-
-/**
- * @brief Configures the TIM peripheral according to the specified
- * parameters in the TIM_ICInitStruct to measure an external PWM signal.
- * @param TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure
- * that contains the configuration information for the specified TIM
- * peripheral.
- * @retval None
- */
-void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
-{
- uint16_t icoppositepolarity = TIM_ICPolarity_Rising;
- uint16_t icoppositeselection = TIM_ICSelection_DirectTI;
- /* Check the parameters */
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));
- /* Select the Opposite Input Polarity */
- if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising)
- {
- icoppositepolarity = TIM_ICPolarity_Falling;
- }
- else
- {
- icoppositepolarity = TIM_ICPolarity_Rising;
- }
- /* Select the Opposite Input */
- if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI)
- {
- icoppositeselection = TIM_ICSelection_IndirectTI;
- }
- else
- {
- icoppositeselection = TIM_ICSelection_DirectTI;
- }
- if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
- {
- /* TI1 Configuration */
- TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
- TIM_ICInitStruct->TIM_ICFilter);
- /* Set the Input Capture Prescaler value */
- TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
- /* TI2 Configuration */
- TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
- /* Set the Input Capture Prescaler value */
- TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
- }
- else
- {
- /* TI2 Configuration */
- TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
- TIM_ICInitStruct->TIM_ICFilter);
- /* Set the Input Capture Prescaler value */
- TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
- /* TI1 Configuration */
- TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
- /* Set the Input Capture Prescaler value */
- TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
- }
-}
-
-/**
- * @brief Gets the TIMx Input Capture 1 value.
- * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @retval Capture Compare 1 Register value.
- */
-uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST4_PERIPH(TIMx));
-
- /* Get the Capture 1 Register value */
- return TIMx->CCR1;
-}
-
-/**
- * @brief Gets the TIMx Input Capture 2 value.
- * @param TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral.
- * @retval Capture Compare 2 Register value.
- */
-uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));
-
- /* Get the Capture 2 Register value */
- return TIMx->CCR2;
-}
-
-/**
- * @brief Gets the TIMx Input Capture 3 value.
- * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @retval Capture Compare 3 Register value.
- */
-uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
-
- /* Get the Capture 3 Register value */
- return TIMx->CCR3;
-}
-
-/**
- * @brief Gets the TIMx Input Capture 4 value.
- * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @retval Capture Compare 4 Register value.
- */
-uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
-
- /* Get the Capture 4 Register value */
- return TIMx->CCR4;
-}
-
-/**
- * @brief Sets the TIMx Input Capture 1 prescaler.
- * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_ICPSC: specifies the Input Capture1 prescaler new value.
- * This parameter can be one of the following values:
- * @arg TIM_ICPSC_DIV1: no prescaler
- * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
- * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
- * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
- * @retval None
- */
-void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST4_PERIPH(TIMx));
- assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
-
- /* Reset the IC1PSC Bits */
- TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC1PSC);
- /* Set the IC1PSC value */
- TIMx->CCMR1 |= TIM_ICPSC;
-}
-
-/**
- * @brief Sets the TIMx Input Capture 2 prescaler.
- * @param TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_ICPSC: specifies the Input Capture2 prescaler new value.
- * This parameter can be one of the following values:
- * @arg TIM_ICPSC_DIV1: no prescaler
- * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
- * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
- * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
- * @retval None
- */
-void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));
- assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
-
- /* Reset the IC2PSC Bits */
- TIMx->CCMR1 &= (uint16_t)~((uint16_t)TIM_CCMR1_IC2PSC);
- /* Set the IC2PSC value */
- TIMx->CCMR1 |= (uint16_t)(TIM_ICPSC << 8);
-}
-
-/**
- * @brief Sets the TIMx Input Capture 3 prescaler.
- * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_ICPSC: specifies the Input Capture3 prescaler new value.
- * This parameter can be one of the following values:
- * @arg TIM_ICPSC_DIV1: no prescaler
- * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
- * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
- * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
- * @retval None
- */
-void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
-
- /* Reset the IC3PSC Bits */
- TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC3PSC);
- /* Set the IC3PSC value */
- TIMx->CCMR2 |= TIM_ICPSC;
-}
-
-/**
- * @brief Sets the TIMx Input Capture 4 prescaler.
- * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_ICPSC: specifies the Input Capture4 prescaler new value.
- * This parameter can be one of the following values:
- * @arg TIM_ICPSC_DIV1: no prescaler
- * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
- * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
- * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
- * @retval None
- */
-void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
-
- /* Reset the IC4PSC Bits */
- TIMx->CCMR2 &= (uint16_t)~((uint16_t)TIM_CCMR2_IC4PSC);
- /* Set the IC4PSC value */
- TIMx->CCMR2 |= (uint16_t)(TIM_ICPSC << 8);
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Group5 Interrupts DMA and flags management functions
- * @brief Interrupts, DMA and flags management functions
- *
-@verbatim
- ===============================================================================
- ##### Interrupts, DMA and flags management functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the specified TIM interrupts.
- * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 or 17 to select the TIMx peripheral.
- * @note TIM7 is applicable only for STM32F072 devices
- * @note TIM6 is not applivable for STM32F031 devices.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_IT: specifies the TIM interrupts sources to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg TIM_IT_Update: TIM update Interrupt source
- * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
- * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
- * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
- * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
- * @arg TIM_IT_COM: TIM Commutation Interrupt source
- * @arg TIM_IT_Trigger: TIM Trigger Interrupt source
- * @arg TIM_IT_Break: TIM Break Interrupt source
- *
- * @note TIM6 and TIM7 can only generate an update interrupt.
- * @note TIM15 can have only TIM_IT_Update, TIM_IT_CC1,TIM_IT_CC2 or TIM_IT_Trigger.
- * @note TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1.
- * @note TIM_IT_Break is used only with TIM1 and TIM15.
- * @note TIM_IT_COM is used only with TIM1, TIM15, TIM16 and TIM17.
- *
- * @param NewState: new state of the TIM interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_TIM_IT(TIM_IT));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the Interrupt sources */
- TIMx->DIER |= TIM_IT;
- }
- else
- {
- /* Disable the Interrupt sources */
- TIMx->DIER &= (uint16_t)~TIM_IT;
- }
-}
-
-/**
- * @brief Configures the TIMx event to be generate by software.
- * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 or 17 to select the
- * TIM peripheral.
- * @note TIM7 is applicable only for STM32F072 devices
- * @note TIM6 is not applivable for STM32F031 devices.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_EventSource: specifies the event source.
- * This parameter can be one or more of the following values:
- * @arg TIM_EventSource_Update: Timer update Event source
- * @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source
- * @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source
- * @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source
- * @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source
- * @arg TIM_EventSource_COM: Timer COM event source
- * @arg TIM_EventSource_Trigger: Timer Trigger Event source
- * @arg TIM_EventSource_Break: Timer Break event source
- *
- * @note TIM6 and TIM7 can only generate an update event.
- * @note TIM_EventSource_COM and TIM_EventSource_Break are used only with TIM1.
- *
- * @retval None
- */
-void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_TIM_EVENT_SOURCE(TIM_EventSource));
- /* Set the event sources */
- TIMx->EGR = TIM_EventSource;
-}
-
-/**
- * @brief Checks whether the specified TIM flag is set or not.
- * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 or 17 to select the TIM peripheral.
- * @note TIM7 is applicable only for STM32F072 devices
- * @note TIM6 is not applivable for STM32F031 devices.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_FLAG: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg TIM_FLAG_Update: TIM update Flag
- * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag
- * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag
- * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag
- * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag
- * @arg TIM_FLAG_COM: TIM Commutation Flag
- * @arg TIM_FLAG_Trigger: TIM Trigger Flag
- * @arg TIM_FLAG_Break: TIM Break Flag
- * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag
- * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag
- * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag
- * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag
- *
- * @note TIM6 and TIM7 can have only one update flag.
- * @note TIM15 can have only TIM_FLAG_Update, TIM_FLAG_CC1, TIM_FLAG_CC2 or TIM_FLAG_Trigger.
- * @note TIM14, TIM16 and TIM17 can have TIM_FLAG_Update or TIM_FLAG_CC1.
- * @note TIM_FLAG_Break is used only with TIM1 and TIM15.
- * @note TIM_FLAG_COM is used only with TIM1 TIM15, TIM16 and TIM17.
- *
- * @retval The new state of TIM_FLAG (SET or RESET).
- */
-FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)
-{
- ITStatus bitstatus = RESET;
-
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_TIM_GET_FLAG(TIM_FLAG));
-
- if ((TIMx->SR & TIM_FLAG) != (uint16_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Clears the TIMx's pending flags.
- * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 or 17 to select the TIM peripheral.
- * @note TIM7 is applicable only for STM32F072 devices
- * @note TIM6 is not applivable for STM32F031 devices.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_FLAG: specifies the flag bit to clear.
- * This parameter can be any combination of the following values:
- * @arg TIM_FLAG_Update: TIM update Flag
- * @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag
- * @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag
- * @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag
- * @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag
- * @arg TIM_FLAG_COM: TIM Commutation Flag
- * @arg TIM_FLAG_Trigger: TIM Trigger Flag
- * @arg TIM_FLAG_Break: TIM Break Flag
- * @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 overcapture Flag
- * @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 overcapture Flag
- * @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 overcapture Flag
- * @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 overcapture Flag
- *
- * @note TIM6 and TIM7 can have only one update flag.
- * @note TIM15 can have only TIM_FLAG_Update, TIM_FLAG_CC1,TIM_FLAG_CC2 or
- * TIM_FLAG_Trigger.
- * @note TIM14, TIM16 and TIM17 can have TIM_FLAG_Update or TIM_FLAG_CC1.
- * @note TIM_FLAG_Break is used only with TIM1 and TIM15.
- * @note TIM_FLAG_COM is used only with TIM1, TIM15, TIM16 and TIM17.
- *
- * @retval None
- */
-void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_TIM_CLEAR_FLAG(TIM_FLAG));
-
- /* Clear the flags */
- TIMx->SR = (uint16_t)~TIM_FLAG;
-}
-
-/**
- * @brief Checks whether the TIM interrupt has occurred or not.
- * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 or 17 to select the TIM peripheral.
- * @note TIM7 is applicable only for STM32F072 devices
- * @note TIM6 is not applivable for STM32F031 devices.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_IT: specifies the TIM interrupt source to check.
- * This parameter can be one of the following values:
- * @arg TIM_IT_Update: TIM update Interrupt source
- * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
- * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
- * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
- * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
- * @arg TIM_IT_COM: TIM Commutation Interrupt source
- * @arg TIM_IT_Trigger: TIM Trigger Interrupt source
- * @arg TIM_IT_Break: TIM Break Interrupt source
- *
- * @note TIM6 and TIM7 can generate only an update interrupt.
- * @note TIM15 can have only TIM_IT_Update, TIM_IT_CC1, TIM_IT_CC2 or TIM_IT_Trigger.
- * @note TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1.
- * @note TIM_IT_Break is used only with TIM1 and TIM15.
- * @note TIM_IT_COM is used only with TIM1, TIM15, TIM16 and TIM17.
- *
- * @retval The new state of the TIM_IT(SET or RESET).
- */
-ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT)
-{
- ITStatus bitstatus = RESET;
- uint16_t itstatus = 0x0, itenable = 0x0;
-
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_TIM_GET_IT(TIM_IT));
-
- itstatus = TIMx->SR & TIM_IT;
-
- itenable = TIMx->DIER & TIM_IT;
- if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET))
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Clears the TIMx's interrupt pending bits.
- * @param TIMx: where x can be 1, 2, 3, 6, 7, 14, 15, 16 or 17 to select the TIM peripheral.
- * @note TIM7 is applicable only for STM32F072 devices
- * @note TIM6 is not applivable for STM32F031 devices.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_IT: specifies the pending bit to clear.
- * This parameter can be any combination of the following values:
- * @arg TIM_IT_Update: TIM1 update Interrupt source
- * @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
- * @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
- * @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
- * @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
- * @arg TIM_IT_COM: TIM Commutation Interrupt source
- * @arg TIM_IT_Trigger: TIM Trigger Interrupt source
- * @arg TIM_IT_Break: TIM Break Interrupt source
- *
- * @note TIM6 and TIM7 can generate only an update interrupt.
- * @note TIM15 can have only TIM_IT_Update, TIM_IT_CC1, TIM_IT_CC2 or TIM_IT_Trigger.
- * @note TIM14, TIM16 and TIM17 can have TIM_IT_Update or TIM_IT_CC1.
- * @note TIM_IT_Break is used only with TIM1 and TIM15.
- * @note TIM_IT_COM is used only with TIM1, TIM15, TIM16 and TIM17.
- *
- * @retval None
- */
-void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT)
-{
- /* Check the parameters */
- assert_param(IS_TIM_ALL_PERIPH(TIMx));
- assert_param(IS_TIM_IT(TIM_IT));
-
- /* Clear the IT pending Bit */
- TIMx->SR = (uint16_t)~TIM_IT;
-}
-
-/**
- * @brief Configures the TIMx's DMA interface.
- * @param TIMx: where x can be 1, 2, 3, 15, 16 or 17 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_DMABase: DMA Base address.
- * This parameter can be one of the following values:
- * @arg TIM_DMABase_CR1
- * @arg TIM_DMABase_CR2
- * @arg TIM_DMABase_SMCR
- * @arg TIM_DMABase_DIER
- * @arg TIM_DMABase_SR
- * @arg TIM_DMABase_EGR
- * @arg TIM_DMABase_CCMR1
- * @arg TIM_DMABase_CCMR2
- * @arg TIM_DMABase_CCER
- * @arg TIM_DMABase_CNT
- * @arg TIM_DMABase_PSC
- * @arg TIM_DMABase_ARR
- * @arg TIM_DMABase_CCR1
- * @arg TIM_DMABase_CCR2
- * @arg TIM_DMABase_CCR3
- * @arg TIM_DMABase_CCR4
- * @arg TIM_DMABase_DCR
- * @arg TIM_DMABase_OR
- * @param TIM_DMABurstLength: DMA Burst length. This parameter can be one value
- * between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.
- * @retval None
- */
-void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST4_PERIPH(TIMx));
- assert_param(IS_TIM_DMA_BASE(TIM_DMABase));
- assert_param(IS_TIM_DMA_LENGTH(TIM_DMABurstLength));
- /* Set the DMA Base and the DMA Burst Length */
- TIMx->DCR = TIM_DMABase | TIM_DMABurstLength;
-}
-
-/**
- * @brief Enables or disables the TIMx's DMA Requests.
- * @param TIMx: where x can be 1, 2, 3, 6, 7, 15, 16 or 17 to select the TIM peripheral.
- * @note TIM7 is applicable only for STM32F072 devices
- * @note TIM6 is not applivable for STM32F031 devices.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_DMASource: specifies the DMA Request sources.
- * This parameter can be any combination of the following values:
- * @arg TIM_DMA_Update: TIM update Interrupt source
- * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
- * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
- * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
- * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
- * @arg TIM_DMA_COM: TIM Commutation DMA source
- * @arg TIM_DMA_Trigger: TIM Trigger DMA source
- * @param NewState: new state of the DMA Request sources.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST10_PERIPH(TIMx));
- assert_param(IS_TIM_DMA_SOURCE(TIM_DMASource));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the DMA sources */
- TIMx->DIER |= TIM_DMASource;
- }
- else
- {
- /* Disable the DMA sources */
- TIMx->DIER &= (uint16_t)~TIM_DMASource;
- }
-}
-
-/**
- * @brief Selects the TIMx peripheral Capture Compare DMA source.
- * @param TIMx: where x can be 1, 2, 3, 15, 16 or 17 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param NewState: new state of the Capture Compare DMA source
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST5_PERIPH(TIMx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Set the CCDS Bit */
- TIMx->CR2 |= TIM_CR2_CCDS;
- }
- else
- {
- /* Reset the CCDS Bit */
- TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_CCDS);
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Group6 Clocks management functions
- * @brief Clocks management functions
- *
-@verbatim
- ===============================================================================
- ##### Clocks management functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures the TIMx internal Clock
- * @param TIMx: where x can be 1, 2, 3, or 15 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @retval None
- */
-void TIM_InternalClockConfig(TIM_TypeDef* TIMx)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));
- /* Disable slave mode to clock the prescaler directly with the internal clock */
- TIMx->SMCR &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS));
-}
-
-/**
- * @brief Configures the TIMx Internal Trigger as External Clock
- * @param TIMx: where x can be 1, 2, 3, or 15 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_ITRSource: Trigger source.
- * This parameter can be one of the following values:
- * @arg TIM_TS_ITR0: Internal Trigger 0
- * @arg TIM_TS_ITR1: Internal Trigger 1
- * @arg TIM_TS_ITR2: Internal Trigger 2
- * @arg TIM_TS_ITR3: Internal Trigger 3
- * @retval None
- */
-void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));
- assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource));
- /* Select the Internal Trigger */
- TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource);
- /* Select the External clock mode1 */
- TIMx->SMCR |= TIM_SlaveMode_External1;
-}
-
-/**
- * @brief Configures the TIMx Trigger as External Clock
- * @param TIMx: where x can be 1, 2, 3, or 15 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_TIxExternalCLKSource: Trigger source.
- * This parameter can be one of the following values:
- * @arg TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector
- * @arg TIM_TIxExternalCLK1Source_TI1: Filtered Timer Input 1
- * @arg TIM_TIxExternalCLK1Source_TI2: Filtered Timer Input 2
- * @param TIM_ICPolarity: specifies the TIx Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ICPolarity_Rising
- * @arg TIM_ICPolarity_Falling
- * @param ICFilter: specifies the filter value.
- * This parameter must be a value between 0x0 and 0xF.
- * @retval None
- */
-void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,
- uint16_t TIM_ICPolarity, uint16_t ICFilter)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));
- assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity));
- assert_param(IS_TIM_IC_FILTER(ICFilter));
-
- /* Configure the Timer Input Clock Source */
- if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2)
- {
- TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
- }
- else
- {
- TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
- }
- /* Select the Trigger source */
- TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource);
- /* Select the External clock mode1 */
- TIMx->SMCR |= TIM_SlaveMode_External1;
-}
-
-/**
- * @brief Configures the External clock Mode1
- * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
- * This parameter can be one of the following values:
- * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
- * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
- * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
- * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
- * @param TIM_ExtTRGPolarity: The external Trigger Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
- * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
- * @param ExtTRGFilter: External Trigger Filter.
- * This parameter must be a value between 0x00 and 0x0F
- * @retval None
- */
-void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
- uint16_t ExtTRGFilter)
-{
- uint16_t tmpsmcr = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
- assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
- assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
-
- /* Configure the ETR Clock source */
- TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
-
- /* Get the TIMx SMCR register value */
- tmpsmcr = TIMx->SMCR;
- /* Reset the SMS Bits */
- tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS));
- /* Select the External clock mode1 */
- tmpsmcr |= TIM_SlaveMode_External1;
- /* Select the Trigger selection : ETRF */
- tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS));
- tmpsmcr |= TIM_TS_ETRF;
- /* Write to TIMx SMCR */
- TIMx->SMCR = tmpsmcr;
-}
-
-/**
- * @brief Configures the External clock Mode2
- * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
- * This parameter can be one of the following values:
- * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
- * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
- * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
- * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
- * @param TIM_ExtTRGPolarity: The external Trigger Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
- * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
- * @param ExtTRGFilter: External Trigger Filter.
- * This parameter must be a value between 0x00 and 0x0F
- * @retval None
- */
-void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
- uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
- assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
- assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
-
- /* Configure the ETR Clock source */
- TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
- /* Enable the External clock mode2 */
- TIMx->SMCR |= TIM_SMCR_ECE;
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Group7 Synchronization management functions
- * @brief Synchronization management functions
- *
-@verbatim
- ===============================================================================
- ##### Synchronization management functions #####
- ===============================================================================
- *** TIM Driver: how to use it in synchronization Mode ***
- ===============================================================================
- [..] Case of two/several Timers
- (#) Configure the Master Timers using the following functions:
- (++) void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx,
- uint16_t TIM_TRGOSource).
- (++) void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx,
- uint16_t TIM_MasterSlaveMode);
- (#) Configure the Slave Timers using the following functions:
- (++) void TIM_SelectInputTrigger(TIM_TypeDef* TIMx,
- uint16_t TIM_InputTriggerSource);
- (++) void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode);
- [..] Case of Timers and external trigger(ETR pin)
- (#) Configure the Etrenal trigger using this function:
- (++) void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
- uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter);
- (#) Configure the Slave Timers using the following functions:
- (++) void TIM_SelectInputTrigger(TIM_TypeDef* TIMx,
- uint16_t TIM_InputTriggerSource);
- (++) void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode);
-
-@endverbatim
- * @{
- */
-/**
- * @brief Selects the Input Trigger source
- * @param TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_InputTriggerSource: The Input Trigger source.
- * This parameter can be one of the following values:
- * @arg TIM_TS_ITR0: Internal Trigger 0
- * @arg TIM_TS_ITR1: Internal Trigger 1
- * @arg TIM_TS_ITR2: Internal Trigger 2
- * @arg TIM_TS_ITR3: Internal Trigger 3
- * @arg TIM_TS_TI1F_ED: TI1 Edge Detector
- * @arg TIM_TS_TI1FP1: Filtered Timer Input 1
- * @arg TIM_TS_TI2FP2: Filtered Timer Input 2
- * @arg TIM_TS_ETRF: External Trigger input
- * @retval None
- */
-void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)
-{
- uint16_t tmpsmcr = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));
- assert_param(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource));
-
- /* Get the TIMx SMCR register value */
- tmpsmcr = TIMx->SMCR;
- /* Reset the TS Bits */
- tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_TS));
- /* Set the Input Trigger source */
- tmpsmcr |= TIM_InputTriggerSource;
- /* Write to TIMx SMCR */
- TIMx->SMCR = tmpsmcr;
-}
-
-/**
- * @brief Selects the TIMx Trigger Output Mode.
- * @param TIMx: where x can be 1, 2, 3, 6, 7, or 15 to select the TIM peripheral.
- * @note TIM7 is applicable only for STM32F072 devices
- * @note TIM6 is not applivable for STM32F031 devices.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_TRGOSource: specifies the Trigger Output source.
- * This parameter can be one of the following values:
- *
- * - For all TIMx
- * @arg TIM_TRGOSource_Reset: The UG bit in the TIM_EGR register is used as the trigger output (TRGO).
- * @arg TIM_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output (TRGO).
- * @arg TIM_TRGOSource_Update: The update event is selected as the trigger output (TRGO).
- *
- * - For all TIMx except TIM6 and TIM7
- * @arg TIM_TRGOSource_OC1: The trigger output sends a positive pulse when the CC1IF flag
- * is to be set, as soon as a capture or compare match occurs (TRGO).
- * @arg TIM_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output (TRGO).
- * @arg TIM_TRGOSource_OC2Ref: OC2REF signal is used as the trigger output (TRGO).
- * @arg TIM_TRGOSource_OC3Ref: OC3REF signal is used as the trigger output (TRGO).
- * @arg TIM_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output (TRGO).
- *
- * @retval None
- */
-void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST9_PERIPH(TIMx));
- assert_param(IS_TIM_TRGO_SOURCE(TIM_TRGOSource));
-
- /* Reset the MMS Bits */
- TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_MMS);
- /* Select the TRGO source */
- TIMx->CR2 |= TIM_TRGOSource;
-}
-
-/**
- * @brief Selects the TIMx Slave Mode.
- * @param TIMx: where x can be 1, 2, 3 or 15 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_SlaveMode: specifies the Timer Slave Mode.
- * This parameter can be one of the following values:
- * @arg TIM_SlaveMode_Reset: Rising edge of the selected trigger signal (TRGI) re-initializes
- * the counter and triggers an update of the registers.
- * @arg TIM_SlaveMode_Gated: The counter clock is enabled when the trigger signal (TRGI) is high.
- * @arg TIM_SlaveMode_Trigger: The counter starts at a rising edge of the trigger TRGI.
- * @arg TIM_SlaveMode_External1: Rising edges of the selected trigger (TRGI) clock the counter.
- * @retval None
- */
-void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));
- assert_param(IS_TIM_SLAVE_MODE(TIM_SlaveMode));
-
- /* Reset the SMS Bits */
- TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_SMS);
- /* Select the Slave Mode */
- TIMx->SMCR |= TIM_SlaveMode;
-}
-
-/**
- * @brief Sets or Resets the TIMx Master/Slave Mode.
- * @param TIMx: where x can be 1, 2, 3, or 15 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_MasterSlaveMode: specifies the Timer Master Slave Mode.
- * This parameter can be one of the following values:
- * @arg TIM_MasterSlaveMode_Enable: synchronization between the current timer
- * and its slaves (through TRGO).
- * @arg TIM_MasterSlaveMode_Disable: No action
- * @retval None
- */
-void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST6_PERIPH(TIMx));
- assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode));
-
- /* Reset the MSM Bit */
- TIMx->SMCR &= (uint16_t)~((uint16_t)TIM_SMCR_MSM);
-
- /* Set or Reset the MSM Bit */
- TIMx->SMCR |= TIM_MasterSlaveMode;
-}
-
-/**
- * @brief Configures the TIMx External Trigger (ETR).
- * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
- * This parameter can be one of the following values:
- * @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
- * @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
- * @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
- * @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
- * @param TIM_ExtTRGPolarity: The external Trigger Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
- * @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
- * @param ExtTRGFilter: External Trigger Filter.
- * This parameter must be a value between 0x00 and 0x0F
- * @retval None
- */
-void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
- uint16_t ExtTRGFilter)
-{
- uint16_t tmpsmcr = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
- assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
- assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
-
- tmpsmcr = TIMx->SMCR;
- /* Reset the ETR Bits */
- tmpsmcr &= SMCR_ETR_MASK;
- /* Set the Prescaler, the Filter value and the Polarity */
- tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8)));
- /* Write to TIMx SMCR */
- TIMx->SMCR = tmpsmcr;
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Group8 Specific interface management functions
- * @brief Specific interface management functions
- *
-@verbatim
- ===============================================================================
- ##### Specific interface management functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures the TIMx Encoder Interface.
- * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_EncoderMode: specifies the TIMx Encoder Mode.
- * This parameter can be one of the following values:
- * @arg TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level.
- * @arg TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level.
- * @arg TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending
- * on the level of the other input.
- * @param TIM_IC1Polarity: specifies the IC1 Polarity
- * This parmeter can be one of the following values:
- * @arg TIM_ICPolarity_Falling: IC Falling edge.
- * @arg TIM_ICPolarity_Rising: IC Rising edge.
- * @param TIM_IC2Polarity: specifies the IC2 Polarity
- * This parmeter can be one of the following values:
- * @arg TIM_ICPolarity_Falling: IC Falling edge.
- * @arg TIM_ICPolarity_Rising: IC Rising edge.
- * @retval None
- */
-void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
- uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity)
-{
- uint16_t tmpsmcr = 0;
- uint16_t tmpccmr1 = 0;
- uint16_t tmpccer = 0;
-
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode));
- assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity));
- assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity));
-
- /* Get the TIMx SMCR register value */
- tmpsmcr = TIMx->SMCR;
- /* Get the TIMx CCMR1 register value */
- tmpccmr1 = TIMx->CCMR1;
- /* Get the TIMx CCER register value */
- tmpccer = TIMx->CCER;
- /* Set the encoder Mode */
- tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMCR_SMS));
- tmpsmcr |= TIM_EncoderMode;
- /* Select the Capture Compare 1 and the Capture Compare 2 as input */
- tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & (uint16_t)(~((uint16_t)TIM_CCMR1_CC2S)));
- tmpccmr1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0;
- /* Set the TI1 and the TI2 Polarities */
- tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC1P | TIM_CCER_CC1NP)) & (uint16_t)~((uint16_t)(TIM_CCER_CC2P | TIM_CCER_CC2NP));
- tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4));
- /* Write to TIMx SMCR */
- TIMx->SMCR = tmpsmcr;
- /* Write to TIMx CCMR1 */
- TIMx->CCMR1 = tmpccmr1;
- /* Write to TIMx CCER */
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Enables or disables the TIMx's Hall sensor interface.
- * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param NewState: new state of the TIMx Hall sensor interface.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST3_PERIPH(TIMx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Set the TI1S Bit */
- TIMx->CR2 |= TIM_CR2_TI1S;
- }
- else
- {
- /* Reset the TI1S Bit */
- TIMx->CR2 &= (uint16_t)~((uint16_t)TIM_CR2_TI1S);
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup TIM_Group9 Specific remapping management function
- * @brief Specific remapping management function
- *
-@verbatim
- ===============================================================================
- ##### Specific remapping management function #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-/**
- * @brief Configures the TIM14 Remapping input Capabilities.
- * @param TIMx: where x can be 14 to select the TIM peripheral.
- * @param TIM_Remap: specifies the TIM input reampping source.
- * This parameter can be one of the following values:
- * @arg TIM14_GPIO: TIM14 Channel 1 is connected to GPIO.
- * @arg TIM14_RTC_CLK: TIM14 Channel 1 is connected to RTC input clock.
- * RTC input clock can be LSE, LSI or HSE/div128.
- * @arg TIM14_HSE_DIV32: TIM14 Channel 1 is connected to HSE/32 clock.
- * @arg TIM14_MCO: TIM14 Channel 1 is connected to MCO clock.
- * MCO clock can be HSI14, SYSCLK, HSI, HSE or PLL/2.
- * @retval None
- */
-void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap)
-{
- /* Check the parameters */
- assert_param(IS_TIM_LIST11_PERIPH(TIMx));
- assert_param(IS_TIM_REMAP(TIM_Remap));
-
- /* Set the Timer remapping configuration */
- TIMx->OR = TIM_Remap;
-}
-
-/**
- * @}
- */
-
-/**
- * @brief Configure the TI1 as Input.
- * @param TIMx: where x can be 1, 2, 3, 14, 15, 16 or 17 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_ICPolarity: The Input Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ICPolarity_Rising
- * @arg TIM_ICPolarity_Falling
- * @param TIM_ICSelection: specifies the input to be used.
- * This parameter can be one of the following values:
- * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
- * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
- * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
- * @param TIM_ICFilter: Specifies the Input Capture Filter.
- * This parameter must be a value between 0x00 and 0x0F.
- * @retval None
- */
-static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
- uint16_t TIM_ICFilter)
-{
- uint16_t tmpccmr1 = 0, tmpccer = 0;
- /* Disable the Channel 1: Reset the CC1E Bit */
- TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC1E);
- tmpccmr1 = TIMx->CCMR1;
- tmpccer = TIMx->CCER;
- /* Select the Input and set the filter */
- tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC1S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC1F)));
- tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));
-
- /* Select the Polarity and set the CC1E Bit */
- tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC1P | TIM_CCER_CC1NP));
- tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E);
- /* Write to TIMx CCMR1 and CCER registers */
- TIMx->CCMR1 = tmpccmr1;
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configure the TI2 as Input.
- * @param TIMx: where x can be 1, 2, 3, or 15 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_ICPolarity: The Input Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ICPolarity_Rising
- * @arg TIM_ICPolarity_Falling
- * @param TIM_ICSelection: specifies the input to be used.
- * This parameter can be one of the following values:
- * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.
- * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.
- * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.
- * @param TIM_ICFilter: Specifies the Input Capture Filter.
- * This parameter must be a value between 0x00 and 0x0F.
- * @retval None
- */
-static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
- uint16_t TIM_ICFilter)
-{
- uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0;
- /* Disable the Channel 2: Reset the CC2E Bit */
- TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC2E);
- tmpccmr1 = TIMx->CCMR1;
- tmpccer = TIMx->CCER;
- tmp = (uint16_t)(TIM_ICPolarity << 4);
- /* Select the Input and set the filter */
- tmpccmr1 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR1_CC2S)) & ((uint16_t)~((uint16_t)TIM_CCMR1_IC2F)));
- tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12);
- tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8);
- /* Select the Polarity and set the CC2E Bit */
- tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC2P | TIM_CCER_CC2NP));
- tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC2E);
- /* Write to TIMx CCMR1 and CCER registers */
- TIMx->CCMR1 = tmpccmr1 ;
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configure the TI3 as Input.
- * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_ICPolarity: The Input Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ICPolarity_Rising
- * @arg TIM_ICPolarity_Falling
- * @param TIM_ICSelection: specifies the input to be used.
- * This parameter can be one of the following values:
- * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.
- * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.
- * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.
- * @param TIM_ICFilter: Specifies the Input Capture Filter.
- * This parameter must be a value between 0x00 and 0x0F.
- * @retval None
- */
-static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
- uint16_t TIM_ICFilter)
-{
- uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
- /* Disable the Channel 3: Reset the CC3E Bit */
- TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC3E);
- tmpccmr2 = TIMx->CCMR2;
- tmpccer = TIMx->CCER;
- tmp = (uint16_t)(TIM_ICPolarity << 8);
- /* Select the Input and set the filter */
- tmpccmr2 &= (uint16_t)(((uint16_t)~((uint16_t)TIM_CCMR2_CC3S)) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC3F)));
- tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));
- /* Select the Polarity and set the CC3E Bit */
- tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC3P | TIM_CCER_CC3NP));
- tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC3E);
- /* Write to TIMx CCMR2 and CCER registers */
- TIMx->CCMR2 = tmpccmr2;
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @brief Configure the TI4 as Input.
- * @param TIMx: where x can be 1, 2 or 3 to select the TIM peripheral.
- * @note TIM2 is not applicable for STM32F030 devices.
- * @param TIM_ICPolarity: The Input Polarity.
- * This parameter can be one of the following values:
- * @arg TIM_ICPolarity_Rising
- * @arg TIM_ICPolarity_Falling
- * @param TIM_ICSelection: specifies the input to be used.
- * This parameter can be one of the following values:
- * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.
- * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.
- * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.
- * @param TIM_ICFilter: Specifies the Input Capture Filter.
- * This parameter must be a value between 0x00 and 0x0F.
- * @retval None
- */
-static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
- uint16_t TIM_ICFilter)
-{
- uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
-
- /* Disable the Channel 4: Reset the CC4E Bit */
- TIMx->CCER &= (uint16_t)~((uint16_t)TIM_CCER_CC4E);
- tmpccmr2 = TIMx->CCMR2;
- tmpccer = TIMx->CCER;
- tmp = (uint16_t)(TIM_ICPolarity << 12);
- /* Select the Input and set the filter */
- tmpccmr2 &= (uint16_t)((uint16_t)(~(uint16_t)TIM_CCMR2_CC4S) & ((uint16_t)~((uint16_t)TIM_CCMR2_IC4F)));
- tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8);
- tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12);
- /* Select the Polarity and set the CC4E Bit */
- tmpccer &= (uint16_t)~((uint16_t)(TIM_CCER_CC4P | TIM_CCER_CC4NP));
- tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC4E);
- /* Write to TIMx CCMR2 and CCER registers */
- TIMx->CCMR2 = tmpccmr2;
- TIMx->CCER = tmpccer;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_usart.c b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_usart.c
deleted file mode 100644
index 43392f0b617f1a114ea6c9c6455d472d365f29d7..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_usart.c
+++ /dev/null
@@ -1,2096 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f0xx_usart.c
- * @author MCD Application Team
- * @version V1.3.0
- * @date 16-January-2014
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Universal synchronous asynchronous receiver
- * transmitter (USART):
- * + Initialization and Configuration
- * + STOP Mode
- * + AutoBaudRate
- * + Data transfers
- * + Multi-Processor Communication
- * + LIN mode
- * + Half-duplex mode
- * + Smartcard mode
- * + IrDA mode
- * + RS485 mode
- * + DMA transfers management
- * + Interrupts and flags management
- *
- * @verbatim
- ===============================================================================
- ##### How to use this driver #####
- ===============================================================================
- [..]
- (#) Enable peripheral clock using RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE)
- function for USART1 or using RCC_APB1PeriphClockCmd(RCC_APB1Periph_USARTx, ENABLE)
- function for USART2 and USART3.
- (#) According to the USART mode, enable the GPIO clocks using
- RCC_AHBPeriphClockCmd() function. (The I/O can be TX, RX, CTS,
- or and SCLK).
- (#) Peripheral's alternate function:
- (++) Connect the pin to the desired peripherals' Alternate
- Function (AF) using GPIO_PinAFConfig() function.
- (++) Configure the desired pin in alternate function by:
- GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF.
- (++) Select the type, pull-up/pull-down and output speed via
- GPIO_PuPd, GPIO_OType and GPIO_Speed members.
- (++) Call GPIO_Init() function.
- (#) Program the Baud Rate, Word Length , Stop Bit, Parity, Hardware
- flow control and Mode(Receiver/Transmitter) using the SPI_Init()
- function.
- (#) For synchronous mode, enable the clock and program the polarity,
- phase and last bit using the USART_ClockInit() function.
- (#) Enable the NVIC and the corresponding interrupt using the function
- USART_ITConfig() if you need to use interrupt mode.
- (#) When using the DMA mode:
- (++) Configure the DMA using DMA_Init() function.
- (++) Active the needed channel Request using USART_DMACmd() function.
- (#) Enable the USART using the USART_Cmd() function.
- (#) Enable the DMA using the DMA_Cmd() function, when using DMA mode.
- [..]
- Refer to Multi-Processor, LIN, half-duplex, Smartcard, IrDA sub-sections
- for more details.
-
-@endverbatim
-
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx_usart.h"
-#include "stm32f0xx_rcc.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup USART
- * @brief USART driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-/*!< USART CR1 register clear Mask ((~(uint32_t)0xFFFFE6F3)) */
-#define CR1_CLEAR_MASK ((uint32_t)(USART_CR1_M | USART_CR1_PCE | \
- USART_CR1_PS | USART_CR1_TE | \
- USART_CR1_RE))
-
-/*!< USART CR2 register clock bits clear Mask ((~(uint32_t)0xFFFFF0FF)) */
-#define CR2_CLOCK_CLEAR_MASK ((uint32_t)(USART_CR2_CLKEN | USART_CR2_CPOL | \
- USART_CR2_CPHA | USART_CR2_LBCL))
-
-/*!< USART CR3 register clear Mask ((~(uint32_t)0xFFFFFCFF)) */
-#define CR3_CLEAR_MASK ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE))
-
-/*!< USART Interrupts mask */
-#define IT_MASK ((uint32_t)0x000000FF)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup USART_Private_Functions
- * @{
- */
-
-/** @defgroup USART_Group1 Initialization and Configuration functions
- * @brief Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
- ##### Initialization and Configuration functions #####
- ===============================================================================
- [..]
- This subsection provides a set of functions allowing to initialize the USART
- in asynchronous and in synchronous modes.
- (+) For the asynchronous mode only these parameters can be configured:
- (++) Baud Rate.
- (++) Word Length.
- (++) Stop Bit.
- (++) Parity: If the parity is enabled, then the MSB bit of the data written
- in the data register is transmitted but is changed by the parity bit.
- Depending on the frame length defined by the M bit (8-bits or 9-bits),
- the possible USART frame formats are as listed in the following table:
-
- +-------------------------------------------------------------+
- | M bit | PCE bit | USART frame |
- |---------------------|---------------------------------------|
- | 0 | 0 | | SB | 8 bit data | STB | |
- |---------|-----------|---------------------------------------|
- | 0 | 1 | | SB | 7 bit data | PB | STB | |
- |---------|-----------|---------------------------------------|
- | 1 | 0 | | SB | 9 bit data | STB | |
- |---------|-----------|---------------------------------------|
- | 1 | 1 | | SB | 8 bit data | PB | STB | |
- +-------------------------------------------------------------+
-
- (++) Hardware flow control.
- (++) Receiver/transmitter modes.
- [..] The USART_Init() function follows the USART asynchronous configuration
- procedure(details for the procedure are available in reference manual.
- (+) For the synchronous mode in addition to the asynchronous mode parameters
- these parameters should be also configured:
- (++) USART Clock Enabled.
- (++) USART polarity.
- (++) USART phase.
- (++) USART LastBit.
- [..] These parameters can be configured using the USART_ClockInit() function.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitializes the USARTx peripheral registers to their default reset values.
- * @param USARTx: where x can be 1, 2, 3 or 4 to select the USART peripheral.
- * @note USART3 and USART4 are available only for STM32F072 devices.
- * @note USART2 is not available for STM32F031 devices.
- * @retval None
- */
-void USART_DeInit(USART_TypeDef* USARTx)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
-
- if (USARTx == USART1)
- {
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE);
- RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE);
- }
- else if (USARTx == USART2)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE);
- }
- else if (USARTx == USART3)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE);
- }
- else
- {
- if (USARTx == USART4)
- {
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART4, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART4, DISABLE);
- }
- }
-}
-
-/**
- * @brief Initializes the USARTx peripheral according to the specified
- * parameters in the USART_InitStruct .
- * @param USARTx: where x can be 1, 2, 3 or 4 to select the USART peripheral.
- * @note USART3 and USART4 are available only for STM32F072 devices.
- * @note USART2 is not available for STM32F031 devices.
- * @param USART_InitStruct: pointer to a USART_InitTypeDef structure that contains
- * the configuration information for the specified USART peripheral.
- * @retval None
- */
-void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct)
-{
- uint32_t divider = 0, apbclock = 0, tmpreg = 0;
- RCC_ClocksTypeDef RCC_ClocksStatus;
-
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_BAUDRATE(USART_InitStruct->USART_BaudRate));
- assert_param(IS_USART_WORD_LENGTH(USART_InitStruct->USART_WordLength));
- assert_param(IS_USART_STOPBITS(USART_InitStruct->USART_StopBits));
- assert_param(IS_USART_PARITY(USART_InitStruct->USART_Parity));
- assert_param(IS_USART_MODE(USART_InitStruct->USART_Mode));
- assert_param(IS_USART_HARDWARE_FLOW_CONTROL(USART_InitStruct->USART_HardwareFlowControl));
-
- /* Disable USART */
- USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_UE);
-
- /*---------------------------- USART CR2 Configuration -----------------------*/
- tmpreg = USARTx->CR2;
- /* Clear STOP[13:12] bits */
- tmpreg &= (uint32_t)~((uint32_t)USART_CR2_STOP);
-
- /* Configure the USART Stop Bits, Clock, CPOL, CPHA and LastBit ------------*/
- /* Set STOP[13:12] bits according to USART_StopBits value */
- tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits;
-
- /* Write to USART CR2 */
- USARTx->CR2 = tmpreg;
-
- /*---------------------------- USART CR1 Configuration -----------------------*/
- tmpreg = USARTx->CR1;
- /* Clear M, PCE, PS, TE and RE bits */
- tmpreg &= (uint32_t)~((uint32_t)CR1_CLEAR_MASK);
-
- /* Configure the USART Word Length, Parity and mode ----------------------- */
- /* Set the M bits according to USART_WordLength value */
- /* Set PCE and PS bits according to USART_Parity value */
- /* Set TE and RE bits according to USART_Mode value */
- tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity |
- USART_InitStruct->USART_Mode;
-
- /* Write to USART CR1 */
- USARTx->CR1 = tmpreg;
-
- /*---------------------------- USART CR3 Configuration -----------------------*/
- tmpreg = USARTx->CR3;
- /* Clear CTSE and RTSE bits */
- tmpreg &= (uint32_t)~((uint32_t)CR3_CLEAR_MASK);
-
- /* Configure the USART HFC -------------------------------------------------*/
- /* Set CTSE and RTSE bits according to USART_HardwareFlowControl value */
- tmpreg |= USART_InitStruct->USART_HardwareFlowControl;
-
- /* Write to USART CR3 */
- USARTx->CR3 = tmpreg;
-
- /*---------------------------- USART BRR Configuration -----------------------*/
- /* Configure the USART Baud Rate -------------------------------------------*/
- RCC_GetClocksFreq(&RCC_ClocksStatus);
-
- if (USARTx == USART1)
- {
- apbclock = RCC_ClocksStatus.USART1CLK_Frequency;
- }
- else if (USARTx == USART2)
- {
- apbclock = RCC_ClocksStatus.USART2CLK_Frequency;
- }
- else
- {
- apbclock = RCC_ClocksStatus.PCLK_Frequency;
- }
-
- /* Determine the integer part */
- if ((USARTx->CR1 & USART_CR1_OVER8) != 0)
- {
- /* (divider * 10) computing in case Oversampling mode is 8 Samples */
- divider = (uint32_t)((2 * apbclock) / (USART_InitStruct->USART_BaudRate));
- tmpreg = (uint32_t)((2 * apbclock) % (USART_InitStruct->USART_BaudRate));
- }
- else /* if ((USARTx->CR1 & CR1_OVER8_Set) == 0) */
- {
- /* (divider * 10) computing in case Oversampling mode is 16 Samples */
- divider = (uint32_t)((apbclock) / (USART_InitStruct->USART_BaudRate));
- tmpreg = (uint32_t)((apbclock) % (USART_InitStruct->USART_BaudRate));
- }
-
- /* round the divider : if fractional part i greater than 0.5 increment divider */
- if (tmpreg >= (USART_InitStruct->USART_BaudRate) / 2)
- {
- divider++;
- }
-
- /* Implement the divider in case Oversampling mode is 8 Samples */
- if ((USARTx->CR1 & USART_CR1_OVER8) != 0)
- {
- /* get the LSB of divider and shift it to the right by 1 bit */
- tmpreg = (divider & (uint16_t)0x000F) >> 1;
-
- /* update the divider value */
- divider = (divider & (uint16_t)0xFFF0) | tmpreg;
- }
-
- /* Write to USART BRR */
- USARTx->BRR = (uint16_t)divider;
-}
-
-/**
- * @brief Fills each USART_InitStruct member with its default value.
- * @param USART_InitStruct: pointer to a USART_InitTypeDef structure
- * which will be initialized.
- * @retval None
- */
-void USART_StructInit(USART_InitTypeDef* USART_InitStruct)
-{
- /* USART_InitStruct members default value */
- USART_InitStruct->USART_BaudRate = 9600;
- USART_InitStruct->USART_WordLength = USART_WordLength_8b;
- USART_InitStruct->USART_StopBits = USART_StopBits_1;
- USART_InitStruct->USART_Parity = USART_Parity_No ;
- USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
- USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None;
-}
-
-/**
- * @brief Initializes the USARTx peripheral Clock according to the
- * specified parameters in the USART_ClockInitStruct.
- * @param USARTx: where x can be 1, 2, 3 or 4 to select the USART peripheral.
- * @note USART3 and USART4 are available only for STM32F072 devices.
- * @note USART2 is not available for STM32F031 devices.
- * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef
- * structure that contains the configuration information for the specified
- * USART peripheral.
- * @retval None
- */
-void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct)
-{
- uint32_t tmpreg = 0;
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_CLOCK(USART_ClockInitStruct->USART_Clock));
- assert_param(IS_USART_CPOL(USART_ClockInitStruct->USART_CPOL));
- assert_param(IS_USART_CPHA(USART_ClockInitStruct->USART_CPHA));
- assert_param(IS_USART_LASTBIT(USART_ClockInitStruct->USART_LastBit));
-/*---------------------------- USART CR2 Configuration -----------------------*/
- tmpreg = USARTx->CR2;
- /* Clear CLKEN, CPOL, CPHA, LBCL and SSM bits */
- tmpreg &= (uint32_t)~((uint32_t)CR2_CLOCK_CLEAR_MASK);
- /* Configure the USART Clock, CPOL, CPHA, LastBit and SSM ------------*/
- /* Set CLKEN bit according to USART_Clock value */
- /* Set CPOL bit according to USART_CPOL value */
- /* Set CPHA bit according to USART_CPHA value */
- /* Set LBCL bit according to USART_LastBit value */
- tmpreg |= (uint32_t)(USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL |
- USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit);
- /* Write to USART CR2 */
- USARTx->CR2 = tmpreg;
-}
-
-/**
- * @brief Fills each USART_ClockInitStruct member with its default value.
- * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef
- * structure which will be initialized.
- * @retval None
- */
-void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct)
-{
- /* USART_ClockInitStruct members default value */
- USART_ClockInitStruct->USART_Clock = USART_Clock_Disable;
- USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low;
- USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge;
- USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable;
-}
-
-/**
- * @brief Enables or disables the specified USART peripheral.
- * @param USARTx: where x can be 1, 2, 3 or 4 to select the USART peripheral.
- * @note USART3 and USART4 are available only for STM32F072 devices.
- * @note USART2 is not available for STM32F031 devices.
- * @param NewState: new state of the USARTx peripheral.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected USART by setting the UE bit in the CR1 register */
- USARTx->CR1 |= USART_CR1_UE;
- }
- else
- {
- /* Disable the selected USART by clearing the UE bit in the CR1 register */
- USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_UE);
- }
-}
-
-/**
- * @brief Enables or disables the USART's transmitter or receiver.
- * @param USARTx: where x can be 1, 2, 3 or 4 to select the USART peripheral.
- * @note USART3 and USART4 are available only for STM32F072 devices.
- * @note USART2 is not available for STM32F031 devices.
- * @param USART_Direction: specifies the USART direction.
- * This parameter can be any combination of the following values:
- * @arg USART_Mode_Tx: USART Transmitter
- * @arg USART_Mode_Rx: USART Receiver
- * @param NewState: new state of the USART transfer direction.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_DirectionModeCmd(USART_TypeDef* USARTx, uint32_t USART_DirectionMode, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_MODE(USART_DirectionMode));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the USART's transfer interface by setting the TE and/or RE bits
- in the USART CR1 register */
- USARTx->CR1 |= USART_DirectionMode;
- }
- else
- {
- /* Disable the USART's transfer interface by clearing the TE and/or RE bits
- in the USART CR3 register */
- USARTx->CR1 &= (uint32_t)~USART_DirectionMode;
- }
-}
-
-/**
- * @brief Enables or disables the USART's 8x oversampling mode.
- * @param USARTx: where x can be 1, 2, 3 or 4 to select the USART peripheral.
- * @note USART3 and USART4 are available only for STM32F072 devices.
- * @note USART2 is not available for STM32F031 devices.
- * @param NewState: new state of the USART 8x oversampling mode.
- * This parameter can be: ENABLE or DISABLE.
- * @note This function has to be called before calling USART_Init() function
- * in order to have correct baudrate Divider value.
- * @retval None
- */
-void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the 8x Oversampling mode by setting the OVER8 bit in the CR1 register */
- USARTx->CR1 |= USART_CR1_OVER8;
- }
- else
- {
- /* Disable the 8x Oversampling mode by clearing the OVER8 bit in the CR1 register */
- USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_OVER8);
- }
-}
-
-/**
- * @brief Enables or disables the USART's one bit sampling method.
- * @param USARTx: where x can be 1, 2, 3 or 4 to select the USART peripheral.
- * @note USART3 and USART4 are available only for STM32F072 devices.
- * @note USART2 is not available for STM32F031 devices.
- * @param NewState: new state of the USART one bit sampling method.
- * This parameter can be: ENABLE or DISABLE.
- * @note This function has to be called before calling USART_Cmd() function.
- * @retval None
- */
-void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the one bit method by setting the ONEBITE bit in the CR3 register */
- USARTx->CR3 |= USART_CR3_ONEBIT;
- }
- else
- {
- /* Disable the one bit method by clearing the ONEBITE bit in the CR3 register */
- USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT);
- }
-}
-
-/**
- * @brief Enables or disables the USART's most significant bit first
- * transmitted/received following the start bit.
- * @param USARTx: where x can be 1, 2, 3 or 4 to select the USART peripheral.
- * @note USART3 and USART4 are available only for STM32F072 devices.
- * @note USART2 is not available for STM32F031 devices.
- * @param NewState: new state of the USART most significant bit first
- * transmitted/received following the start bit.
- * This parameter can be: ENABLE or DISABLE.
- * @note This function has to be called before calling USART_Cmd() function.
- * @retval None
- */
-void USART_MSBFirstCmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the most significant bit first transmitted/received following the
- start bit by setting the MSBFIRST bit in the CR2 register */
- USARTx->CR2 |= USART_CR2_MSBFIRST;
- }
- else
- {
- /* Disable the most significant bit first transmitted/received following the
- start bit by clearing the MSBFIRST bit in the CR2 register */
- USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_MSBFIRST);
- }
-}
-
-/**
- * @brief Enables or disables the binary data inversion.
- * @param USARTx: where x can be 1, 2, 3 or 4 to select the USART peripheral.
- * @note USART3 and USART4 are available only for STM32F072 devices.
- * @note USART2 is not available for STM32F031 devices.
- * @param NewState: new defined levels for the USART data.
- * This parameter can be:
- * @arg ENABLE: Logical data from the data register are send/received in negative
- * logic (1=L, 0=H). The parity bit is also inverted.
- * @arg DISABLE: Logical data from the data register are send/received in positive
- * logic (1=H, 0=L)
- * @note This function has to be called before calling USART_Cmd() function.
- * @retval None
- */
-void USART_DataInvCmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the binary data inversion feature by setting the DATAINV bit in
- the CR2 register */
- USARTx->CR2 |= USART_CR2_DATAINV;
- }
- else
- {
- /* Disable the binary data inversion feature by clearing the DATAINV bit in
- the CR2 register */
- USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_DATAINV);
- }
-}
-
-/**
- * @brief Enables or disables the Pin(s) active level inversion.
- * @param USARTx: where x can be 1, 2, 3 or 4 to select the USART peripheral.
- * @note USART3 and USART4 are available only for STM32F072 devices.
- * @note USART2 is not available for STM32F031 devices.
- * @param USART_InvPin: specifies the USART pin(s) to invert.
- * This parameter can be any combination of the following values:
- * @arg USART_InvPin_Tx: USART Tx pin active level inversion.
- * @arg USART_InvPin_Rx: USART Rx pin active level inversion.
- * @param NewState: new active level status for the USART pin(s).
- * This parameter can be:
- * @arg ENABLE: pin(s) signal values are inverted (Vdd =0, Gnd =1).
- * @arg DISABLE: pin(s) signal works using the standard logic levels (Vdd =1, Gnd =0).
- * @note This function has to be called before calling USART_Cmd() function.
- * @retval None
- */
-void USART_InvPinCmd(USART_TypeDef* USARTx, uint32_t USART_InvPin, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_INVERSTION_PIN(USART_InvPin));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the active level inversion for selected pins by setting the TXINV
- and/or RXINV bits in the USART CR2 register */
- USARTx->CR2 |= USART_InvPin;
- }
- else
- {
- /* Disable the active level inversion for selected requests by clearing the
- TXINV and/or RXINV bits in the USART CR2 register */
- USARTx->CR2 &= (uint32_t)~USART_InvPin;
- }
-}
-
-/**
- * @brief Enables or disables the swap Tx/Rx pins.
- * @param USARTx: where x can be 1, 2, 3 or 4 to select the USART peripheral.
- * @note USART3 and USART4 are available only for STM32F072 devices.
- * @note USART2 is not available for STM32F031 devices.
- * @param NewState: new state of the USARTx TX/RX pins pinout.
- * This parameter can be:
- * @arg ENABLE: The TX and RX pins functions are swapped.
- * @arg DISABLE: TX/RX pins are used as defined in standard pinout
- * @note This function has to be called before calling USART_Cmd() function.
- * @retval None
- */
-void USART_SWAPPinCmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the SWAP feature by setting the SWAP bit in the CR2 register */
- USARTx->CR2 |= USART_CR2_SWAP;
- }
- else
- {
- /* Disable the SWAP feature by clearing the SWAP bit in the CR2 register */
- USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_SWAP);
- }
-}
-
-/**
- * @brief Enables or disables the receiver Time Out feature.
- * @param USARTx: where x can be 1 to select the USART peripheral.
- * @param NewState: new state of the USARTx receiver Time Out.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_ReceiverTimeOutCmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_12_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the receiver time out feature by setting the RTOEN bit in the CR2
- register */
- USARTx->CR2 |= USART_CR2_RTOEN;
- }
- else
- {
- /* Disable the receiver time out feature by clearing the RTOEN bit in the CR2
- register */
- USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_RTOEN);
- }
-}
-
-/**
- * @brief Sets the receiver Time Out value.
- * @param USARTx: where x can be 1or 2 to select the USART peripheral.
- * @note USART2 is available only for STM32F072 devices.
- * @param USART_ReceiverTimeOut: specifies the Receiver Time Out value.
- * @retval None
- */
-void USART_SetReceiverTimeOut(USART_TypeDef* USARTx, uint32_t USART_ReceiverTimeOut)
-{
- /* Check the parameters */
- assert_param(IS_USART_12_PERIPH(USARTx));
- assert_param(IS_USART_TIMEOUT(USART_ReceiverTimeOut));
-
- /* Clear the receiver Time Out value by clearing the RTO[23:0] bits in the RTOR
- register */
- USARTx->RTOR &= (uint32_t)~((uint32_t)USART_RTOR_RTO);
- /* Set the receiver Time Out value by setting the RTO[23:0] bits in the RTOR
- register */
- USARTx->RTOR |= USART_ReceiverTimeOut;
-}
-
-/**
- * @brief Sets the system clock prescaler.
- * @note This function is not available for STM32F030 devices.
- * @param USARTx: where x can be 1or 2 to select the USART peripheral.
- * @note USART2 is available only for STM32F072 devices.
- * @param USART_Prescaler: specifies the prescaler clock.
- * @note This function has to be called before calling USART_Cmd() function.
- * @retval None
- */
-void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler)
-{
- /* Check the parameters */
- assert_param(IS_USART_12_PERIPH(USARTx));
-
- /* Clear the USART prescaler */
- USARTx->GTPR &= USART_GTPR_GT;
- /* Set the USART prescaler */
- USARTx->GTPR |= USART_Prescaler;
-}
-
-/**
- * @}
- */
-
-
-/** @defgroup USART_Group2 STOP Mode functions
- * @brief STOP Mode functions
- *
-@verbatim
- ===============================================================================
- ##### STOP Mode functions #####
- ===============================================================================
- [..] This subsection provides a set of functions allowing to manage
- WakeUp from STOP mode.
-
- [..] The USART is able to WakeUp from Stop Mode if USART clock is set to HSI
- or LSI.
-
- [..] The WakeUp source is configured by calling USART_StopModeWakeUpSourceConfig()
- function.
-
- [..] After configuring the source of WakeUp and before entering in Stop Mode
- USART_STOPModeCmd() function should be called to allow USART WakeUp.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the specified USART peripheral in STOP Mode.
- * @param USARTx: where x can be 1or 2 to select the USART peripheral.
- * @note USART2 is available only for STM32F072 devices.
- * @param NewState: new state of the USARTx peripheral state in stop mode.
- * This parameter can be: ENABLE or DISABLE.
- * @note This function has to be called when USART clock is set to HSI or LSE.
- * @retval None
- */
-void USART_STOPModeCmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_12_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected USART in STOP mode by setting the UESM bit in the CR1
- register */
- USARTx->CR1 |= USART_CR1_UESM;
- }
- else
- {
- /* Disable the selected USART in STOP mode by clearing the UE bit in the CR1
- register */
- USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_UESM);
- }
-}
-
-/**
- * @brief Selects the USART WakeUp method form stop mode.
- * @note This function is not available for STM32F030 devices.
- * @param USARTx: where x can be 1or 2 to select the USART peripheral.
- * @note USART2 is available only for STM32F072 devices.
- * @param USART_WakeUp: specifies the selected USART wakeup method.
- * This parameter can be one of the following values:
- * @arg USART_WakeUpSource_AddressMatch: WUF active on address match.
- * @arg USART_WakeUpSource_StartBit: WUF active on Start bit detection.
- * @arg USART_WakeUpSource_RXNE: WUF active on RXNE.
- * @note This function has to be called before calling USART_Cmd() function.
- * @retval None
- */
-void USART_StopModeWakeUpSourceConfig(USART_TypeDef* USARTx, uint32_t USART_WakeUpSource)
-{
- /* Check the parameters */
- assert_param(IS_USART_12_PERIPH(USARTx));
- assert_param(IS_USART_STOPMODE_WAKEUPSOURCE(USART_WakeUpSource));
-
- USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_WUS);
- USARTx->CR3 |= USART_WakeUpSource;
-}
-
-/**
- * @}
- */
-
-
-/** @defgroup USART_Group3 AutoBaudRate functions
- * @brief AutoBaudRate functions
- *
-@verbatim
- ===============================================================================
- ##### AutoBaudRate functions #####
- ===============================================================================
- [..] This subsection provides a set of functions allowing to manage
- the AutoBaudRate detections.
-
- [..] Before Enabling AutoBaudRate detection using USART_AutoBaudRateCmd ()
- The character patterns used to calculate baudrate must be chosen by calling
- USART_AutoBaudRateConfig() function. These function take as parameter :
- (#)USART_AutoBaudRate_StartBit : any character starting with a bit 1.
- (#)USART_AutoBaudRate_FallingEdge : any character starting with a 10xx bit pattern.
-
- [..] At any later time, another request for AutoBaudRate detection can be performed
- using USART_RequestCmd() function.
-
- [..] The AutoBaudRate detection is monitored by the status of ABRF flag which indicate
- that the AutoBaudRate detection is completed. In addition to ABRF flag, the ABRE flag
- indicate that this procedure is completed without success. USART_GetFlagStatus ()
- function should be used to monitor the status of these flags.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the Auto Baud Rate.
- * @param USARTx: where x can be 1or 2 to select the USART peripheral.
- * @note USART2 is available only for STM32F072 devices.
- * @param NewState: new state of the USARTx auto baud rate.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_AutoBaudRateCmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_12_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the auto baud rate feature by setting the ABREN bit in the CR2
- register */
- USARTx->CR2 |= USART_CR2_ABREN;
- }
- else
- {
- /* Disable the auto baud rate feature by clearing the ABREN bit in the CR2
- register */
- USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_ABREN);
- }
-}
-
-/**
- * @brief Selects the USART auto baud rate method.
- * @param USARTx: where x can be 1or 2 to select the USART peripheral.
- * @note USART2 is available only for STM32F072 devices.
- * @param USART_AutoBaudRate: specifies the selected USART auto baud rate method.
- * This parameter can be one of the following values:
- * @arg USART_AutoBaudRate_StartBit: Start Bit duration measurement.
- * @arg USART_AutoBaudRate_FallingEdge: Falling edge to falling edge measurement.
- * @note This function has to be called before calling USART_Cmd() function.
- * @retval None
- */
-void USART_AutoBaudRateConfig(USART_TypeDef* USARTx, uint32_t USART_AutoBaudRate)
-{
- /* Check the parameters */
- assert_param(IS_USART_12_PERIPH(USARTx));
- assert_param(IS_USART_AUTOBAUDRATE_MODE(USART_AutoBaudRate));
-
- USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_ABRMODE);
- USARTx->CR2 |= USART_AutoBaudRate;
-}
-
-/**
- * @}
- */
-
-
-/** @defgroup USART_Group4 Data transfers functions
- * @brief Data transfers functions
- *
-@verbatim
- ===============================================================================
- ##### Data transfers functions #####
- ===============================================================================
- [..] This subsection provides a set of functions allowing to manage
- the USART data transfers.
- [..] During an USART reception, data shifts in least significant bit first
- through the RX pin. When a transmission is taking place, a write instruction to
- the USART_TDR register stores the data in the shift register.
- [..] The read access of the USART_RDR register can be done using
- the USART_ReceiveData() function and returns the RDR value.
- Whereas a write access to the USART_TDR can be done using USART_SendData()
- function and stores the written data into TDR.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Transmits single data through the USARTx peripheral.
- * @param USARTx: where x can be 1, 2, 3 or 4 to select the USART peripheral.
- * @note USART3 and USART4 are available only for STM32F072 devices.
- * @note USART2 is not available for STM32F031 devices.
- * @param Data: the data to transmit.
- * @retval None
- */
-void USART_SendData(USART_TypeDef* USARTx, uint16_t Data)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_DATA(Data));
-
- /* Transmit Data */
- USARTx->TDR = (Data & (uint16_t)0x01FF);
-}
-
-/**
- * @brief Returns the most recent received data by the USARTx peripheral.
- * @param USARTx: where x can be 1, 2, 3 or 4 to select the USART peripheral.
- * @note USART3 and USART4 are available only for STM32F072 devices.
- * @note USART2 is not available for STM32F031 devices.
- * @retval The received data.
- */
-uint16_t USART_ReceiveData(USART_TypeDef* USARTx)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
-
- /* Receive Data */
- return (uint16_t)(USARTx->RDR & (uint16_t)0x01FF);
-}
-
-/**
- * @}
- */
-
-/** @defgroup USART_Group5 MultiProcessor Communication functions
- * @brief Multi-Processor Communication functions
- *
-@verbatim
- ===============================================================================
- ##### Multi-Processor Communication functions #####
- ===============================================================================
- [..] This subsection provides a set of functions allowing to manage the USART
- multiprocessor communication.
- [..] For instance one of the USARTs can be the master, its TX output is
- connected to the RX input of the other USART. The others are slaves,
- their respective TX outputs are logically ANDed together and connected
- to the RX input of the master. USART multiprocessor communication is
- possible through the following procedure:
- (#) Program the Baud rate, Word length = 9 bits, Stop bits, Parity,
- Mode transmitter or Mode receiver and hardware flow control values
- using the USART_Init() function.
- (#) Configures the USART address using the USART_SetAddress() function.
- (#) Configures the wake up methode (USART_WakeUp_IdleLine or
- USART_WakeUp_AddressMark) using USART_WakeUpConfig() function only
- for the slaves.
- (#) Enable the USART using the USART_Cmd() function.
- (#) Enter the USART slaves in mute mode using USART_ReceiverWakeUpCmd()
- function.
- [..] The USART Slave exit from mute mode when receive the wake up condition.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Sets the address of the USART node.
- * @param USARTx: where x can be 1, 2, 3 or 4 to select the USART peripheral.
- * @note USART3 and USART4 are available only for STM32F072 devices.
- * @note USART2 is not available for STM32F031 devices.
- * @param USART_Address: Indicates the address of the USART node.
- * @retval None
- */
-void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
-
- /* Clear the USART address */
- USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_ADD);
- /* Set the USART address node */
- USARTx->CR2 |=((uint32_t)USART_Address << (uint32_t)0x18);
-}
-
-/**
- * @brief Enables or disables the USART's mute mode.
- * @param USARTx: where x can be 1, 2, 3 or 4 to select the USART peripheral.
- * @note USART3 and USART4 are available only for STM32F072 devices.
- * @note USART2 is not available for STM32F031 devices.
- * @param NewState: new state of the USART mute mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_MuteModeCmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the USART mute mode by setting the MME bit in the CR1 register */
- USARTx->CR1 |= USART_CR1_MME;
- }
- else
- {
- /* Disable the USART mute mode by clearing the MME bit in the CR1 register */
- USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_MME);
- }
-}
-
-/**
- * @brief Selects the USART WakeUp method from mute mode.
- * @param USARTx: where x can be 1, 2, 3 or 4 to select the USART peripheral.
- * @note USART3 and USART4 are available only for STM32F072 devices.
- * @note USART2 is not available for STM32F031 devices.
- * @param USART_WakeUp: specifies the USART wakeup method.
- * This parameter can be one of the following values:
- * @arg USART_WakeUp_IdleLine: WakeUp by an idle line detection
- * @arg USART_WakeUp_AddressMark: WakeUp by an address mark
- * @retval None
- */
-void USART_MuteModeWakeUpConfig(USART_TypeDef* USARTx, uint32_t USART_WakeUp)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_MUTEMODE_WAKEUP(USART_WakeUp));
-
- USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_WAKE);
- USARTx->CR1 |= USART_WakeUp;
-}
-
-/**
- * @brief Configure the the USART Address detection length.
- * @param USARTx: where x can be 1, 2, 3 or 4 to select the USART peripheral.
- * @note USART3 and USART4 are available only for STM32F072 devices.
- * @note USART2 is not available for STM32F031 devices.
- * @param USART_AddressLength: specifies the USART address length detection.
- * This parameter can be one of the following values:
- * @arg USART_AddressLength_4b: 4-bit address length detection
- * @arg USART_AddressLength_7b: 7-bit address length detection
- * @retval None
- */
-void USART_AddressDetectionConfig(USART_TypeDef* USARTx, uint32_t USART_AddressLength)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_ADDRESS_DETECTION(USART_AddressLength));
-
- USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_ADDM7);
- USARTx->CR2 |= USART_AddressLength;
-}
-
-/**
- * @}
- */
-
-/** @defgroup USART_Group6 LIN mode functions
- * @brief LIN mode functions
- *
-@verbatim
- ===============================================================================
- ##### LIN mode functions #####
- ===============================================================================
- [..] This subsection provides a set of functions allowing to manage the USART
- LIN Mode communication.
- [..] In LIN mode, 8-bit data format with 1 stop bit is required in accordance
- with the LIN standard.
- [..] Only this LIN Feature is supported by the USART IP:
- (+) LIN Master Synchronous Break send capability and LIN slave break
- detection capability : 13-bit break generation and 10/11 bit break
- detection.
- [..] USART LIN Master transmitter communication is possible through the
- following procedure:
- (#) Program the Baud rate, Word length = 8bits, Stop bits = 1bit, Parity,
- Mode transmitter or Mode receiver and hardware flow control values
- using the USART_Init() function.
- (#) Enable the LIN mode using the USART_LINCmd() function.
- (#) Enable the USART using the USART_Cmd() function.
- (#) Send the break character using USART_SendBreak() function.
- [..] USART LIN Master receiver communication is possible through the
- following procedure:
- (#) Program the Baud rate, Word length = 8bits, Stop bits = 1bit, Parity,
- Mode transmitter or Mode receiver and hardware flow control values
- using the USART_Init() function.
- (#) Configures the break detection length
- using the USART_LINBreakDetectLengthConfig() function.
- (#) Enable the LIN mode using the USART_LINCmd() function.
- -@- In LIN mode, the following bits must be kept cleared:
- (+@) CLKEN in the USART_CR2 register.
- (+@) STOP[1:0], SCEN, HDSEL and IREN in the USART_CR3 register.
- (#) Enable the USART using the USART_Cmd() function.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Sets the USART LIN Break detection length.
- * @note This function is not available for STM32F030 devices.
- * @param USARTx: where x can be 1or 2 to select the USART peripheral.
- * @note USART2 is available only for STM32F072 devices.
- * @param USART_LINBreakDetectLength: specifies the LIN break detection length.
- * This parameter can be one of the following values:
- * @arg USART_LINBreakDetectLength_10b: 10-bit break detection
- * @arg USART_LINBreakDetectLength_11b: 11-bit break detection
- * @retval None
- */
-void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint32_t USART_LINBreakDetectLength)
-{
- /* Check the parameters */
- assert_param(IS_USART_12_PERIPH(USARTx));
- assert_param(IS_USART_LIN_BREAK_DETECT_LENGTH(USART_LINBreakDetectLength));
-
- USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_LBDL);
- USARTx->CR2 |= USART_LINBreakDetectLength;
-}
-
-/**
- * @brief Enables or disables the USART's LIN mode.
- * @note This function is not available for STM32F030 devices.
- * @param USARTx: where x can be 1or 2 to select the USART peripheral.
- * @note USART2 is available only for STM32F072 devices.
- * @param NewState: new state of the USART LIN mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_12_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the LIN mode by setting the LINEN bit in the CR2 register */
- USARTx->CR2 |= USART_CR2_LINEN;
- }
- else
- {
- /* Disable the LIN mode by clearing the LINEN bit in the CR2 register */
- USARTx->CR2 &= (uint32_t)~((uint32_t)USART_CR2_LINEN);
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup USART_Group7 Halfduplex mode function
- * @brief Half-duplex mode function
- *
-@verbatim
- ===============================================================================
- ##### Half-duplex mode function #####
- ===============================================================================
- [..] This subsection provides a set of functions allowing to manage the USART
- Half-duplex communication.
- [..] The USART can be configured to follow a single-wire half-duplex protocol
- where the TX and RX lines are internally connected.
- [..] USART Half duplex communication is possible through the following procedure:
- (#) Program the Baud rate, Word length, Stop bits, Parity, Mode transmitter
- or Mode receiver and hardware flow control values using the USART_Init()
- function.
- (#) Configures the USART address using the USART_SetAddress() function.
- (#) Enable the half duplex mode using USART_HalfDuplexCmd() function.
- (#) Enable the USART using the USART_Cmd() function.
- -@- The RX pin is no longer used.
- -@- In Half-duplex mode the following bits must be kept cleared:
- (+@) LINEN and CLKEN bits in the USART_CR2 register.
- (+@) SCEN and IREN bits in the USART_CR3 register.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the USART's Half Duplex communication.
- * @param USARTx: where x can be 1, 2, 3 or 4 to select the USART peripheral.
- * @note USART3 and USART4 are available only for STM32F072 devices.
- * @note USART2 is not available for STM32F031 devices.
- * @param NewState: new state of the USART Communication.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */
- USARTx->CR3 |= USART_CR3_HDSEL;
- }
- else
- {
- /* Disable the Half-Duplex mode by clearing the HDSEL bit in the CR3 register */
- USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_HDSEL);
- }
-}
-
-/**
- * @}
- */
-
-
-/** @defgroup USART_Group8 Smartcard mode functions
- * @brief Smartcard mode functions
- *
-@verbatim
- ===============================================================================
- ##### Smartcard mode functions #####
- ===============================================================================
- [..] This subsection provides a set of functions allowing to manage the USART
- Smartcard communication.
- [..] The Smartcard interface is designed to support asynchronous protocol
- Smartcards as defined in the ISO 7816-3 standard. The USART can provide
- a clock to the smartcard through the SCLK output. In smartcard mode,
- SCLK is not associated to the communication but is simply derived from
- the internal peripheral input clock through a 5-bit prescaler.
- [..] Smartcard communication is possible through the following procedure:
- (#) Configures the Smartcard Prsecaler using the USART_SetPrescaler()
- function.
- (#) Configures the Smartcard Guard Time using the USART_SetGuardTime()
- function.
- (#) Program the USART clock using the USART_ClockInit() function as following:
- (++) USART Clock enabled.
- (++) USART CPOL Low.
- (++) USART CPHA on first edge.
- (++) USART Last Bit Clock Enabled.
- (#) Program the Smartcard interface using the USART_Init() function as
- following:
- (++) Word Length = 9 Bits.
- (++) 1.5 Stop Bit.
- (++) Even parity.
- (++) BaudRate = 12096 baud.
- (++) Hardware flow control disabled (RTS and CTS signals).
- (++) Tx and Rx enabled
- (#) Optionally you can enable the parity error interrupt using
- the USART_ITConfig() function.
- (#) Enable the Smartcard NACK using the USART_SmartCardNACKCmd() function.
- (#) Enable the Smartcard interface using the USART_SmartCardCmd() function.
- (#) Enable the USART using the USART_Cmd() function.
- [..]
- Please refer to the ISO 7816-3 specification for more details.
- [..]
- (@) It is also possible to choose 0.5 stop bit for receiving but it is
- recommended to use 1.5 stop bits for both transmitting and receiving
- to avoid switching between the two configurations.
- (@) In smartcard mode, the following bits must be kept cleared:
- (+@) LINEN bit in the USART_CR2 register.
- (+@) HDSEL and IREN bits in the USART_CR3 register.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Sets the specified USART guard time.
- * @note This function is not available for STM32F030 devices.
- * @param USARTx: where x can be 1or 2 to select the USART peripheral.
- * @note USART2 is applicable only for STM32F072 devices.
- * @param USART_GuardTime: specifies the guard time.
- * @retval None
- */
-void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime)
-{
- /* Check the parameters */
- assert_param(IS_USART_12_PERIPH(USARTx));
-
- /* Clear the USART Guard time */
- USARTx->GTPR &= USART_GTPR_PSC;
- /* Set the USART guard time */
- USARTx->GTPR |= (uint16_t)((uint16_t)USART_GuardTime << 0x08);
-}
-
-/**
- * @brief Enables or disables the USART's Smart Card mode.
- * @note This function is not available for STM32F030 devices.
- * @param USARTx: where x can be 1or 2 to select the USART peripheral.
- * @note USART2 is applicable only for STM32F072 devices.
- * @param NewState: new state of the Smart Card mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_12_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the SC mode by setting the SCEN bit in the CR3 register */
- USARTx->CR3 |= USART_CR3_SCEN;
- }
- else
- {
- /* Disable the SC mode by clearing the SCEN bit in the CR3 register */
- USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_SCEN);
- }
-}
-
-/**
- * @brief Enables or disables NACK transmission.
- * @note This function is not available for STM32F030 devices.
- * @param USARTx: where x can be 1or 2 to select the USART peripheral.
- * @note USART2 is applicable only for STM32F072 devices.
- * @param NewState: new state of the NACK transmission.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_12_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the NACK transmission by setting the NACK bit in the CR3 register */
- USARTx->CR3 |= USART_CR3_NACK;
- }
- else
- {
- /* Disable the NACK transmission by clearing the NACK bit in the CR3 register */
- USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_NACK);
- }
-}
-
-/**
- * @brief Sets the Smart Card number of retries in transmit and receive.
- * @note This function is not available for STM32F030 devices.
- * @param USARTx: where x can be 1or 2 to select the USART peripheral.
- * @note USART2 is applicable only for STM32F072 devices.
- * @param USART_AutoCount: specifies the Smart Card auto retry count.
- * @retval None
- */
-void USART_SetAutoRetryCount(USART_TypeDef* USARTx, uint8_t USART_AutoCount)
-{
- /* Check the parameters */
- assert_param(IS_USART_12_PERIPH(USARTx));
- assert_param(IS_USART_AUTO_RETRY_COUNTER(USART_AutoCount));
- /* Clear the USART auto retry count */
- USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_SCARCNT);
- /* Set the USART auto retry count*/
- USARTx->CR3 |= (uint32_t)((uint32_t)USART_AutoCount << 0x11);
-}
-
-/**
- * @brief Sets the Smart Card Block length.
- * @note This function is not available for STM32F030 devices.
- * @param USARTx: where x can be 1or 2 to select the USART peripheral.
- * @note USART2 is applicable only for STM32F072 devices.
- * @param USART_BlockLength: specifies the Smart Card block length.
- * @retval None
- */
-void USART_SetBlockLength(USART_TypeDef* USARTx, uint8_t USART_BlockLength)
-{
- /* Check the parameters */
- assert_param(IS_USART_12_PERIPH(USARTx));
-
- /* Clear the Smart card block length */
- USARTx->RTOR &= (uint32_t)~((uint32_t)USART_RTOR_BLEN);
- /* Set the Smart Card block length */
- USARTx->RTOR |= (uint32_t)((uint32_t)USART_BlockLength << 0x18);
-}
-
-/**
- * @}
- */
-
-/** @defgroup USART_Group9 IrDA mode functions
- * @brief IrDA mode functions
- *
-@verbatim
- ===============================================================================
- ##### IrDA mode functions #####
- ===============================================================================
- [..] This subsection provides a set of functions allowing to manage the USART
- IrDA communication.
- [..] IrDA is a half duplex communication protocol. If the Transmitter is busy,
- any data on the IrDA receive line will be ignored by the IrDA decoder
- and if the Receiver is busy, data on the TX from the USART to IrDA will
- not be encoded by IrDA. While receiving data, transmission should be
- avoided as the data to be transmitted could be corrupted.
- [..] IrDA communication is possible through the following procedure:
- (#) Program the Baud rate, Word length = 8 bits, Stop bits, Parity,
- Transmitter/Receiver modes and hardware flow control values using
- the USART_Init() function.
- (#) Configures the IrDA pulse width by configuring the prescaler using
- the USART_SetPrescaler() function.
- (#) Configures the IrDA USART_IrDAMode_LowPower or USART_IrDAMode_Normal
- mode using the USART_IrDAConfig() function.
- (#) Enable the IrDA using the USART_IrDACmd() function.
- (#) Enable the USART using the USART_Cmd() function.
- [..]
- (@) A pulse of width less than two and greater than one PSC period(s) may or
- may not be rejected.
- (@) The receiver set up time should be managed by software. The IrDA physical
- layer specification specifies a minimum of 10 ms delay between
- transmission and reception (IrDA is a half duplex protocol).
- (@) In IrDA mode, the following bits must be kept cleared:
- (+@) LINEN, STOP and CLKEN bits in the USART_CR2 register.
- (+@) SCEN and HDSEL bits in the USART_CR3 register.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Configures the USART's IrDA interface.
- * @note This function is not available for STM32F030 devices.
- * @param USARTx: where x can be 1or 2 to select the USART peripheral.
- * @note USART2 is applicable only for STM32F072 devices.
- * @param USART_IrDAMode: specifies the IrDA mode.
- * This parameter can be one of the following values:
- * @arg USART_IrDAMode_LowPower
- * @arg USART_IrDAMode_Normal
- * @retval None
- */
-void USART_IrDAConfig(USART_TypeDef* USARTx, uint32_t USART_IrDAMode)
-{
- /* Check the parameters */
- assert_param(IS_USART_12_PERIPH(USARTx));
- assert_param(IS_USART_IRDA_MODE(USART_IrDAMode));
-
- USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_IRLP);
- USARTx->CR3 |= USART_IrDAMode;
-}
-
-/**
- * @brief Enables or disables the USART's IrDA interface.
- * @note This function is not available for STM32F030 devices.
- * @param USARTx: where x can be 1or 2 to select the USART peripheral.
- * @note USART2 is applicable only for STM32F072 devices.
- * @param NewState: new state of the IrDA mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_12_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the IrDA mode by setting the IREN bit in the CR3 register */
- USARTx->CR3 |= USART_CR3_IREN;
- }
- else
- {
- /* Disable the IrDA mode by clearing the IREN bit in the CR3 register */
- USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_IREN);
- }
-}
-/**
- * @}
- */
-
-/** @defgroup USART_Group10 RS485 mode function
- * @brief RS485 mode function
- *
-@verbatim
- ===============================================================================
- ##### RS485 mode functions #####
- ===============================================================================
- [..] This subsection provides a set of functions allowing to manage the USART
- RS485 flow control.
- [..] RS485 flow control (Driver enable feature) handling is possible through
- the following procedure:
- (#) Program the Baud rate, Word length = 8 bits, Stop bits, Parity,
- Transmitter/Receiver modes and hardware flow control values using
- the USART_Init() function.
- (#) Enable the Driver Enable using the USART_DECmd() function.
- (#) Configures the Driver Enable polarity using the USART_DEPolarityConfig()
- function.
- (#) Configures the Driver Enable assertion time using USART_SetDEAssertionTime()
- function and deassertion time using the USART_SetDEDeassertionTime()
- function.
- (#) Enable the USART using the USART_Cmd() function.
- -@-
- (+@) The assertion and dessertion times are expressed in sample time units (1/8 or
- 1/16 bit time, depending on the oversampling rate).
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the USART's DE functionality.
- * @param USARTx: where x can be 1, 2, 3 or 4 to select the USART peripheral.
- * @note USART3 and USART4 are available only for STM32F072 devices.
- * @note USART2 is not available for STM32F031 devices.
- * @param NewState: new state of the driver enable mode.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_DECmd(USART_TypeDef* USARTx, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- if (NewState != DISABLE)
- {
- /* Enable the DE functionality by setting the DEM bit in the CR3 register */
- USARTx->CR3 |= USART_CR3_DEM;
- }
- else
- {
- /* Disable the DE functionality by clearing the DEM bit in the CR3 register */
- USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DEM);
- }
-}
-
-/**
- * @brief Configures the USART's DE polarity
- * @param USARTx: where x can be 1, 2, 3 or 4 to select the USART peripheral.
- * @note USART3 and USART4 are available only for STM32F072 devices.
- * @note USART2 is not available for STM32F031 devices.
- * @param USART_DEPolarity: specifies the DE polarity.
- * This parameter can be one of the following values:
- * @arg USART_DEPolarity_Low
- * @arg USART_DEPolarity_High
- * @retval None
- */
-void USART_DEPolarityConfig(USART_TypeDef* USARTx, uint32_t USART_DEPolarity)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_DE_POLARITY(USART_DEPolarity));
-
- USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DEP);
- USARTx->CR3 |= USART_DEPolarity;
-}
-
-/**
- * @brief Sets the specified RS485 DE assertion time
- * @param USARTx: where x can be 1, 2, 3 or 4 to select the USART peripheral.
- * @note USART3 and USART4 are available only for STM32F072 devices.
- * @note USART2 is not available for STM32F031 devices.
- * @param USART_DEAssertionTime: specifies the time between the activation of
- * the DE signal and the beginning of the start bit
- * @retval None
- */
-void USART_SetDEAssertionTime(USART_TypeDef* USARTx, uint32_t USART_DEAssertionTime)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_DE_ASSERTION_DEASSERTION_TIME(USART_DEAssertionTime));
-
- /* Clear the DE assertion time */
- USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_DEAT);
- /* Set the new value for the DE assertion time */
- USARTx->CR1 |=((uint32_t)USART_DEAssertionTime << (uint32_t)0x15);
-}
-
-/**
- * @brief Sets the specified RS485 DE deassertion time
- * @param USARTx: where x can be 1, 2, 3 or 4 to select the USART peripheral.
- * @note USART3 and USART4 are available only for STM32F072 devices.
- * @note USART2 is not available for STM32F031 devices.
- * @param USART_DeassertionTime: specifies the time between the middle of the last
- * stop bit in a transmitted message and the de-activation of the DE signal
- * @retval None
- */
-void USART_SetDEDeassertionTime(USART_TypeDef* USARTx, uint32_t USART_DEDeassertionTime)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_DE_ASSERTION_DEASSERTION_TIME(USART_DEDeassertionTime));
-
- /* Clear the DE deassertion time */
- USARTx->CR1 &= (uint32_t)~((uint32_t)USART_CR1_DEDT);
- /* Set the new value for the DE deassertion time */
- USARTx->CR1 |=((uint32_t)USART_DEDeassertionTime << (uint32_t)0x10);
-}
-
-/**
- * @}
- */
-
-/** @defgroup USART_Group11 DMA transfers management functions
- * @brief DMA transfers management functions
- *
-@verbatim
- ===============================================================================
- ##### DMA transfers management functions #####
- ===============================================================================
- [..] This section provides two functions that can be used only in DMA mode.
- [..] In DMA Mode, the USART communication can be managed by 2 DMA Channel
- requests:
- (#) USART_DMAReq_Tx: specifies the Tx buffer DMA transfer request.
- (#) USART_DMAReq_Rx: specifies the Rx buffer DMA transfer request.
- [..] In this Mode it is advised to use the following function:
- (+) void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq,
- FunctionalState NewState).
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the USART's DMA interface.
- * @param USARTx: where x can be 1, 2, 3 or 4 to select the USART peripheral.
- * @note USART3 and USART4 are available only for STM32F072 devices.
- * @note USART2 is not available for STM32F031 devices.
- * @param USART_DMAReq: specifies the DMA request.
- * This parameter can be any combination of the following values:
- * @arg USART_DMAReq_Tx: USART DMA transmit request
- * @arg USART_DMAReq_Rx: USART DMA receive request
- * @param NewState: new state of the DMA Request sources.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_DMACmd(USART_TypeDef* USARTx, uint32_t USART_DMAReq, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_DMAREQ(USART_DMAReq));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the DMA transfer for selected requests by setting the DMAT and/or
- DMAR bits in the USART CR3 register */
- USARTx->CR3 |= USART_DMAReq;
- }
- else
- {
- /* Disable the DMA transfer for selected requests by clearing the DMAT and/or
- DMAR bits in the USART CR3 register */
- USARTx->CR3 &= (uint32_t)~USART_DMAReq;
- }
-}
-
-/**
- * @brief Enables or disables the USART's DMA interface when reception error occurs.
- * @param USARTx: where x can be 1, 2, 3 or 4 to select the USART peripheral.
- * @note USART3 and USART4 are available only for STM32F072 devices.
- * @note USART2 is not available for STM32F031 devices.
- * @param USART_DMAOnError: specifies the DMA status in case of reception error.
- * This parameter can be any combination of the following values:
- * @arg USART_DMAOnError_Enable: DMA receive request enabled when the USART DMA
- * reception error is asserted.
- * @arg USART_DMAOnError_Disable: DMA receive request disabled when the USART DMA
- * reception error is asserted.
- * @retval None
- */
-void USART_DMAReceptionErrorConfig(USART_TypeDef* USARTx, uint32_t USART_DMAOnError)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_DMAONERROR(USART_DMAOnError));
-
- /* Clear the DMA Reception error detection bit */
- USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DDRE);
- /* Set the new value for the DMA Reception error detection bit */
- USARTx->CR3 |= USART_DMAOnError;
-}
-
-/**
- * @}
- */
-
-/** @defgroup USART_Group12 Interrupts and flags management functions
- * @brief Interrupts and flags management functions
- *
-@verbatim
- ===============================================================================
- ##### Interrupts and flags management functions #####
- ===============================================================================
- [..] This subsection provides a set of functions allowing to configure the
- USART Interrupts sources, Requests and check or clear the flags or pending bits status.
- The user should identify which mode will be used in his application to
- manage the communication: Polling mode, Interrupt mode.
-
- *** Polling Mode ***
- ====================
- [..] In Polling Mode, the SPI communication can be managed by these flags:
- (#) USART_FLAG_REACK: to indicate the status of the Receive Enable
- acknowledge flag
- (#) USART_FLAG_TEACK: to indicate the status of the Transmit Enable
- acknowledge flag.
- (#) USART_FLAG_WU: to indicate the status of the Wake up flag.
- (#) USART_FLAG_RWU: to indicate the status of the Receive Wake up flag.
- (#) USART_FLAG_SBK: to indicate the status of the Send Break flag.
- (#) USART_FLAG_CM: to indicate the status of the Character match flag.
- (#) USART_FLAG_BUSY: to indicate the status of the Busy flag.
- (#) USART_FLAG_ABRF: to indicate the status of the Auto baud rate flag.
- (#) USART_FLAG_ABRE: to indicate the status of the Auto baud rate error flag.
- (#) USART_FLAG_EOB: to indicate the status of the End of block flag.
- (#) USART_FLAG_RTO: to indicate the status of the Receive time out flag.
- (#) USART_FLAG_nCTSS: to indicate the status of the Inverted nCTS input
- bit status.
- (#) USART_FLAG_TXE: to indicate the status of the transmit buffer register.
- (#) USART_FLAG_RXNE: to indicate the status of the receive buffer register.
- (#) USART_FLAG_TC: to indicate the status of the transmit operation.
- (#) USART_FLAG_IDLE: to indicate the status of the Idle Line.
- (#) USART_FLAG_CTS: to indicate the status of the nCTS input.
- (#) USART_FLAG_LBD: to indicate the status of the LIN break detection.
- (#) USART_FLAG_NE: to indicate if a noise error occur.
- (#) USART_FLAG_FE: to indicate if a frame error occur.
- (#) USART_FLAG_PE: to indicate if a parity error occur.
- (#) USART_FLAG_ORE: to indicate if an Overrun error occur.
- [..] In this Mode it is advised to use the following functions:
- (+) FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG).
- (+) void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG).
-
- *** Interrupt Mode ***
- ======================
- [..] In Interrupt Mode, the USART communication can be managed by 8 interrupt
- sources and 10 pending bits:
- (+) Pending Bits:
- (##) USART_IT_WU: to indicate the status of the Wake up interrupt.
- (##) USART_IT_CM: to indicate the status of Character match interrupt.
- (##) USART_IT_EOB: to indicate the status of End of block interrupt.
- (##) USART_IT_RTO: to indicate the status of Receive time out interrupt.
- (##) USART_IT_CTS: to indicate the status of CTS change interrupt.
- (##) USART_IT_LBD: to indicate the status of LIN Break detection interrupt.
- (##) USART_IT_TC: to indicate the status of Transmission complete interrupt.
- (##) USART_IT_IDLE: to indicate the status of IDLE line detected interrupt.
- (##) USART_IT_ORE: to indicate the status of OverRun Error interrupt.
- (##) USART_IT_NE: to indicate the status of Noise Error interrupt.
- (##) USART_IT_FE: to indicate the status of Framing Error interrupt.
- (##) USART_IT_PE: to indicate the status of Parity Error interrupt.
-
- (+) Interrupt Source:
- (##) USART_IT_WU: specifies the interrupt source for Wake up interrupt.
- (##) USART_IT_CM: specifies the interrupt source for Character match
- interrupt.
- (##) USART_IT_EOB: specifies the interrupt source for End of block
- interrupt.
- (##) USART_IT_RTO: specifies the interrupt source for Receive time-out
- interrupt.
- (##) USART_IT_CTS: specifies the interrupt source for CTS change interrupt.
- (##) USART_IT_LBD: specifies the interrupt source for LIN Break
- detection interrupt.
- (##) USART_IT_TXE: specifies the interrupt source for Tansmit Data
- Register empty interrupt.
- (##) USART_IT_TC: specifies the interrupt source for Transmission
- complete interrupt.
- (##) USART_IT_RXNE: specifies the interrupt source for Receive Data
- register not empty interrupt.
- (##) USART_IT_IDLE: specifies the interrupt source for Idle line
- detection interrupt.
- (##) USART_IT_PE: specifies the interrupt source for Parity Error interrupt.
- (##) USART_IT_ERR: specifies the interrupt source for Error interrupt
- (Frame error, noise error, overrun error)
- -@@- Some parameters are coded in order to use them as interrupt
- source or as pending bits.
- [..] In this Mode it is advised to use the following functions:
- (+) void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState).
- (+) ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT).
- (+) void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT).
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the specified USART interrupts.
- * @param USARTx: where x can be 1, 2, 3 or 4 to select the USART peripheral.
- * @note USART3 and USART4 are available only for STM32F072 devices.
- * @note USART2 is not available for STM32F031 devices.
- * @param USART_IT: specifies the USART interrupt sources to be enabled or disabled.
- * This parameter can be one of the following values:
- * @arg USART_IT_WU: Wake up interrupt, not available for STM32F030 devices.
- * @arg USART_IT_CM: Character match interrupt.
- * @arg USART_IT_EOB: End of block interrupt, not available for STM32F030 devices.
- * @arg USART_IT_RTO: Receive time out interrupt.
- * @arg USART_IT_CTS: CTS change interrupt.
- * @arg USART_IT_LBD: LIN Break detection interrupt, not available for STM32F030 devices.
- * @arg USART_IT_TXE: Tansmit Data Register empty interrupt.
- * @arg USART_IT_TC: Transmission complete interrupt.
- * @arg USART_IT_RXNE: Receive Data register not empty interrupt.
- * @arg USART_IT_IDLE: Idle line detection interrupt.
- * @arg USART_IT_PE: Parity Error interrupt.
- * @arg USART_IT_ERR: Error interrupt(Frame error, noise error, overrun error)
- * @param NewState: new state of the specified USARTx interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_ITConfig(USART_TypeDef* USARTx, uint32_t USART_IT, FunctionalState NewState)
-{
- uint32_t usartreg = 0, itpos = 0, itmask = 0;
- uint32_t usartxbase = 0;
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_CONFIG_IT(USART_IT));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- usartxbase = (uint32_t)USARTx;
-
- /* Get the USART register index */
- usartreg = (((uint16_t)USART_IT) >> 0x08);
-
- /* Get the interrupt position */
- itpos = USART_IT & IT_MASK;
- itmask = (((uint32_t)0x01) << itpos);
-
- if (usartreg == 0x02) /* The IT is in CR2 register */
- {
- usartxbase += 0x04;
- }
- else if (usartreg == 0x03) /* The IT is in CR3 register */
- {
- usartxbase += 0x08;
- }
- else /* The IT is in CR1 register */
- {
- }
- if (NewState != DISABLE)
- {
- *(__IO uint32_t*)usartxbase |= itmask;
- }
- else
- {
- *(__IO uint32_t*)usartxbase &= ~itmask;
- }
-}
-
-/**
- * @brief Enables the specified USART's Request.
- * @param USARTx: where x can be 1, 2, 3 or 4 to select the USART peripheral.
- * @note USART3 and USART4 are available only for STM32F072 devices.
- * @note USART2 is not available for STM32F031 devices.
- * @param USART_Request: specifies the USART request.
- * This parameter can be any combination of the following values:
- * @arg USART_Request_TXFRQ: Transmit data flush ReQuest
- * @arg USART_Request_RXFRQ: Receive data flush ReQuest
- * @arg USART_Request_MMRQ: Mute Mode ReQuest
- * @arg USART_Request_SBKRQ: Send Break ReQuest
- * @arg USART_Request_ABRRQ: Auto Baud Rate ReQuest
- * @param NewState: new state of the DMA interface when reception error occurs.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void USART_RequestCmd(USART_TypeDef* USARTx, uint32_t USART_Request, FunctionalState NewState)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_REQUEST(USART_Request));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the USART ReQuest by setting the dedicated request bit in the RQR
- register.*/
- USARTx->RQR |= USART_Request;
- }
- else
- {
- /* Disable the USART ReQuest by clearing the dedicated request bit in the RQR
- register.*/
- USARTx->RQR &= (uint32_t)~USART_Request;
- }
-}
-
-/**
- * @brief Enables or disables the USART's Overrun detection.
- * @param USARTx: where x can be 1, 2, 3 or 4 to select the USART peripheral.
- * @note USART3 and USART4 are available only for STM32F072 devices.
- * @note USART2 is not available for STM32F031 devices.
- * @param USART_OVRDetection: specifies the OVR detection status in case of OVR error.
- * This parameter can be any combination of the following values:
- * @arg USART_OVRDetection_Enable: OVR error detection enabled when
- * the USART OVR error is asserted.
- * @arg USART_OVRDetection_Disable: OVR error detection disabled when
- * the USART OVR error is asserted.
- * @retval None
- */
-void USART_OverrunDetectionConfig(USART_TypeDef* USARTx, uint32_t USART_OVRDetection)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_OVRDETECTION(USART_OVRDetection));
-
- /* Clear the OVR detection bit */
- USARTx->CR3 &= (uint32_t)~((uint32_t)USART_CR3_OVRDIS);
- /* Set the new value for the OVR detection bit */
- USARTx->CR3 |= USART_OVRDetection;
-}
-
-/**
- * @brief Checks whether the specified USART flag is set or not.
- * @param USARTx: where x can be 1, 2, 3 or 4 to select the USART peripheral.
- * @note USART3 and USART4 are available only for STM32F072 devices.
- * @note USART2 is not available for STM32F031 devices.
- * @param USART_FLAG: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg USART_FLAG_REACK: Receive Enable acknowledge flag.
- * @arg USART_FLAG_TEACK: Transmit Enable acknowledge flag.
- * @arg USART_FLAG_WU: Wake up flag, not available for STM32F030 devices.
- * @arg USART_FLAG_RWU: Receive Wake up flag, not available for STM32F030 devices.
- * @arg USART_FLAG_SBK: Send Break flag.
- * @arg USART_FLAG_CM: Character match flag.
- * @arg USART_FLAG_BUSY: Busy flag.
- * @arg USART_FLAG_ABRF: Auto baud rate flag.
- * @arg USART_FLAG_ABRE: Auto baud rate error flag.
- * @arg USART_FLAG_EOB: End of block flag, not available for STM32F030 devices.
- * @arg USART_FLAG_RTO: Receive time out flag.
- * @arg USART_FLAG_nCTSS: Inverted nCTS input bit status.
- * @arg USART_FLAG_CTS: CTS Change flag.
- * @arg USART_FLAG_LBD: LIN Break detection flag, not available for STM32F030 devices.
- * @arg USART_FLAG_TXE: Transmit data register empty flag.
- * @arg USART_FLAG_TC: Transmission Complete flag.
- * @arg USART_FLAG_RXNE: Receive data register not empty flag.
- * @arg USART_FLAG_IDLE: Idle Line detection flag.
- * @arg USART_FLAG_ORE: OverRun Error flag.
- * @arg USART_FLAG_NE: Noise Error flag.
- * @arg USART_FLAG_FE: Framing Error flag.
- * @arg USART_FLAG_PE: Parity Error flag.
- * @retval The new state of USART_FLAG (SET or RESET).
- */
-FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint32_t USART_FLAG)
-{
- FlagStatus bitstatus = RESET;
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_FLAG(USART_FLAG));
-
- if ((USARTx->ISR & USART_FLAG) != (uint16_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Clears the USARTx's pending flags.
- * @param USARTx: where x can be 1, 2, 3 or 4 to select the USART peripheral.
- * @note USART3 and USART4 are available only for STM32F072 devices.
- * @note USART2 is not available for STM32F031 devices.
- * @param USART_FLAG: specifies the flag to clear.
- * This parameter can be any combination of the following values:
- * @arg USART_FLAG_WU: Wake up flag, not available for STM32F030 devices.
- * @arg USART_FLAG_CM: Character match flag.
- * @arg USART_FLAG_EOB: End of block flag, not available for STM32F030 devices.
- * @arg USART_FLAG_RTO: Receive time out flag.
- * @arg USART_FLAG_CTS: CTS Change flag.
- * @arg USART_FLAG_LBD: LIN Break detection flag, not available for STM32F030 devices.
- * @arg USART_FLAG_TC: Transmission Complete flag.
- * @arg USART_FLAG_IDLE: IDLE line detected flag.
- * @arg USART_FLAG_ORE: OverRun Error flag.
- * @arg USART_FLAG_NE: Noise Error flag.
- * @arg USART_FLAG_FE: Framing Error flag.
- * @arg USART_FLAG_PE: Parity Errorflag.
- *
- * @note RXNE pending bit is cleared by a read to the USART_RDR register
- * (USART_ReceiveData()) or by writing 1 to the RXFRQ in the register
- * USART_RQR (USART_RequestCmd()).
- * @note TC flag can be also cleared by software sequence: a read operation
- * to USART_SR register (USART_GetFlagStatus()) followed by a write
- * operation to USART_TDR register (USART_SendData()).
- * @note TXE flag is cleared by a write to the USART_TDR register (USART_SendData())
- * or by writing 1 to the TXFRQ in the register USART_RQR (USART_RequestCmd()).
- * @note SBKF flag is cleared by 1 to the SBKRQ in the register USART_RQR
- * (USART_RequestCmd()).
- * @retval None
- */
-void USART_ClearFlag(USART_TypeDef* USARTx, uint32_t USART_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_CLEAR_FLAG(USART_FLAG));
-
- USARTx->ICR = USART_FLAG;
-}
-
-/**
- * @brief Checks whether the specified USART interrupt has occurred or not.
- * @param USARTx: where x can be 1, 2, 3 or 4 to select the USART peripheral.
- * @note USART3 and USART4 are available only for STM32F072 devices.
- * @note USART2 is not available for STM32F031 devices.
- * @param USART_IT: specifies the USART interrupt source to check.
- * This parameter can be one of the following values:
- * @arg USART_IT_WU: Wake up interrupt, not available for STM32F030 devices.
- * @arg USART_IT_CM: Character match interrupt.
- * @arg USART_IT_EOB: End of block interrupt, not available for STM32F030 devices.
- * @arg USART_IT_RTO: Receive time out interrupt.
- * @arg USART_IT_CTS: CTS change interrupt.
- * @arg USART_IT_LBD: LIN Break detection interrupt, not available for STM32F030 devices.
- * @arg USART_IT_TXE: Tansmit Data Register empty interrupt.
- * @arg USART_IT_TC: Transmission complete interrupt.
- * @arg USART_IT_RXNE: Receive Data register not empty interrupt.
- * @arg USART_IT_IDLE: Idle line detection interrupt.
- * @arg USART_IT_ORE: OverRun Error interrupt.
- * @arg USART_IT_NE: Noise Error interrupt.
- * @arg USART_IT_FE: Framing Error interrupt.
- * @arg USART_IT_PE: Parity Error interrupt.
- * @retval The new state of USART_IT (SET or RESET).
- */
-ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint32_t USART_IT)
-{
- uint32_t bitpos = 0, itmask = 0, usartreg = 0;
- ITStatus bitstatus = RESET;
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_GET_IT(USART_IT));
-
- /* Get the USART register index */
- usartreg = (((uint16_t)USART_IT) >> 0x08);
- /* Get the interrupt position */
- itmask = USART_IT & IT_MASK;
- itmask = (uint32_t)0x01 << itmask;
-
- if (usartreg == 0x01) /* The IT is in CR1 register */
- {
- itmask &= USARTx->CR1;
- }
- else if (usartreg == 0x02) /* The IT is in CR2 register */
- {
- itmask &= USARTx->CR2;
- }
- else /* The IT is in CR3 register */
- {
- itmask &= USARTx->CR3;
- }
-
- bitpos = USART_IT >> 0x10;
- bitpos = (uint32_t)0x01 << bitpos;
- bitpos &= USARTx->ISR;
- if ((itmask != (uint16_t)RESET)&&(bitpos != (uint16_t)RESET))
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
-
- return bitstatus;
-}
-
-/**
- * @brief Clears the USARTx's interrupt pending bits.
- * @param USARTx: where x can be 1, 2, 3 or 4 to select the USART peripheral.
- * @note USART3 and USART4 are available only for STM32F072 devices.
- * @note USART2 is not available for STM32F031 devices.
- * @param USART_IT: specifies the interrupt pending bit to clear.
- * This parameter can be one of the following values:
- * @arg USART_IT_WU: Wake up interrupt, not available for STM32F030 devices.
- * @arg USART_IT_CM: Character match interrupt.
- * @arg USART_IT_EOB: End of block interrupt, not available for STM32F030 devices.
- * @arg USART_IT_RTO: Receive time out interrupt.
- * @arg USART_IT_CTS: CTS change interrupt.
- * @arg USART_IT_LBD: LIN Break detection interrupt, not available for STM32F030 devices.
- * @arg USART_IT_TC: Transmission complete interrupt.
- * @arg USART_IT_IDLE: IDLE line detected interrupt.
- * @arg USART_IT_ORE: OverRun Error interrupt.
- * @arg USART_IT_NE: Noise Error interrupt.
- * @arg USART_IT_FE: Framing Error interrupt.
- * @arg USART_IT_PE: Parity Error interrupt.
- *
- * @note RXNE pending bit is cleared by a read to the USART_RDR register
- * (USART_ReceiveData()) or by writing 1 to the RXFRQ in the register
- * USART_RQR (USART_RequestCmd()).
- * @note TC pending bit can be also cleared by software sequence: a read
- * operation to USART_SR register (USART_GetITStatus()) followed by
- * a write operation to USART_TDR register (USART_SendData()).
- * @note TXE pending bit is cleared by a write to the USART_TDR register
- * (USART_SendData()) or by writing 1 to the TXFRQ in the register
- * USART_RQR (USART_RequestCmd()).
- * @retval None
- */
-void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint32_t USART_IT)
-{
- uint32_t bitpos = 0, itmask = 0;
- /* Check the parameters */
- assert_param(IS_USART_ALL_PERIPH(USARTx));
- assert_param(IS_USART_CLEAR_IT(USART_IT));
-
- bitpos = USART_IT >> 0x10;
- itmask = ((uint32_t)0x01 << (uint32_t)bitpos);
- USARTx->ICR = (uint32_t)itmask;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_wwdg.c b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_wwdg.c
deleted file mode 100644
index ab92920dea81c4443de04cd3b26828456f0ea7e1..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32F0xx_StdPeriph_Driver/src/stm32f0xx_wwdg.c
+++ /dev/null
@@ -1,303 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32f0xx_wwdg.c
- * @author MCD Application Team
- * @version V1.3.0
- * @date 16-January-2014
- * @brief This file provides firmware functions to manage the following
- * functionalities of the Window watchdog (WWDG) peripheral:
- * + Prescaler, Refresh window and Counter configuration
- * + WWDG activation
- * + Interrupts and flags management
- *
- * @verbatim
- *
- ==============================================================================
- ##### WWDG features #####
- ==============================================================================
- [..] Once enabled the WWDG generates a system reset on expiry of a programmed
- time period, unless the program refreshes the counter (downcounter)
- before to reach 0x3F value (i.e. a reset is generated when the counter
- value rolls over from 0x40 to 0x3F).
- [..] An MCU reset is also generated if the counter value is refreshed
- before the counter has reached the refresh window value. This
- implies that the counter must be refreshed in a limited window.
-
- [..] Once enabled the WWDG cannot be disabled except by a system reset.
-
- [..] WWDGRST flag in RCC_CSR register can be used to inform when a WWDG
- reset occurs.
-
- [..] The WWDG counter input clock is derived from the APB clock divided
- by a programmable prescaler.
-
- [..] WWDG counter clock = PCLK1 / Prescaler.
- [..] WWDG timeout = (WWDG counter clock) * (counter value).
-
- [..] Min-max timeout value @32MHz (PCLK1): ~85us / ~43ms.
-
- ##### How to use this driver #####
- ==============================================================================
- [..]
- (#) Enable WWDG clock using RCC_APB1PeriphClockCmd(RCC_APB1Periph_WWDG, ENABLE)
- function.
-
- (#) Configure the WWDG prescaler using WWDG_SetPrescaler() function.
-
- (#) Configure the WWDG refresh window using WWDG_SetWindowValue() function.
-
- (#) Set the WWDG counter value and start it using WWDG_Enable() function.
- When the WWDG is enabled the counter value should be configured to
- a value greater than 0x40 to prevent generating an immediate reset.
-
- (#) Optionally you can enable the Early wakeup interrupt which is
- generated when the counter reach 0x40.
- Once enabled this interrupt cannot be disabled except by a system reset.
-
- (#) Then the application program must refresh the WWDG counter at regular
- intervals during normal operation to prevent an MCU reset, using
- WWDG_SetCounter() function. This operation must occur only when
- the counter value is lower than the refresh window value,
- programmed using WWDG_SetWindowValue().
-
- * @endverbatim
- *
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx_wwdg.h"
-#include "stm32f0xx_rcc.h"
-
-/** @addtogroup STM32F0xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup WWDG
- * @brief WWDG driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* --------------------- WWDG registers bit mask ---------------------------- */
-/* CFR register bit mask */
-#define CFR_WDGTB_MASK ((uint32_t)0xFFFFFE7F)
-#define CFR_W_MASK ((uint32_t)0xFFFFFF80)
-#define BIT_MASK ((uint8_t)0x7F)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup WWDG_Private_Functions
- * @{
- */
-
-/** @defgroup WWDG_Group1 Prescaler, Refresh window and Counter configuration functions
- * @brief Prescaler, Refresh window and Counter configuration functions
- *
-@verbatim
- ==============================================================================
- ##### Prescaler, Refresh window and Counter configuration functions #####
- ==============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Deinitializes the WWDG peripheral registers to their default reset values.
- * @param None
- * @retval None
- */
-void WWDG_DeInit(void)
-{
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE);
- RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE);
-}
-
-/**
- * @brief Sets the WWDG Prescaler.
- * @param WWDG_Prescaler: specifies the WWDG Prescaler.
- * This parameter can be one of the following values:
- * @arg WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1
- * @arg WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2
- * @arg WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4
- * @arg WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8
- * @retval None
- */
-void WWDG_SetPrescaler(uint32_t WWDG_Prescaler)
-{
- uint32_t tmpreg = 0;
- /* Check the parameters */
- assert_param(IS_WWDG_PRESCALER(WWDG_Prescaler));
- /* Clear WDGTB[1:0] bits */
- tmpreg = WWDG->CFR & CFR_WDGTB_MASK;
- /* Set WDGTB[1:0] bits according to WWDG_Prescaler value */
- tmpreg |= WWDG_Prescaler;
- /* Store the new value */
- WWDG->CFR = tmpreg;
-}
-
-/**
- * @brief Sets the WWDG window value.
- * @param WindowValue: specifies the window value to be compared to the downcounter.
- * This parameter value must be lower than 0x80.
- * @retval None
- */
-void WWDG_SetWindowValue(uint8_t WindowValue)
-{
- __IO uint32_t tmpreg = 0;
-
- /* Check the parameters */
- assert_param(IS_WWDG_WINDOW_VALUE(WindowValue));
- /* Clear W[6:0] bits */
-
- tmpreg = WWDG->CFR & CFR_W_MASK;
-
- /* Set W[6:0] bits according to WindowValue value */
- tmpreg |= WindowValue & (uint32_t) BIT_MASK;
-
- /* Store the new value */
- WWDG->CFR = tmpreg;
-}
-
-/**
- * @brief Enables the WWDG Early Wakeup interrupt(EWI).
- * @note Once enabled this interrupt cannot be disabled except by a system reset.
- * @param None
- * @retval None
- */
-void WWDG_EnableIT(void)
-{
- WWDG->CFR |= WWDG_CFR_EWI;
-}
-
-/**
- * @brief Sets the WWDG counter value.
- * @param Counter: specifies the watchdog counter value.
- * This parameter must be a number between 0x40 and 0x7F (to prevent
- * generating an immediate reset).
- * @retval None
- */
-void WWDG_SetCounter(uint8_t Counter)
-{
- /* Check the parameters */
- assert_param(IS_WWDG_COUNTER(Counter));
- /* Write to T[6:0] bits to configure the counter value, no need to do
- a read-modify-write; writing a 0 to WDGA bit does nothing */
- WWDG->CR = Counter & BIT_MASK;
-}
-
-/**
- * @}
- */
-
-/** @defgroup WWDG_Group2 WWDG activation functions
- * @brief WWDG activation functions
- *
-@verbatim
- ==============================================================================
- ##### WWDG activation function #####
- ==============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables WWDG and load the counter value.
- * @param Counter: specifies the watchdog counter value.
- * This parameter must be a number between 0x40 and 0x7F (to prevent
- * generating an immediate reset).
- * @retval None
- */
-void WWDG_Enable(uint8_t Counter)
-{
- /* Check the parameters */
- assert_param(IS_WWDG_COUNTER(Counter));
- WWDG->CR = WWDG_CR_WDGA | Counter;
-}
-
-/**
- * @}
- */
-
-/** @defgroup WWDG_Group3 Interrupts and flags management functions
- * @brief Interrupts and flags management functions
- *
-@verbatim
- ==============================================================================
- ##### Interrupts and flags management functions #####
- ==============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Checks whether the Early Wakeup interrupt flag is set or not.
- * @param None
- * @retval The new state of the Early Wakeup interrupt flag (SET or RESET).
- */
-FlagStatus WWDG_GetFlagStatus(void)
-{
- FlagStatus bitstatus = RESET;
-
- if ((WWDG->SR) != (uint32_t)RESET)
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Clears Early Wakeup interrupt flag.
- * @param None
- * @retval None
- */
-void WWDG_ClearFlag(void)
-{
- WWDG->SR = (uint32_t)RESET;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Driver/inc/usb_bsp.h b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Driver/inc/usb_bsp.h
deleted file mode 100644
index f105636bfdabac0ee73cc4f5684261249e1e8c4b..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Driver/inc/usb_bsp.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/**
- ******************************************************************************
- * @file usb_bsp.h
- * @author MCD Application Team
- * @version V1.0.1
- * @date 31-January-2014
- * @brief Specific api's related to the used hardware platform
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __USB_BSP__H__
-#define __USB_BSP__H__
-
-/* Includes ------------------------------------------------------------------*/
-#include "usb_dcd.h"
-
-/* Exported defines ----------------------------------------------------------*/
-/* Exported types ------------------------------------------------------------*/
-/* Exported macros -----------------------------------------------------------*/
-/* Exported variables --------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-void USB_BSP_Init (USB_CORE_HANDLE *pdev);
-void USB_BSP_EnableInterrupt (USB_CORE_HANDLE *pdev);
-void USB_BSP_uDelay (const uint32_t usec);
-void USB_BSP_mDelay (const uint32_t msec);
-
-#endif /* __USB_BSP__H__ */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Driver/inc/usb_conf_template.h b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Driver/inc/usb_conf_template.h
deleted file mode 100644
index 2b8d174c5f28df59c56d1a2e6531c833c08f0be8..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Driver/inc/usb_conf_template.h
+++ /dev/null
@@ -1,76 +0,0 @@
-/**
- ******************************************************************************
- * @file usb_conf_template.h
- * @author MCD Application Team
- * @version V1.0.1
- * @date 31-January-2014
- * @brief General low level driver configuration
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __USB_CONF__H__
-#define __USB_CONF__H__
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f0xx.h"
-#include "stm32072b_eval.h"
-
-/* Exported defines ----------------------------------------------------------*/
-/* Select D+ pull up: internal or external */
-#ifdef USE_STM32072B_EVAL
- /* When using STM32072B_EVAL board the internal pull up must be enabled */
- #define INTERNAL_PULLUP
-#endif
-
-/* Define if Low power mode is enabled; it allows entering the device into STOP mode
- following USB Suspend event, and wakes up after the USB wakeup event is received. */
-/* #define USB_DEVICE_LOW_PWR_MGMT_SUPPORT */
-
-/* Select the CRS using HSI48 internal clock as USB clock source.
- If this define is commented, PLL will be used as USB clock source.
- User need to ensure that the PLL output clock to USB is 48MHz for proper
- USB functioning */
-#define USB_CLOCK_SOURCE_CRS
-
-/* Endpoints used by the device */
-#define EP_NUM (3) /* EP0 + EP1 for MSC IN + EP2 for MSC OUT */
-
-/* Buffer table base address */
-#define BTABLE_ADDRESS (0x00)
-
-/* EP0, RX/TX buffers base address */
-#define ENDP0_RX_ADDRESS (0x18)
-#define ENDP0_TX_ADDRESS (0x58)
-
-/* EP1, TX buffer base address */
-#define MSC_IN_TX_ADDRESS (0x98)
-
-/* EP2, Rx buffer base address */
-#define MSC_OUT_RX_ADDRESS (0xD8)
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported macros -----------------------------------------------------------*/
-/* Exported variables --------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-#endif /* __USB_CONF__H__ */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Driver/inc/usb_core.h b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Driver/inc/usb_core.h
deleted file mode 100644
index f3cee3c61d6d66619f8476fdc75abc26ab0940a3..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Driver/inc/usb_core.h
+++ /dev/null
@@ -1,495 +0,0 @@
-/**
- ******************************************************************************
- * @file usb_core.h
- * @author MCD Application Team
- * @version V1.0.1
- * @date 31-January-2014
- * @brief This file provides Interface prototype functions to USB cell registers
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __USB_CORE_H__
-#define __USB_CORE_H__
-/* Includes ------------------------------------------------------------------*/
-#include "usb_conf.h"
-#include "usb_regs.h"
-
-/* Exported defines ----------------------------------------------------------*/
-#define EP_TYPE_CTRL 0
-
-#define USB_EP0_IDLE 0
-#define USB_EP0_SETUP 1
-#define USB_EP0_DATA_IN 2
-#define USB_EP0_DATA_OUT 3
-#define USB_EP0_STATUS_IN 4
-#define USB_EP0_STATUS_OUT 5
-
-
-#define USB_MAX_EP0_SIZE 64
-
-#define USB_SPEED_FULL 1
-
-/* Exported types ------------------------------------------------------------*/
-typedef enum {
- USB_OK = 0,
- USB_FAIL
-}USB_STS;
-
-/* Exported macros -----------------------------------------------------------*/
-/* SetCNTR */
-#define _SetCNTR(wRegValue) (*CNTR = (uint16_t)wRegValue)
-
-/* SetISTR */
-#define _SetISTR(wRegValue) (*ISTR = (uint16_t)wRegValue)
-
-/* SetDADDR */
-#define _SetDADDR(wRegValue) (*DADDR = (uint16_t)wRegValue)
-
-/* SetBCDR */
-#define _SetBCDR(wRegValue) (*BCDR = (uint16_t)wRegValue)
-
-/* SetBTABLE */
-#define _SetBTABLE(wRegValue)(*BTABLE = (uint16_t)(wRegValue & 0xFFF8))
-
-/*SetLPMCSR */
-#define _SetLPMCSR(wRegValue) (*LPMCSR = (uint16_t)wRegValue)
-
-/* GetCNTR */
-#define _GetCNTR() ((uint16_t) *CNTR)
-
-/* GetISTR */
-#define _GetISTR() ((uint16_t) *ISTR)
-
-/* GetFNR */
-#define _GetFNR() ((uint16_t) *FNR)
-
-/* GetDADDR */
-#define _GetDADDR() ((uint16_t) *DADDR)
-
-/* GetBTABLE */
-#define _GetBTABLE() ((uint16_t) *BTABLE)
-
-/*GetLPMCSR */
-#define _GetLPMCSR() ((uint16_t) *LPMCSR)
-
-
-/* SetENDPOINT */
-#define _SetENDPOINT(bEpNum,wRegValue) (*(EP0REG + bEpNum)= \
- (uint16_t)wRegValue)
-
-/* GetENDPOINT */
-#define _GetENDPOINT(bEpNum) ((uint16_t)(*(EP0REG + bEpNum)))
-
-
-
-/**
- * @brief sets the type in the endpoint register(bits EP_TYPE[1:0])
- * @param bEpNum: Endpoint Number.
- * @param wType: Endpoint Type.
- * @retval None
- */
-#define _SetEPType(bEpNum,wType) (_SetENDPOINT(bEpNum,\
- ((_GetENDPOINT(bEpNum) & EP_T_MASK) | wType )))
-
-/**
- * @brief gets the type in the endpoint register(bits EP_TYPE[1:0])
- * @param bEpNum: Endpoint Number.
- * @retval Endpoint Type
- */
-#define _GetEPType(bEpNum) (_GetENDPOINT(bEpNum) & EP_T_FIELD)
-
-
-/**
- * @brief sets the status for tx transfer (bits STAT_TX[1:0]).
- * @param bEpNum: Endpoint Number.
- * @param wState: new state
- * @retval None
- */
-#define _SetEPTxStatus(bEpNum,wState) {\
-register uint16_t _wRegVal; \
- _wRegVal = _GetENDPOINT(bEpNum) & EPTX_DTOGMASK;\
- /* toggle first bit ? */ \
- if((EPTX_DTOG1 & wState)!= 0) \
- _wRegVal ^= EPTX_DTOG1; \
- /* toggle second bit ? */ \
- if((EPTX_DTOG2 & wState)!= 0) \
- _wRegVal ^= EPTX_DTOG2; \
- _SetENDPOINT(bEpNum, (_wRegVal | EP_CTR_RX|EP_CTR_TX)); \
- } /* _SetEPTxStatus */
-
-/**
- * @brief sets the status for rx transfer (bits STAT_TX[1:0])
- * @param bEpNum: Endpoint Number.
- * @param wState: new state
- * @retval None
- */
-#define _SetEPRxStatus(bEpNum,wState) {\
- register uint16_t _wRegVal; \
- \
- _wRegVal = _GetENDPOINT(bEpNum) & EPRX_DTOGMASK;\
- /* toggle first bit ? */ \
- if((EPRX_DTOG1 & wState)!= 0) \
- _wRegVal ^= EPRX_DTOG1; \
- /* toggle second bit ? */ \
- if((EPRX_DTOG2 & wState)!= 0) \
- _wRegVal ^= EPRX_DTOG2; \
- _SetENDPOINT(bEpNum, (_wRegVal | EP_CTR_RX|EP_CTR_TX)); \
- } /* _SetEPRxStatus */
-
-/**
- * @brief sets the status for rx & tx (bits STAT_TX[1:0] & STAT_RX[1:0])
- * @param bEpNum: Endpoint Number.
- * @param wStaterx: new state.
- * @param wStatetx: new state.
- * @retval None
- */
-#define _SetEPRxTxStatus(bEpNum,wStaterx,wStatetx) {\
- register uint32_t _wRegVal; \
- \
- _wRegVal = _GetENDPOINT(bEpNum) & (EPRX_DTOGMASK |EPTX_STAT) ;\
- /* toggle first bit ? */ \
- if((EPRX_DTOG1 & wStaterx)!= 0) \
- _wRegVal ^= EPRX_DTOG1; \
- /* toggle second bit ? */ \
- if((EPRX_DTOG2 & wStaterx)!= 0) \
- _wRegVal ^= EPRX_DTOG2; \
- /* toggle first bit ? */ \
- if((EPTX_DTOG1 & wStatetx)!= 0) \
- _wRegVal ^= EPTX_DTOG1; \
- /* toggle second bit ? */ \
- if((EPTX_DTOG2 & wStatetx)!= 0) \
- _wRegVal ^= EPTX_DTOG2; \
- _SetENDPOINT(bEpNum, _wRegVal | EP_CTR_RX|EP_CTR_TX); \
- } /* _SetEPRxTxStatus */
-
-/**
- * @brief gets the status for tx/rx transfer (bits STAT_TX[1:0]
- * /STAT_RX[1:0])
- * @param bEpNum: Endpoint Number.
- * @retval status
- */
-#define _GetEPTxStatus(bEpNum) ((uint16_t)_GetENDPOINT(bEpNum) & EPTX_STAT)
-
-#define _GetEPRxStatus(bEpNum) ((uint16_t)_GetENDPOINT(bEpNum) & EPRX_STAT)
-
-/**
- * @brief sets directly the VALID tx/rx-status into the endpoint register
- * @param bEpNum: Endpoint Number.
- * @retval None
- */
-#define _SetEPTxValid(bEpNum) (_SetEPTxStatus(bEpNum, EP_TX_VALID))
-
-#define _SetEPRxValid(bEpNum) (_SetEPRxStatus(bEpNum, EP_RX_VALID))
-
-/**
- * @brief checks stall condition in an endpoint.
- * @param bEpNum: Endpoint Number.
- * @retval TRUE = endpoint in stall condition.
- */
-#define _GetTxStallStatus(bEpNum) (_GetEPTxStatus(bEpNum) \
- == EP_TX_STALL)
-#define _GetRxStallStatus(bEpNum) (_GetEPRxStatus(bEpNum) \
- == EP_RX_STALL)
-
-/**
- * @brief set & clear EP_KIND bit.
- * @param bEpNum: Endpoint Number.
- * @retval None
- */
-#define _SetEP_KIND(bEpNum) (_SetENDPOINT(bEpNum, \
- (EP_CTR_RX|EP_CTR_TX|((_GetENDPOINT(bEpNum) | EP_KIND) & EPREG_MASK))))
-#define _ClearEP_KIND(bEpNum) (_SetENDPOINT(bEpNum, \
- (EP_CTR_RX|EP_CTR_TX|(_GetENDPOINT(bEpNum) & EPKIND_MASK))))
-
-/**
- * @brief Sets/clears directly STATUS_OUT bit in the endpoint register.
- * @param bEpNum: Endpoint Number.
- * @retval None
- */
-#define _Set_Status_Out(bEpNum) _SetEP_KIND(bEpNum)
-#define _Clear_Status_Out(bEpNum) _ClearEP_KIND(bEpNum)
-
-/**
- * @brief Sets/clears directly EP_KIND bit in the endpoint register.
- * @param bEpNum: Endpoint Number.
- * @retval None
- */
-#define _SetEPDoubleBuff(bEpNum) _SetEP_KIND(bEpNum)
-#define _ClearEPDoubleBuff(bEpNum) _ClearEP_KIND(bEpNum)
-
-/**
- * @brief Clears bit CTR_RX / CTR_TX in the endpoint register.
- * @param bEpNum: Endpoint Number.
- * @retval None
- */
-#define _ClearEP_CTR_RX(bEpNum) (_SetENDPOINT(bEpNum,\
- _GetENDPOINT(bEpNum) & 0x7FFF & EPREG_MASK))
-#define _ClearEP_CTR_TX(bEpNum) (_SetENDPOINT(bEpNum,\
- _GetENDPOINT(bEpNum) & 0xFF7F & EPREG_MASK))
-
-/**
- * @brief Toggles DTOG_RX / DTOG_TX bit in the endpoint register.
- * @param bEpNum: Endpoint Number.
- * @retval None
- */
-#define _ToggleDTOG_RX(bEpNum) (_SetENDPOINT(bEpNum, \
- EP_CTR_RX|EP_CTR_TX|EP_DTOG_RX | (_GetENDPOINT(bEpNum) & EPREG_MASK)))
-#define _ToggleDTOG_TX(bEpNum) (_SetENDPOINT(bEpNum, \
- EP_CTR_RX|EP_CTR_TX|EP_DTOG_TX | (_GetENDPOINT(bEpNum) & EPREG_MASK)))
-
-/**
- * @brief Clears DTOG_RX / DTOG_TX bit in the endpoint register.
- * @param bEpNum: Endpoint Number.
- * @retval None
- */
-#define _ClearDTOG_RX(bEpNum) if((_GetENDPOINT(bEpNum) & EP_DTOG_RX) != 0)\
- _ToggleDTOG_RX(bEpNum)
-#define _ClearDTOG_TX(bEpNum) if((_GetENDPOINT(bEpNum) & EP_DTOG_TX) != 0)\
- _ToggleDTOG_TX(bEpNum)
-
-/**
- * @brief Sets address in an endpoint register.
- * @param bEpNum: Endpoint Number.
- * @param bAddr: Address.
- * @retval None
- */
-#define _SetEPAddress(bEpNum,bAddr) _SetENDPOINT(bEpNum,\
- EP_CTR_RX|EP_CTR_TX|(_GetENDPOINT(bEpNum) & EPREG_MASK) | bAddr)
-
-/**
- * @brief Gets address in an endpoint register.
- * @param bEpNum: Endpoint Number.
- * @retval None
- */
-#define _GetEPAddress(bEpNum) ((uint8_t)(_GetENDPOINT(bEpNum) & EPADDR_FIELD))
-#define _pEPTxAddr(bEpNum) ((uint16_t *)((_GetBTABLE()+bEpNum*8) + PMAAddr))
-#define _pEPTxCount(bEpNum) ((uint16_t *)((_GetBTABLE()+bEpNum*8+2) + PMAAddr))
-#define _pEPRxAddr(bEpNum) ((uint16_t *)((_GetBTABLE()+bEpNum*8+4) + PMAAddr))
-#define _pEPRxCount(bEpNum) ((uint16_t *)((_GetBTABLE()+bEpNum*8+6) + PMAAddr))
-
-/**
- * @brief sets address of the tx/rx buffer.
- * @param bEpNum: Endpoint Number.
- * @param wAddr: address to be set (must be word aligned).
- * @retval None
- */
-#define _SetEPTxAddr(bEpNum,wAddr) (*_pEPTxAddr(bEpNum) = ((wAddr >> 1) << 1))
-#define _SetEPRxAddr(bEpNum,wAddr) (*_pEPRxAddr(bEpNum) = ((wAddr >> 1) << 1))
-
-/**
- * @brief Gets address of the tx/rx buffer.
- * @param bEpNum: Endpoint Number.
- * @retval address of the buffer.
- */
-#define _GetEPTxAddr(bEpNum) ((uint16_t)*_pEPTxAddr(bEpNum))
-#define _GetEPRxAddr(bEpNum) ((uint16_t)*_pEPRxAddr(bEpNum))
-
-/**
- * @brief Sets counter of rx buffer with no. of blocks.
- * @param bEpNum: Endpoint Number.
- * @param wCount: Counter.
- * @retval None
- */
-#define _BlocksOf32(dwReg,wCount,wNBlocks) {\
- wNBlocks = wCount >> 5;\
- if((wCount & 0x1f) == 0)\
- wNBlocks--;\
- *pdwReg = (uint16_t)((wNBlocks << 10) | 0x8000);\
- }/* _BlocksOf32 */
-
-#define _BlocksOf2(dwReg,wCount,wNBlocks) {\
- wNBlocks = wCount >> 1;\
- if((wCount & 0x1) != 0)\
- wNBlocks++;\
- *pdwReg = (uint16_t)(wNBlocks << 10);\
- }/* _BlocksOf2 */
-
-#define _SetEPCountRxReg(dwReg,wCount) {\
- uint16_t wNBlocks;\
- if(wCount > 62){_BlocksOf32(dwReg,wCount,wNBlocks);}\
- else {_BlocksOf2(dwReg,wCount,wNBlocks);}\
- }/* _SetEPCountRxReg */
-
-#define _SetEPRxDblBuf0Count(bEpNum,wCount) {\
- uint16_t *pdwReg = _pEPTxCount(bEpNum); \
- _SetEPCountRxReg(pdwReg, wCount);\
- }
-/**
- * @brief sets counter for the tx/rx buffer.
- * @param bEpNum: Endpoint Number.
- * @param wCount: Counter value.
- * @retval None
- */
-#define _SetEPTxCount(bEpNum,wCount) (*_pEPTxCount(bEpNum) = wCount)
-#define _SetEPRxCount(bEpNum,wCount) {\
- uint16_t *pdwReg = _pEPRxCount(bEpNum); \
- _SetEPCountRxReg(pdwReg, wCount);\
- }
-
-/**
- * @brief gets counter of the tx buffer.
- * @param bEpNum: Endpoint Number.
- * @retval Counter value
- */
-#define _GetEPTxCount(bEpNum)((uint16_t)(*_pEPTxCount(bEpNum)) & 0x3ff)
-#define _GetEPRxCount(bEpNum)((uint16_t)(*_pEPRxCount(bEpNum)) & 0x3ff)
-
-/**
- * @brief Sets buffer 0/1 address in a double buffer endpoint.
- * @param bEpNum: Endpoint Number.
- * @param wBuf0Addr: buffer 0 address.
- * @retval Counter value
- */
-#define _SetEPDblBuf0Addr(bEpNum,wBuf0Addr) {_SetEPTxAddr(bEpNum, wBuf0Addr);}
-#define _SetEPDblBuf1Addr(bEpNum,wBuf1Addr) {_SetEPRxAddr(bEpNum, wBuf1Addr);}
-
-/**
- * @brief Sets addresses in a double buffer endpoint.
- * @param bEpNum: Endpoint Number.
- * @param wBuf0Addr: buffer 0 address.
- * @param wBuf1Addr = buffer 1 address.
- * @retval None
- */
-#define _SetEPDblBuffAddr(bEpNum,wBuf0Addr,wBuf1Addr) { \
- _SetEPDblBuf0Addr(bEpNum, wBuf0Addr);\
- _SetEPDblBuf1Addr(bEpNum, wBuf1Addr);\
- } /* _SetEPDblBuffAddr */
-
-/**
- * @brief Gets buffer 0/1 address of a double buffer endpoint.
- * @param bEpNum: Endpoint Number.
- * @retval None
- */
-#define _GetEPDblBuf0Addr(bEpNum) (_GetEPTxAddr(bEpNum))
-#define _GetEPDblBuf1Addr(bEpNum) (_GetEPRxAddr(bEpNum))
-
-/**
- * @brief Gets buffer 0/1 address of a double buffer endpoint.
- * @param bEpNum: Endpoint Number.
- * bDir: endpoint dir EP_DBUF_OUT = OUT
- * EP_DBUF_IN = IN
- * @param wCount: Counter value
- * @retval None
- */
-#define _SetEPDblBuf0Count(bEpNum, bDir, wCount) { \
- if(bDir == EP_DBUF_OUT)\
- /* OUT endpoint */ \
- {_SetEPRxDblBuf0Count(bEpNum,wCount);} \
- else if(bDir == EP_DBUF_IN)\
- /* IN endpoint */ \
- *_pEPTxCount(bEpNum) = (uint32_t)wCount; \
- } /* SetEPDblBuf0Count*/
-
-#define _SetEPDblBuf1Count(bEpNum, bDir, wCount) { \
- if(bDir == EP_DBUF_OUT)\
- /* OUT endpoint */ \
- {_SetEPRxCount(bEpNum,wCount);}\
- else if(bDir == EP_DBUF_IN)\
- /* IN endpoint */\
- *_pEPRxCount(bEpNum) = (uint32_t)wCount; \
- } /* SetEPDblBuf1Count */
-
-#define _SetEPDblBuffCount(bEpNum, bDir, wCount) {\
- _SetEPDblBuf0Count(bEpNum, bDir, wCount); \
- _SetEPDblBuf1Count(bEpNum, bDir, wCount); \
- } /* _SetEPDblBuffCount */
-
-/**
- * @brief Gets buffer 0/1 rx/tx counter for double buffering.
- * @param bEpNum: Endpoint Number.
- * @retval None
- */
-#define _GetEPDblBuf0Count(bEpNum) (_GetEPTxCount(bEpNum))
-#define _GetEPDblBuf1Count(bEpNum) (_GetEPRxCount(bEpNum))
-
-/* Exported variables --------------------------------------------------------*/
-extern __IO uint16_t wIstr; /* ISTR register last read value */
-
-/* Exported functions ------------------------------------------------------- */
-void SetCNTR(uint16_t /*wRegValue*/);
-void SetISTR(uint16_t /*wRegValue*/);
-void SetDADDR(uint16_t /*wRegValue*/);
-void SetBTABLE(uint16_t /*wRegValue*/);
-void SetBTABLE(uint16_t /*wRegValue*/);
-void SetLPMCSR(uint16_t /*wRegValue*/);
-uint16_t GetCNTR(void);
-uint16_t GetISTR(void);
-uint16_t GetFNR(void);
-uint16_t GetDADDR(void);
-uint16_t GetBTABLE(void);
-uint16_t GetLPMCSR(void);
-void SetENDPOINT(uint8_t /*bEpNum*/, uint16_t /*wRegValue*/);
-uint16_t GetENDPOINT(uint8_t /*bEpNum*/);
-void SetEPType(uint8_t /*bEpNum*/, uint16_t /*wType*/);
-uint16_t GetEPType(uint8_t /*bEpNum*/);
-void SetEPTxStatus(uint8_t /*bEpNum*/, uint16_t /*wState*/);
-void SetEPRxStatus(uint8_t /*bEpNum*/, uint16_t /*wState*/);
-void SetDouBleBuffEPStall(uint8_t /*bEpNum*/, uint8_t bDir);
-uint16_t GetEPTxStatus(uint8_t /*bEpNum*/);
-uint16_t GetEPRxStatus(uint8_t /*bEpNum*/);
-void SetEPTxValid(uint8_t /*bEpNum*/);
-void SetEPRxValid(uint8_t /*bEpNum*/);
-uint16_t GetTxStallStatus(uint8_t /*bEpNum*/);
-uint16_t GetRxStallStatus(uint8_t /*bEpNum*/);
-void SetEP_KIND(uint8_t /*bEpNum*/);
-void ClearEP_KIND(uint8_t /*bEpNum*/);
-void Set_Status_Out(uint8_t /*bEpNum*/);
-void Clear_Status_Out(uint8_t /*bEpNum*/);
-void SetEPDoubleBuff(uint8_t /*bEpNum*/);
-void ClearEPDoubleBuff(uint8_t /*bEpNum*/);
-void ClearEP_CTR_RX(uint8_t /*bEpNum*/);
-void ClearEP_CTR_TX(uint8_t /*bEpNum*/);
-void ToggleDTOG_RX(uint8_t /*bEpNum*/);
-void ToggleDTOG_TX(uint8_t /*bEpNum*/);
-void ClearDTOG_RX(uint8_t /*bEpNum*/);
-void ClearDTOG_TX(uint8_t /*bEpNum*/);
-void SetEPAddress(uint8_t /*bEpNum*/, uint8_t /*bAddr*/);
-uint8_t GetEPAddress(uint8_t /*bEpNum*/);
-void SetEPTxAddr(uint8_t /*bEpNum*/, uint16_t /*wAddr*/);
-void SetEPRxAddr(uint8_t /*bEpNum*/, uint16_t /*wAddr*/);
-uint16_t GetEPTxAddr(uint8_t /*bEpNum*/);
-uint16_t GetEPRxAddr(uint8_t /*bEpNum*/);
-void SetEPCountRxReg(uint16_t * /*pdwReg*/, uint16_t /*wCount*/);
-void SetEPTxCount(uint8_t /*bEpNum*/, uint16_t /*wCount*/);
-void SetEPRxCount(uint8_t /*bEpNum*/, uint16_t /*wCount*/);
-uint16_t GetEPTxCount(uint8_t /*bEpNum*/);
-uint16_t GetEPRxCount(uint8_t /*bEpNum*/);
-void SetEPDblBuf0Addr(uint8_t /*bEpNum*/, uint16_t /*wBuf0Addr*/);
-void SetEPDblBuf1Addr(uint8_t /*bEpNum*/, uint16_t /*wBuf1Addr*/);
-void SetEPDblBuffAddr(uint8_t /*bEpNum*/, uint16_t /*wBuf0Addr*/, uint16_t /*wBuf1Addr*/);
-uint16_t GetEPDblBuf0Addr(uint8_t /*bEpNum*/);
-uint16_t GetEPDblBuf1Addr(uint8_t /*bEpNum*/);
-void SetEPDblBuffCount(uint8_t /*bEpNum*/, uint8_t /*bDir*/, uint16_t /*wCount*/);
-void SetEPDblBuf0Count(uint8_t /*bEpNum*/, uint8_t /*bDir*/, uint16_t /*wCount*/);
-void SetEPDblBuf1Count(uint8_t /*bEpNum*/, uint8_t /*bDir*/, uint16_t /*wCount*/);
-uint16_t GetEPDblBuf0Count(uint8_t /*bEpNum*/);
-uint16_t GetEPDblBuf1Count(uint8_t /*bEpNum*/);
-EP_DBUF_DIR GetEPDblBufDir(uint8_t /*bEpNum*/);
-void FreeUserBuffer(uint8_t bEpNum/*bEpNum*/, uint8_t bDir);
-uint16_t ToWord(uint8_t, uint8_t);
-uint16_t ByteSwap(uint16_t);
-void SetDeviceAddress(uint8_t);
-void UserToPMABufferCopy(uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes);
-void PMAToUserBufferCopy(uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes);
-
-#endif /* __USB_CORE_H__ */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Driver/inc/usb_dcd.h b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Driver/inc/usb_dcd.h
deleted file mode 100644
index a387a93a51e1edbdfa4a2f2812f7a2e8c97b1c5e..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Driver/inc/usb_dcd.h
+++ /dev/null
@@ -1,228 +0,0 @@
-/**
- ******************************************************************************
- * @file usb_dcd.h
- * @author MCD Application Team
- * @version V1.0.1
- * @date 31-January-2014
- * @brief Device Control Driver Header file
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __DCD_H__
-#define __DCD_H__
-
-/* Includes ------------------------------------------------------------------*/
-#include "usb_core.h"
-
-/* Exported defines ----------------------------------------------------------*/
-#define USB_EP_CONTROL 0
-#define USB_EP_ISOC 1
-#define USB_EP_BULK 2
-#define USB_EP_INT 3
-
-/* Endpoint Kind */
-#define USB_SNG_BUF 0
-#define USB_DBL_BUF 1
-
-/* Device Status */
-#define USB_UNCONNECTED 0
-#define USB_DEFAULT 1
-#define USB_ADDRESSED 2
-#define USB_CONFIGURED 3
-#define USB_SUSPENDED 4
-
-
-/* Exported types ------------------------------------------------------------*/
-/********************************************************************************
-Data structure type
-********************************************************************************/
-typedef struct
-{
- uint8_t bLength;
- uint8_t bDescriptorType;
- uint8_t bEndpointAddress;
- uint8_t bmAttributes;
- uint16_t wMaxPacketSize;
- uint8_t bInterval;
-}
-EP_DESCRIPTOR , *PEP_DESCRIPTOR;
-
-typedef struct USB_ep
-{
- uint8_t num;
- uint8_t is_in;
- uint8_t is_stall;
- uint8_t type;
- uint16_t pmaadress;
- uint16_t pmaaddr0;
- uint16_t pmaaddr1;
- uint8_t doublebuffer;
- uint32_t maxpacket;
- /* transaction level variables !!! up to one max packet per transaction !!! */
- uint8_t *xfer_buff;
- uint32_t xfer_len ;
- uint32_t xfer_count;
- /* control transfer variables*/
- uint32_t rem_data_len;
- uint32_t total_data_len;
- uint32_t ctl_data_len;
-}
-USB_EP;
-
-typedef struct usb_setup_req {
-
- uint8_t bmRequest;
- uint8_t bRequest;
- uint16_t wValue;
- uint16_t wIndex;
- uint16_t wLength;
-} USB_SETUP_REQ;
-
-typedef struct _Device_TypeDef
-{
- uint8_t *(*GetDeviceDescriptor)( uint8_t speed , uint16_t *length);
-#ifdef LPM_ENABLED
- uint8_t *(*GetBOSDescriptor)( uint8_t speed , uint16_t *length);
-#endif
- uint8_t *(*GetLangIDStrDescriptor)( uint8_t speed , uint16_t *length);
- uint8_t *(*GetManufacturerStrDescriptor)( uint8_t speed , uint16_t *length);
- uint8_t *(*GetProductStrDescriptor)( uint8_t speed , uint16_t *length);
- uint8_t *(*GetSerialStrDescriptor)( uint8_t speed , uint16_t *length);
- uint8_t *(*GetConfigurationStrDescriptor)( uint8_t speed , uint16_t *length);
- uint8_t *(*GetInterfaceStrDescriptor)( uint8_t speed , uint16_t *length);
-} USBD_DEVICE, *pUSBD_DEVICE;
-
-
-
-
-typedef struct _Device_cb
-{
- uint8_t (*Init) (void *pdev , uint8_t cfgidx);
- uint8_t (*DeInit) (void *pdev , uint8_t cfgidx);
- /* Control Endpoints*/
- uint8_t (*Setup) (void *pdev , USB_SETUP_REQ *req);
- uint8_t (*EP0_TxSent) (void *pdev );
- uint8_t (*EP0_RxReady) (void *pdev);
- /* Class Specific Endpoints*/
- uint8_t (*DataIn) (void *pdev , uint8_t epnum);
- uint8_t (*DataOut) (void *pdev , uint8_t epnum);
- uint8_t (*SOF) (void *pdev);
- uint8_t *(*GetConfigDescriptor)( uint8_t speed , uint16_t *length);
-
-#ifdef USB_SUPPORT_USER_STRING_DESC
- uint8_t *(*GetUsrStrDescriptor)( uint8_t speed ,uint8_t index, uint16_t *length);
-#endif
-
-} USBD_Class_cb_TypeDef;
-
-
-
-typedef struct _USBD_USR_PROP
-{
- void (*Init)(void);
- void (*DeviceReset)(uint8_t speed);
- void (*DeviceConfigured)(void);
- void (*DeviceSuspended)(void);
- void (*DeviceResumed)(void);
-}
-USBD_Usr_cb_TypeDef;
-
-typedef struct _DCD
-{
- uint8_t device_config;
- uint8_t device_state;
- uint8_t device_status;
- uint8_t device_old_status;
- uint8_t device_address;
- uint32_t DevRemoteWakeup;
- uint32_t speed;
- uint8_t setup_packet [8];
- USB_EP in_ep [EP_NUM];
- USB_EP out_ep [EP_NUM];
- USBD_Class_cb_TypeDef *class_cb;
- USBD_Usr_cb_TypeDef *usr_cb;
- USBD_DEVICE *usr_device;
- uint8_t *pConfig_descriptor;
- }
-DCD_DEV , *DCD_PDEV;
-
-typedef struct USB_Device_handle
-{
- DCD_DEV dev;
-}
-USB_DEVICE_HANDLE, USB_CORE_HANDLE;
-
-/* Exported macros -----------------------------------------------------------*/
-/* Exported variables --------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-/********************************************************************************
-EXPORTED FUNCTION FROM THE USB-DEVICE LAYER
-********************************************************************************/
-void DCD_Init(USB_CORE_HANDLE *pdev);
-
-void DCD_DevConnect (USB_CORE_HANDLE *pdev);
-void DCD_DevDisconnect (USB_CORE_HANDLE *pdev);
-void DCD_EP_SetAddress (USB_CORE_HANDLE *pdev,
- uint8_t address);
-
-uint32_t DCD_PMA_Config(USB_CORE_HANDLE *pdev ,
- uint16_t ep_addr,
- uint16_t ep_kind,
- uint32_t pmaadress);
-
-uint32_t DCD_EP_Open(USB_CORE_HANDLE *pdev ,
- uint16_t ep_addr,
- uint16_t ep_mps,
- uint8_t ep_type);
-
-uint32_t DCD_EP_Close (USB_CORE_HANDLE *pdev,
- uint8_t ep_addr);
-
-
-uint32_t DCD_EP_PrepareRx ( USB_CORE_HANDLE *pdev,
- uint8_t ep_addr,
- uint8_t *pbuf,
- uint16_t buf_len);
-
-uint32_t DCD_EP_Tx (USB_CORE_HANDLE *pdev,
- uint8_t ep_addr,
- uint8_t *pbuf,
- uint32_t buf_len);
-uint32_t DCD_EP_Stall (USB_CORE_HANDLE *pdev,
- uint8_t epnum);
-uint32_t DCD_EP_ClrStall (USB_CORE_HANDLE *pdev,
- uint8_t epnum);
-
-uint32_t DCD_Handle_ISR(USB_CORE_HANDLE *pdev);
-
-uint32_t DCD_GetEPStatus(USB_CORE_HANDLE *pdev ,
- uint8_t epnum);
-
-void DCD_SetEPStatus (USB_CORE_HANDLE *pdev ,
- uint8_t epnum ,
- uint32_t Status);
-
-void DCD_StopDevice(USB_CORE_HANDLE *pdev);
-
-#endif /* __DCD_H__ */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Driver/inc/usb_dcd_int.h b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Driver/inc/usb_dcd_int.h
deleted file mode 100644
index 13155a815db71c67ea0c560ab2a9656930adb652..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Driver/inc/usb_dcd_int.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/**
- ******************************************************************************
- * @file usb_dcd_int.h
- * @author MCD Application Team
- * @version V1.0.1
- * @date 31-January-2014
- * @brief Device Control driver Interrupt management Header file
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef USB_DCD_INT_H__
-#define USB_DCD_INT_H__
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_pwr.h"
-
-/* Exported defines ----------------------------------------------------------*/
-/* Mask defining which events has to be handled by the device application software */
-#define IMR_MSK (CNTR_CTRM | CNTR_WKUPM | CNTR_SUSPM | CNTR_ERRM | CNTR_SOFM | \
- CNTR_ESOFM | CNTR_RESETM)
-#ifdef LPM_ENABLED
-#undef IMR_MSK
-#define IMR_MSK (CNTR_CTRM | CNTR_WKUPM | CNTR_SUSPM | CNTR_ERRM | CNTR_SOFM | \
- CNTR_ESOFM | CNTR_RESETM | CNTR_L1REQM)
-#endif
-
-
-
-/* Exported types ------------------------------------------------------------*/
-typedef struct _USBD_DCD_INT
-{
- uint8_t (* DataOutStage) (USB_CORE_HANDLE *pdev , uint8_t epnum);
- uint8_t (* DataInStage) (USB_CORE_HANDLE *pdev , uint8_t epnum);
- uint8_t (* SetupStage) (USB_CORE_HANDLE *pdev);
- uint8_t (* SOF) (USB_CORE_HANDLE *pdev);
- uint8_t (* Reset) (USB_CORE_HANDLE *pdev);
- uint8_t (* Suspend) (USB_CORE_HANDLE *pdev);
- uint8_t (* Resume) (USB_CORE_HANDLE *pdev);
-
-}USBD_DCD_INT_cb_TypeDef;
-
-extern USBD_DCD_INT_cb_TypeDef *USBD_DCD_INT_fops;
-
-/* Exported macros -----------------------------------------------------------*/
-/* Exported variables --------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-void CTR(void);
-void USB_Istr(void);
-
-#endif /* USB_DCD_INT_H__ */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Driver/inc/usb_regs.h b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Driver/inc/usb_regs.h
deleted file mode 100644
index befaa24ffa73a6827f44877f17f12a633e6ff121..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Driver/inc/usb_regs.h
+++ /dev/null
@@ -1,233 +0,0 @@
-/**
- ******************************************************************************
- * @file usb_regs.h
- * @author MCD Application Team
- * @version V1.0.1
- * @date 31-January-2014
- * @brief Interface prototype functions to USB cell registers
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __USB_REGS_H
-#define __USB_REGS_H
-
-/* Exported types ------------------------------------------------------------*/
-typedef enum _EP_DBUF_DIR
-{
- /* double buffered endpoint direction */
- EP_DBUF_OUT,
- EP_DBUF_IN,
- EP_DBUF_ERR,
-}EP_DBUF_DIR;
-
-/* endpoint buffer number */
-enum EP_BUF_NUM
-{
- EP_NOBUF,
- EP_BUF0,
- EP_BUF1
-};
-
-/* Exported defines ----------------------------------------------------------*/
-#define RegBase (0x40005C00L) /* USB_IP Peripheral Registers base address */
-#define PMAAddr (0x40006000L) /* USB_IP Packet Memory Area base address */
-
-/******************************************************************************/
-/* General registers */
-/******************************************************************************/
-
-/* Control register */
-#define CNTR ((__IO unsigned *)(RegBase + 0x40))
-/* Interrupt status register */
-#define ISTR ((__IO unsigned *)(RegBase + 0x44))
-/* Frame number register */
-#define FNR ((__IO unsigned *)(RegBase + 0x48))
-/* Device address register */
-#define DADDR ((__IO unsigned *)(RegBase + 0x4C))
-/* Buffer Table address register */
-#define BTABLE ((__IO unsigned *)(RegBase + 0x50))
-
-/* Battery Charging detector register*/
-#define BCDR (( __IO unsigned *)(RegBase + 0x58))
- /* LPM Control and Status register */
-#define LPMCSR (( __IO unsigned *)(RegBase + 0x54))
-
-/******************************************************************************/
-/* Endpoint registers */
-/******************************************************************************/
-#define EP0REG ((__IO unsigned *)(RegBase)) /* endpoint 0 register address */
-
-/* Endpoint Addresses (w/direction) */
-#define EP0_OUT ((uint8_t)0x00)
-#define EP0_IN ((uint8_t)0x80)
-#define EP1_OUT ((uint8_t)0x01)
-#define EP1_IN ((uint8_t)0x81)
-#define EP2_OUT ((uint8_t)0x02)
-#define EP2_IN ((uint8_t)0x82)
-#define EP3_OUT ((uint8_t)0x03)
-#define EP3_IN ((uint8_t)0x83)
-#define EP4_OUT ((uint8_t)0x04)
-#define EP4_IN ((uint8_t)0x84)
-#define EP5_OUT ((uint8_t)0x05)
-#define EP5_IN ((uint8_t)0x85)
-#define EP6_OUT ((uint8_t)0x06)
-#define EP6_IN ((uint8_t)0x86)
-#define EP7_OUT ((uint8_t)0x07)
-#define EP7_IN ((uint8_t)0x87)
-
-/* endpoints enumeration */
-#define ENDP0 ((uint8_t)0)
-#define ENDP1 ((uint8_t)1)
-#define ENDP2 ((uint8_t)2)
-#define ENDP3 ((uint8_t)3)
-#define ENDP4 ((uint8_t)4)
-#define ENDP5 ((uint8_t)5)
-#define ENDP6 ((uint8_t)6)
-#define ENDP7 ((uint8_t)7)
-
-/******************************************************************************/
-/* ISTR interrupt events */
-/******************************************************************************/
-#define ISTR_CTR (0x8000) /* Correct TRansfer (clear-only bit) */
-#define ISTR_DOVR (0x4000) /* DMA OVeR/underrun (clear-only bit) */
-#define ISTR_ERR (0x2000) /* ERRor (clear-only bit) */
-#define ISTR_WKUP (0x1000) /* WaKe UP (clear-only bit) */
-#define ISTR_SUSP (0x0800) /* SUSPend (clear-only bit) */
-#define ISTR_RESET (0x0400) /* RESET (clear-only bit) */
-#define ISTR_SOF (0x0200) /* Start Of Frame (clear-only bit) */
-#define ISTR_ESOF (0x0100) /* Expected Start Of Frame (clear-only bit) */
-#define ISTR_L1REQ (0x0080) /* LPM L1 state request */
-#define ISTR_DIR (0x0010) /* DIRection of transaction (read-only bit) */
-#define ISTR_EP_ID (0x000F) /* EndPoint IDentifier (read-only bit) */
-
-#define CLR_CTR (~ISTR_CTR) /* clear Correct TRansfer bit */
-#define CLR_DOVR (~ISTR_DOVR) /* clear DMA OVeR/underrun bit*/
-#define CLR_ERR (~ISTR_ERR) /* clear ERRor bit */
-#define CLR_WKUP (~ISTR_WKUP) /* clear WaKe UP bit */
-#define CLR_SUSP (~ISTR_SUSP) /* clear SUSPend bit */
-#define CLR_RESET (~ISTR_RESET) /* clear RESET bit */
-#define CLR_SOF (~ISTR_SOF) /* clear Start Of Frame bit */
-#define CLR_ESOF (~ISTR_ESOF) /* clear Expected Start Of Frame bit */
-#define CLR_L1REQ (~ISTR_L1REQ) /* clear LPM L1 bit */
-
-/******************************************************************************/
-/* CNTR control register bits definitions */
-/******************************************************************************/
-#define CNTR_CTRM (0x8000) /* Correct TRansfer Mask */
-#define CNTR_DOVRM (0x4000) /* DMA OVeR/underrun Mask */
-#define CNTR_ERRM (0x2000) /* ERRor Mask */
-#define CNTR_WKUPM (0x1000) /* WaKe UP Mask */
-#define CNTR_SUSPM (0x0800) /* SUSPend Mask */
-#define CNTR_RESETM (0x0400) /* RESET Mask */
-#define CNTR_SOFM (0x0200) /* Start Of Frame Mask */
-#define CNTR_ESOFM (0x0100) /* Expected Start Of Frame Mask */
-#define CNTR_L1REQM (0x0080) /* LPM L1 state request interrupt mask */
-#define CNTR_L1RESUME (0x0020) /* LPM L1 Resume request */
-#define CNTR_RESUME (0x0010) /* RESUME request */
-#define CNTR_FSUSP (0x0008) /* Force SUSPend */
-#define CNTR_LPMODE (0x0004) /* Low-power MODE */
-#define CNTR_PDWN (0x0002) /* Power DoWN */
-#define CNTR_FRES (0x0001) /* Force USB RESet */
-
-/******************************************************************************/
-/* BCDR control register bits definitions */
-/******************************************************************************/
-#define BCDR_DPPU ((uint16_t)0x8000) /* DP Pull-up Enable */
-#define BCDR_PS2DET ((uint16_t)0x0080) /* PS2 port or proprietary charger detected */
-#define BCDR_SDET ((uint16_t)0x0040) /* Secondary detection (SD) status */
-#define BCDR_PDET ((uint16_t)0x0020) /* Primary detection (PD) status */
-#define BCDR_DCDET ((uint16_t)0x0010) /* Data contact detection (DCD) status */
-#define BCDR_SDEN ((uint16_t)0x0008) /* Secondary detection (SD) mode enable */
-#define BCDR_PDEN ((uint16_t)0x0004) /* Primary detection (PD) mode enable */
-#define BCDR_DCDEN ((uint16_t)0x0002) /* Data contact detection (DCD) mode enable*/
-#define BCDR_BCDEN ((uint16_t)0x0001) /* Battery charging detector (BCD) enable */
-
-/******************************************************************************/
-/* Bit definition for LPM register */
-/******************************************************************************/
-#define LPMCSR_BESL ((uint16_t)0x00F0) /* BESL value received with last ACKed LPM Token */
-#define LPMCSR_REMWAKE ((uint16_t)0x0008) /* bRemoteWake value received with last ACKed LPM Token */
-#define LPMCSR_LPMACK ((uint16_t)0x0002) /* LPM Token acknowledge enable*/
-#define LPMCSR_LMPEN ((uint16_t)0x0001) /* LPM support enable */
-
-/******************************************************************************/
-/* FNR Frame Number Register bit definitions */
-/******************************************************************************/
-#define FNR_RXDP (0x8000) /* status of D+ data line */
-#define FNR_RXDM (0x4000) /* status of D- data line */
-#define FNR_LCK (0x2000) /* LoCKed */
-#define FNR_LSOF (0x1800) /* Lost SOF */
-#define FNR_FN (0x07FF) /* Frame Number */
-/******************************************************************************/
-/* DADDR Device ADDRess bit definitions */
-/******************************************************************************/
-#define DADDR_EF (0x80)
-#define DADDR_ADD (0x7F)
-/******************************************************************************/
-/* Endpoint register */
-/******************************************************************************/
-/* bit positions */
-#define EP_CTR_RX (0x8000) /* EndPoint Correct TRansfer RX */
-#define EP_DTOG_RX (0x4000) /* EndPoint Data TOGGLE RX */
-#define EPRX_STAT (0x3000) /* EndPoint RX STATus bit field */
-#define EP_SETUP (0x0800) /* EndPoint SETUP */
-#define EP_T_FIELD (0x0600) /* EndPoint TYPE */
-#define EP_KIND (0x0100) /* EndPoint KIND */
-#define EP_CTR_TX (0x0080) /* EndPoint Correct TRansfer TX */
-#define EP_DTOG_TX (0x0040) /* EndPoint Data TOGGLE TX */
-#define EPTX_STAT (0x0030) /* EndPoint TX STATus bit field */
-#define EPADDR_FIELD (0x000F) /* EndPoint ADDRess FIELD */
-
-/* EndPoint REGister MASK (no toggle fields) */
-#define EPREG_MASK (EP_CTR_RX|EP_SETUP|EP_T_FIELD|EP_KIND|EP_CTR_TX|EPADDR_FIELD)
-
-/* EP_TYPE[1:0] EndPoint TYPE */
-#define EP_TYPE_MASK (0x0600) /* EndPoint TYPE Mask */
-#define EP_BULK (0x0000) /* EndPoint BULK */
-#define EP_CONTROL (0x0200) /* EndPoint CONTROL */
-#define EP_ISOCHRONOUS (0x0400) /* EndPoint ISOCHRONOUS */
-#define EP_INTERRUPT (0x0600) /* EndPoint INTERRUPT */
-#define EP_T_MASK (~EP_T_FIELD & EPREG_MASK)
-
-/* EP_KIND EndPoint KIND */
-#define EPKIND_MASK (~EP_KIND & EPREG_MASK)
-
-/* STAT_TX[1:0] STATus for TX transfer */
-#define EP_TX_DIS (0x0000) /* EndPoint TX DISabled */
-#define EP_TX_STALL (0x0010) /* EndPoint TX STALLed */
-#define EP_TX_NAK (0x0020) /* EndPoint TX NAKed */
-#define EP_TX_VALID (0x0030) /* EndPoint TX VALID */
-#define EPTX_DTOG1 (0x0010) /* EndPoint TX Data TOGgle bit1 */
-#define EPTX_DTOG2 (0x0020) /* EndPoint TX Data TOGgle bit2 */
-#define EPTX_DTOGMASK (EPTX_STAT|EPREG_MASK)
-
-/* STAT_RX[1:0] STATus for RX transfer */
-#define EP_RX_DIS (0x0000) /* EndPoint RX DISabled */
-#define EP_RX_STALL (0x1000) /* EndPoint RX STALLed */
-#define EP_RX_NAK (0x2000) /* EndPoint RX NAKed */
-#define EP_RX_VALID (0x3000) /* EndPoint RX VALID */
-#define EPRX_DTOG1 (0x1000) /* EndPoint RX Data TOGgle bit1 */
-#define EPRX_DTOG2 (0x2000) /* EndPoint RX Data TOGgle bit1 */
-#define EPRX_DTOGMASK (EPRX_STAT|EPREG_MASK)
-
-#endif /* __USB_REGS_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Driver/src/usb_bsp_template.c b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Driver/src/usb_bsp_template.c
deleted file mode 100644
index 27d8804c4639aa217ccb9e8ebeea929ffef4e83b..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Driver/src/usb_bsp_template.c
+++ /dev/null
@@ -1,82 +0,0 @@
-/**
- ******************************************************************************
- * @file usb_bsp.c
- * @author MCD Application Team
- * @version V1.0.1
- * @date 31-January-2014
- * @brief This file Provides Device Core configuration Functions
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "usb_bsp.h"
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/**
- * @brief USB_BSP_Init
- * Initialize BSP configurations
- * @param None
- * @retval None
- */
-
-void USB_BSP_Init(void)
-{
-
-}
-/**
- * @brief USB_BSP_EnableInterrupt
- * Enable USB Global interrupt
- * @param None
- * @retval None
- */
-void USB_BSP_EnableInterrupt(void)
-{
-
-}
-
-/**
-* @brief Configure CRS peripheral to automatically trim the HSI
-* oscillator according to USB SOF
-* @param None
-* @retval None
-*/
-void CRS_Config(void)
-{
-
-}
-
-/**
-* @brief Set system clock to HSI48
-* @param None
-* @param None
-* @retval None
-*/
-void SetSystemClockHSI48(void)
-{
-
-}
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Driver/src/usb_core.c b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Driver/src/usb_core.c
deleted file mode 100644
index 730da80e42ef81cdc311a2dd6f58fa4c02fb4d2b..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Driver/src/usb_core.c
+++ /dev/null
@@ -1,712 +0,0 @@
-/**
- ******************************************************************************
- * @file usb_core.c
- * @author MCD Application Team
- * @version V1.0.1
- * @date 31-January-2014
- * @brief This file provides the interface functions to USB cell registers
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "usb_core.h"
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/**
- * @brief Set the CNTR register value
- * @param wRegValue: new register value
- * @retval None
- */
-void SetCNTR(uint16_t wRegValue)
-{
- _SetCNTR(wRegValue);
-}
-
-/**
- * @brief returns the CNTR register value
- * @param None
- * @retval CNTR register Value
- */
-uint16_t GetCNTR(void)
-{
- return(_GetCNTR());
-}
-
-/**
- * @brief Set the ISTR register value
- * @param wRegValue: new register value
- * @retval None
- */
-void SetISTR(uint16_t wRegValue)
-{
- _SetISTR(wRegValue);
-}
-
-/**
- * @brief Returns the ISTR register value
- * @param None
- * @retval ISTR register Value
- */
-uint16_t GetISTR(void)
-{
- return(_GetISTR());
-}
-
-/**
- * @brief Returns the FNR register value
- * @param None
- * @retval FNR register Value
- */
-uint16_t GetFNR(void)
-{
- return(_GetFNR());
-}
-
-/**
- * @brief Set the DADDR register value
- * @param wRegValue: new register value
- * @retval None
- */
-void SetDADDR(uint16_t wRegValue)
-{
- _SetDADDR(wRegValue);
-}
-
-/**
- * @brief Set the LPMCSR register value
- * @param wRegValue: new register value
- * @retval None
- */
-void SetLPMCSR(uint16_t wRegValue)
-{
- _SetLPMCSR(wRegValue);
-}
-
-
-/**
- * @brief Returns the LPMCSR register value
- * @param None
- * @retval LPMCSR register Value
- */
-uint16_t GetLPMCSR(void)
-{
- return(_GetLPMCSR());
-}
-
-/**
- * @brief Returns the DADDR register value
- * @param None
- * @retval DADDR register Value
- */
-uint16_t GetDADDR(void)
-{
- return(_GetDADDR());
-}
-
-/**
- * @brief Set the BTABLE.
- * @param wRegValue: New register value
- * @retval None
- */
-void SetBTABLE(uint16_t wRegValue)
-{
- _SetBTABLE(wRegValue);
-}
-
-/**
- * @brief Returns the BTABLE register value.
- * @param None
- * @retval BTABLE address
- */
-uint16_t GetBTABLE(void)
-{
- return(_GetBTABLE());
-}
-
-/**
- * @brief Set the Endpoint register value.
- * @param bEpNum: Endpoint Number
- * @retval None
- */
-void SetENDPOINT(uint8_t bEpNum, uint16_t wRegValue)
-{
- _SetENDPOINT(bEpNum, wRegValue);
-}
-
-/**
- * @brief Return the Endpoint register value.
- * @param bEpNum: Endpoint Number
- * @retval Endpoint register value.
- */
-uint16_t GetENDPOINT(uint8_t bEpNum)
-{
- return(_GetENDPOINT(bEpNum));
-}
-
-/**
- * @brief sets the type in the endpoint register.
- * @param bEpNum: Endpoint Number
- * @param wType: type definition
- * @retval None.
- */
-void SetEPType(uint8_t bEpNum, uint16_t wType)
-{
- _SetEPType(bEpNum, wType);
-}
-
-/**
- * @brief Returns the endpoint type.
- * @param bEpNum: Endpoint Number
- * @retval Endpoint Type.
- */
-uint16_t GetEPType(uint8_t bEpNum)
-{
- return(_GetEPType(bEpNum));
-}
-
-/**
- * @brief Set the status of Tx endpoint.
- * @param bEpNum: Endpoint Number
- * @param wState: new state.
- * @retval None
- */
-void SetEPTxStatus(uint8_t bEpNum, uint16_t wState)
-{
- _SetEPTxStatus(bEpNum, wState);
-}
-
-/**
- * @brief Set the status of Rx endpoint.
- * @param bEpNum: Endpoint Number
- * @param wState: new state.
- * @retval None
- */
-void SetEPRxStatus(uint8_t bEpNum, uint16_t wState)
-{
- _SetEPRxStatus(bEpNum, wState);
-}
-
-/**
- * @brief sets the status for Double Buffer Endpoint to STALL
- * @param bEpNum: Endpoint Number
- * @param bDir: Endpoint direction
- * @retval None
- */
-void SetDouBleBuffEPStall(uint8_t bEpNum, uint8_t bDir)
-{
- uint16_t Endpoint_DTOG_Status;
- Endpoint_DTOG_Status = GetENDPOINT(bEpNum);
- if (bDir == EP_DBUF_OUT)
- { /* OUT double buffered endpoint */
- _SetENDPOINT(bEpNum, Endpoint_DTOG_Status & ~EPRX_DTOG1);
- }
- else if (bDir == EP_DBUF_IN)
- { /* IN double buffered endpoint */
- _SetENDPOINT(bEpNum, Endpoint_DTOG_Status & ~EPTX_DTOG1);
- }
-}
-
-/**
- * @brief Returns the endpoint Tx status
- * @param bEpNum: Endpoint Number
- * @retval Endpoint TX Status
- */
-uint16_t GetEPTxStatus(uint8_t bEpNum)
-{
- return(_GetEPTxStatus(bEpNum));
-}
-
-/**
- * @brief Returns the endpoint Rx status
- * @param bEpNum: Endpoint Number
- * @retval Endpoint Endpoint RX Status
- */
-uint16_t GetEPRxStatus(uint8_t bEpNum)
-{
- return(_GetEPRxStatus(bEpNum));
-}
-
-/**
- * @brief Valid the endpoint Tx Status.
- * @param bEpNum: Endpoint Number
- * @retval None
- */
-void SetEPTxValid(uint8_t bEpNum)
-{
- _SetEPTxStatus(bEpNum, EP_TX_VALID);
-}
-
-/**
- * @brief Valid the endpoint Rx Status.
- * @param bEpNum: Endpoint Number
- * @retval None
- */
-void SetEPRxValid(uint8_t bEpNum)
-{
- _SetEPRxStatus(bEpNum, EP_RX_VALID);
-}
-
-/**
- * @brief set the EP_KIND bit.
- * @param bEpNum: Endpoint Number
- * @retval None
- */
-void SetEP_KIND(uint8_t bEpNum)
-{
- _SetEP_KIND(bEpNum);
-}
-
-/**
- * @brief ClearEP_KIND
- * @param bEpNum: Endpoint Number
- * @retval None
- */
-void ClearEP_KIND(uint8_t bEpNum)
-{
- _ClearEP_KIND(bEpNum);
-}
-
-/**
- * @brief Clear the Status Out of the related Endpoint
- * @param bEpNum: Endpoint Number
- * @retval None
- */
-void Clear_Status_Out(uint8_t bEpNum)
-{
- _ClearEP_KIND(bEpNum);
-}
-
-/**
- * @brief Set the Status Out of the related Endpoint
- * @param bEpNum: Endpoint Number
- * @retval None
- */
-void Set_Status_Out(uint8_t bEpNum)
-{
- _SetEP_KIND(bEpNum);
-}
-
-/**
- * @brief Enable the double buffer feature for the endpoint.
- * @param bEpNum: Endpoint Number
- * @retval None
- */
-void SetEPDoubleBuff(uint8_t bEpNum)
-{
- _SetEP_KIND(bEpNum);
-}
-
-/**
- * @brief Disable the double buffer feature for the endpoint
- * @param bEpNum: Endpoint Number
- * @retval None
- */
-void ClearEPDoubleBuff(uint8_t bEpNum)
-{
- _ClearEP_KIND(bEpNum);
-}
-
-/**
- * @brief Returns the Stall status of the Tx endpoint
- * @param bEpNum: Endpoint Number
- * @retval Tx Stall status
- */
-uint16_t GetTxStallStatus(uint8_t bEpNum)
-{
- return(_GetTxStallStatus(bEpNum));
-}
-
-/**
- * @brief Returns the Stall status of the Rx endpoint
- * @param bEpNum: Endpoint Number
- * @retval Rx Stall status.
- */
-uint16_t GetRxStallStatus(uint8_t bEpNum)
-{
- return(_GetRxStallStatus(bEpNum));
-}
-
-/**
- * @brief Returns the Stall status of the Rx endpoint
- * @param bEpNum: Endpoint Number
- * @retval None
- */
-void ClearEP_CTR_RX(uint8_t bEpNum)
-{
- _ClearEP_CTR_RX(bEpNum);
-}
-
-/**
- * @brief Clear the CTR_TX bit
- * @param bEpNum: Endpoint Number
- * @retval None
- */
-void ClearEP_CTR_TX(uint8_t bEpNum)
-{
- _ClearEP_CTR_TX(bEpNum);
-}
-
-/**
- * @brief Toggle the DTOG_RX bit.
- * @param bEpNum: Endpoint Number
- * @retval None
- */
-void ToggleDTOG_RX(uint8_t bEpNum)
-{
- _ToggleDTOG_RX(bEpNum);
-}
-
-/**
- * @brief Toggle the DTOG_TX bit.
- * @param bEpNum: Endpoint Number
- * @retval None
- */
-void ToggleDTOG_TX(uint8_t bEpNum)
-{
- _ToggleDTOG_TX(bEpNum);
-}
-
-/**
- * @brief Clear the DTOG_RX bit.
- * @param bEpNum: Endpoint Number
- * @retval None
- */
-void ClearDTOG_RX(uint8_t bEpNum)
-{
- _ClearDTOG_RX(bEpNum);
-}
-
-/**
- * @brief Clear the DTOG_TX bit.
- * @param bEpNum: Endpoint Number
- * @retval None
- */
-void ClearDTOG_TX(uint8_t bEpNum)
-{
- _ClearDTOG_TX(bEpNum);
-}
-
-/**
- * @brief Set the endpoint address.
- * @param bEpNum: Endpoint Number
- * @param bAddr: New endpoint address.
- * @retval None
- */
-void SetEPAddress(uint8_t bEpNum, uint8_t bAddr)
-{
- _SetEPAddress(bEpNum, bAddr);
-}
-
-/**
- * @brief Get the endpoint address.
- * @param bEpNum: Endpoint Number
- * @retval Endpoint address.
- */
-uint8_t GetEPAddress(uint8_t bEpNum)
-{
- return(_GetEPAddress(bEpNum));
-}
-
-/**
- * @brief Set the endpoint Tx buffer address.
- * @param bEpNum: Endpoint Number
- * @param wAddr: new address.
- * @retval Endpoint address.
- */
-void SetEPTxAddr(uint8_t bEpNum, uint16_t wAddr)
-{
- _SetEPTxAddr(bEpNum, wAddr);
-}
-
-/**
- * @brief Set the endpoint Rx buffer address.
- * @param bEpNum: Endpoint Number
- * @param wAddr: new address.
- * @retval Endpoint address.
- */
-void SetEPRxAddr(uint8_t bEpNum, uint16_t wAddr)
-{
- _SetEPRxAddr(bEpNum, wAddr);
-}
-
-/**
- * @brief Returns the endpoint Tx buffer address.
- * @param bEpNum: Endpoint Number
- * @retval Tx buffer address.
- */
-uint16_t GetEPTxAddr(uint8_t bEpNum)
-{
- return(_GetEPTxAddr(bEpNum));
-}
-
-/**
- * @brief Returns the endpoint Rx buffer address.
- * @param bEpNum: Endpoint Number
- * @retval Rx buffer address.
- */
-uint16_t GetEPRxAddr(uint8_t bEpNum)
-{
- return(_GetEPRxAddr(bEpNum));
-}
-
-/**
- * @brief Set the Tx count.
- * @param bEpNum: Endpoint Number
- * @param wCount: new count value.
- * @retval Rx buffer address.
- */
-void SetEPTxCount(uint8_t bEpNum, uint16_t wCount)
-{
- _SetEPTxCount(bEpNum, wCount);
-}
-
-/**
- * @brief Set the Count Rx Register value.
- * @param *pdwReg: point to the register.
- * @param wCount: the new register value.
- * @retval None
- */
-void SetEPCountRxReg(uint16_t *pdwReg, uint16_t wCount)
-{
- _SetEPCountRxReg(pdwReg, wCount);
-}
-
-/**
- * @brief Set the Rx count.
- * @param bEpNum: Endpoint Number.
- * @param wCount: the new register value.
- * @retval None
- */
-void SetEPRxCount(uint8_t bEpNum, uint16_t wCount)
-{
- _SetEPRxCount(bEpNum, wCount);
-}
-
-/**
- * @brief Get the Tx count.
- * @param bEpNum: Endpoint Number.
- * @retval Tx count value.
- */
-uint16_t GetEPTxCount(uint8_t bEpNum)
-{
- return(_GetEPTxCount(bEpNum));
-}
-
-/**
- * @brief Get the Rx count.
- * @param bEpNum: Endpoint Number.
- * @retval Rx count value.
- */
-uint16_t GetEPRxCount(uint8_t bEpNum)
-{
- return(_GetEPRxCount(bEpNum));
-}
-
-/**
- * @brief Set the addresses of the buffer 0 and 1.
- * @param bEpNum: Endpoint Number.
- * @param wBuf0Addr: new address of buffer 0.
- * @param wBuf1Addr: new address of buffer 1.
- * @retval None
- */
-void SetEPDblBuffAddr(uint8_t bEpNum, uint16_t wBuf0Addr, uint16_t wBuf1Addr)
-{
- _SetEPDblBuffAddr(bEpNum, wBuf0Addr, wBuf1Addr);
-}
-
-/**
- * @brief Set the Buffer 1 address.
- * @param bEpNum: Endpoint Number.
- * @param wBuf0Addr: new address.
- * @retval None
- */
-void SetEPDblBuf0Addr(uint8_t bEpNum, uint16_t wBuf0Addr)
-{
- _SetEPDblBuf0Addr(bEpNum, wBuf0Addr);
-}
-
-/**
- * @brief Set the Buffer 1 address.
- * @param bEpNum: Endpoint Number.
- * @param wBuf1Addr: new address.
- * @retval None
- */
-void SetEPDblBuf1Addr(uint8_t bEpNum, uint16_t wBuf1Addr)
-{
- _SetEPDblBuf1Addr(bEpNum, wBuf1Addr);
-}
-
-/**
- * @brief Returns the address of the Buffer 0.
- * @param bEpNum: Endpoint Number.
- * @retval None
- */
-uint16_t GetEPDblBuf0Addr(uint8_t bEpNum)
-{
- return(_GetEPDblBuf0Addr(bEpNum));
-}
-
-/**
- * @brief Returns the address of the Buffer 1.
- * @param bEpNum: Endpoint Number.
- * @retval Address of the Buffer 1.
- */
-uint16_t GetEPDblBuf1Addr(uint8_t bEpNum)
-{
- return(_GetEPDblBuf1Addr(bEpNum));
-}
-
-/**
- * @brief Set the number of bytes for a double Buffer
- * @param bEpNum,bDir, wCount
- * @retval Address of the Buffer 1.
- */
-void SetEPDblBuffCount(uint8_t bEpNum, uint8_t bDir, uint16_t wCount)
-{
- _SetEPDblBuffCount(bEpNum, bDir, wCount);
-}
-
-/**
- * @brief Set the number of bytes in the buffer 0 of a double Buffer endpoint.
- * @param bEpNum,bDir, wCount
- * @retval None
- */
-void SetEPDblBuf0Count(uint8_t bEpNum, uint8_t bDir, uint16_t wCount)
-{
- _SetEPDblBuf0Count(bEpNum, bDir, wCount);
-}
-
-/**
- * @brief Set the number of bytes in the buffer 0 of a double Buffer
- * @param bEpNum,bDir, wCount
- * @retval None
- */
-void SetEPDblBuf1Count(uint8_t bEpNum, uint8_t bDir, uint16_t wCount)
-{
- _SetEPDblBuf1Count(bEpNum, bDir, wCount);
-}
-
-/**
- * @brief Returns the number of byte received in the buffer 0 of a double
- * Buffer endpoint.
- * @param bEpNum: Endpoint Number.
- * @retval Endpoint Buffer 0 count
- */
-uint16_t GetEPDblBuf0Count(uint8_t bEpNum)
-{
- return(_GetEPDblBuf0Count(bEpNum));
-}
-
-/**
- * @brief Returns the number of data received in the buffer 1 of a double
- * @param bEpNum: Endpoint Number.
- * @retval Endpoint Buffer 1 count
- */
-uint16_t GetEPDblBuf1Count(uint8_t bEpNum)
-{
- return(_GetEPDblBuf1Count(bEpNum));
-}
-
-/**
- * @brief gets direction of the double buffered endpoint
- * @param bEpNum: Endpoint Number.
- * @retval EP_DBUF_OUT, EP_DBUF_IN,
- * EP_DBUF_ERR if the endpoint counter not yet programmed.
- */
-EP_DBUF_DIR GetEPDblBufDir(uint8_t bEpNum)
-{
- if ((uint16_t)(*_pEPRxCount(bEpNum) & 0xFC00) != 0)
- return(EP_DBUF_OUT);
- else if (((uint16_t)(*_pEPTxCount(bEpNum)) & 0x03FF) != 0)
- return(EP_DBUF_IN);
- else
- return(EP_DBUF_ERR);
-}
-
-/**
- * @brief free buffer used from the application realizing it to the line
- toggles bit SW_BUF in the double buffered endpoint register
- * @param bEpNum, bDir
- * @retval None
- */
-void FreeUserBuffer(uint8_t bEpNum, uint8_t bDir)
-{
- if (bDir == EP_DBUF_OUT)
- { /* OUT double buffered endpoint */
- _ToggleDTOG_TX(bEpNum);
- }
- else if (bDir == EP_DBUF_IN)
- { /* IN double buffered endpoint */
- _ToggleDTOG_RX(bEpNum);
- }
-}
-
-/**
- * @brief Copy a buffer from user memory area to packet memory area (PMA)
- * @param pbUsrBuf: pointer to user memory area.
- * @param wPMABufAddr: address into PMA.
- * @param wNBytes: no. of bytes to be copied.
- * @retval None
- */
-void UserToPMABufferCopy(uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
-{
- uint32_t n = (wNBytes + 1) >> 1;
- uint32_t i;
- uint16_t temp1, temp2;
- uint16_t *pdwVal;
- pdwVal = (uint16_t *)(wPMABufAddr + PMAAddr);
-
- for (i = n; i != 0; i--)
- {
- temp1 = (uint16_t) * pbUsrBuf;
- pbUsrBuf++;
- temp2 = temp1 | (uint16_t) * pbUsrBuf << 8;
- *pdwVal++ = temp2;
- pbUsrBuf++;
- }
-}
-
-/**
- * @brief Copy a buffer from user memory area to packet memory area (PMA)
- * @param pbUsrBuf = pointer to user memory area.
- * @param wPMABufAddr: address into PMA.
- * @param wNBytes: no. of bytes to be copied.
- * @retval None
- */
-void PMAToUserBufferCopy(uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
-{
- uint32_t n = (wNBytes + 1) >> 1;
- uint32_t i;
- uint16_t *pdwVal;
- pdwVal = (uint16_t *)(wPMABufAddr + PMAAddr);
- for (i = n; i != 0; i--)
- {
- *(uint16_t*)pbUsrBuf++ = *pdwVal++;
- pbUsrBuf++;
- }
-}
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Driver/src/usb_dcd.c b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Driver/src/usb_dcd.c
deleted file mode 100644
index 0544cbfce6e6c1e016b011b6b4cff59c95296fb7..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Driver/src/usb_dcd.c
+++ /dev/null
@@ -1,648 +0,0 @@
-/**
- ******************************************************************************
- * @file usb_dcd.c
- * @author MCD Application Team
- * @version V1.0.1
- * @date 31-January-2014
- * @brief Device interface layer used by the library to access the core.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "usb_dcd.h"
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-uint32_t wInterrupt_Mask=0;
-
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/**
- * @brief Device Initialization
- * @param pdev: device instance
- * @retval : None
- */
-void DCD_Init(USB_CORE_HANDLE *pdev)
-{
- /*Device is in Default State*/
- pdev->dev.device_status = USB_DEFAULT;
- pdev->dev.device_address = 0;
- pdev->dev.DevRemoteWakeup = 0;
-
- pdev->dev.speed = USB_SPEED_FULL; /*kept for API compatibility reason*/
-
- /*CNTR_FRES = 1*/
- SetCNTR(CNTR_FRES);
-
- /*CNTR_FRES = 0*/
- SetCNTR(0);
-
- /*Clear pending interrupts*/
- SetISTR(0);
-
- /*Set Btable Address*/
- SetBTABLE(BTABLE_ADDRESS);
-
- /*set wInterrupt_Mask global variable*/
- wInterrupt_Mask = CNTR_CTRM | CNTR_WKUPM | CNTR_SUSPM | CNTR_ERRM | CNTR_SOFM \
- | CNTR_ESOFM | CNTR_RESETM;
-
-#ifdef LPM_ENABLED
- /* enable L1REQ interrupt */
- wInterrupt_Mask |= CNTR_L1REQM;
-
- /* Enable LPM support and enable ACK answer to LPM request*/
- _SetLPMCSR(LPMCSR_LMPEN | LPMCSR_LPMACK);
-#endif
-
- /*Set interrupt mask*/
- SetCNTR(wInterrupt_Mask);
-}
-
-
-/**
- * @brief Stop device
- * @param pdev: device instance
- * @retval : None
- */
-void DCD_StopDevice(USB_CORE_HANDLE *pdev)
-{
- /* disable all interrupts and force USB reset */
- _SetCNTR(CNTR_FRES);
-
- /* clear interrupt status register */
- _SetISTR(0);
-
- /* switch-off device */
- _SetCNTR(CNTR_FRES + CNTR_PDWN);
-
- /*Device is in default state*/
- pdev->dev.device_status = USB_DEFAULT;
-
-}
-
-/**
- * @brief Configure PMA for EP
- * @param pdev : Device instance
- * @param ep_addr: endpoint address
- * @param ep_Kind: endpoint Kind
- * @arg USB_SNG_BUF: Single Buffer used
- * @arg USB_DBL_BUF: Double Buffer used
- * @param pmaadress: EP address in The PMA: In case of single buffer endpoint
- * this parameter is 16-bit value providing the address
- * in PMA allocated to endpoint.
- * In case of double buffer endpoint this parameter
- * is a 32-bit value providing the endpoint buffer 0 address
- * in the LSB part of 32-bit value and endpoint buffer 1 address
- * in the MSB part of 32-bit value.
- * @retval : status
- */
-
-uint32_t DCD_PMA_Config(USB_CORE_HANDLE *pdev ,
- uint16_t ep_addr,
- uint16_t ep_kind,
- uint32_t pmaadress)
-
-{
- USB_EP *ep;
- /* initialize ep structure*/
- if ((ep_addr & 0x80) == 0x80)
- {
- ep = &pdev->dev.in_ep[ep_addr & 0x7F];
- }
- else
- {
- ep = &pdev->dev.out_ep[ep_addr & 0x7F];
- }
-
- /* Here we check if the endpoint is single or double Buffer*/
- if (ep_kind == USB_SNG_BUF)
- {
- /*Single Buffer*/
- ep->doublebuffer = 0;
- /*Configure te PMA*/
- ep->pmaadress = (uint16_t)pmaadress;
- }
- else /*USB_DBL_BUF*/
- {
- /*Double Buffer Endpoint*/
- ep->doublebuffer = 1;
- /*Configure the PMA*/
- ep->pmaaddr0 = pmaadress & 0xFFFF;
- ep->pmaaddr1 = (pmaadress & 0xFFFF0000) >> 16;
- }
-
- return USB_OK;
-}
-
-/**
- * @brief Configure an EP
- * @param pdev : Device instance
- * @param ep_addr: endpoint address
- * @param ep_mps: endpoint max packet size
- * @param ep_type: endpoint Type
- */
-uint32_t DCD_EP_Open(USB_CORE_HANDLE *pdev ,
- uint16_t ep_addr,
- uint16_t ep_mps,
- uint8_t ep_type)
-{
-
- USB_EP *ep;
-
- /* initialize ep structure*/
- if ((ep_addr & 0x80) == 0x80)
- {
- ep = &pdev->dev.in_ep[ep_addr & 0x7F];
- ep->is_in = 1;
- }
- else
- {
- ep = &pdev->dev.out_ep[ep_addr & 0x7F];
- ep->is_in = 0;
- }
-
- ep->maxpacket = ep_mps;
- ep->type = ep_type;
- ep->num = ep_addr & 0x7F;
-
- if (ep->num == 0)
- {
- /* Initialize the control transfer variables*/
- ep->ctl_data_len =0;
- ep->rem_data_len = 0;
- ep->total_data_len = 0;
- }
-
- /* Initialize the transaction level variables */
- ep->xfer_buff = 0;
- ep->xfer_len = 0;
- ep->xfer_count = 0;
- ep->is_stall = 0;
-
- /* initialize HW */
- switch (ep->type)
- {
- case USB_EP_CONTROL:
- SetEPType(ep->num, EP_CONTROL);
- break;
- case USB_EP_BULK:
- SetEPType(ep->num, EP_BULK);
- break;
- case USB_EP_INT:
- SetEPType(ep->num, EP_INTERRUPT);
- break;
- case USB_EP_ISOC:
- SetEPType(ep->num, EP_ISOCHRONOUS);
- break;
- }
-
- if (ep->doublebuffer == 0)
- {
- if (ep->is_in)
- {
- /*Set the endpoint Transmit buffer address */
- SetEPTxAddr(ep->num, ep->pmaadress);
- ClearDTOG_TX(ep->num);
- /* Configure NAK status for the Endpoint*/
- SetEPTxStatus(ep->num, EP_TX_NAK);
- }
- else
- {
- /*Set the endpoint Receive buffer address */
- SetEPRxAddr(ep->num, ep->pmaadress);
- /*Set the endpoint Receive buffer counter*/
- SetEPRxCount(ep->num, ep->maxpacket);
- ClearDTOG_RX(ep->num);
- /* Configure VALID status for the Endpoint*/
- SetEPRxStatus(ep->num, EP_RX_VALID);
- }
- }
- /*Double Buffer*/
- else
- {
- /*Set the endpoint as double buffered*/
- SetEPDoubleBuff(ep->num);
- /*Set buffer address for double buffered mode*/
- SetEPDblBuffAddr(ep->num,ep->pmaaddr0, ep->pmaaddr1);
-
- if (ep->is_in==0)
- {
- /* Clear the data toggle bits for the endpoint IN/OUT*/
- ClearDTOG_RX(ep->num);
- ClearDTOG_TX(ep->num);
-
- /* Reset value of the data toggle bits for the endpoint out*/
- ToggleDTOG_TX(ep->num);
-
- SetEPRxStatus(ep->num, EP_RX_VALID);
- SetEPTxStatus(ep->num, EP_TX_DIS);
- }
- else
- {
- /* Clear the data toggle bits for the endpoint IN/OUT*/
- ClearDTOG_RX(ep->num);
- ClearDTOG_TX(ep->num);
- ToggleDTOG_RX(ep->num);
- /* Configure DISABLE status for the Endpoint*/
- SetEPTxStatus(ep->num, EP_TX_DIS);
- SetEPRxStatus(ep->num, EP_RX_DIS);
- }
- }
- return USB_OK;
-}
-/**
- * @brief called when an EP is disabled
- * @param pdev: device instance
- * @param ep_addr: endpoint address
- * @retval : status
- */
-uint32_t DCD_EP_Close(USB_CORE_HANDLE *pdev , uint8_t ep_addr)
-{
- USB_EP *ep;
-
- if ((ep_addr&0x80) == 0x80)
- {
- ep = &pdev->dev.in_ep[ep_addr & 0x7F];
- }
- else
- {
- ep = &pdev->dev.out_ep[ep_addr & 0x7F];
- }
-
- if (ep->doublebuffer == 0)
- {
- if (ep->is_in)
- {
- ClearDTOG_TX(ep->num);
- /* Configure DISABLE status for the Endpoint*/
- SetEPTxStatus(ep->num, EP_TX_DIS);
- }
- else
- {
- ClearDTOG_RX(ep->num);
- /* Configure DISABLE status for the Endpoint*/
- SetEPRxStatus(ep->num, EP_RX_DIS);
- }
- }
- /*Double Buffer*/
- else
- {
- if (ep->is_in==0)
- {
- /* Clear the data toggle bits for the endpoint IN/OUT*/
- ClearDTOG_RX(ep->num);
- ClearDTOG_TX(ep->num);
-
- /* Reset value of the data toggle bits for the endpoint out*/
- ToggleDTOG_TX(ep->num);
-
- SetEPRxStatus(ep->num, EP_RX_DIS);
- SetEPTxStatus(ep->num, EP_TX_DIS);
- }
- else
- {
- /* Clear the data toggle bits for the endpoint IN/OUT*/
- ClearDTOG_RX(ep->num);
- ClearDTOG_TX(ep->num);
- ToggleDTOG_RX(ep->num);
- /* Configure DISABLE status for the Endpoint*/
- SetEPTxStatus(ep->num, EP_TX_DIS);
- SetEPRxStatus(ep->num, EP_RX_DIS);
- }
- }
- return USB_OK;
-}
-
-
-/**
- * @brief DCD_EP_PrepareRx
- * @param pdev: device instance
- * @param ep_addr: endpoint address
- * @param pbuf: pointer to Rx buffer
- * @param buf_len: data length
- * @retval : status
- */
-uint32_t DCD_EP_PrepareRx( USB_CORE_HANDLE *pdev,
- uint8_t ep_addr,
- uint8_t *pbuf,
- uint16_t buf_len)
-{
- __IO uint32_t len = 0;
- USB_EP *ep;
-
- ep = &pdev->dev.out_ep[ep_addr & 0x7F];
-
- /*setup and start the Xfer */
- ep->xfer_buff = pbuf;
- ep->xfer_len = buf_len;
- ep->xfer_count = 0;
-
- /*Multi packet transfer*/
- if (ep->xfer_len > ep->maxpacket)
- {
- len=ep->maxpacket;
- ep->xfer_len-=len;
- }
- else
- {
- len=ep->xfer_len;
- ep->xfer_len =0;
- }
-
- /* configure and validate Rx endpoint */
- if (ep->doublebuffer == 0)
- {
- /*Set RX buffer count*/
- SetEPRxCount(ep->num, len);
- }
- else
- {
- /*Set the Double buffer counter*/
- SetEPDblBuffCount(ep->num, ep->is_in, len);
- }
-
- SetEPRxStatus(ep->num, EP_RX_VALID);
-
- return USB_OK;
-}
-
-/**
- * @brief Transmit data Buffer
- * @param pdev: device instance
- * @param ep_addr: endpoint address
- * @param pbuf: pointer to Tx buffer
- * @param buf_len: data length
- * @retval : status
- */
-uint32_t DCD_EP_Tx ( USB_CORE_HANDLE *pdev,
- uint8_t ep_addr,
- uint8_t *pbuf,
- uint32_t buf_len)
-{
- __IO uint32_t len = 0;
- USB_EP *ep;
-
- ep = &pdev->dev.in_ep[ep_addr & 0x7F];
-
- /*setup and start the Xfer */
- ep->num = ep_addr & 0x7F;
- ep->xfer_buff = pbuf;
- ep->xfer_len = buf_len;
- ep->xfer_count = 0;
-
- /*Multi packet transfer*/
- if (ep->xfer_len > ep->maxpacket)
- {
- len=ep->maxpacket;
- ep->xfer_len-=len;
- }
- else
- {
- len=ep->xfer_len;
- ep->xfer_len =0;
- }
-
- /* configure and validate Tx endpoint */
- if (ep->doublebuffer == 0)
- {
- UserToPMABufferCopy(ep->xfer_buff, ep->pmaadress, len);
- SetEPTxCount(ep->num, len);
- }
- else
- {
- uint16_t pmabuffer=0;
- /*Set the Double buffer counter*/
- SetEPDblBuffCount(ep->num, ep->is_in, len);
-
- /*Write the data to the USB endpoint*/
- if (GetENDPOINT(ep->num)&EP_DTOG_TX)
- {
- pmabuffer = ep->pmaaddr1;
- }
- else
- {
- pmabuffer = ep->pmaaddr0;
- }
- UserToPMABufferCopy(ep->xfer_buff, pmabuffer, len);
- FreeUserBuffer(ep->num, ep->is_in);
- }
-
- SetEPTxStatus(ep->num, EP_TX_VALID);
-
- return USB_OK;
-}
-
-
-/**
- * @brief Stall an endpoint.
- * @param pdev: device instance
- * @param epnum: endpoint address
- * @retval : status
- */
-uint32_t DCD_EP_Stall (USB_CORE_HANDLE *pdev, uint8_t epnum)
-{
- USB_EP *ep;
- if ((0x80 & epnum) == 0x80)
- {
- ep = &pdev->dev.in_ep[epnum & 0x7F];
- }
- else
- {
- ep = &pdev->dev.out_ep[epnum];
- }
-
- if (ep->num ==0)
- {
- /* This macro sets STALL status for RX & TX*/
- _SetEPRxTxStatus(ep->num,EP_RX_STALL,EP_TX_STALL);
- /*Endpoint is stalled */
- ep->is_stall = 1;
- return USB_OK;
- }
- if (ep->is_in)
- {
- /* IN endpoint */
- ep->is_stall = 1;
- /* IN Endpoint stalled */
- SetEPTxStatus(ep->num , EP_TX_STALL);
- }
- else
- {
- ep->is_stall = 1;
- /* OUT Endpoint stalled */
- SetEPRxStatus(ep->num , EP_RX_STALL);
- }
-
- return USB_OK;
-}
-
-
-/**
- * @brief Clear stall condition on endpoints.
- * @param pdev: device instance
- * @param epnum: endpoint address
- * @retval : status
- */
-uint32_t DCD_EP_ClrStall (USB_CORE_HANDLE *pdev, uint8_t epnum)
-{
- USB_EP *ep;
- if ((0x80 & epnum) == 0x80)
- {
- ep = &pdev->dev.in_ep[epnum & 0x7F];
- }
- else
- {
- ep = &pdev->dev.out_ep[epnum];
- }
-
- if (ep->is_in)
- {
- ClearDTOG_TX(ep->num);
- SetEPTxStatus(ep->num, EP_TX_VALID);
- ep->is_stall = 0;
- }
- else
- {
- ClearDTOG_RX(ep->num);
- SetEPRxStatus(ep->num, EP_RX_VALID);
- ep->is_stall = 0;
- }
-
- return USB_OK;
-}
-
-/**
- * @brief This Function set USB device address
- * @param pdev: device instance
- * @param address: new device address
- */
-void DCD_EP_SetAddress (USB_CORE_HANDLE *pdev, uint8_t address)
-{
- uint32_t i=0;
- pdev->dev.device_address = address;
-
- /* set address in every used endpoint */
- for (i = 0; i < EP_NUM; i++)
- {
- _SetEPAddress((uint8_t)i, (uint8_t)i);
- } /* set device address and enable function */
- _SetDADDR(address | DADDR_EF);
-}
-
-/**
- * @brief Connect device (enable internal pull-up)
- * @param pdev: device instance
- * @retval : None
- */
-void DCD_DevConnect (USB_CORE_HANDLE *pdev)
-{
- /* Enabling DP Pull-Down bit to Connect internal pull-up on USB DP line */
- *BCDR|=BCDR_DPPU;
- /*Device is in default state*/
- pdev->dev.device_status = USB_DEFAULT;
-}
-
-/**
- * @brief Disconnect device (disable internal pull-up)
- * @param pdev: device instance
- * @retval : None
- */
-void DCD_DevDisconnect (USB_CORE_HANDLE *pdev)
-{
-
- /* Disable DP Pull-Down bit*/
- *BCDR&=~BCDR_DPPU;
-
- /*Device is in unconnected state*/
- pdev->dev.device_status = USB_UNCONNECTED;
-}
-
-/**
- * @brief returns the EP Status
- * @param pdev : Selected device
- * epnum : endpoint address
- * @retval : EP status
- */
-
-uint32_t DCD_GetEPStatus(USB_CORE_HANDLE *pdev ,uint8_t epnum)
-{
- uint16_t Status=0;
-
- USB_EP *ep;
- if ((0x80 & epnum) == 0x80)
- {
- ep = &pdev->dev.in_ep[epnum & 0x7F];
- }
- else
- {
- ep = &pdev->dev.out_ep[epnum];
- }
-
- if (ep->is_in)
- {
- Status = GetEPTxStatus(ep->num);
- }
- else
- {
- Status = GetEPRxStatus(ep->num);
- }
-
- return Status;
-}
-
-/**
- * @brief Set the EP Status
- * @param pdev : Selected device
- * Status : new Status
- * epnum : EP address
- * @retval : None
- */
-void DCD_SetEPStatus (USB_CORE_HANDLE *pdev , uint8_t epnum , uint32_t Status)
-{
- USB_EP *ep;
- if ((0x80 & epnum) == 0x80)
- {
- ep = &pdev->dev.in_ep[epnum & 0x7F];
- }
- else
- {
- ep = &pdev->dev.out_ep[epnum];
- }
-
- if (ep->is_in)
- {
- SetEPTxStatus(ep->num, (uint16_t)Status);
- }
- else
- {
- SetEPRxStatus(ep->num, (uint16_t)Status);
- }
-
- if ((Status == EP_RX_STALL) || (Status == EP_TX_STALL))
- {
- ep->is_stall =1;
- }
-}
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Driver/src/usb_dcd_int.c b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Driver/src/usb_dcd_int.c
deleted file mode 100644
index 6ad48c7f48f6326616f8e8205c885abc6c801818..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Driver/src/usb_dcd_int.c
+++ /dev/null
@@ -1,369 +0,0 @@
-/**
- ******************************************************************************
- * @file usb_dcd_int.c
- * @author MCD Application Team
- * @version V1.0.1
- * @date 31-January-2014
- * @brief This file provides the interrupt subroutines for the Device
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "usb_dcd_int.h"
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-extern USB_CORE_HANDLE USB_Device_dev;
-extern uint32_t wInterrupt_Mask;
-#ifdef LPM_ENABLED
-__IO uint32_t L1_remote_wakeup =0;
-__IO uint32_t BESL = 0;
-#endif
-
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/**
- * @brief Correct Transfer interrupt's service
- * @param None
- * @retval None
- */
-void CTR(void)
-{
- USB_EP *ep;
- uint16_t count=0;
- uint8_t EPindex;
- __IO uint16_t wIstr;
- __IO uint16_t wEPVal = 0;
- /* stay in loop while pending interrupts */
- while (((wIstr = _GetISTR()) & ISTR_CTR) != 0)
- {
- /* extract highest priority endpoint number */
- EPindex = (uint8_t)(wIstr & ISTR_EP_ID);
-
- if (EPindex == 0)
- {
- /* Decode and service control endpoint interrupt */
-
- /* DIR bit = origin of the interrupt */
- if ((wIstr & ISTR_DIR) == 0)
- {
- /* DIR = 0 */
-
- /* DIR = 0 => IN int */
- /* DIR = 0 implies that (EP_CTR_TX = 1) always */
- _ClearEP_CTR_TX(ENDP0);
- ep = &((&USB_Device_dev)->dev.in_ep[0]);
-
- ep->xfer_count = GetEPTxCount(ep->num);
- ep->xfer_buff += ep->xfer_count;
-
- /* TX COMPLETE */
- USBD_DCD_INT_fops->DataInStage(&USB_Device_dev, 0x00);
- }
- else
- {
- /* DIR = 1 */
-
- /* DIR = 1 & CTR_RX => SETUP or OUT int */
- /* DIR = 1 & (CTR_TX | CTR_RX) => 2 int pending */
- ep = &((&USB_Device_dev)->dev.out_ep[0]);
- wEPVal = _GetENDPOINT(ENDP0);
-
- if ((wEPVal &EP_SETUP) != 0)
- {
- /* Get SETUP Packet*/
- ep->xfer_count = GetEPRxCount(ep->num);
- PMAToUserBufferCopy(&((&USB_Device_dev)->dev.setup_packet[0]),ep->pmaadress , ep->xfer_count);
- /* SETUP bit kept frozen while CTR_RX = 1*/
- _ClearEP_CTR_RX(ENDP0);
-
- /* Process SETUP Packet*/
- USBD_DCD_INT_fops->SetupStage(&USB_Device_dev);
- }
-
- else if ((wEPVal & EP_CTR_RX) != 0)
- {
- _ClearEP_CTR_RX(ENDP0);
- /* Get Control Data OUT Packet*/
- ep->xfer_count = GetEPRxCount(ep->num);
-
- if (ep->xfer_count != 0)
- {
- PMAToUserBufferCopy(ep->xfer_buff, ep->pmaadress, ep->xfer_count);
- ep->xfer_buff+=ep->xfer_count;
- }
-
- /* Process Control Data OUT Packet*/
- USBD_DCD_INT_fops->DataOutStage(&USB_Device_dev, 0x00);
-
- _SetEPRxCount(ENDP0, ep->maxpacket);
- _SetEPRxStatus(ENDP0,EP_RX_VALID);
- }
- }
- }/* if(EPindex == 0) */
- else
- {
-
- /* Decode and service non control endpoints interrupt */
-
- /* process related endpoint register */
- wEPVal = _GetENDPOINT(EPindex);
- if ((wEPVal & EP_CTR_RX) != 0)
- {
- /* clear int flag */
- _ClearEP_CTR_RX(EPindex);
- ep = &((&USB_Device_dev)->dev.out_ep[EPindex]);
-
- /* OUT double Buffering*/
- if (ep->doublebuffer == 0)
- {
- count = GetEPRxCount(ep->num);
- if (count != 0)
- {
- PMAToUserBufferCopy(ep->xfer_buff, ep->pmaadress, count);
- }
- }
- else
- {
- if (GetENDPOINT(ep->num) & EP_DTOG_RX)
- {
- /*read from endpoint BUF0Addr buffer*/
- count = GetEPDblBuf0Count(ep->num);
- if (count != 0)
- {
- PMAToUserBufferCopy(ep->xfer_buff, ep->pmaaddr0, count);
- }
- }
- else
- {
- /*read from endpoint BUF1Addr buffer*/
- count = GetEPDblBuf1Count(ep->num);
- if (count != 0)
- {
- PMAToUserBufferCopy(ep->xfer_buff, ep->pmaaddr1, count);
- }
- }
- FreeUserBuffer(ep->num, EP_DBUF_OUT);
- }
- /*multi-packet on the NON control OUT endpoint*/
- ep->xfer_count+=count;
- ep->xfer_buff+=count;
-
- if ((ep->xfer_len == 0) || (count < ep->maxpacket))
- {
- /* RX COMPLETE */
- USBD_DCD_INT_fops->DataOutStage(&USB_Device_dev, ep->num);
- }
- else
- {
- DCD_EP_PrepareRx (&USB_Device_dev,ep->num, ep->xfer_buff, ep->xfer_len);
- }
-
- } /* if((wEPVal & EP_CTR_RX) */
-
- if ((wEPVal & EP_CTR_TX) != 0)
- {
- ep = &((&USB_Device_dev)->dev.in_ep[EPindex]);
-
- /* clear int flag */
- _ClearEP_CTR_TX(EPindex);
-
- /* IN double Buffering*/
- if (ep->doublebuffer == 0)
- {
- ep->xfer_count = GetEPTxCount(ep->num);
- if (ep->xfer_count != 0)
- {
- UserToPMABufferCopy(ep->xfer_buff, ep->pmaadress, ep->xfer_count);
- }
- }
- else
- {
- if (GetENDPOINT(ep->num) & EP_DTOG_TX)
- {
- /*read from endpoint BUF0Addr buffer*/
- ep->xfer_count = GetEPDblBuf0Count(ep->num);
- if (ep->xfer_count != 0)
- {
- UserToPMABufferCopy(ep->xfer_buff, ep->pmaaddr0, ep->xfer_count);
- }
- }
- else
- {
- /*read from endpoint BUF1Addr buffer*/
- ep->xfer_count = GetEPDblBuf1Count(ep->num);
- if (ep->xfer_count != 0)
- {
- UserToPMABufferCopy(ep->xfer_buff, ep->pmaaddr1, ep->xfer_count);
- }
- }
- FreeUserBuffer(ep->num, EP_DBUF_IN);
- }
- /*multi-packet on the NON control IN endpoint*/
- ep->xfer_count =GetEPTxCount(ep->num);
- ep->xfer_buff+=ep->xfer_count;
-
- /* Zero Length Packet? */
- if (ep->xfer_len == 0)
- {
- /* TX COMPLETE */
- USBD_DCD_INT_fops->DataInStage(&USB_Device_dev, ep->num);
- }
- else
- {
- DCD_EP_Tx (&USB_Device_dev,ep->num, ep->xfer_buff, ep->xfer_len);
- }
-
- } /* if((wEPVal & EP_CTR_TX) != 0) */
-
- }/* if(EPindex == 0) else */
-
- }/* while(...) */
-}
-
-/**
- * @brief ISTR events interrupt service routine
- * @param None
- * @retval None
- */
-void USB_Istr(void)
-{
- __IO uint16_t wIstr = 0;
-
- wIstr = _GetISTR();
-
-#if (IMR_MSK & ISTR_CTR)
- if (wIstr & ISTR_CTR & wInterrupt_Mask)
- {
- /* servicing of the endpoint correct transfer interrupt */
- /* clear of the CTR flag into the sub */
- CTR();
- }
-#endif
- /*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
-#if (IMR_MSK & ISTR_RESET)
- if (wIstr & ISTR_RESET & wInterrupt_Mask)
- {
- _SetISTR((uint16_t)CLR_RESET);
- USBD_DCD_INT_fops->Reset(&USB_Device_dev);
- DCD_EP_SetAddress(&USB_Device_dev, 0);
- }
-#endif
- /*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
-#if (IMR_MSK & ISTR_DOVR)
- if (wIstr & ISTR_DOVR & wInterrupt_Mask)
- {
- _SetISTR((uint16_t)CLR_DOVR);
- }
-#endif
- /*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
-#if (IMR_MSK & ISTR_ERR)
- if (wIstr & ISTR_ERR & wInterrupt_Mask)
- {
- _SetISTR((uint16_t)CLR_ERR);
- }
-#endif
- /*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
-#if (IMR_MSK & ISTR_WKUP)
- if (wIstr & ISTR_WKUP & wInterrupt_Mask)
- {
- _SetISTR((uint16_t)CLR_WKUP);
-
- USBD_DCD_INT_fops->Resume(&USB_Device_dev);
-
- /* Handle Resume state machine */
- Resume(RESUME_EXTERNAL);
-
-#ifdef LPM_ENABLED
- /* clear L1 remote wakeup flag */
- L1_remote_wakeup = 0;
-#endif
- }
-#endif
- /*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
-#if (IMR_MSK & ISTR_SUSP)
- if (wIstr & ISTR_SUSP & wInterrupt_Mask)
- {
- /* clear of the ISTR bit must be done after setting of CNTR_FSUSP */
- _SetISTR((uint16_t)CLR_SUSP);
-
- /* process library core layer suspend routine*/
- USBD_DCD_INT_fops->Suspend(&USB_Device_dev);
-
- /* enter macrocell in suspend and system in low power mode when
- USB_DEVICE_LOW_PWR_MGMT_SUPPORT defined in usb_conf.h */
- Suspend();
- }
-#endif
- /*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
-#if (IMR_MSK & ISTR_SOF)
- if (wIstr & ISTR_SOF & wInterrupt_Mask)
- {
- _SetISTR((uint16_t)CLR_SOF);
- USBD_DCD_INT_fops->SOF(&USB_Device_dev);
- }
-#endif
- /*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*/
-#if (IMR_MSK & ISTR_ESOF)
- if (wIstr & ISTR_ESOF & wInterrupt_Mask)
- {
- /* clear ESOF flag in ISTR */
- _SetISTR((uint16_t)CLR_ESOF);
-
- /* resume handling timing is made with ESOFs */
- Resume(RESUME_ESOF); /* request without change of the machine state */
- }
-#endif
-
-#ifdef LPM_ENABLED
-#if (IMR_MSK & ISTR_L1REQ)
- if (wIstr & ISTR_L1REQ & wInterrupt_Mask)
- {
- /* clear L1REQ flag in ISTR */
- _SetISTR((uint16_t)CLR_L1REQ);
-
- /* read BESL field which coressponds to HIRD parameter in LPM spec*/
- /* In your application depending on BESL value, you can choose the right
- low power mode during L1 state, allowing wakeup time within the request time from host.*/
- BESL = (_GetLPMCSR()&LPMCSR_BESL) >>4 ;
-
- /* read REMWAKE bit which corresponding to bRemoteWake bit in LPM request*/
- /* if this bit is set then L1 remote wakeup is possible */
- L1_remote_wakeup = (_GetLPMCSR()&LPMCSR_REMWAKE) >>3;
-
- /* process library core layer suspend routine*/
- USBD_DCD_INT_fops->Suspend(&USB_Device_dev);
-
- /* enter macrocell in suspend and system in low power mode (STOP mode) when
- USB_DEVICE_LOW_PWR_MGMT_SUPPORT defined in usb_conf.h.*/
- /* Please note that in this example we enter in STOP mode during L1 state independently
- from value read in BESL (even for BESL= 0 which corresponds to 50us delay) because
- STM32F072 can wakeup system from STOP mode in less than 50 us */
- Suspend();
- }
-#endif
-#endif
-} /* USB_Istr */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/audio/inc/usbd_audio_core.h b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/audio/inc/usbd_audio_core.h
deleted file mode 100644
index 414cc71ba7e612f98560f49483de53f4f645db71..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/audio/inc/usbd_audio_core.h
+++ /dev/null
@@ -1,141 +0,0 @@
-/**
- ******************************************************************************
- * @file usbd_audio_core.h
- * @author MCD Application Team
- * @version V1.0.1
- * @date 31-January-2014
- * @brief header file for the usbd_audio_core.c file.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __USB_AUDIO_CORE_H_
-#define __USB_AUDIO_CORE_H_
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_req.h"
-#include "stm32_audio_out_if.h"
-
-/** @addtogroup STM32_USB_DEVICE_LIBRARY
- * @{
- */
-
-/** @defgroup usbd_audio
- * @brief This file is the Header file for USBD_audio.c
- * @{
- */
-
-/* Exported defines ----------------------------------------------------------*/
-
-/* AudioFreq * DataSize (2 bytes) * NumChannels (Stereo: 2) */
-#define DEFAULT_OUT_BIT_RESOLUTION 16
-#define DEFAULT_OUT_CHANNEL_NBR 2 /* Mono = 1, Stereo = 2 */
-#define AUDIO_OUT_PACKET (uint32_t)(((DEFAULT_OUT_AUDIO_FREQ * \
- (DEFAULT_OUT_BIT_RESOLUTION/8) *\
- DEFAULT_OUT_CHANNEL_NBR) /1000))
-
-/* Out endpoint max packet size (in Feedback Synchronization mode, this parameter should be set high enough
- in order to tolerate the fluctuations of out packets size) */
-#define AUDIO_OUT_MPS 384
-
-#define AUDIO_CONFIG_DESC_SIZE 109
-#define AUDIO_INTERFACE_DESC_SIZE 0x09
-#define USB_AUDIO_DESC_SIZ 0x09
-#define AUDIO_STANDARD_ENDPOINT_DESC_SIZE 0x09
-#define AUDIO_STREAMING_ENDPOINT_DESC_SIZE 0x07
-
-#define AUDIO_DESCRIPTOR_TYPE 0x21
-#define USB_DEVICE_CLASS_AUDIO 0x01
-#define AUDIO_SUBCLASS_AUDIOCONTROL 0x01
-#define AUDIO_SUBCLASS_AUDIOSTREAMING 0x02
-#define AUDIO_PROTOCOL_UNDEFINED 0x00
-#define AUDIO_STREAMING_GENERAL 0x01
-#define AUDIO_STREAMING_FORMAT_TYPE 0x02
-
-/* Audio Descriptor Types */
-#define AUDIO_INTERFACE_DESCRIPTOR_TYPE 0x24
-#define AUDIO_ENDPOINT_DESCRIPTOR_TYPE 0x25
-
-/* Audio Control Interface Descriptor Subtypes */
-#define AUDIO_CONTROL_HEADER 0x01
-#define AUDIO_CONTROL_INPUT_TERMINAL 0x02
-#define AUDIO_CONTROL_OUTPUT_TERMINAL 0x03
-#define AUDIO_CONTROL_FEATURE_UNIT 0x06
-
-#define AUDIO_INPUT_TERMINAL_DESC_SIZE 0x0C
-#define AUDIO_OUTPUT_TERMINAL_DESC_SIZE 0x09
-#define AUDIO_STREAMING_INTERFACE_DESC_SIZE 0x07
-
-#define AUDIO_CONTROL_MUTE 0x0001
-
-#define AUDIO_FORMAT_TYPE_I 0x01
-#define AUDIO_FORMAT_TYPE_III 0x03
-
-#define USB_ENDPOINT_TYPE_ISOCHRONOUS 0x01
-#define AUDIO_ENDPOINT_GENERAL 0x01
-
-#define AUDIO_REQ_GET_CUR 0x81
-#define AUDIO_REQ_SET_CUR 0x01
-
-#define AUDIO_OUT_STREAMING_CTRL 0x02
-
-/* Buffering state definitions */
-#define STATE_IDLE 0
-#define STATE_BUFFERING 1
-#define STATE_READY 2
-#define STATE_CLOSING 3
-#define STATE_RUN 4
-#define STATE_RUN_OVR (STATE_RUN + 1)
-#define STATE_RUN_UDR (STATE_RUN + 2)
-#define STATE_RUN_ERR (STATE_RUN + 3)
-#define STATE_ERROR 8
-
-/* Number of empty frame after which the communication should be considered as closed. */
-#define EMPTY_FRAME_THRESHOLD 3
-
-/* Exported types ------------------------------------------------------------*/
-typedef struct _Buff_Desc
-{
- uint32_t Size;
- uint8_t* Next;
-}BUFF_DESC_TypeDef;
-
-/* Exported macros -----------------------------------------------------------*/
-#define AUDIO_PACKET_SZE(frq) (uint8_t)(AUDIO_OUT_PACKET & 0xFF), \
- (uint8_t)((AUDIO_OUT_PACKET >> 8) & 0xFF)
-#define SAMPLE_FREQ(frq) (uint8_t)(frq), (uint8_t)((frq >> 8)), (uint8_t)((frq >> 16))
-
-/* Exported variables --------------------------------------------------------*/
-extern USBD_Class_cb_TypeDef AUDIO_cb;
-
-/* Exported functions ------------------------------------------------------- */
-/* This function should be called by low layer functions when current buffer transfer is complete */
-void usbd_audio_BuffXferCplt (uint8_t** pbuf, uint32_t* pSize);
-
-#endif /* __USB_AUDIO_CORE_H_ */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/audio/src/usbd_audio_core.c b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/audio/src/usbd_audio_core.c
deleted file mode 100644
index 924c778ede6e7272f58124f2ea44a5de20a66be7..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/audio/src/usbd_audio_core.c
+++ /dev/null
@@ -1,776 +0,0 @@
-/**
- ******************************************************************************
- * @file usbd_audio_core.c
- * @author MCD Application Team
- * @version V1.0.1
- * @date 31-January-2014
- * @brief This file provides the high layer firmware functions to manage the
- * following functionalities of the USB Audio Class:
- * - Initialization and Configuration of high and low layer
- * - Enumeration as Audio Streaming Device
- * - Audio Streaming data transfer
- * - AudioControl requests management
- * - Error management
- *
- * @verbatim
- *
- * ===================================================================
- * Audio Class Driver Description
- * ===================================================================
- * This driver manages the Audio Class 1.0 following the "USB Device Class Definition for
- * Audio Devices V1.0 Mar 18, 98".
- * This driver implements the following aspects of the specification:
- * - Device descriptor management
- * - Configuration descriptor management
- * - Standard AC Interface Descriptor management
- * - 1 Audio Streaming Interface (with single channel, PCM, Stereo mode)
- * - 1 Audio Streaming Endpoint
- * - 1 Audio Terminal Input (1 channel)
- * - Audio Class-Specific AC Interfaces
- * - Audio Class-Specific AS Interfaces
- * - AudioControl Requests: only SET_CUR and GET_CUR requests are supported (for Mute)
- * - Audio Feature Unit (limited to Mute control)
- * - Audio Synchronization type: Asynchronous
- * - Single fixed audio sampling rate (configurable in usbd_conf.h file)
- *
- * @note
- * The Audio Class 1.0 is based on USB Specification 1.0 and thus supports only
- * Low and Full speed modes and does not allow High Speed transfers.
- * Please refer to "USB Device Class Definition for Audio Devices V1.0 Mar 18, 98"
- * for more details.
- *
- * These aspects may be enriched or modified for a specific user application.
- *
- * This driver doesn't implement the following aspects of the specification
- * (but it is possible to manage these features with some modifications on this driver):
- * - AudioControl Endpoint management
- * - AudioControl requests other than SET_CUR and GET_CUR
- * - Abstraction layer for AudioControl requests (only Mute functionality is managed)
- * - Audio Synchronization type: Adaptive
- * - Audio Compression modules and interfaces
- * - MIDI interfaces and modules
- * - Mixer/Selector/Processing/Extension Units (Feature unit is limited to Mute control)
- * - Any other application-specific modules
- * - Multiple and Variable audio sampling rates
- * - Out Streaming Endpoint/Interface (microphone)
- *
- * @endverbatim
- *
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_audio_core.h"
-
-/** @addtogroup STM32_USB_DEVICE_LIBRARY
- * @{
- */
-
-
-/** @defgroup usbd_audio
- * @brief usbd core module
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/*********************************************
- AUDIO Device library callbacks
- *********************************************/
-static uint8_t usbd_audio_Init (void *pdev, uint8_t cfgidx);
-static uint8_t usbd_audio_DeInit (void *pdev, uint8_t cfgidx);
-static uint8_t usbd_audio_Setup (void *pdev, USB_SETUP_REQ *req);
-static uint8_t usbd_audio_EP0_RxReady(void *pdev);
-static uint8_t usbd_audio_DataIn (void *pdev, uint8_t epnum);
-static uint8_t usbd_audio_DataOut (void *pdev, uint8_t epnum);
-static uint8_t usbd_audio_SOF (void *pdev);
-
-static uint8_t *USBD_audio_GetCfgDesc (uint8_t speed, uint16_t *length);
-
-/*********************************************
- AUDIO Requests management functions
- *********************************************/
-static void AUDIO_Req_GetCurrent(void *pdev, USB_SETUP_REQ *req);
-static void AUDIO_Req_SetCurrent(void *pdev, USB_SETUP_REQ *req);
-
-/* Private variables ---------------------------------------------------------*/
- /* Main Buffer for Audio Data Out transfers and its related pointers */
-/* This is the main buffer where all out audio data are stored */
-uint8_t IsocOutBuff [TOTAL_OUT_BUF_SIZE];
-/* This is the pointer used by the write process (from host to device) */
-uint8_t* IsocOutWrPtr = IsocOutBuff;
-/* This is the pointer used by the read process (from buffers to I2S) */
-uint8_t* IsocOutRdPtr = IsocOutBuff;
-
-uint8_t OutEmptyFrameCount = 0;
-
-BUFF_DESC_TypeDef IsocOutBufDesc[OUT_PACKET_NUM];
-uint32_t IsocOutWrBufDescIdx = 0;
-uint32_t IsocOutRdBufDescIdx = 0;
-uint8_t IsocOutWrState = STATE_IDLE;
-uint8_t IsocOutRdState = STATE_IDLE;
-
-/* Main Buffer for Audio Control Requests transfers and its related variables */
-uint8_t AudioCtl[64];
-uint8_t AudioCtlCmd = 0;
-uint32_t AudioCtlLen = 0;
-uint8_t AudioCtlUnit = 0;
-
-
-/* USB AUDIO device Configuration Descriptor */
-const uint8_t usbd_audio_CfgDesc[AUDIO_CONFIG_DESC_SIZE] =
-{
- /* Configuration 1 */
- 0x09, /* bLength */
- USB_CONFIGURATION_DESCRIPTOR_TYPE, /* bDescriptorType */
- LOBYTE(AUDIO_CONFIG_DESC_SIZE), /* wTotalLength 109 bytes*/
- HIBYTE(AUDIO_CONFIG_DESC_SIZE),
- 0x02, /* bNumInterfaces */
- 0x01, /* bConfigurationValue */
- 0x00, /* iConfiguration */
- 0xC0, /* bmAttributes BUS Powred*/
- 0x32, /* bMaxPower = 100 mA*/
- /* 09 byte*/
-
- /* USB Speaker Standard interface descriptor */
- AUDIO_INTERFACE_DESC_SIZE, /* bLength */
- USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */
- 0x00, /* bInterfaceNumber */
- 0x00, /* bAlternateSetting */
- 0x00, /* bNumEndpoints */
- USB_DEVICE_CLASS_AUDIO, /* bInterfaceClass */
- AUDIO_SUBCLASS_AUDIOCONTROL, /* bInterfaceSubClass */
- AUDIO_PROTOCOL_UNDEFINED, /* bInterfaceProtocol */
- 0x00, /* iInterface */
- /* 09 byte*/
-
- /* USB Speaker Class-specific AC Interface Descriptor */
- AUDIO_INTERFACE_DESC_SIZE, /* bLength */
- AUDIO_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */
- AUDIO_CONTROL_HEADER, /* bDescriptorSubtype */
- 0x00, /* 1.00 */ /* bcdADC */
- 0x01,
- 0x27, /* wTotalLength = 39*/
- 0x00,
- 0x01, /* bInCollection */
- 0x01, /* baInterfaceNr */
- /* 09 byte*/
-
- /* USB Speaker Input Terminal Descriptor */
- AUDIO_INPUT_TERMINAL_DESC_SIZE, /* bLength */
- AUDIO_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */
- AUDIO_CONTROL_INPUT_TERMINAL, /* bDescriptorSubtype */
- 0x01, /* bTerminalID */
- 0x01, /* wTerminalType AUDIO_TERMINAL_USB_STREAMING 0x0101 */
- 0x01,
- 0x00, /* bAssocTerminal */
- 0x01, /* bNrChannels */
- 0x00, /* wChannelConfig 0x0000 Mono */
- 0x00,
- 0x00, /* iChannelNames */
- 0x00, /* iTerminal */
- /* 12 byte*/
-
- /* USB Speaker Audio Feature Unit Descriptor */
- 0x09, /* bLength */
- AUDIO_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */
- AUDIO_CONTROL_FEATURE_UNIT, /* bDescriptorSubtype */
- AUDIO_OUT_STREAMING_CTRL, /* bUnitID */
- 0x01, /* bSourceID */
- 0x01, /* bControlSize */
- AUDIO_CONTROL_MUTE, /* bmaControls(0) */
- 0x00, /* bmaControls(1) */
- 0x00, /* iTerminal */
- /* 09 byte*/
-
- /*USB Speaker Output Terminal Descriptor */
- 0x09, /* bLength */
- AUDIO_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */
- AUDIO_CONTROL_OUTPUT_TERMINAL, /* bDescriptorSubtype */
- 0x03, /* bTerminalID */
- 0x01, /* wTerminalType 0x0301*/
- 0x03,
- 0x00, /* bAssocTerminal */
- 0x02, /* bSourceID */
- 0x00, /* iTerminal */
- /* 09 byte*/
-
- /* USB Speaker Standard AS Interface Descriptor - Audio Streaming Zero Bandwidth */
- /* Interface 1, Alternate Setting 0 */
- AUDIO_INTERFACE_DESC_SIZE, /* bLength */
- USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */
- 0x01, /* bInterfaceNumber */
- 0x00, /* bAlternateSetting */
- 0x00, /* bNumEndpoints */
- USB_DEVICE_CLASS_AUDIO, /* bInterfaceClass */
- AUDIO_SUBCLASS_AUDIOSTREAMING, /* bInterfaceSubClass */
- AUDIO_PROTOCOL_UNDEFINED, /* bInterfaceProtocol */
- 0x00, /* iInterface */
- /* 09 byte*/
-
- /* USB Speaker Standard AS Interface Descriptor - Audio Streaming Operational */
- /* Interface 1, Alternate Setting 1 */
- AUDIO_INTERFACE_DESC_SIZE, /* bLength */
- USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */
- 0x01, /* bInterfaceNumber */
- 0x01, /* bAlternateSetting */
- 0x01, /* bNumEndpoints */
- USB_DEVICE_CLASS_AUDIO, /* bInterfaceClass */
- AUDIO_SUBCLASS_AUDIOSTREAMING, /* bInterfaceSubClass */
- AUDIO_PROTOCOL_UNDEFINED, /* bInterfaceProtocol */
- 0x00, /* iInterface */
- /* 09 byte*/
-
- /* USB Speaker Audio Streaming Interface Descriptor */
- AUDIO_STREAMING_INTERFACE_DESC_SIZE, /* bLength */
- AUDIO_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */
- AUDIO_STREAMING_GENERAL, /* bDescriptorSubtype */
- 0x01, /* bTerminalLink */
- 0x01, /* bDelay */
- 0x01, /* wFormatTag AUDIO_FORMAT_PCM 0x0001 */
- 0x00,
- /* 07 byte*/
-
- /* USB Speaker Audio Type III Format Interface Descriptor */
- (0x08 + (3 * SUPPORTED_FREQ_NBR)), /* bLength */
- AUDIO_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */
- AUDIO_STREAMING_FORMAT_TYPE, /* bDescriptorSubtype */
- AUDIO_FORMAT_TYPE_I, /* bFormatType */
-
- DEFAULT_OUT_CHANNEL_NBR, /* bNrChannels */
- DEFAULT_OUT_CHANNEL_NBR, /* bSubFrameSize : 2 Bytes per frame (16bits) */
- DEFAULT_OUT_BIT_RESOLUTION, /* bBitResolution (16-bits per sample) */
- SUPPORTED_FREQ_NBR, /* bSamFreqType only one frequency supported */
- SAMPLE_FREQ(DEFAULT_OUT_AUDIO_FREQ), /* Audio sampling frequency coded on 3 bytes */
-#if (SUPPORTED_FREQ_NBR > 1)
- SAMPLE_FREQ(USBD_AUDIO_FREQ_2), /* Audio sampling frequency coded on 3 bytes */
-#endif
-#if (SUPPORTED_FREQ_NBR > 2)
- SAMPLE_FREQ(USBD_AUDIO_FREQ_3), /* Audio sampling frequency coded on 3 bytes */
-#endif
-#if (SUPPORTED_FREQ_NBR > 3)
- SAMPLE_FREQ(USBD_AUDIO_FREQ_4), /* Audio sampling frequency coded on 3 bytes */
-#endif
-#if (SUPPORTED_FREQ_NBR > 4)
- #error "Error: Max nbr of frequencies exceeded, you have to modify the conf descriptor in usbd_audio_core.c file!"
-#endif
- /* 11 + 3*N byte */
-
- /* USB Speaker Streaming Standard Endpoint Descriptor */
- AUDIO_STANDARD_ENDPOINT_DESC_SIZE, /* bLength */
- USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType */
- AUDIO_OUT_EP, /* bEndpointAddress 1 out endpoint*/
- USB_ENDPOINT_TYPE_ISOCHRONOUS, /* bmAttributes */
- LOBYTE(AUDIO_OUT_MPS), /* wMaxPacketSize */
- HIBYTE(AUDIO_OUT_MPS),
- 0x01, /* bInterval */
- 0x00, /* bRefresh */
- 0x00, /* bSynchAddress */
- /* 09 byte*/
-
- /* Endpoint - Audio Streaming Descriptor*/
- AUDIO_STREAMING_ENDPOINT_DESC_SIZE, /* bLength */
- AUDIO_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType */
- AUDIO_ENDPOINT_GENERAL, /* bDescriptor */
-#if (SUPPORTED_FREQ_NBR > 1)
- 0x01, /* bmAttributes: Freq selection */
-#else
- 0x00, /* bmAttributes: None */
-#endif /* (SUPPORTED_FREQ_NBR > 1) */
- 0x00, /* bLockDelayUnits */
- 0x00, /* wLockDelay */
- 0x00,
- /* 07 byte*/
-};
-
-/* AUDIO interface class callbacks structure */
-USBD_Class_cb_TypeDef AUDIO_cb =
-{
- usbd_audio_Init,
- usbd_audio_DeInit,
- usbd_audio_Setup,
- NULL, /* EP0_TxSent */
- usbd_audio_EP0_RxReady,
- usbd_audio_DataIn,
- usbd_audio_DataOut,
- usbd_audio_SOF,
- USBD_audio_GetCfgDesc,
-};
-
-/* Private function ----------------------------------------------------------*/
-
-/**
- * @brief usbd_audio_Init
- * Initializes the AUDIO interface.
- * @param pdev: device instance
- * @param cfgidx: Configuration index
- * @retval status
- */
-static uint8_t usbd_audio_Init (void *pdev,
- uint8_t cfgidx)
-{
- /* Open EP OUT */
- DCD_PMA_Config(pdev, AUDIO_OUT_EP, USB_DBL_BUF, Audio_IN_TX_ADRESS);
-
- DCD_EP_Open(pdev, AUDIO_OUT_EP, AUDIO_OUT_PACKET, USB_EP_ISOC);
-
- /* Initialize the Audio output Hardware layer */
- if (AUDIO_OUT_fops.Init(DEFAULT_OUT_AUDIO_FREQ, DEFAULT_VOLUME, (DEFAULT_OUT_CHANNEL_NBR << 6 | DEFAULT_OUT_BIT_RESOLUTION)) != USBD_OK)
- {
- return USBD_FAIL;
- }
-
-#if (DEFAULT_OUT_BIT_RESOLUTION == 16)
- WAVADDON_Init((DEFAULT_OUT_CHANNEL_NBR<<6 | DEFAULT_OUT_BIT_RESOLUTION), 0);
-#endif /* DEFAULT_OUT_BIT_RESOLUTION */
-
- /* Prepare Out endpoint to receive audio data */
- DCD_EP_PrepareRx(pdev,
- AUDIO_OUT_EP,
- (uint8_t*)IsocOutBuff,
- AUDIO_OUT_PACKET);
-
- return USBD_OK;
-}
-
-/**
- * @brief usbd_audio_DeInit
- * DeInitializes the AUDIO layer.
- * @param pdev: device instance
- * @param cfgidx: Configuration index
- * @retval status
- */
-static uint8_t usbd_audio_DeInit (void *pdev,
- uint8_t cfgidx)
-{
- DCD_EP_Close (pdev , AUDIO_OUT_EP);
-
- /* DeInitialize the Audio output Hardware layer */
- if (AUDIO_OUT_fops.DeInit() != USBD_OK)
- {
- return USBD_FAIL;
- }
-
- return USBD_OK;
-}
-
-/**
- * @brief usbd_audio_Setup
- * Handles the Audio control request parsing.
- * @param pdev: instance
- * @param req: usb requests
- * @retval status
- */
-static uint8_t usbd_audio_Setup (void *pdev,
- USB_SETUP_REQ *req)
-{
-
- __IO uint32_t usbd_audio_AltSet = 0;
- uint16_t len=USB_AUDIO_DESC_SIZ;
- uint8_t *pbuf= (uint8_t *) usbd_audio_CfgDesc + 18;
-
- switch (req->bmRequest & USB_REQ_TYPE_MASK)
- {
- /* AUDIO Class Requests -------------------------------*/
- case USB_REQ_TYPE_CLASS :
- switch (req->bRequest)
- {
- case AUDIO_REQ_GET_CUR:
- AUDIO_Req_GetCurrent(pdev, req);
- break;
-
- case AUDIO_REQ_SET_CUR:
- AUDIO_Req_SetCurrent(pdev, req);
- break;
-
- default:
- USBD_CtlError (pdev, req);
- return USBD_FAIL;
- }
- break;
-
- /* Standard Requests -------------------------------*/
- case USB_REQ_TYPE_STANDARD:
- switch (req->bRequest)
- {
- case USB_REQ_GET_DESCRIPTOR:
- if( (req->wValue >> 8) == AUDIO_DESCRIPTOR_TYPE)
- {
- pbuf = (uint8_t *)usbd_audio_CfgDesc + 18;
- len = MIN(USB_AUDIO_DESC_SIZ , req->wLength);
- }
-
- USBD_CtlSendData (pdev,
- pbuf,
- len);
- break;
-
- case USB_REQ_GET_INTERFACE :
- USBD_CtlSendData (pdev,
- (uint8_t *)&usbd_audio_AltSet,
- 1);
- break;
-
- case USB_REQ_SET_INTERFACE :
- if ((uint8_t)(req->wValue) < AUDIO_TOTAL_IF_NUM)
- {
- usbd_audio_AltSet = (uint8_t)(req->wValue);
- }
- else
- {
- /* Call the error management function (command will be nacked */
- USBD_CtlError (pdev, req);
- }
- break;
- }
- }
- return USBD_OK;
-}
-
-/**
- * @brief usbd_audio_EP0_RxReady
- * Handles audio control requests data.
- * @param pdev: device device instance
- * @retval status
- */
-static uint8_t usbd_audio_EP0_RxReady (void *pdev)
-{
- /* Check if an AudioControl request has been issued */
- if (AudioCtlCmd == AUDIO_REQ_SET_CUR)
- {
- /* In this driver, to simplify code, only SET_CUR request is managed */
- /* Check for which addressed unit the AudioControl request has been issued */
- if (AudioCtlUnit == AUDIO_OUT_STREAMING_CTRL)
- {
- /* In this driver, to simplify code, only one unit is manage */
- /* Call the audio interface mute function */
- AUDIO_OUT_fops.MuteCtl(AudioCtl[0]);
-
- /* Reset the AudioCtlCmd variable to prevent re-entering this function */
- AudioCtlCmd = 0;
- AudioCtlLen = 0;
- }
- }
-
- return USBD_OK;
-}
-
-/**
- * @brief usbd_audio_DataIn
- * Handles the audio IN data stage.
- * @param pdev: instance
- * @param epnum: endpoint number
- * @retval status
- */
-static uint8_t usbd_audio_DataIn (void *pdev, uint8_t epnum)
-{
- return USBD_OK;
-}
-
-/**
- * @brief usbd_audio_DataOut
- * Handles the Audio Out data stage.
- * @param pdev: instance
- * @param epnum: endpoint number
- * @retval status
- */
-static uint8_t usbd_audio_DataOut (void *pdev, uint8_t epnum)
-{
- uint32_t IsocOutPacketSze = AUDIO_OUT_PACKET;
- if (epnum == AUDIO_OUT_EP)
- {
- /* Set the Isochronous Buffer Out linked chain parameters */
- IsocOutBufDesc[IsocOutWrBufDescIdx].Size = ((USB_CORE_HANDLE*)pdev)->dev.out_ep[epnum].xfer_count;
- IsocOutBufDesc[IsocOutWrBufDescIdx].Next = (uint8_t*)(IsocOutWrPtr + IsocOutBufDesc[IsocOutWrBufDescIdx].Size);
-
-#if (DEFAULT_OUT_BIT_RESOLUTION == 16)
- WAVADDON_AudioProcessing(IsocOutWrPtr, IsocOutBufDesc[IsocOutWrBufDescIdx].Size);
-#endif /* DEFAULT_OUT_BIT_RESOLUTION */
-
- /* Increment the write buffer pointer */
- IsocOutWrPtr += IsocOutBufDesc[IsocOutWrBufDescIdx].Size;
-
- /* Increment the linked chain member index */
- IsocOutWrBufDescIdx++;
-
- /* Check if the end of the the buffer has been reached */
- if (IsocOutWrBufDescIdx >= OUT_PACKET_NUM)
- {
- /* All buffers are full: roll back */
- IsocOutWrPtr = IsocOutBuff;
- IsocOutBufDesc[IsocOutWrBufDescIdx - 1].Next = IsocOutBuff;
- IsocOutWrBufDescIdx = 0;
- }
-
- /* Check and update the buffering state machine */
- switch (IsocOutWrState)
- {
- case STATE_IDLE:
- IsocOutWrState = STATE_BUFFERING;
- break;
-
- case STATE_BUFFERING:
- /* Check if the buffer index reached the half of total out buffer */
- if (IsocOutWrBufDescIdx >= (OUT_PACKET_NUM / 2))
- {
- /* Switch current state to Ready: allow read operation from the buffer */
- IsocOutWrState = STATE_READY;
- }
- break;
-
- case STATE_READY:
- /* Decrement the empty frame counter */
- if (OutEmptyFrameCount)
- {
- OutEmptyFrameCount --;
- }
- break;
-
- case STATE_CLOSING:
- break;
-
- default:
- break;
- }
-
- /* Prepare Out endpoint to receive next audio packet */
- DCD_EP_PrepareRx(pdev,
- AUDIO_OUT_EP,
- IsocOutWrPtr,
- IsocOutPacketSze);
- }
-
- return USBD_OK;
-}
-
-/**
- * @brief usbd_audio_SOF
- * Handles the SOF event (data buffer update and synchronization).
- * @param pdev: instance
- * @param epnum: endpoint number
- * @retval status
- */
-static uint8_t usbd_audio_SOF (void *pdev)
-{
- /*Uncomment this line to visualize the shift between SOF and audio clock*/
- STM_EVAL_LEDToggle(LED1);
-
- /* Check on current state */
- if (IsocOutWrState == STATE_READY)
- {
- /* Increment the empty frame counter */
- OutEmptyFrameCount ++;
-
- /* Check if the output read operation has been started */
- if (IsocOutRdState == STATE_IDLE)
- {
- /* Start playing received packet */
- AUDIO_OUT_fops.AudioCmd(IsocOutBuff, /* Samples buffer pointer */
- IsocOutBufDesc[IsocOutRdBufDescIdx].Size, /* Number of samples in Bytes */
- AUDIO_CMD_PLAY); /* Command to be processed */
-
- /* Set the current read pointer */
- IsocOutRdPtr = IsocOutBufDesc[IsocOutRdBufDescIdx].Next;
-
- /* Increment the read buffer descriptor index */
- IsocOutRdBufDescIdx++;
-
- /* Update the out read operation state */
- IsocOutRdState = STATE_RUN;
- }
- }
-
- /* Check if the empty frame counter reached the threshold (means audio streaming stopped) */
- if (OutEmptyFrameCount >= EMPTY_FRAME_THRESHOLD)
- {
- IsocOutWrState = STATE_CLOSING;
- OutEmptyFrameCount = 0;
- }
-
- /* Check if there are available data in stream buffer.
- The play operation must be executed as soon as possible after the SOF detection. */
- if (/*(IsocOutWrState == STATE_CLOSING) && */
- (IsocOutRdPtr == IsocOutWrPtr) &&
- (IsocOutRdState != STATE_IDLE))
- {
- /* Pause the audio stream */
- AUDIO_OUT_fops.AudioCmd(IsocOutBufDesc[IsocOutRdBufDescIdx - 1].Next, /* Samples buffer pointer */
- IsocOutBufDesc[IsocOutRdBufDescIdx].Size, /* Number of samples in Bytes */
- AUDIO_CMD_PAUSE); /* Command to be processed */
-
- IsocOutWrState = STATE_IDLE;
- IsocOutRdState = STATE_IDLE;
-
- /* Reset buffer pointers */
- IsocOutRdPtr = IsocOutBuff;
- IsocOutWrPtr = IsocOutBuff;
- IsocOutRdBufDescIdx = 0;
- IsocOutWrBufDescIdx = 0;
- }
-
- return USBD_OK;
-}
-
-/**
- * @brief usbd_audio_BuffXferCplt
- * Manage end of buffer transfer for each device.
- * @param Direction: could be DIRECTION_IN or DIRECTION_OUT
- * @param pbuf: Pointer to the address of the current buffer
- * @param pSize: pointer to the variable which holds current buffer size
- * @retval status
- */
-void usbd_audio_BuffXferCplt (uint8_t** pbuf, uint32_t* pSize)
-{
- uint8_t* pRdPtr = IsocOutRdPtr;
- uint32_t currDistanceOut = 0;
-
- if (IsocOutRdState & STATE_RUN)
- {
- STM_EVAL_LEDToggle(LED2);
-
- if (IsocOutRdBufDescIdx == 0)
- {
- /* Start playing received packet */
- AUDIO_OUT_fops.AudioCmd(IsocOutBufDesc[OUT_PACKET_NUM - 1].Next, /* Samples buffer pointer */
- IsocOutBufDesc[IsocOutRdBufDescIdx].Size, /* Number of samples in Bytes */
- AUDIO_CMD_PLAY); /* Command to be processed */
-
- /* Set the current read pointer */
- IsocOutRdPtr = IsocOutBufDesc[OUT_PACKET_NUM - 1].Next;
- }
- else
- {
- /* Start playing received packet */
- AUDIO_OUT_fops.AudioCmd(IsocOutBufDesc[IsocOutRdBufDescIdx - 1].Next, /* Samples buffer pointer */
- IsocOutBufDesc[IsocOutRdBufDescIdx].Size, /* Number of samples in Bytes */
- AUDIO_CMD_PLAY); /* Command to be processed */
-
- /* Set the current read pointer */
- IsocOutRdPtr = IsocOutBufDesc[IsocOutRdBufDescIdx - 1].Next;
- }
-
- /* Check if roll-back has been detected */
- if (((uint32_t)IsocOutWrPtr) >= (uint32_t)pRdPtr)
- {/* No roll-back */
- currDistanceOut = (uint32_t)(((uint32_t)IsocOutWrPtr) - (uint32_t)pRdPtr);
- }
- else
- {/* Roll-back occured */
- currDistanceOut = (uint32_t)(((uint32_t)(IsocOutBufDesc[OUT_PACKET_NUM-2].Next) + \
- IsocOutBufDesc[OUT_PACKET_NUM-1].Size) - \
- (uint32_t)pRdPtr + ((uint32_t)IsocOutWrPtr) - \
- (uint32_t)(IsocOutBufDesc[OUT_PACKET_NUM-1].Next));
- }
-
- /* Speed-up the timer (trigger of DAC) when the distance between write buffer
- and read buffer pointers is higher than 3/4 buffer size */
- if(currDistanceOut > 1176)/* 3/4 buffer size = 1568 * 3/4 = 1176 */
- {
- TIM6->ARR = 998;/* This value is hard-coded for 48KHz: 48MHz/48KHz - 2 */
- }
- /* Slow-down the timer (trigger of DAC) when the distance between write buffer
- and read buffer pointers is lower than 1/4 buffer size */
- else if(currDistanceOut < 392)/* 1/4 buffer size = 1568 * 1/4 = 392 */
- {
- TIM6->ARR = 1000;/* This value is hard-coded for 48KHz: 48MHz/48KHz */
- }
- /* Set the default timer frequency */
- else
- {
- TIM6->ARR = 999;/* This value is hard-coded for 48KHz: 48MHz/48KHz - 1 */
- }
- /* Increment the read buffer descriptor index */
- IsocOutRdBufDescIdx++;
-
- /* Check if the end of the the buffer has been reached */
- if (IsocOutRdBufDescIdx == OUT_PACKET_NUM)
- {
- /* All buffers are full: roll back */
- IsocOutRdBufDescIdx = 0;
- }
- }
-}
-
-/******************************************************************************
- AUDIO Class requests management
-******************************************************************************/
-/**
- * @brief AUDIO_Req_GetCurrent
- * Handles the GET_CUR Audio control request.
- * @param pdev: instance
- * @param req: setup class request
- * @retval status
- */
-static void AUDIO_Req_GetCurrent(void *pdev, USB_SETUP_REQ *req)
-{
- /* Send the current mute state */
- USBD_CtlSendData (pdev,
- AudioCtl,
- req->wLength);
-}
-
-/**
- * @brief AUDIO_Req_SetCurrent
- * Handles the SET_CUR Audio control request.
- * @param pdev: instance
- * @param req: setup class request
- * @retval status
- */
-static void AUDIO_Req_SetCurrent(void *pdev, USB_SETUP_REQ *req)
-{
- if (req->wLength)
- {
- /* Prepare the reception of the buffer over EP0 */
- USBD_CtlPrepareRx (pdev,
- AudioCtl,
- req->wLength);
-
- /* Set the global variables indicating current request and its length
- to the function usbd_audio_EP0_RxReady() which will process the request */
- AudioCtlCmd = AUDIO_REQ_SET_CUR; /* Set the request value */
- AudioCtlLen = req->wLength; /* Set the request data length */
- AudioCtlUnit = HIBYTE(req->wIndex); /* Set the request target unit */
- }
-}
-
-/**
- * @brief USBD_audio_GetCfgDesc
- * Returns configuration descriptor.
- * @param speed : current device speed
- * @param length : pointer data length
- * @retval pointer to descriptor buffer
- */
-static uint8_t *USBD_audio_GetCfgDesc (uint8_t speed, uint16_t *length)
-{
- *length = sizeof (usbd_audio_CfgDesc);
- return (uint8_t *)usbd_audio_CfgDesc;
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/ccid/inc/usbd_ccid_cmd.h b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/ccid/inc/usbd_ccid_cmd.h
deleted file mode 100644
index f0e5114b289bb0d7e4658ce222fefba2e31a7e8e..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/ccid/inc/usbd_ccid_cmd.h
+++ /dev/null
@@ -1,190 +0,0 @@
-/**
- ******************************************************************************
- * @file usbd_ccid_cmd.h
- * @author MCD Application Team
- * @version V1.0.1
- * @date 31-January-2014
- * @brief CCID Commands handling prototype
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __USBD_CCID_CMD_H
-#define __USBD_CCID_CMD_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_ccid_core.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-
-/******************************************************************************/
-/* ERROR CODES for USB Bulk In Messages : bError */
-/******************************************************************************/
-
-#define SLOT_NO_ERROR 0x81
-#define SLOTERROR_UNKNOWN 0x82
-
-/* Index of not supported / incorrect message parameter : 7Fh to 01h */
-/* These Values are used for Return Types between Firmware Layers */
-/*
-Failure of a command
-The CCID cannot parse one parameter or the ICC is not supporting one parameter.
-Then the Slot Error register contains the index of the first bad parameter as a
-positive number (1-127). For instance, if the CCID receives an ICC command to
-an unimplemented slot, then the Slot Error register shall be set to
-‘5’ (index of bSlot field).
- */
-
-#define SLOTERROR_BAD_LENTGH 0x01
-#define SLOTERROR_BAD_SLOT 0x05
-#define SLOTERROR_BAD_POWERSELECT 0x07
-#define SLOTERROR_BAD_PROTOCOLNUM 0x07
-#define SLOTERROR_BAD_CLOCKCOMMAND 0x07
-#define SLOTERROR_BAD_ABRFU_3B 0x07
-#define SLOTERROR_BAD_BMCHANGES 0x07
-#define SLOTERROR_BAD_BFUNCTION_MECHANICAL 0x07
-#define SLOTERROR_BAD_ABRFU_2B 0x08
-#define SLOTERROR_BAD_LEVELPARAMETER 0x08
-#define SLOTERROR_BAD_FIDI 0x0A
-#define SLOTERROR_BAD_T01CONVCHECKSUM 0x0B
-#define SLOTERROR_BAD_GUARDTIME 0x0C
-#define SLOTERROR_BAD_WAITINGINTEGER 0x0D
-#define SLOTERROR_BAD_CLOCKSTOP 0x0E
-#define SLOTERROR_BAD_IFSC 0x0F
-#define SLOTERROR_BAD_NAD 0x10
-#define SLOTERROR_BAD_DWLENGTH 0x08 /* Used in PC_to_RDR_XfrBlock*/
-
-/*---------- Table 6.2-2 Slot error register when bmCommandStatus = 1 */
-#define SLOTERROR_CMD_ABORTED 0xFF
-#define SLOTERROR_ICC_MUTE 0xFE
-#define SLOTERROR_XFR_PARITY_ERROR 0xFD
-#define SLOTERROR_XFR_OVERRUN 0xFC
-#define SLOTERROR_HW_ERROR 0xFB
-#define SLOTERROR_BAD_ATR_TS 0xF8
-#define SLOTERROR_BAD_ATR_TCK 0xF7
-#define SLOTERROR_ICC_PROTOCOL_NOT_SUPPORTED 0xF6
-#define SLOTERROR_ICC_CLASS_NOT_SUPPORTED 0xF5
-#define SLOTERROR_PROCEDURE_BYTE_CONFLICT 0xF4
-#define SLOTERROR_DEACTIVATED_PROTOCOL 0xF3
-#define SLOTERROR_BUSY_WITH_AUTO_SEQUENCE 0xF2
-#define SLOTERROR_PIN_TIMEOUT 0xF0
-#define SLOTERROR_PIN_CANCELLED 0xEF
-#define SLOTERROR_CMD_SLOT_BUSY 0xE0
-#define SLOTERROR_CMD_NOT_SUPPORTED 0x00
-
-
-#define DEFAULT_FIDI 0x11 /* DEFAULT_FIDI_VALUE */
-#define DEFAULT_T01CONVCHECKSUM 0x00
-#define DEFAULT_EXTRA_GUARDTIME 0x00
-#define DEFAULT_WAITINGINTEGER 0x0A
-#define DEFAULT_CLOCKSTOP 0x00
-#define DEFAULT_IFSC 0x20
-#define DEFAULT_NAD 0x00
-
-#define DEFAULT_DATA_RATE 0x000025CD
-#define DEFAULT_CLOCK_FREQ 0x00000E10
-
-
-/*
-Offset=0 bmICCStatus 2 bit 0, 1, 2
- 0 - An ICC is present and active (power is on and stable, RST is inactive)
- 1 - An ICC is present and inactive (not activated or shut down by hardware error)
- 2 - No ICC is present
- 3 - RFU
-Offset=0 bmRFU 4 bits 0 RFU
-Offset=6 bmCommandStatus 2 bits 0, 1, 2
- 0 - Processed without error
- 1 - Failed (error code provided by the error register)
- 2 - Time Extension is requested
- 3 - RFU
- */
-
-#define BM_ICC_PRESENT_ACTIVE 0x00
-#define BM_ICC_PRESENT_INACTIVE 0x01
-#define BM_ICC_NO_ICC_PRESENT 0x02
-
-#define BM_COMMAND_STATUS_OFFSET 0x06
-#define BM_COMMAND_STATUS_NO_ERROR 0x00
-#define BM_COMMAND_STATUS_FAILED (0x01 << BM_COMMAND_STATUS_OFFSET)
-#define BM_COMMAND_STATUS_TIME_EXTN (0x02 << BM_COMMAND_STATUS_OFFSET)
-
-/* defines for the CCID_CMD Layers */
-#define SIZE_OF_ATR 33
-#define LEN_RDR_TO_PC_SLOTSTATUS 10
-#define LEN_PROTOCOL_STRUCT_T0 5
-
-#define BPROTOCOL_NUM_T0 0
-#define BPROTOCOL_NUM_T1 1
-
-/************************************************************************************/
-/* ERROR CODES for RDR_TO_PC_HARDWAREERROR Message : bHardwareErrorCode */
-/************************************************************************************/
-
-#define HARDWAREERRORCODE_OVERCURRENT 0x01
-#define HARDWAREERRORCODE_VOLTAGEERROR 0x02
-#define HARDWAREERRORCODE_OVERCURRENT_IT 0x04
-#define HARDWAREERRORCODE_VOLTAGEERROR_IT 0x08
-
-typedef enum
-{
- CHK_PARAM_SLOT = 1,
- CHK_PARAM_DWLENGTH = (1<<1),
- CHK_PARAM_abRFU2 = (1<<2),
- CHK_PARAM_abRFU3 = (1<<3),
- CHK_PARAM_CARD_PRESENT = (1<<4),
- CHK_PARAM_ABORT = (1<<5),
- CHK_ACTIVE_STATE = (1<<6)
-} ChkParam_t;
-
-
-/* Exported functions ------------------------------------------------------- */
-
-uint8_t PC_to_RDR_IccPowerOn(void);
-uint8_t PC_to_RDR_IccPowerOff(void);
-uint8_t PC_to_RDR_GetSlotStatus(void);
-uint8_t PC_to_RDR_XfrBlock(void);
-uint8_t PC_to_RDR_GetParameters(void);
-uint8_t PC_to_RDR_ResetParameters(void);
-uint8_t PC_to_RDR_SetParameters(void);
-uint8_t PC_to_RDR_Escape(void);
-uint8_t PC_to_RDR_IccClock(void);
-uint8_t PC_to_RDR_Abort(void);
-uint8_t PC_TO_RDR_T0Apdu(void);
-uint8_t PC_TO_RDR_Mechanical(void);
-uint8_t PC_TO_RDR_SetDataRateAndClockFrequency(void);
-uint8_t PC_TO_RDR_Secure(void);
-
-void RDR_to_PC_DataBlock(unsigned char );
-void RDR_to_PC_NotifySlotChange(void);
-void RDR_to_PC_SlotStatus(unsigned char );
-void RDR_to_PC_Parameters(unsigned char );
-void RDR_to_PC_Escape(unsigned char );
-void RDR_to_PC_DataRateAndClockFrequency(uint8_t errorCode);
-
-
-void CCID_UpdSlotStatus (uint8_t );
-void CCID_UpdSlotChange (uint8_t );
-uint8_t CCID_IsSlotStatusChange (void);
-uint8_t CCID_CmdAbort(uint8_t slot, uint8_t seq);
-
-#endif /* __USBD_CCID_CMD_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/ccid/inc/usbd_ccid_core.h b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/ccid/inc/usbd_ccid_core.h
deleted file mode 100644
index 4ce1b06f7f96f09b856afb0bd5f14afb35d61ce6..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/ccid/inc/usbd_ccid_core.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/**
- ******************************************************************************
- * @file usbd_ccid_core.h
- * @author MCD Application Team
- * @version V1.0.1
- * @date 31-January-2014
- * @brief This file provides all the CCID core functions.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef _USB_CCID_CORE_H_
-#define _USB_CCID_CORE_H_
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_req.h"
-#include "sc_itf.h"
-
-/* Exported defines ----------------------------------------------------------*/
-#define TPDU_EXCHANGE 0x01
-#define SHORT_APDU_EXCHANGE 0x02
-#define EXTENDED_APDU_EXCHANGE 0x04
-#define CHARACTER_EXCHANGE 0x00
-
-#define EXCHANGE_LEVEL_FEATURE TPDU_EXCHANGE
-
-#define REQUEST_ABORT 0x01
-#define REQUEST_GET_CLOCK_FREQUENCIES 0x02
-#define REQUEST_GET_DATA_RATES 0x03
-
-#define SMARTCARD_SIZ_CONFIG_DESC 93
-
-#define CCID_BULK_EPIN_SIZE CCID_BULK_EP_MAX_PACKET
-#define CCID_BULK_EPOUT_SIZE CCID_BULK_EP_MAX_PACKET
-#define CCID_INTR_EPIN_SIZE CCID_INTR_EP_MAX_PACKET
-#define CCID_EP0_BUFF_SIZ 64
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported macros -----------------------------------------------------------*/
-/* Exported variables --------------------------------------------------------*/
-extern USBD_Class_cb_TypeDef USBD_CCID_cb;
-/* Exported functions ------------------------------------------------------- */
-
-#endif /* _USB_CCID_CORE_H_ */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/ccid/inc/usbd_ccid_if.h b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/ccid/inc/usbd_ccid_if.h
deleted file mode 100644
index f4948e12c631a84ec82e74dcfd83af7717bde479..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/ccid/inc/usbd_ccid_if.h
+++ /dev/null
@@ -1,184 +0,0 @@
-/**
- ******************************************************************************
- * @file usbd_ccid_if.h
- * @author MCD Application Team
- * @version V1.0.1
- * @date 31-January-2014
- * @brief This file provides all the functions prototypes for USB CCID
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __USBD_CCID_IF_H
-#define __USBD_CCID_IF_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_ccid_core.h"
-
-/* Exported defines ----------------------------------------------------------*/
-/* Bulk-only Command Block Wrapper */
-#define ABDATA_SIZE 261
-#define CCID_CMD_HEADER_SIZE 10
-#define CCID_RESPONSE_HEADER_SIZE 10
-
-
-#define CCID_INT_BUFF_SIZ 2
-
-#define CARD_SLOT_FITTED 1
-#define CARD_SLOT_REMOVED 0
-
-#define BULK_MAX_PACKET_SIZE 0x40
-#define CCID_IN_EP_SIZE 0x40
-#define INTR_MAX_PACKET_SIZE 8
-#define CCID_MESSAGE_HEADER_SIZE 10
-#define CCID_NUMBER_OF_SLOTS 1
- /* Number of SLOTS. For single card, this value is 1 */
-
-/* Following Parameters used in PC_to_RDR_IccPowerOn */
-#define VOLTAGE_SELECTION_AUTOMATIC 0xFF
-#define VOLTAGE_SELECTION_3V 0x02
-#define VOLTAGE_SELECTION_5V 0x01
-#define VOLTAGE_SELECTION_1V8 0x03
-
-#define PC_TO_RDR_ICCPOWERON 0x62
-#define PC_TO_RDR_ICCPOWEROFF 0x63
-#define PC_TO_RDR_GETSLOTSTATUS 0x65
-#define PC_TO_RDR_XFRBLOCK 0x6F
-#define PC_TO_RDR_GETPARAMETERS 0x6C
-#define PC_TO_RDR_RESETPARAMETERS 0x6D
-#define PC_TO_RDR_SETPARAMETERS 0x61
-#define PC_TO_RDR_ESCAPE 0x6B
-#define PC_TO_RDR_ICCCLOCK 0x6E
-#define PC_TO_RDR_T0APDU 0x6A
-#define PC_TO_RDR_SECURE 0x69
-#define PC_TO_RDR_MECHANICAL 0x71
-#define PC_TO_RDR_ABORT 0x72
-#define PC_TO_RDR_SETDATARATEANDCLOCKFREQUENCY 0x73
-
-#define RDR_TO_PC_DATABLOCK 0x80
-#define RDR_TO_PC_SLOTSTATUS 0x81
-#define RDR_TO_PC_PARAMETERS 0x82
-#define RDR_TO_PC_ESCAPE 0x83
-#define RDR_TO_PC_DATARATEANDCLOCKFREQUENCY 0x84
-
-#define RDR_TO_PC_NOTIFYSLOTCHANGE 0x50
-#define RDR_TO_PC_HARDWAREERROR 0x51
-
-#define OFFSET_INT_BMESSAGETYPE 0
-#define OFFSET_INT_BMSLOTICCSTATE 1
-#define SLOT_ICC_PRESENT 0x01
- /* LSb : (0b = no ICC present, 1b = ICC present) */
-
-#define SLOT_ICC_CHANGE 0x02 /* MSb : (0b = no change, 1b = change) */
-/*****************************************************************************/
-/*********************** CCID Bulk Transfer State machine ********************/
-/*****************************************************************************/
-#define CCID_STATE_IDLE 0 /* Idle state */
-#define CCID_STATE_DATA_OUT 1 /* Data Out state */
-#define CCID_STATE_RECEIVE_DATA 2
-#define CCID_STATE_SEND_RESP 3
-#define CCID_STATE_DATAIN 4
-#define CCID_STATE_UNCORRECT_LENGTH 5
-
-#define DIR_IN 0
-#define DIR_OUT 1
-#define BOTH_DIR 2
-
-/* Exported types ------------------------------------------------------------*/
-#pragma pack(1)
-typedef struct
-{
- uint8_t bMessageType; /* Offset = 0*/
- uint32_t dwLength; /* Offset = 1, The length field (dwLength) is the length
- of the message not including the 10-byte header.*/
- uint8_t bSlot; /* Offset = 5*/
- uint8_t bSeq; /* Offset = 6*/
- uint8_t bSpecific_0; /* Offset = 7*/
- uint8_t bSpecific_1; /* Offset = 8*/
- uint8_t bSpecific_2; /* Offset = 9*/
- uint8_t abData [ABDATA_SIZE]; /* Offset = 10, For reference, the absolute
- maximum block size for a TPDU T=0 block is 260 bytes
- (5 bytes command; 255 bytes data),
- or for a TPDU T=1 block is 259 bytes,
- or for a short APDU T=1 block is 261 bytes,
- or for an extended APDU T=1 block is 65544 bytes.*/
-} Ccid_bulkout_data_t;
-#pragma pack()
-
-#pragma pack(1)
-typedef struct
-{
- uint8_t bMessageType; /* Offset = 0*/
- uint32_t dwLength; /* Offset = 1*/
- uint8_t bSlot; /* Offset = 5, Same as Bulk-OUT message */
- uint8_t bSeq; /* Offset = 6, Same as Bulk-OUT message */
- uint8_t bStatus; /* Offset = 7, Slot status as defined in § 6.2.6*/
- uint8_t bError; /* Offset = 8, Slot error as defined in § 6.2.6*/
- uint8_t bSpecific; /* Offset = 9*/
- uint8_t abData[ABDATA_SIZE]; /* Offset = 10*/
- uint16_t u16SizeToSend;
-} Ccid_bulkin_data_t;
-#pragma pack()
-
-typedef struct
-{
- __IO uint8_t SlotStatus;
- __IO uint8_t SlotStatusChange;
-} Ccid_SlotStatus_t;
-
-
-typedef struct
-{
- __IO uint8_t bAbortRequestFlag;
- __IO uint8_t bSeq;
- __IO uint8_t bSlot;
-} usb_ccid_param_t;
-
-extern usb_ccid_param_t usb_ccid_param;
-extern Ccid_bulkout_data_t Ccid_bulkout_data; /* Buffer for the Out Data */
-extern Ccid_bulkin_data_t Ccid_bulkin_data; /* Buffer for the IN Data */
-extern Ccid_SlotStatus_t Ccid_SlotStatus;
-extern uint8_t UsbIntMessageBuffer[];
-extern uint8_t Ccid_BulkState;
-
-/* Exported macros -----------------------------------------------------------*/
-/* Exported variables --------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-void CCID_BulkMessage_In (USB_CORE_HANDLE *pdev,
- uint8_t epnum);
-
-void CCID_BulkMessage_Out (USB_CORE_HANDLE *pdev,
- uint8_t epnum);
-
-void CCID_ReceiveCmdHeader(uint8_t* pDst, uint8_t u8length);
-void CCID_CmdDecode(USB_CORE_HANDLE *pdev);
-
-void CCID_IntMessage(USB_CORE_HANDLE *pdev);
-void CCID_Init(USB_CORE_HANDLE *pdev);
-void CCID_DeInit(USB_CORE_HANDLE *pdev);
-
-uint8_t CCID_IsIntrTransferComplete(void);
-void CCID_SetIntrTransferStatus (uint8_t );
-void Transfer_Data_Request(uint8_t* dataPointer, uint16_t dataLen);
-void Set_CSW (uint8_t CSW_Status, uint8_t Send_Permission);
-
-#endif /* __USBD_CCID_IF_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/ccid/src/usbd_ccid_cmd.c b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/ccid/src/usbd_ccid_cmd.c
deleted file mode 100644
index 01df95ce76163ef41be392667eff365cdc107c3a..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/ccid/src/usbd_ccid_cmd.c
+++ /dev/null
@@ -1,1091 +0,0 @@
-/**
- ******************************************************************************
- * @file usbd_ccid_cmd.c
- * @author MCD Application Team
- * @version V1.0.1
- * @date 31-January-2014
- * @brief CCID Commands handling
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_ccid_cmd.h"
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-#define CCID_UpdateCommandStatus(cmd_status,icc_status)\
- Ccid_bulkin_data.bStatus=(cmd_status|icc_status)
- /*
- The Above Macro can take any of following Values
- #define BM_ICC_PRESENT_ACTIVE 0x00
- #define BM_ICC_PRESENT_INACTIVE 0x01
- #define BM_ICC_NO_ICC_PRESENT 0x02
-
- #define BM_COMMAND_STATUS_OFFSET 0x06
- #define BM_COMMAND_STATUS_NO_ERROR 0x00
- #define BM_COMMAND_STATUS_FAILED (0x01 << BM_COMMAND_STATUS_OFFSET)
- #define BM_COMMAND_STATUS_TIME_EXTN (0x02 << BM_COMMAND_STATUS_OFFSET)
- */
-
-/* Private variables ---------------------------------------------------------*/
-Ccid_bulkin_data_t Ccid_resp_buff;
-
-/* Private function prototypes -----------------------------------------------*/
-static uint8_t CCID_CheckCommandParams (uint32_t param_type);
-
-/* Private functions ---------------------------------------------------------*/
-
-/**
- * @brief PC_to_RDR_IccPowerOn
- * PC_TO_RDR_ICCPOWERON message execution, apply voltage and get ATR
- * @param None
- * @retval uint8_t status of the command execution
- */
-uint8_t PC_to_RDR_IccPowerOn(void)
-{
- /* Apply the ICC VCC
- Fills the Response buffer with ICC ATR
- This Command is returned with RDR_to_PC_DataBlock();
- */
-
- uint8_t voltage;
- uint8_t sc_voltage = 0;
- uint8_t index;
- uint8_t error;
-
- Ccid_bulkin_data.dwLength = 0; /* Reset Number of Bytes in abData */
-
- error = CCID_CheckCommandParams(CHK_PARAM_SLOT |\
- CHK_PARAM_DWLENGTH | \
- CHK_PARAM_abRFU2 |\
- CHK_PARAM_CARD_PRESENT |\
- CHK_PARAM_ABORT );
- if (error != 0)
- {
- return error;
- }
-
- /* Voltage that is applied to the ICC
- 00h – Automatic Voltage Selection
- 01h – 5.0 volts
- 02h – 3.0 volts
- 03h – 1.8 volts
- */
- /* Ccid_bulkout_data.bSpecific_0 Contains bPowerSelect */
- voltage = Ccid_bulkout_data.bSpecific_0;
- if (voltage >= VOLTAGE_SELECTION_1V8)
- {
- CCID_UpdateCommandStatus(BM_COMMAND_STATUS_FAILED, BM_ICC_PRESENT_ACTIVE);
- return SLOTERROR_BAD_POWERSELECT; /* The Voltage specified is out of Spec */
- }
-
- /* Correct Voltage Requested by the Host */
- if ((voltage == VOLTAGE_SELECTION_AUTOMATIC) ||
- (voltage == VOLTAGE_SELECTION_3V))
- {
- /* voltage == 00 Voltage Automatic
- voltage == 01 Voltage Automatic = 5.0V
- voltage == 02 Voltage Automatic = 3V
- voltage == 03 Voltage Automatic = 1.8V
- */
- sc_voltage = SC_VOLTAGE_3V;
- }
- else if (voltage == VOLTAGE_SELECTION_5V)
- {
- sc_voltage = SC_VOLTAGE_5V;
- }
-
- SC_AnswerToReset(sc_voltage);
-
- /* Check if the Card has come to Active State*/
- error = CCID_CheckCommandParams(CHK_ACTIVE_STATE);
- if (error != 0)
- {
- /* Check if Voltage is not Automatic */
- if (voltage != 0)
- { /* If Specific Voltage requested by Host i.e 3V or 5V*/
- return error;
- }
- else
- {/* Automatic Voltage selection requested by Host */
-
- if (sc_voltage != SC_VOLTAGE_5V)
- { /* If voltage selected was Automatic and 5V is not yet tried */
- sc_voltage = SC_VOLTAGE_5V;
- SC_AnswerToReset(sc_voltage);
-
- /* Check again the State */
- error = CCID_CheckCommandParams(CHK_ACTIVE_STATE);
- if (error != 0)
- return error;
-
- }
- else
- { /* Voltage requested from Host was 5V already*/
- CCID_UpdateCommandStatus(BM_COMMAND_STATUS_FAILED, BM_ICC_PRESENT_INACTIVE);
- return error;
- }
- } /* Voltage Selection was automatic */
- } /* If Active State */
-
- /* ATR is received, No Error Condition Found */
- Ccid_bulkin_data.dwLength = SIZE_OF_ATR;
- CCID_UpdateCommandStatus(BM_COMMAND_STATUS_NO_ERROR, BM_ICC_PRESENT_ACTIVE);
-
- for (index=0; index < SIZE_OF_ATR ; index++)
- {/* Copy the ATR to the Response Buffer */
- Ccid_bulkin_data.abData[index] = SC_ATR_Table[index];
- }
-
- return SLOT_NO_ERROR;
-}
-
-/**
- * @brief PC_to_RDR_IccPowerOff
- * Icc VCC is switched Off
- * @param None
- * @retval uint8_t error: status of the command execution
- */
-uint8_t PC_to_RDR_IccPowerOff(void)
-{
- /* The response to this command message is the RDR_to_PC_SlotStatus
- response message. */
- uint8_t error;
-
- error = CCID_CheckCommandParams(CHK_PARAM_SLOT |\
- CHK_PARAM_abRFU3 |\
- CHK_PARAM_DWLENGTH );
- if (error != 0)
- {
- return error;
- }
-
- /* Command is ok, Check for Card Presence */
- if (SC_Detect())
- {
- CCID_UpdateCommandStatus(BM_COMMAND_STATUS_NO_ERROR,BM_ICC_PRESENT_INACTIVE);
- }
- else
- {
- CCID_UpdateCommandStatus(BM_COMMAND_STATUS_NO_ERROR,BM_ICC_NO_ICC_PRESENT);
- }
-
- /* Power OFF the card */
- SC_PowerCmd(DISABLE);
- SC_SetState(SC_POWER_OFF);
-
- return SLOT_NO_ERROR;
-}
-
-/**
- * @brief PC_to_RDR_GetSlotStatus
- * Provides the Slot status to the host
- * @param None
- * @retval uint8_t status of the command execution
- */
-uint8_t PC_to_RDR_GetSlotStatus(void)
-{
- uint8_t error;
-
- error = CCID_CheckCommandParams(CHK_PARAM_SLOT |\
- CHK_PARAM_DWLENGTH |\
- CHK_PARAM_CARD_PRESENT |\
- CHK_PARAM_abRFU3 );
- if (error != 0)
- {
- return error;
- }
-
- CCID_UpdateCommandStatus(BM_COMMAND_STATUS_NO_ERROR,BM_ICC_PRESENT_ACTIVE);
- return SLOT_NO_ERROR;
-}
-
-
-/**
- * @brief PC_to_RDR_XfrBlock
- * Handles the Block transfer from Host.
- * Response to this command message is the RDR_to_PC_DataBlock
- * @param None
- * @retval uint8_t status of the command execution
- */
-uint8_t PC_to_RDR_XfrBlock(void)
-{
- uint16_t expectedLength;
-
- uint8_t error;
-
- error = CCID_CheckCommandParams(CHK_PARAM_SLOT |\
- CHK_PARAM_CARD_PRESENT |\
- CHK_PARAM_abRFU3 |\
- CHK_PARAM_ABORT |\
- CHK_ACTIVE_STATE );
- if (error != 0)
- return error;
-
- if (Ccid_bulkout_data.dwLength > ABDATA_SIZE)
- { /* Check amount of Data Sent by Host is > than memory allocated ? */
-
- return SLOTERROR_BAD_DWLENGTH;
- }
-
-
- /* wLevelParameter = Size of expected data to be returned by the
- bulk-IN endpoint */
- expectedLength = (Ccid_bulkout_data.bSpecific_2 << 8) |
- Ccid_bulkout_data.bSpecific_1;
-
- Ccid_bulkin_data.dwLength = (uint16_t)expectedLength;
-
-
- error = SC_XferBlock(&Ccid_bulkout_data.abData[0],
- Ccid_bulkout_data.dwLength,
- expectedLength);
-
- if (error != SLOT_NO_ERROR)
- {
- CCID_UpdateCommandStatus(BM_COMMAND_STATUS_FAILED, BM_ICC_PRESENT_ACTIVE);
- }
- else
- {
- CCID_UpdateCommandStatus(BM_COMMAND_STATUS_NO_ERROR, BM_ICC_PRESENT_ACTIVE);
- error = SLOT_NO_ERROR;
- }
-
- return error;
-}
-
-
-/**
- * @brief PC_to_RDR_GetParameters
- * Provides the ICC parameters to the host
- * Response to this command message is the RDR_to_PC_Parameters
- * @param None
- * @retval uint8_t status of the command execution
- */
-uint8_t PC_to_RDR_GetParameters(void)
-{
- uint8_t error;
-
- error = CCID_CheckCommandParams(CHK_PARAM_SLOT |\
- CHK_PARAM_DWLENGTH |\
- CHK_PARAM_CARD_PRESENT |\
- CHK_PARAM_abRFU3 );
- if (error != 0)
- return error;
-
- CCID_UpdateCommandStatus(BM_COMMAND_STATUS_NO_ERROR, BM_ICC_PRESENT_ACTIVE);
-
- return SLOT_NO_ERROR;
-}
-
-
-/**
- * @brief PC_to_RDR_ResetParameters
- * Set the ICC parameters to the default
- * Response to this command message is the RDR_to_PC_Parameters
- * @param None
- * @retval uint8_t status of the command execution
- */
-uint8_t PC_to_RDR_ResetParameters(void)
-{
- uint8_t error;
-
- error = CCID_CheckCommandParams(CHK_PARAM_SLOT |\
- CHK_PARAM_DWLENGTH |\
- CHK_PARAM_CARD_PRESENT |\
- CHK_PARAM_abRFU3 |\
- CHK_ACTIVE_STATE);
- if (error != 0)
- return error;
-
- /* This command resets the slot parameters to their default values */
- Ccid_bulkout_data.abData[0] = DEFAULT_FIDI;
- Ccid_bulkout_data.abData[1] = DEFAULT_T01CONVCHECKSUM;
- Ccid_bulkout_data.abData[2] = DEFAULT_EXTRA_GUARDTIME;
- Ccid_bulkout_data.abData[3] = DEFAULT_WAITINGINTEGER;
- Ccid_bulkout_data.abData[4] = DEFAULT_CLOCKSTOP;
- Ccid_bulkout_data.abData[5] = 0x00;
- Ccid_bulkout_data.abData[6] = 0x00;
-
- error = SC_SetParams((Protocol0_DataStructure_t*)(&(Ccid_bulkout_data.abData[0])));
-
- if (error != SLOT_NO_ERROR)
- {
- CCID_UpdateCommandStatus(BM_COMMAND_STATUS_FAILED, BM_ICC_PRESENT_ACTIVE);
- }
- else
- {
- CCID_UpdateCommandStatus(BM_COMMAND_STATUS_NO_ERROR, BM_ICC_PRESENT_ACTIVE);
- error = SLOT_NO_ERROR;
- }
-
- return error;
-}
-
-
-/**
- * @brief PC_to_RDR_SetParameters
- * Set the ICC parameters to the host defined parameters
- * Response to this command message is the RDR_to_PC_Parameters
- * @param None
- * @retval uint8_t status of the command execution
- */
-uint8_t PC_to_RDR_SetParameters(void)
-{
- uint8_t error;
-
- error = CCID_CheckCommandParams(CHK_PARAM_SLOT |\
- CHK_PARAM_CARD_PRESENT |\
- CHK_PARAM_abRFU2 |\
- CHK_ACTIVE_STATE);
- if (error != 0)
- return error;
-
- error = SLOT_NO_ERROR;
-
- /* for Protocol T=0 (bProtocolNum=0) (dwLength=00000005h) */
- if ( (Ccid_bulkout_data.dwLength == 5) &&
- (Ccid_bulkout_data.bSpecific_0 != 0))
- error = SLOTERROR_BAD_PROTOCOLNUM;
-
- /* for Protocol T=1 (bProtocolNum=1) (dwLength=00000007h) */
- if ( (Ccid_bulkout_data.dwLength == 7) &&
- (Ccid_bulkout_data.bSpecific_0 != 1))
- error = SLOTERROR_CMD_NOT_SUPPORTED;
-
- /* For T0, Waiting Integer 0 supported */
- if (Ccid_bulkout_data.abData[3] != 0)
- error = SLOTERROR_BAD_WAITINGINTEGER;
-
- if (Ccid_bulkout_data.abData[4] != DEFAULT_CLOCKSTOP)
- error = SLOTERROR_BAD_CLOCKSTOP;
-
- if (error != SLOT_NO_ERROR)
- {
- CCID_UpdateCommandStatus(BM_COMMAND_STATUS_FAILED, BM_ICC_PRESENT_ACTIVE);
- }
-
- error = SC_SetParams((Protocol0_DataStructure_t*)(&(Ccid_bulkout_data.abData[0])));
-
- if (error != SLOT_NO_ERROR)
- {
- CCID_UpdateCommandStatus(BM_COMMAND_STATUS_FAILED, BM_ICC_PRESENT_ACTIVE);
- }
- else
- {
- CCID_UpdateCommandStatus(BM_COMMAND_STATUS_NO_ERROR, BM_ICC_PRESENT_ACTIVE);
- error = SLOT_NO_ERROR;
- }
-
- return error;
-}
-
-
-/**
- * @brief PC_to_RDR_Escape
- * Execute the Escape command. This is user specific Implementation
- * Response to this command message is the RDR_to_PC_Escape
- * @param None
- * @retval uint8_t status of the command execution
- */
-uint8_t PC_to_RDR_Escape(void)
-{
- uint8_t error;
- uint16_t size;
-
- error = CCID_CheckCommandParams(CHK_PARAM_SLOT |\
- CHK_PARAM_CARD_PRESENT |\
- CHK_PARAM_abRFU3 |\
- CHK_PARAM_ABORT |\
- CHK_ACTIVE_STATE);
-
- if (error != 0)
- return error;
-
- error = SC_ExecuteEscape(&Ccid_bulkout_data.abData[0],
- Ccid_bulkout_data.dwLength,
- &Ccid_bulkin_data.abData[0],
- &size);
-
- Ccid_bulkin_data.dwLength = size;
-
- if (error != SLOT_NO_ERROR)
- {
- CCID_UpdateCommandStatus(BM_COMMAND_STATUS_FAILED, BM_ICC_PRESENT_ACTIVE);
- }
- else
- {
- CCID_UpdateCommandStatus(BM_COMMAND_STATUS_NO_ERROR, BM_ICC_PRESENT_ACTIVE);
- }
-
- return error;
-}
-
-
-/**
- * @brief PC_to_RDR_IccClock
- * Execute the Clock specific command from host
- * Response to this command message is the RDR_to_PC_SlotStatus
- * @param None
- * @retval uint8_t status of the command execution
- */
-uint8_t PC_to_RDR_IccClock(void)
-{
- uint8_t error;
-
- error = CCID_CheckCommandParams(CHK_PARAM_SLOT |\
- CHK_PARAM_CARD_PRESENT |\
- CHK_PARAM_abRFU2 |\
- CHK_PARAM_DWLENGTH|\
- CHK_ACTIVE_STATE);
- if (error != 0)
- return error;
-
- /* bClockCommand • 00h restarts Clock
- • 01h Stops Clock in the state shown in the bClockStop
- field of the PC_to_RDR_SetParameters command
- and RDR_to_PC_Parameters message.*/
- if (Ccid_bulkout_data.bSpecific_0 > 1)
- {
- CCID_UpdateCommandStatus(BM_COMMAND_STATUS_FAILED, BM_ICC_PRESENT_ACTIVE);
- return SLOTERROR_BAD_CLOCKCOMMAND;
- }
-
- error = SC_SetClock(Ccid_bulkout_data.bSpecific_0);
-
- if (error != SLOT_NO_ERROR)
- {
- CCID_UpdateCommandStatus(BM_COMMAND_STATUS_FAILED, BM_ICC_PRESENT_ACTIVE);
- }
- else
- {
- CCID_UpdateCommandStatus(BM_COMMAND_STATUS_NO_ERROR, BM_ICC_PRESENT_ACTIVE);
- }
-
- return error;
-}
-
-
-/**
- * @brief PC_to_RDR_Abort
- * Execute the Abort command from host, This stops all Bulk transfers
- * from host and ICC
- * Response to this command message is the RDR_to_PC_SlotStatus
- * @param None
- * @retval uint8_t status of the command execution
- */
-uint8_t PC_to_RDR_Abort(void)
-{
- uint8_t error;
-
- error = CCID_CheckCommandParams(CHK_PARAM_SLOT |\
- CHK_PARAM_abRFU3 |\
- CHK_PARAM_DWLENGTH);
- if (error != 0)
- return error;
-
- CCID_CmdAbort (Ccid_bulkout_data.bSlot, Ccid_bulkout_data.bSeq);
- CCID_UpdateCommandStatus(BM_COMMAND_STATUS_NO_ERROR,BM_ICC_PRESENT_ACTIVE);
- return SLOT_NO_ERROR;
-}
-
-/**
- * @brief CCID_CmdAbort
- * Execute the Abort command from Bulk EP or from Control EP,
- * This stops all Bulk transfers from host and ICC
- * @param uint8_t slot: slot number that host wants to abort
- * @param uint8_t seq : Seq number for PC_to_RDR_Abort
- * @retval uint8_t status of the command execution
- */
-uint8_t CCID_CmdAbort(uint8_t slot, uint8_t seq)
-{
- /* This function is called for REQUEST_ABORT & PC_to_RDR_Abort */
-
- if (slot >= CCID_NUMBER_OF_SLOTS)
- { /* This error condition is possible only from CLASS_REQUEST, otherwise
- Slot is already checked in parameters from PC_to_RDR_Abort request */
- /* Slot requested is more than supported by Firmware */
- CCID_UpdateCommandStatus(BM_COMMAND_STATUS_FAILED,BM_ICC_NO_ICC_PRESENT);
- return SLOTERROR_BAD_SLOT;
- }
-
- if ( usb_ccid_param.bAbortRequestFlag == 1)
- { /* Abort Command was already received from ClassReq or PC_to_RDR */
- if (( usb_ccid_param.bSeq == seq) && (usb_ccid_param.bSlot == slot))
- {
- /* CLASS Specific request is already Received, Reset the abort flag */
- usb_ccid_param.bAbortRequestFlag = 0;
- }
- }
- else
- {
- /* Abort Command was NOT received from ClassReq or PC_to_RDR,
- so save them for next ABORT command to verify */
- usb_ccid_param.bAbortRequestFlag = 1;
- usb_ccid_param.bSeq = seq ;
- usb_ccid_param.bSlot = slot;
- }
-
- return 0;
-}
-
-/**
- * @brief PC_TO_RDR_T0Apdu
- * Execute the PC_TO_RDR_T0APDU command from host
- * Response to this command message is the RDR_to_PC_SlotStatus
- * @param None
- * @retval uint8_t status of the command execution
- */
-uint8_t PC_TO_RDR_T0Apdu(void)
-{
- uint8_t error;
-
- error = CCID_CheckCommandParams(CHK_PARAM_SLOT |\
- CHK_PARAM_CARD_PRESENT |\
- CHK_PARAM_DWLENGTH |
- CHK_PARAM_ABORT );
- if (error != 0)
- return error;
-
- if (Ccid_bulkout_data.bSpecific_0 > 0x03)
- {/* Bit 0 is associated with field bClassGetResponse
- Bit 1 is associated with field bClassEnvelope
- Other bits are RFU.*/
-
- CCID_UpdateCommandStatus(BM_COMMAND_STATUS_FAILED, BM_ICC_PRESENT_ACTIVE);
- return SLOTERROR_BAD_BMCHANGES;
- }
-
- error = SC_T0Apdu(Ccid_bulkout_data.bSpecific_0,
- Ccid_bulkout_data.bSpecific_1,
- Ccid_bulkout_data.bSpecific_2);
-
- if (error != SLOT_NO_ERROR)
- {
- CCID_UpdateCommandStatus(BM_COMMAND_STATUS_FAILED, BM_ICC_PRESENT_ACTIVE);
- }
- else
- {
- CCID_UpdateCommandStatus(BM_COMMAND_STATUS_NO_ERROR, BM_ICC_PRESENT_ACTIVE);
- }
-
- return error;
-}
-
-/**
- * @brief PC_TO_RDR_Mechanical
- * Execute the PC_TO_RDR_MECHANICAL command from host
- * Response to this command message is the RDR_to_PC_SlotStatus
- * @param None
- * @retval uint8_t status of the command execution
- */
-uint8_t PC_TO_RDR_Mechanical(void)
-{
- uint8_t error;
-
- error = CCID_CheckCommandParams(CHK_PARAM_SLOT |\
- CHK_PARAM_CARD_PRESENT |\
- CHK_PARAM_abRFU2 |\
- CHK_PARAM_DWLENGTH
- );
- if (error != 0)
- return error;
-
- if (Ccid_bulkout_data.bSpecific_0 > 0x05)
- {/* 01h – Accept Card
- 02h – Eject Card
- 03h – Capture Card
- 04h – Lock Card
- 05h – Unlock Card*/
-
- CCID_UpdateCommandStatus(BM_COMMAND_STATUS_FAILED, BM_ICC_PRESENT_ACTIVE);
- return SLOTERROR_BAD_BFUNCTION_MECHANICAL;
- }
-
- error = SC_Mechanical(Ccid_bulkout_data.bSpecific_0);
-
- if (error != SLOT_NO_ERROR)
- {
- CCID_UpdateCommandStatus(BM_COMMAND_STATUS_FAILED, BM_ICC_PRESENT_ACTIVE);
- }
- else
- {
- CCID_UpdateCommandStatus(BM_COMMAND_STATUS_NO_ERROR, BM_ICC_PRESENT_ACTIVE);
- }
-
- return error;
-}
-
-/**
- * @brief PC_TO_RDR_SetDataRateAndClockFrequency
- * Set the required Card Frequency and Data rate from the host.
- * Response to this command message is the
- * RDR_to_PC_DataRateAndClockFrequency
- * @param None
- * @retval uint8_t status of the command execution
- */
-uint8_t PC_TO_RDR_SetDataRateAndClockFrequency(void)
-{
- uint8_t error;
- uint32_t clockFrequency;
- uint32_t dataRate;
- uint32_t temp =0;
-
- error = CCID_CheckCommandParams(CHK_PARAM_SLOT |\
- CHK_PARAM_CARD_PRESENT |\
- CHK_PARAM_abRFU3);
- if (error != 0)
- return error;
-
- if (Ccid_bulkout_data.dwLength != 0x08)
- {
- CCID_UpdateCommandStatus(BM_COMMAND_STATUS_FAILED,BM_ICC_PRESENT_ACTIVE);
- return SLOTERROR_BAD_LENTGH;
- }
-
- /* HERE we avoiding to an unaligned memory access*/
- temp = (Ccid_bulkout_data.abData[0]) & 0x000000FF;
- clockFrequency = temp;
-
- temp= (Ccid_bulkout_data.abData[1]) & 0x000000FF;
- clockFrequency |= temp << 8;
-
- temp= (Ccid_bulkout_data.abData[2]) & 0x000000FF;
- clockFrequency |= temp << 16;
-
- temp= (Ccid_bulkout_data.abData[3]) & 0x000000FF;
- clockFrequency |= temp << 24;
-
- temp = (Ccid_bulkout_data.abData[4]) & 0x000000FF;
- dataRate = temp;
-
- temp= (Ccid_bulkout_data.abData[5]) & 0x000000FF;
- dataRate |= temp << 8;
-
- temp= (Ccid_bulkout_data.abData[6]) & 0x000000FF;
- dataRate |= temp << 16;
-
- temp= (Ccid_bulkout_data.abData[7]) & 0x000000FF;
- dataRate |= temp << 24;
-
- error = SC_SetDataRateAndClockFrequency(clockFrequency, dataRate);
- Ccid_bulkin_data.bError = error;
-
- if (error != SLOT_NO_ERROR)
- {
- Ccid_bulkin_data.dwLength = 0;
- CCID_UpdateCommandStatus(BM_COMMAND_STATUS_FAILED, BM_ICC_PRESENT_ACTIVE);
- }
- else
- {
- Ccid_bulkin_data.dwLength = 8;
-
- (Ccid_bulkin_data.abData[0]) = clockFrequency & 0x000000FF ;
-
- (Ccid_bulkin_data.abData[1]) = (clockFrequency & 0x0000FF00) >> 8;
-
- (Ccid_bulkin_data.abData[2]) = (clockFrequency & 0x00FF0000) >> 16;
-
- (Ccid_bulkin_data.abData[3]) = (clockFrequency & 0xFF000000) >> 24;
-
- (Ccid_bulkin_data.abData[4]) = dataRate & 0x000000FF ;
-
- (Ccid_bulkin_data.abData[5]) = (dataRate & 0x0000FF00) >> 8;
-
- (Ccid_bulkin_data.abData[6]) = (dataRate & 0x00FF0000) >> 16;
-
- (Ccid_bulkin_data.abData[7]) = (dataRate & 0xFF000000) >> 24;
-
- CCID_UpdateCommandStatus(BM_COMMAND_STATUS_NO_ERROR, BM_ICC_PRESENT_ACTIVE);
- }
-
- return error;
-}
-
-/**
- * @brief PC_TO_RDR_Secure
- * Execute the Secure Command from the host.
- * Response to this command message is the RDR_to_PC_DataBlock
- * @param None
- * @retval uint8_t status of the command execution
- */
-uint8_t PC_TO_RDR_Secure(void)
-{
- uint8_t error;
- uint8_t bBWI;
- uint16_t wLevelParameter;
- uint32_t responseLen;
-
- Ccid_bulkin_data.dwLength =0;
-
- error = CCID_CheckCommandParams(CHK_PARAM_SLOT |\
- CHK_PARAM_CARD_PRESENT |\
- CHK_PARAM_ABORT );
-
- if (error != 0)
- return error;
-
- bBWI = Ccid_bulkout_data.bSpecific_0;
- wLevelParameter = (Ccid_bulkout_data.bSpecific_1 + ((uint16_t)Ccid_bulkout_data.bSpecific_2<<8));
-
- if ((EXCHANGE_LEVEL_FEATURE == TPDU_EXCHANGE) ||
- (EXCHANGE_LEVEL_FEATURE == SHORT_APDU_EXCHANGE))
- {
- /* TPDU level & short APDU level, wLevelParameter is RFU, = 0000h */
- if (wLevelParameter != 0 )
- {
- CCID_UpdateCommandStatus(BM_COMMAND_STATUS_FAILED, BM_ICC_PRESENT_ACTIVE);
- error = SLOTERROR_BAD_LEVELPARAMETER;
- return error;
- }
- }
-
- error = SC_Secure(Ccid_bulkout_data.dwLength, bBWI, wLevelParameter,
- &Ccid_bulkout_data.abData[0], &responseLen);
-
- Ccid_bulkin_data.dwLength = responseLen;
-
- if (error != SLOT_NO_ERROR)
- {
- CCID_UpdateCommandStatus(BM_COMMAND_STATUS_FAILED, BM_ICC_PRESENT_ACTIVE);
- }
- else
- {
- CCID_UpdateCommandStatus(BM_COMMAND_STATUS_NO_ERROR, BM_ICC_PRESENT_ACTIVE);
- }
-
- return error;
-}
-
-/******************************************************************************/
-/* BULK IN ROUTINES */
-/******************************************************************************/
-
-/**
- * @brief RDR_to_PC_DataBlock
- * Provide the data block response to the host
- * Response for PC_to_RDR_IccPowerOn, PC_to_RDR_XfrBlock
- * @param uint8_t errorCode: code to be returned to the host
- * @retval None
- */
-void RDR_to_PC_DataBlock(uint8_t errorCode)
-{
- uint16_t length = CCID_RESPONSE_HEADER_SIZE;
-
- Ccid_bulkin_data.bMessageType = RDR_TO_PC_DATABLOCK;
- Ccid_bulkin_data.bError = errorCode;
- Ccid_bulkin_data.bSpecific=0; /* bChainParameter */
-
- if(errorCode == SLOT_NO_ERROR)
- {
- length += Ccid_bulkin_data.dwLength; /* Length Specified in Command */
- }
-
- Transfer_Data_Request( (uint8_t*) (&Ccid_bulkin_data), length);
-
-}
-
-
-/**
- * @brief RDR_to_PC_SlotStatus
- * Provide the Slot status response to the host
- * Response for PC_to_RDR_IccPowerOff
- * PC_to_RDR_GetSlotStatus
- * PC_to_RDR_IccClock
- * PC_to_RDR_T0APDU
- * PC_to_RDR_Mechanical
- * Also the device sends this response message when it has completed
- * aborting a slot after receiving both the Class Specific ABORT request
- * and PC_to_RDR_Abort command message.
- * @param uint8_t errorCode: code to be returned to the host
- * @retval None
- */
-void RDR_to_PC_SlotStatus(uint8_t errorCode)
-{
-
- Ccid_bulkin_data.bMessageType = RDR_TO_PC_SLOTSTATUS;
- Ccid_bulkin_data.dwLength =0;
- Ccid_bulkin_data.bError = errorCode;
- Ccid_bulkin_data.bSpecific=0; /* bClockStatus = 00h Clock running
- 01h Clock stopped in state L
- 02h Clock stopped in state H
- 03h Clock stopped in an unknown state
- All other values are RFU. */
-
- Transfer_Data_Request( (uint8_t*) (&Ccid_bulkin_data),
- LEN_RDR_TO_PC_SLOTSTATUS);
-
-}
-
-/**
- * @brief RDR_to_PC_Parameters
- * Provide the data block response to the host
- * Response for PC_to_RDR_GetParameters, PC_to_RDR_ResetParameters
- * PC_to_RDR_SetParameters
- * @param uint8_t errorCode: code to be returned to the host
- * @retval None
- */
-void RDR_to_PC_Parameters(uint8_t errorCode)
-{
- uint16_t length = CCID_RESPONSE_HEADER_SIZE;
-
- Ccid_bulkin_data.bMessageType = RDR_TO_PC_PARAMETERS;
- Ccid_bulkin_data.bError = errorCode;
-
- if(errorCode == SLOT_NO_ERROR)
- {
- Ccid_bulkin_data.dwLength = LEN_PROTOCOL_STRUCT_T0;
- length += LEN_PROTOCOL_STRUCT_T0;
- }
- else
- {
- Ccid_bulkin_data.dwLength = 0;
- }
-
- Ccid_bulkin_data.abData[0] = Protocol0_DataStructure.bmFindexDindex ;
- Ccid_bulkin_data.abData[1] = Protocol0_DataStructure.bmTCCKST0;
- Ccid_bulkin_data.abData[2] = Protocol0_DataStructure.bGuardTimeT0;
- Ccid_bulkin_data.abData[3] = Protocol0_DataStructure.bWaitingIntegerT0;
- Ccid_bulkin_data.abData[4] = Protocol0_DataStructure.bClockStop;
-
- /* bProtocolNum */
- Ccid_bulkin_data.bSpecific = BPROTOCOL_NUM_T0;
-
- Transfer_Data_Request( (uint8_t*) (&Ccid_bulkin_data), length);
-}
-
-/**
- * @brief RDR_to_PC_Escape
- * Provide the Escaped data block response to the host
- * Response for PC_to_RDR_Escape
- * @param uint8_t errorCode: code to be returned to the host
- * @retval None
- */
-void RDR_to_PC_Escape(uint8_t errorCode)
-{
- uint16_t length = CCID_RESPONSE_HEADER_SIZE;
-
- Ccid_bulkin_data.bMessageType = RDR_TO_PC_ESCAPE;
-
- Ccid_bulkin_data.bSpecific=0; /* Reserved for Future Use */
- Ccid_bulkin_data.bError = errorCode;
-
- if(errorCode == SLOT_NO_ERROR)
- {
- length += Ccid_bulkin_data.dwLength; /* Length Specified in Command */
- }
-
- Transfer_Data_Request( (uint8_t*) (&Ccid_bulkin_data), length);
-}
-
-
-
-/**
- * @brief RDR_to_PC_DataRateAndClockFrequency
- * Provide the Clock and Data Rate information to host
- * Response for PC_TO_RDR_SetDataRateAndClockFrequency
- * @param uint8_t errorCode: code to be returned to the host
- * @retval None
- */
-void RDR_to_PC_DataRateAndClockFrequency(uint8_t errorCode)
-{
- uint16_t length = CCID_RESPONSE_HEADER_SIZE;
-
- Ccid_bulkin_data.bMessageType = RDR_TO_PC_DATARATEANDCLOCKFREQUENCY;
- Ccid_bulkin_data.bError = errorCode;
- Ccid_bulkin_data.bSpecific=0; /* Reserved for Future Use */
-
- if(errorCode == SLOT_NO_ERROR)
- {
- length += Ccid_bulkin_data.dwLength; /* Length Specified in Command */
- }
-
- Transfer_Data_Request( (uint8_t*) (&Ccid_bulkin_data), length);
-}
-
-/**
- * @brief RDR_to_PC_NotifySlotChange
- * Interrupt message to be sent to the host, Checks the card presence
- * status and update the buffer accordingly
- * @param None
- * @retval None
- */
-void RDR_to_PC_NotifySlotChange(void)
-{
- UsbIntMessageBuffer[OFFSET_INT_BMESSAGETYPE] = RDR_TO_PC_NOTIFYSLOTCHANGE;
-
- if (SC_Detect() )
- {
- /*
- SLOT_ICC_PRESENT 0x01 : LSb : (0b = no ICC present, 1b = ICC present)
- SLOT_ICC_CHANGE 0x02 : MSb : (0b = no change, 1b = change).
- */
- UsbIntMessageBuffer[OFFSET_INT_BMSLOTICCSTATE] = SLOT_ICC_PRESENT |
- SLOT_ICC_CHANGE;
- }
- else
- {
- UsbIntMessageBuffer[OFFSET_INT_BMSLOTICCSTATE] = SLOT_ICC_CHANGE;
-
- /* Power OFF the card */
- SC_PowerCmd(DISABLE);
- SC_SetState(SC_POWER_OFF);
- }
-}
-
-
-/**
- * @brief CCID_UpdSlotStatus
- * Updates the variable for the slot status
- * @param uint8_t slotStatus : slot status from the calling function
- * @retval None
- */
-void CCID_UpdSlotStatus (uint8_t slotStatus)
-{
- Ccid_SlotStatus.SlotStatus = slotStatus;
-}
-
-/**
- * @brief CCID_UpdSlotChange
- * Updates the variable for the slot change status
- * @param uint8_t changeStatus : slot change status from the calling function
- * @retval None
- */
-void CCID_UpdSlotChange (uint8_t changeStatus)
-{
- Ccid_SlotStatus.SlotStatusChange = changeStatus;
-}
-
-/**
- * @brief CCID_IsSlotStatusChange
- * Provides the value of the variable for the slot change status
- * @param None
- * @retval uint8_t slot change status
- */
-uint8_t CCID_IsSlotStatusChange (void)
-{
- return Ccid_SlotStatus.SlotStatusChange;
-}
-
-/**
- * @brief CCID_CheckCommandParams
- * Checks the specific parameters requested by the function and update
- * status accordingly. This function is called from all
- * PC_to_RDR functions
- * @param uint32_t param_type : Parameter enum to be checked by calling function
- * @retval uint8_t status
- */
-static uint8_t CCID_CheckCommandParams (uint32_t param_type)
-{
- uint32_t parameter;
-
- Ccid_bulkin_data.bStatus = BM_ICC_PRESENT_ACTIVE | BM_COMMAND_STATUS_NO_ERROR ;
-
- parameter = (uint32_t)param_type;
-
- if (parameter & CHK_PARAM_SLOT)
- {
- /*
- The slot number (bSlot) identifies which ICC slot is being addressed
- by the message, if the CCID supports multiple slots.
- The slot number is zero-relative, and is in the range of zero to FFh.
- */
-
- /* SLOT Number is 0 onwards, so always < CCID_NUMBER_OF_SLOTs */
- /* Error Condition !!! */
- if (Ccid_bulkout_data.bSlot >= CCID_NUMBER_OF_SLOTS)
- { /* Slot requested is more than supported by Firmware */
- CCID_UpdateCommandStatus(BM_COMMAND_STATUS_FAILED,BM_ICC_NO_ICC_PRESENT);
- return SLOTERROR_BAD_SLOT;
- }
- }
-
- if (parameter & CHK_PARAM_CARD_PRESENT)
- {
- /* Commands Parameters ok, Check the Card Status */
- if (SC_Detect() == 0)
- { /* Card is Not detected */
- CCID_UpdateCommandStatus(BM_COMMAND_STATUS_FAILED,BM_ICC_NO_ICC_PRESENT);
- return SLOTERROR_ICC_MUTE;
- }
- }
-
- /* Check that DwLength is 0 */
- if (parameter & CHK_PARAM_DWLENGTH)
- {
- if (Ccid_bulkout_data.dwLength != 0)
- {
- CCID_UpdateCommandStatus(BM_COMMAND_STATUS_FAILED,BM_ICC_PRESENT_ACTIVE);
- return SLOTERROR_BAD_LENTGH;
- }
- }
-
- /* abRFU 2 : Reserved for Future Use*/
- if (parameter & CHK_PARAM_abRFU2)
- {
-
- if ((Ccid_bulkout_data.bSpecific_1 != 0) ||
- (Ccid_bulkout_data.bSpecific_2 != 0))
- {
- CCID_UpdateCommandStatus(BM_COMMAND_STATUS_FAILED,BM_ICC_PRESENT_ACTIVE);
- return SLOTERROR_BAD_ABRFU_2B; /* bSpecific_1 */
- }
- }
-
- if (parameter & CHK_PARAM_abRFU3)
- {
- /* abRFU 3 : Reserved for Future Use*/
- if ((Ccid_bulkout_data.bSpecific_0 != 0) ||
- (Ccid_bulkout_data.bSpecific_1 != 0) ||
- (Ccid_bulkout_data.bSpecific_2 != 0))
- {
- CCID_UpdateCommandStatus(BM_COMMAND_STATUS_FAILED,BM_ICC_PRESENT_ACTIVE);
- return SLOTERROR_BAD_ABRFU_3B;
- }
- }
-
-
- if (parameter & CHK_PARAM_ABORT)
- {
- if( usb_ccid_param.bAbortRequestFlag )
- {
- CCID_UpdateCommandStatus(BM_COMMAND_STATUS_FAILED,BM_ICC_PRESENT_INACTIVE);
- return SLOTERROR_CMD_ABORTED;
- }
- }
-
- if (parameter & CHK_ACTIVE_STATE)
- {
- /* Commands Parameters ok, Check the Card Status */
- /* Card is detected */
- if (SC_GetState() != SC_ACTIVE_ON_T0)
- {
- /* Check that from Lower Layers, the SmartCard come to known state */
- CCID_UpdateCommandStatus(BM_COMMAND_STATUS_FAILED,BM_ICC_PRESENT_INACTIVE);
- return SLOTERROR_HW_ERROR;
- }
- }
-
- return 0;
-}
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/ccid/src/usbd_ccid_core.c b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/ccid/src/usbd_ccid_core.c
deleted file mode 100644
index 45404b945b82b75372c3ed5db2b05bc7d69d5982..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/ccid/src/usbd_ccid_core.c
+++ /dev/null
@@ -1,455 +0,0 @@
-/**
- ******************************************************************************
- * @file usbd_ccid_core.c
- * @author MCD Application Team
- * @version V1.0.1
- * @date 31-January-2014
- * @brief This file provides all the CCID core functions.
- *
- * @verbatim
- *
- * ===================================================================
- * CCID Class Description
- * ===================================================================
- * This module manages the Specification for Integrated Circuit(s)
- * Cards Interface Revision 1.1
- * This driver implements the following aspects of the specification:
- * - Bulk Transfers
- *
- * @endverbatim
- *
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_ccid_core.h"
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-static uint8_t USBD_CCID_Init (void *pdev,
- uint8_t cfgidx);
-
-static uint8_t USBD_CCID_DeInit (void *pdev,
- uint8_t cfgidx);
-
-static uint8_t USBD_CCID_Setup (void *pdev,
- USB_SETUP_REQ *req);
-
-static uint8_t USBD_CCID_DataIn (void *pdev,
- uint8_t epnum);
-
-
-static uint8_t USBD_CCID_DataOut (void *pdev,
- uint8_t epnum);
-
-static uint8_t *USBD_CCID_GetCfgDesc (uint8_t speed,
- uint16_t *length);
-
-static uint8_t USBD_CCID_EP0_Buff[CCID_EP0_BUFF_SIZ] ;
-
-USBD_Class_cb_TypeDef USBD_CCID_cb =
-{
- USBD_CCID_Init,
- USBD_CCID_DeInit,
- USBD_CCID_Setup,
- NULL, /*EP0_TxSent*/
- NULL, /*EP0_RxReady*/
- USBD_CCID_DataIn,
- USBD_CCID_DataOut,
- NULL, /*SOF */
- USBD_CCID_GetCfgDesc,
-};
-
-/* USB Mass storage device Configuration Descriptor */
-/* All Descriptors (Configuration, Interface, Endpoint, Class, Vendor */
-const uint8_t USBD_CCID_CfgDesc[SMARTCARD_SIZ_CONFIG_DESC] =
-{
-
- 0x09, /* bLength: Configuration Descriptor size */
- USB_DESC_TYPE_CONFIGURATION, /* bDescriptorType: Configuration */
- SMARTCARD_SIZ_CONFIG_DESC,
-
- 0x00,
- 0x01, /* bNumInterfaces: 1 interface */
- 0x01, /* bConfigurationValue: */
- 0x04, /* iConfiguration: */
- 0x80, /*bmAttributes: bus powered */
- 0x32, /* MaxPower 100 mA */
-
- /******************** CCID **** interface ********************/
- 0x09, /* bLength: Interface Descriptor size */
- 0x04, /* bDescriptorType: */
- 0x00, /* bInterfaceNumber: Number of Interface */
- 0x00, /* bAlternateSetting: Alternate setting */
- 0x03, /* bNumEndpoints: 3 endpoints used */
- 0x0B, /* bInterfaceClass: user's interface for CCID */
- 0x00, /* bInterfaceSubClass : */
- 0x00, /* nInterfaceProtocol : None */
- 0x05, /* iInterface: */
-
- /******************* CCID class descriptor ********************/
- 0x36, /* bLength: CCID Descriptor size */
- 0x21, /* bDescriptorType: Functional Descriptor type. */
- 0x10, /* bcdCCID(LSB): CCID Class Spec release number (1.00) */
- 0x01, /* bcdCCID(MSB) */
-
- 0x00, /* bMaxSlotIndex :highest available slot on this device */
- 0x03, /* bVoltageSupport: bit Wise OR for 01h-5.0V 02h-3.0V
- 04h 1.8V*/
-
- 0x01,0x00,0x00,0x00, /* dwProtocols: 0001h = Protocol T=0 */
- 0x10,0x0E,0x00,0x00, /* dwDefaultClock: 3.6Mhz = 3600kHz = 0x0E10,
- for 4 Mhz the value is (0x00000FA0) :
- This is used in ETU and waiting time calculations*/
- 0x10,0x0E,0x00,0x00, /* dwMaximumClock: Maximum supported ICC clock frequency
- in KHz. So, 3.6Mhz = 3600kHz = 0x0E10,
- 4 Mhz (0x00000FA0) : */
- 0x00, /* bNumClockSupported : no setting from PC
- If the value is 00h, the
- supported clock frequencies are assumed to be the
- default clock frequency defined by dwDefaultClock
- and the maximum clock frequency defined by
- dwMaximumClock */
-
- 0xCD,0x25,0x00,0x00, /* dwDataRate: Default ICC I/O data rate in bps
- 9677 bps = 0x25CD
- for example 10752 bps (0x00002A00) */
-
- 0xCD,0x25,0x00,0x00, /* dwMaxDataRate: Maximum supported ICC I/O data
- rate in bps */
- 0x00, /* bNumDataRatesSupported :
- The number of data rates that are supported by the CCID
- If the value is 00h, all data rates between the default
- data rate dwDataRate and the maximum data rate
- dwMaxDataRate are supported.
- Dont support GET_CLOCK_FREQUENCIES
- */
-
- 0x00,0x00,0x00,0x00, /* dwMaxIFSD: 0 (T=0 only) */
- 0x00,0x00,0x00,0x00, /* dwSynchProtocols */
- 0x00,0x00,0x00,0x00, /* dwMechanical: no special characteristics */
-
- 0x38,0x00,EXCHANGE_LEVEL_FEATURE,0x00,
- /* dwFeatures: clk, baud rate, voltage : automatic */
- /* 00000008h Automatic ICC voltage selection
- 00000010h Automatic ICC clock frequency change
- 00000020h Automatic baud rate change according to
- active parameters provided by the Host or self
- determined 00000100h CCID can set
- ICC in clock stop mode
-
- Only one of the following values may be present to
- select a level of exchange:
- 00010000h TPDU level exchanges with CCID
- 00020000h Short APDU level exchange with CCID
- 00040000h Short and Extended APDU level exchange
- If none of those values : character level of exchange*/
- 0x0F,0x01,0x00,0x00, /* dwMaxCCIDMessageLength: Maximum block size + header*/
- /* 261 + 10 */
-
- 0x00, /* bClassGetResponse*/
- 0x00, /* bClassEnvelope */
- 0x00,0x00, /* wLcdLayout : 0000h no LCD. */
- 0x00, /* bPINSupport : no PIN verif and modif */
- 0x01, /* bMaxCCIDBusySlots */
-
- /******************** CCID Endpoints ********************/
- 0x07, /*Endpoint descriptor length = 7*/
- 0x05, /*Endpoint descriptor type */
- CCID_BULK_IN_EP, /*Endpoint address (IN, address 1) */
- 0x02, /*Bulk endpoint type */
- LOBYTE(CCID_BULK_EPIN_SIZE),
- HIBYTE(CCID_BULK_EPIN_SIZE),
- 0x00, /*Polling interval in milliseconds */
-
- 0x07, /*Endpoint descriptor length = 7 */
- 0x05, /*Endpoint descriptor type */
- CCID_BULK_OUT_EP, /*Endpoint address (OUT, address 1) */
- 0x02, /*Bulk endpoint type */
- LOBYTE(CCID_BULK_EPOUT_SIZE),
- HIBYTE(CCID_BULK_EPOUT_SIZE),
- 0x00, /*Polling interval in milliseconds*/
-
-
- 0x07, /*bLength: Endpoint Descriptor size*/
- 0x05, /*bDescriptorType:*/
- CCID_INTR_IN_EP, /*bEndpointAddress: Endpoint Address (IN)*/
- 0x03, /* bmAttributes: Interrupt endpoint */
- LOBYTE(CCID_INTR_EPIN_SIZE),
- HIBYTE(CCID_INTR_EPIN_SIZE),
- 0x18 /*Polling interval in milliseconds */
-};
-
-/* Private function ----------------------------------------------------------*/
-
-/**
- * @brief USBD_CCID_Init
- * Initialize the USB CCID Interface
- * @param pdev: device instance
- * @param cfgidx: configuration index
- * @retval status
- */
-static uint8_t USBD_CCID_Init (void *pdev,
- uint8_t cfgidx)
-{
-
- DCD_PMA_Config(pdev , CCID_BULK_IN_EP,USB_SNG_BUF,CCID_BULK_TX_ADDRESS);
- DCD_PMA_Config(pdev , CCID_INTR_IN_EP,USB_SNG_BUF,CCID_INT_TX_ADDRESS);
- DCD_PMA_Config(pdev , CCID_BULK_OUT_EP,USB_SNG_BUF,CCID_BULK_RX_ADDRESS);
-
-
- /* Open EP IN */
- DCD_EP_Open(pdev,
- CCID_BULK_IN_EP,
- CCID_BULK_EPIN_SIZE,
- USB_EP_BULK);
-
- /* Open EP OUT */
- DCD_EP_Open(pdev,
- CCID_BULK_OUT_EP,
- CCID_BULK_EPOUT_SIZE,
- USB_EP_BULK);
-
- /* Open INTR EP IN */
- DCD_EP_Open(pdev,
- CCID_INTR_IN_EP,
- CCID_INTR_EPIN_SIZE,
- USB_EP_INT);
-
- /* Init the CCID layer */
- CCID_Init(pdev);
-
- return USBD_OK;
-}
-
-/**
- * @brief USBD_CCID_DeInit
- * DeInitilaize the usb ccid configuration
- * @param pdev: device instance
- * @param cfgidx: configuration index
- * @retval status
- */
-static uint8_t USBD_CCID_DeInit (void *pdev,
- uint8_t cfgidx)
-{
- /* Close CCID EPs */
- DCD_EP_Close (pdev , CCID_BULK_IN_EP);
- DCD_EP_Close (pdev , CCID_BULK_OUT_EP);
- DCD_EP_Close (pdev , CCID_INTR_IN_EP);
-
- /* Un Init the CCID layer */
- CCID_DeInit(pdev);
- return USBD_OK;
-}
-
-/**
- * @brief USBD_CCID_Setup
- * Handle the CCID specific requests
- * @param pdev: device instance
- * @param req: USB request
- * @retval status
- */
-static uint8_t USBD_CCID_Setup (void *pdev, USB_SETUP_REQ *req)
-{
- uint8_t slot_nb;
- uint8_t seq_nb;
- uint16_t len;
-
- switch (req->bmRequest & USB_REQ_TYPE_MASK)
- {
- /* Class request */
- case USB_REQ_TYPE_CLASS :
- switch (req->bRequest)
- {
- case REQUEST_ABORT :
-
- if ((req->wLength == 0) &&
- ((req->bmRequest & 0x80) != 0x80))
- { /* Check bmRequest : No Data-In stage. 0x80 is Data Direction */
-
- /* The wValue field contains the slot number (bSlot) in the low byte
- and the sequence number (bSeq) in the high byte.*/
- slot_nb = (uint8_t) ((req->wValue) & 0x00ff);
- seq_nb = (uint8_t) (((req->wValue) & 0xff00)>>8);
-
- if ( CCID_CmdAbort(slot_nb, seq_nb) != 0 )
- { /* If error is returned by lower layer :
- Generally Slot# may not have matched */
- USBD_CtlError(pdev , req);
- return USBD_FAIL;
- }
- }
- else
- {
- USBD_CtlError(pdev , req);
- return USBD_FAIL;
- }
- break;
-
- case REQUEST_GET_CLOCK_FREQUENCIES :
- if((req->wValue == 0) &&
- (req->wLength != 0) &&
- ((req->bmRequest & 0x80) == 0x80))
- { /* Check bmRequest : Data-In stage. 0x80 is Data Direction */
-
- if ( SC_Request_GetClockFrequencies(USBD_CCID_EP0_Buff, &len) != 0 )
- { /* If error is returned by lower layer */
- USBD_CtlError(pdev , req);
- return USBD_FAIL;
- }
- else
- {
- if (len > CCID_EP0_BUFF_SIZ)
- {
- len = CCID_EP0_BUFF_SIZ;
- }
-
- USBD_CtlSendData (pdev,
- USBD_CCID_EP0_Buff,
- len);
- }
- }
- else
- {
- USBD_CtlError(pdev , req);
- return USBD_FAIL;
- }
- break;
-
- case REQUEST_GET_DATA_RATES :
- if((req->wValue == 0) &&
- (req->wLength != 0) &&
- ((req->bmRequest & 0x80) == 0x80))
- { /* Check bmRequest : Data-In stage. 0x80 is Data Direction */
-
- if ( SC_Request_GetDataRates(USBD_CCID_EP0_Buff, &len) != 0 )
- { /* If error is returned by lower layer */
- USBD_CtlError(pdev , req);
- return USBD_FAIL;
- }
- else
- {
- if (len > CCID_EP0_BUFF_SIZ)
- {
- len = CCID_EP0_BUFF_SIZ;
- }
-
- USBD_CtlSendData (pdev,
- USBD_CCID_EP0_Buff,
- len);
- }
- }
- else
- {
- USBD_CtlError(pdev , req);
- return USBD_FAIL;
- }
- break;
-
- default:
- USBD_CtlError(pdev , req);
- return USBD_FAIL;
- }
- break;
- /* Interface & Endpoint request */
- case USB_REQ_TYPE_STANDARD:
- switch (req->bRequest)
- {
- case USB_REQ_GET_INTERFACE :
- break;
-
- case USB_REQ_SET_INTERFACE :
- break;
-
- case USB_REQ_CLEAR_FEATURE:
-
- /* Re-activate the EP */
- DCD_EP_Close (pdev , (uint8_t)req->wIndex);
- if((((uint8_t)req->wIndex) & 0x80) == 0x80)
- {
- DCD_EP_Open(pdev,
- ((uint8_t)req->wIndex),
- CCID_BULK_EPIN_SIZE,
- USB_EP_BULK);
- }
- else
- {
- DCD_EP_Open(pdev,
- ((uint8_t)req->wIndex),
- CCID_BULK_EPOUT_SIZE,
- USB_EP_BULK);
- }
-
- break;
-
- }
- break;
-
- default:
- break;
- }
- return USBD_OK;
-}
-
-/**
- * @brief USBD_CCID_DataIn
- * handle data IN Stage
- * @param pdev: device instance
- * @param epnum: endpoint index
- * @retval status
- */
-static uint8_t USBD_CCID_DataIn (void *pdev,
- uint8_t epnum)
-{
- CCID_BulkMessage_In(pdev , epnum);
- return USBD_OK;
-}
-
-/**
- * @brief USBD_CCID_DataOut
- * handle data OUT Stage
- * @param pdev: device instance
- * @param epnum: endpoint index
- * @retval status
- */
-static uint8_t USBD_CCID_DataOut (void *pdev,
- uint8_t epnum)
-{
- CCID_BulkMessage_Out(pdev , epnum);
- return USBD_OK;
-}
-
-/**
- * @brief USBD_CCID_GetCfgDesc
- * return configuration descriptor
- * @param speed : current device speed
- * @param length : pointer data length
- * @retval pointer to descriptor buffer
- */
-static uint8_t *USBD_CCID_GetCfgDesc (uint8_t speed, uint16_t *length)
-{
- *length = sizeof (USBD_CCID_CfgDesc);
- return (uint8_t*)USBD_CCID_CfgDesc;
-}
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/ccid/src/usbd_ccid_if.c b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/ccid/src/usbd_ccid_if.c
deleted file mode 100644
index 2efa3172bfa84f4976c61445bfcadbde0181c354..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/ccid/src/usbd_ccid_if.c
+++ /dev/null
@@ -1,428 +0,0 @@
-/**
- ******************************************************************************
- * @file usbd_ccid_if.c
- * @author MCD Application Team
- * @version V1.0.1
- * @date 31-January-2014
- * @brief This file provides all the functions for USB Interface for CCID
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_ccid_if.h"
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-uint8_t Ccid_BulkState;
-uint8_t UsbIntMessageBuffer[INTR_MAX_PACKET_SIZE]; /* data buffer*/
-__IO uint8_t PrevXferComplete_IntrIn;
-usb_ccid_param_t usb_ccid_param;
-
-uint8_t* pUsbMessageBuffer;
-static uint32_t UsbMessageLength;
-Ccid_bulkin_data_t pCcid_resp_buff;
-Ccid_SlotStatus_t Ccid_SlotStatus;
-
-
-uint8_t BulkOut_Data_Buff[BULK_MAX_PACKET_SIZE] ;
-
-Ccid_bulkin_data_t Ccid_bulkin_data ;
-
-Ccid_bulkout_data_t Ccid_bulkout_data ;
-
-uint8_t UsbIntMessageBuffer[INTR_MAX_PACKET_SIZE] ;
-
-/* Private function prototypes -----------------------------------------------*/
-static void CCID_Response_SendData (USB_CORE_HANDLE *pdev,
- uint8_t* pbuf,
- uint16_t len);
-/* Private function ----------------------------------------------------------*/
-/**
- * @brief CCID_Init
- * Initialize the CCID USB Layer
- * @param pdev: device instance
- * @retval None
- */
-void CCID_Init (USB_CORE_HANDLE *pdev)
-{
- /* CCID Related Initialization */
- CCID_SetIntrTransferStatus(1); /* Transfer Complete Status */
- CCID_UpdSlotChange(1);
- SC_InitParams();
-
- /* Prepare EP to Receive First Cmd */
- DCD_EP_PrepareRx (pdev,
- CCID_BULK_OUT_EP,
- (uint8_t *)&BulkOut_Data_Buff[0],
- CCID_BULK_EPOUT_SIZE);
-}
-
-/**
- * @brief CCID_DeInit
- * Uninitialize the CCID Machine
- * @param pdev: device instance
- * @retval None
- */
-void CCID_DeInit (USB_CORE_HANDLE *pdev)
-{
- Ccid_BulkState = CCID_STATE_IDLE;
-}
-
-/**
- * @brief CCID_Message_In
- * Handle Bulk IN & Intr IN data stage
- * @param pdev: device instance
- * @param uint8_t epnum: endpoint index
- * @retval None
- */
-void CCID_BulkMessage_In (USB_CORE_HANDLE *pdev,
- uint8_t epnum)
-{
- if (epnum == (CCID_BULK_IN_EP & 0x7F))
- {/* Filter the epnum by masking with 0x7f (mask of IN Direction) */
-
- /*************** Handle Bulk Transfer IN data completion *****************/
-
- /* Toggle LED1 */
- STM_EVAL_LEDToggle(LED1);
-
- switch (Ccid_BulkState)
- {
- case CCID_STATE_SEND_RESP:
-
- Ccid_BulkState = CCID_STATE_IDLE;
-
- /* Prepare EP to Receive First Cmd */
- DCD_EP_PrepareRx (pdev,
- CCID_BULK_OUT_EP,
- (uint8_t *)&BulkOut_Data_Buff[0],
- CCID_BULK_EPOUT_SIZE);
-
- break;
-
- default:
- break;
- }
- }
- else if (epnum == (CCID_INTR_IN_EP & 0x7F))
- {
- /* Filter the epnum by masking with 0x7f (mask of IN Direction) */
- CCID_SetIntrTransferStatus(1); /* Transfer Complete Status */
- }
-}
-
-/**
- * @brief CCID_BulkMessage_Out
- * Proccess CCID OUT data
- * @param pdev: device instance
- * @param uint8_t epnum: endpoint index
- * @retval None
- */
-void CCID_BulkMessage_Out (USB_CORE_HANDLE *pdev,
- uint8_t epnum)
-{
- uint16_t dataLen;
- dataLen = USBD_GetRxCount (pdev, CCID_BULK_OUT_EP);
-
- switch (Ccid_BulkState)
- {
- case CCID_STATE_IDLE:
- if (dataLen == 0x00)
- { /* Zero Length Packet Received */
- Ccid_BulkState = CCID_STATE_IDLE;
- }
- else if (dataLen >= CCID_MESSAGE_HEADER_SIZE)
- {
- UsbMessageLength = dataLen; /* Store for future use */
-
- /* Expected Data Length Packet Received */
- pUsbMessageBuffer = (uint8_t*) &Ccid_bulkout_data;
-
- /* Fill CCID_BulkOut Data Buffer from USB Buffer */
- CCID_ReceiveCmdHeader(pUsbMessageBuffer, dataLen);
-
- /*
- Refer : 6 CCID Messages
- The response messages always contain the exact same slot number,
- and sequence number fields from the header that was contained in
- the Bulk-OUT command message.
- */
- Ccid_bulkin_data.bSlot = Ccid_bulkout_data.bSlot;
- Ccid_bulkin_data.bSeq = Ccid_bulkout_data.bSeq;
-
- if (dataLen < CCID_BULK_EPOUT_SIZE)
- {/* Short message, less than the EP Out Size, execute the command,
- if parameter like dwLength is too big, the appropriate command will
- give an error */
- CCID_CmdDecode(pdev);
- }
- else
- { /* Long message, receive additional data with command */
- /* (u8dataLen == CCID_BULK_EPOUT_SIZE) */
-
- if (Ccid_bulkout_data.dwLength > ABDATA_SIZE)
- { /* Check if length of data to be sent by host is > buffer size */
-
- /* Too long data received.... Error ! */
- Ccid_BulkState = CCID_STATE_UNCORRECT_LENGTH;
- }
-
- else
- { /* Expect more data on OUT EP */
- Ccid_BulkState = CCID_STATE_RECEIVE_DATA;
- pUsbMessageBuffer += dataLen; /* Point to new offset */
-
- /* Prepare EP to Receive next Cmd */
- DCD_EP_PrepareRx (pdev,
- CCID_BULK_OUT_EP,
- (uint8_t *)&BulkOut_Data_Buff[0],
- CCID_BULK_EPOUT_SIZE);
-
- } /* if (dataLen == CCID_BULK_EPOUT_SIZE) ends */
- } /* if (dataLen >= CCID_BULK_EPOUT_SIZE) ends */
- } /* if (dataLen >= CCID_MESSAGE_HEADER_SIZE) ends */
- break;
-
- case CCID_STATE_RECEIVE_DATA:
-
- UsbMessageLength += dataLen;
-
- if (dataLen < CCID_BULK_EPOUT_SIZE)
- {/* Short message, less than the EP Out Size, execute the command,
- if parameter like dwLength is too big, the appropriate command will
- give an error */
-
- /* Full command is received, process the Command */
- CCID_ReceiveCmdHeader(pUsbMessageBuffer, dataLen);
- CCID_CmdDecode(pdev);
- }
- else if (dataLen == CCID_BULK_EPOUT_SIZE)
- {
- if (UsbMessageLength < (Ccid_bulkout_data.dwLength + CCID_CMD_HEADER_SIZE))
- {
- CCID_ReceiveCmdHeader(pUsbMessageBuffer, dataLen); /* Copy data */
- pUsbMessageBuffer += dataLen;
- /* Increment the pointer to receive more data */
-
- /* Prepare EP to Receive next Cmd */
- DCD_EP_PrepareRx (pdev,
- CCID_BULK_OUT_EP,
- (uint8_t *)&BulkOut_Data_Buff[0],
- CCID_BULK_EPOUT_SIZE);
- }
- else if (UsbMessageLength == (Ccid_bulkout_data.dwLength + CCID_CMD_HEADER_SIZE))
- {
- /* Full command is received, process the Command */
- CCID_ReceiveCmdHeader(pUsbMessageBuffer, dataLen);
- CCID_CmdDecode(pdev);
- }
- else
- {
- /* Too long data received.... Error ! */
- Ccid_BulkState = CCID_STATE_UNCORRECT_LENGTH;
- }
- }
-
- break;
-
- case CCID_STATE_UNCORRECT_LENGTH:
- Ccid_BulkState = CCID_STATE_IDLE;
- break;
-
- default:
- break;
- }
-}
-
-/**
- * @brief CCID_CmdDecode
- * Parse the commands and Proccess command
- * @param pdev: device instance
- * @retval None
- */
-void CCID_CmdDecode(USB_CORE_HANDLE *pdev)
-{
- uint8_t errorCode;
-
- switch (Ccid_bulkout_data.bMessageType)
- {
- case PC_TO_RDR_ICCPOWERON:
- errorCode = PC_to_RDR_IccPowerOn();
- RDR_to_PC_DataBlock(errorCode);
- break;
- case PC_TO_RDR_ICCPOWEROFF:
- errorCode = PC_to_RDR_IccPowerOff();
- RDR_to_PC_SlotStatus(errorCode);
- break;
- case PC_TO_RDR_GETSLOTSTATUS:
- errorCode = PC_to_RDR_GetSlotStatus();
- RDR_to_PC_SlotStatus(errorCode);
- break;
- case PC_TO_RDR_XFRBLOCK:
- errorCode = PC_to_RDR_XfrBlock();
- RDR_to_PC_DataBlock(errorCode);
- break;
- case PC_TO_RDR_GETPARAMETERS:
- errorCode = PC_to_RDR_GetParameters();
- RDR_to_PC_Parameters(errorCode);
- break;
- case PC_TO_RDR_RESETPARAMETERS:
- errorCode = PC_to_RDR_ResetParameters();
- RDR_to_PC_Parameters(errorCode);
- break;
- case PC_TO_RDR_SETPARAMETERS:
- errorCode = PC_to_RDR_SetParameters();
- RDR_to_PC_Parameters(errorCode);
- break;
- case PC_TO_RDR_ESCAPE:
- errorCode = PC_to_RDR_Escape();
- RDR_to_PC_Escape(errorCode);
- break;
- case PC_TO_RDR_ICCCLOCK:
- errorCode = PC_to_RDR_IccClock();
- RDR_to_PC_SlotStatus(errorCode);
- break;
- case PC_TO_RDR_ABORT:
- errorCode = PC_to_RDR_Abort();
- RDR_to_PC_SlotStatus(errorCode);
- break;
- case PC_TO_RDR_T0APDU:
- errorCode = PC_TO_RDR_T0Apdu();
- RDR_to_PC_SlotStatus(errorCode);
- break;
- case PC_TO_RDR_MECHANICAL:
- errorCode = PC_TO_RDR_Mechanical();
- RDR_to_PC_SlotStatus(errorCode);
- break;
- case PC_TO_RDR_SETDATARATEANDCLOCKFREQUENCY:
- errorCode = PC_TO_RDR_SetDataRateAndClockFrequency();
- RDR_to_PC_DataRateAndClockFrequency(errorCode);
- break;
- case PC_TO_RDR_SECURE:
- errorCode = PC_TO_RDR_Secure();
- RDR_to_PC_DataBlock(errorCode);
- break;
- default:
- RDR_to_PC_SlotStatus(SLOTERROR_CMD_NOT_SUPPORTED);
- break;
- }
-
- /********** Decide for all commands ***************/
- if (Ccid_BulkState == CCID_STATE_SEND_RESP)
- {
- CCID_Response_SendData(pdev, (uint8_t*)&Ccid_bulkin_data,
- Ccid_bulkin_data.u16SizeToSend);
- }
-}
-
-/**
- * @brief Transfer_Data_Request
- * Prepare the request response to be sent to the host
- * @param uint8_t* dataPointer: Pointer to the data buffer to send
- * @param uint16_t dataLen : number of bytes to send
- * @retval None
- */
-void Transfer_Data_Request(uint8_t* dataPointer, uint16_t dataLen)
-{
- /********** Update Global Variables ***************/
- Ccid_bulkin_data.u16SizeToSend = dataLen;
- Ccid_BulkState = CCID_STATE_SEND_RESP;
-}
-
-
-/**
- * @brief CCID_Response_SendData
- * Send the data on bulk-in EP
- * @param pdev: device instance
- * @param uint8_t* buf: pointer to data buffer
- * @param uint16_t len: Data Length
- * @retval None
- */
-static void CCID_Response_SendData(USB_CORE_HANDLE *pdev,
- uint8_t* buf,
- uint16_t len)
-{
- DCD_EP_Tx (pdev, CCID_BULK_IN_EP, buf, len);
-}
-
-/**
- * @brief CCID_IntMessage
- * Send the Interrupt-IN data to the host
- * @param pdev: device instance
- * @retval None
- */
-void CCID_IntMessage(USB_CORE_HANDLE *pdev)
-{
- /* Check if there us change in Smartcard Slot status */
- if ( CCID_IsSlotStatusChange() && CCID_IsIntrTransferComplete() )
- {
- /* Check Slot Status is changed. Card is Removed/ Fitted */
- RDR_to_PC_NotifySlotChange();
-
- CCID_SetIntrTransferStatus(0); /* Reset the Status */
- CCID_UpdSlotChange(0); /* Reset the Status of Slot Change */
-
- DCD_EP_Tx (pdev, CCID_INTR_IN_EP, UsbIntMessageBuffer, 2);
- }
-}
-
-/**
- * @brief CCID_ReceiveCmdHeader
- * Receive the Data from USB BulkOut Buffer to Pointer
- * @param uint8_t* pDst: destination address to copy the buffer
- * @param uint8_t u8length: length of data to copy
- * @retval None
- */
-void CCID_ReceiveCmdHeader(uint8_t* pDst, uint8_t u8length)
-{
- uint32_t Counter;
-
- for (Counter = 0; Counter < u8length; Counter++)
- {
- *pDst++ = BulkOut_Data_Buff[Counter];
- }
-
-}
-
-/**
- * @brief CCID_IsIntrTransferComplete
- * Provides the status of previous Interrupt transfer status
- * @param None
- * @retval uint8_t PrevXferComplete_IntrIn: Value of the previous transfer status
- */
-uint8_t CCID_IsIntrTransferComplete (void)
-{
- return PrevXferComplete_IntrIn;
-}
-
-/**
- * @brief CCID_IsIntrTransferComplete
- * Set the value of the Interrupt transfer status
- * @param uint8_t xfer_Status: Value of the Interrupt transfer status to set
- * @retval None
- */
-void CCID_SetIntrTransferStatus (uint8_t xfer_Status)
-{
- PrevXferComplete_IntrIn = xfer_Status;
-}
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/cdc/inc/usbd_cdc_core.h b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/cdc/inc/usbd_cdc_core.h
deleted file mode 100644
index c71b0a31018a37a5f881ab950271bb103d00002b..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/cdc/inc/usbd_cdc_core.h
+++ /dev/null
@@ -1,95 +0,0 @@
-/**
- ******************************************************************************
- * @file usbd_cdc_core.h
- * @author MCD Application Team
- * @version V1.0.1
- * @date 31-January-2014
- * @brief header file for the usbd_cdc_core.c file.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __USB_CDC_CORE_H_
-#define __USB_CDC_CORE_H_
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_desc.h"
-
-/* Exported defines ----------------------------------------------------------*/
-
-#define USB_CDC_CONFIG_DESC_SIZ (67)
-#define USB_CDC_DESC_SIZ (67-9)
-
-#define CDC_DESCRIPTOR_TYPE 0x21
-
-#define DEVICE_CLASS_CDC 0x02
-#define DEVICE_SUBCLASS_CDC 0x00
-
-
-#define USB_DEVICE_DESCRIPTOR_TYPE 0x01
-#define USB_CONFIGURATION_DESCRIPTOR_TYPE 0x02
-#define USB_STRING_DESCRIPTOR_TYPE 0x03
-#define USB_INTERFACE_DESCRIPTOR_TYPE 0x04
-#define USB_ENDPOINT_DESCRIPTOR_TYPE 0x05
-
-#define STANDARD_ENDPOINT_DESC_SIZE 0x09
-
-#define CDC_DATA_IN_PACKET_SIZE CDC_DATA_MAX_PACKET_SIZE
-
-#define CDC_DATA_OUT_PACKET_SIZE CDC_DATA_MAX_PACKET_SIZE
-
-/*---------------------------------------------------------------------*/
-/* CDC definitions */
-/*---------------------------------------------------------------------*/
-
-/**************************************************/
-/* CDC Requests */
-/**************************************************/
-#define SEND_ENCAPSULATED_COMMAND 0x00
-#define GET_ENCAPSULATED_RESPONSE 0x01
-#define SET_COMM_FEATURE 0x02
-#define GET_COMM_FEATURE 0x03
-#define CLEAR_COMM_FEATURE 0x04
-#define SET_LINE_CODING 0x20
-#define GET_LINE_CODING 0x21
-#define SET_CONTROL_LINE_STATE 0x22
-#define SEND_BREAK 0x23
-#define NO_CMD 0xFF
-
-/* Exported types ------------------------------------------------------------*/
-typedef struct _CDC_IF_PROP
-{
- uint16_t (*pIf_Init) (void);
- uint16_t (*pIf_DeInit) (void);
- uint16_t (*pIf_Ctrl) (uint32_t Cmd, uint8_t* Buf, uint32_t Len);
- uint16_t (*pIf_DataTx) (uint8_t* Buf, uint32_t Len);
- uint16_t (*pIf_DataRx) (uint8_t* Buf, uint32_t Len);
-}
-CDC_IF_Prop_TypeDef;
-
-/* Exported macros -----------------------------------------------------------*/
-/* Exported variables --------------------------------------------------------*/
-extern USBD_Class_cb_TypeDef USBD_CDC_cb;
-
-/* Exported functions ------------------------------------------------------- */
-
-#endif /* __USB_CDC_CORE_H_ */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/cdc/inc/usbd_cdc_if_template.h b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/cdc/inc/usbd_cdc_if_template.h
deleted file mode 100644
index 7cc95ef63bfa942cc0fcf245a8366c1ca9eabaad..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/cdc/inc/usbd_cdc_if_template.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/**
- ******************************************************************************
- * @file usbd_cdc_if_template.h
- * @author MCD Application Team
- * @version V1.0.1
- * @date 31-January-2014
- * @brief Header for usbd_cdc_if_template.c file.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __USBD_CDC_IF_TEMPLATE_H
-#define __USBD_CDC_IF_TEMPLATE_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "usb_conf.h"
-#include "usbd_conf.h"
-#include "usbd_cdc_core.h"
-
-/* Exported defines ----------------------------------------------------------*/
-/* Exported types ------------------------------------------------------------*/
-/* Exported macros -----------------------------------------------------------*/
-/* Exported variables --------------------------------------------------------*/
-extern CDC_IF_Prop_TypeDef TEMPLATE_fops;
-
-/* Exported functions ------------------------------------------------------- */
-
-#endif /* __USBD_CDC_IF_TEMPLATE_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/cdc/src/usbd_cdc_core.c b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/cdc/src/usbd_cdc_core.c
deleted file mode 100644
index cca11347a558ec984a627dfacc2be954011e4785..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/cdc/src/usbd_cdc_core.c
+++ /dev/null
@@ -1,600 +0,0 @@
-/**
- ******************************************************************************
- * @file usbd_cdc_core.c
- * @author MCD Application Team
- * @version V1.0.1
- * @date 31-January-2014
- * @brief This file provides the high layer firmware functions to manage the
- * following functionalities of the USB CDC Class:
- * - Initialization and Configuration of high and low layer
- * - Enumeration as CDC Device (and enumeration for each implemented memory interface)
- * - OUT/IN data transfer
- * - Command IN transfer (class requests management)
- * - Error management
- *
- * @verbatim
- *
- * ===================================================================
- * CDC Class Driver Description
- * ===================================================================
- * This driver manages the "Universal Serial Bus Class Definitions for Communications Devices
- * Revision 1.2 November 16, 2007" and the sub-protocol specification of "Universal Serial Bus
- * Communications Class Subclass Specification for PSTN Devices Revision 1.2 February 9, 2007"
- * This driver implements the following aspects of the specification:
- * - Device descriptor management
- * - Configuration descriptor management
- * - Enumeration as CDC device with 2 data endpoints (IN and OUT) and 1 command endpoint (IN)
- * - Requests management (as described in section 6.2 in specification)
- * - Abstract Control Model compliant
- * - Union Functional collection (using 1 IN endpoint for control)
- * - Data interface class
-
- * @note
- * For the Abstract Control Model, this core allows only transmitting the requests to
- * lower layer dispatcher (ie. usbd_cdc_vcp.c/.h) which should manage each request and
- * perform relative actions.
- *
- * These aspects may be enriched or modified for a specific user application.
- *
- * This driver doesn't implement the following aspects of the specification
- * (but it is possible to manage these features with some modifications on this driver):
- * - Any class-specific aspect relative to communication classes should be managed by user application.
- * - All communication classes other than PSTN are not managed
- *
- * @endverbatim
- *
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_cdc_core.h"
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-
-/*********************************************
- CDC Device library callbacks
- *********************************************/
-uint8_t usbd_cdc_Init (void *pdev, uint8_t cfgidx);
-uint8_t usbd_cdc_DeInit (void *pdev, uint8_t cfgidx);
-uint8_t usbd_cdc_Setup (void *pdev, USB_SETUP_REQ *req);
-uint8_t usbd_cdc_EP0_RxReady (void *pdev);
-uint8_t usbd_cdc_DataIn (void *pdev, uint8_t epnum);
-uint8_t usbd_cdc_DataOut (void *pdev, uint8_t epnum);
-uint8_t usbd_cdc_SOF (void *pdev);
-
-/*********************************************
- CDC specific management functions
- *********************************************/
-static void Handle_USBAsynchXfer (void *pdev);
-static uint8_t *USBD_cdc_GetCfgDesc (uint8_t speed, uint16_t *length);
-
-extern CDC_IF_Prop_TypeDef APP_FOPS;
-extern uint8_t USBD_DeviceDesc [USB_SIZ_DEVICE_DESC];
-
-uint8_t usbd_cdc_OtherCfgDesc [USB_CDC_CONFIG_DESC_SIZ] ;
-
-static __IO uint32_t usbd_cdc_AltSet = 0;
-
-uint8_t USB_Rx_Buffer [CDC_DATA_MAX_PACKET_SIZE] ;
-
-uint8_t APP_Rx_Buffer [APP_RX_DATA_SIZE] ;
-
-uint8_t CmdBuff[CDC_CMD_PACKET_SZE] ;
-__IO uint32_t last_packet = 0;
-uint32_t APP_Rx_ptr_in = 0;
-uint32_t APP_Rx_ptr_out = 0;
-uint32_t APP_Rx_length = 0;
-
-uint8_t USB_Tx_State = 0;
-
-static uint32_t cdcCmd = 0xFF;
-static uint32_t cdcLen = 0;
-
-/* CDC interface class callbacks structure */
-USBD_Class_cb_TypeDef USBD_CDC_cb =
-{
- usbd_cdc_Init,
- usbd_cdc_DeInit,
- usbd_cdc_Setup,
- NULL, /* EP0_TxSent, */
- usbd_cdc_EP0_RxReady,
- usbd_cdc_DataIn,
- usbd_cdc_DataOut,
- usbd_cdc_SOF,
- USBD_cdc_GetCfgDesc,
-};
-
-/* USB CDC device Configuration Descriptor */
-const uint8_t usbd_cdc_CfgDesc[USB_CDC_CONFIG_DESC_SIZ] =
-{
- /*Configuration Descriptor*/
- 0x09, /* bLength: Configuration Descriptor size */
- USB_CONFIGURATION_DESCRIPTOR_TYPE, /* bDescriptorType: Configuration */
- USB_CDC_CONFIG_DESC_SIZ, /* wTotalLength:no of returned bytes */
- 0x00,
- 0x02, /* bNumInterfaces: 2 interface */
- 0x01, /* bConfigurationValue: Configuration value */
- 0x00, /* iConfiguration: Index of string descriptor describing the configuration */
- 0xC0, /* bmAttributes: self powered */
- 0x32, /* MaxPower 0 mA */
-
- /*---------------------------------------------------------------------------*/
-
- /*Interface Descriptor */
- 0x09, /* bLength: Interface Descriptor size */
- USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType: Interface */
- /* Interface descriptor type */
- 0x00, /* bInterfaceNumber: Number of Interface */
- 0x00, /* bAlternateSetting: Alternate setting */
- 0x01, /* bNumEndpoints: One endpoints used */
- 0x02, /* bInterfaceClass: Communication Interface Class */
- 0x02, /* bInterfaceSubClass: Abstract Control Model */
- 0x01, /* bInterfaceProtocol: Common AT commands */
- 0x00, /* iInterface: */
-
- /*Header Functional Descriptor*/
- 0x05, /* bLength: Endpoint Descriptor size */
- 0x24, /* bDescriptorType: CS_INTERFACE */
- 0x00, /* bDescriptorSubtype: Header Func Desc */
- 0x10, /* bcdCDC: spec release number */
- 0x01,
-
- /*Call Management Functional Descriptor*/
- 0x05, /* bFunctionLength */
- 0x24, /* bDescriptorType: CS_INTERFACE */
- 0x01, /* bDescriptorSubtype: Call Management Func Desc */
- 0x00, /* bmCapabilities: D0+D1 */
- 0x01, /* bDataInterface: 1 */
-
- /*ACM Functional Descriptor*/
- 0x04, /* bFunctionLength */
- 0x24, /* bDescriptorType: CS_INTERFACE */
- 0x02, /* bDescriptorSubtype: Abstract Control Management desc */
- 0x02, /* bmCapabilities */
-
- /*Union Functional Descriptor*/
- 0x05, /* bFunctionLength */
- 0x24, /* bDescriptorType: CS_INTERFACE */
- 0x06, /* bDescriptorSubtype: Union func desc */
- 0x00, /* bMasterInterface: Communication class interface */
- 0x01, /* bSlaveInterface0: Data Class Interface */
-
- /*Endpoint 2 Descriptor*/
- 0x07, /* bLength: Endpoint Descriptor size */
- USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: Endpoint */
- CDC_CMD_EP, /* bEndpointAddress */
- 0x03, /* bmAttributes: Interrupt */
- LOBYTE(CDC_CMD_PACKET_SZE), /* wMaxPacketSize: */
- HIBYTE(CDC_CMD_PACKET_SZE),
- 0xFF, /* bInterval: */
-
- /*---------------------------------------------------------------------------*/
-
- /*Data class interface descriptor*/
- 0x09, /* bLength: Endpoint Descriptor size */
- USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType: */
- 0x01, /* bInterfaceNumber: Number of Interface */
- 0x00, /* bAlternateSetting: Alternate setting */
- 0x02, /* bNumEndpoints: Two endpoints used */
- 0x0A, /* bInterfaceClass: CDC */
- 0x00, /* bInterfaceSubClass: */
- 0x00, /* bInterfaceProtocol: */
- 0x00, /* iInterface: */
-
- /*Endpoint OUT Descriptor*/
- 0x07, /* bLength: Endpoint Descriptor size */
- USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: Endpoint */
- CDC_OUT_EP, /* bEndpointAddress */
- 0x02, /* bmAttributes: Bulk */
- LOBYTE(CDC_DATA_MAX_PACKET_SIZE), /* wMaxPacketSize: */
- HIBYTE(CDC_DATA_MAX_PACKET_SIZE),
- 0x00, /* bInterval: ignore for Bulk transfer */
-
- /*Endpoint IN Descriptor*/
- 0x07, /* bLength: Endpoint Descriptor size */
- USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: Endpoint */
- CDC_IN_EP, /* bEndpointAddress */
- 0x02, /* bmAttributes: Bulk */
- LOBYTE(CDC_DATA_MAX_PACKET_SIZE), /* wMaxPacketSize: */
- HIBYTE(CDC_DATA_MAX_PACKET_SIZE),
- 0x00 /* bInterval: ignore for Bulk transfer */
-} ;
-
-/* Private function ----------------------------------------------------------*/
-/**
- * @brief usbd_cdc_Init
- * Initialize the CDC interface
- * @param pdev: device instance
- * @param cfgidx: Configuration index
- * @retval status
- */
-uint8_t usbd_cdc_Init (void *pdev,
- uint8_t cfgidx)
-{
- DCD_PMA_Config(pdev , CDC_IN_EP,USB_SNG_BUF,BULK_IN_TX_ADDRESS);
- DCD_PMA_Config(pdev , CDC_CMD_EP,USB_SNG_BUF,INT_IN_TX_ADDRESS);
- DCD_PMA_Config(pdev , CDC_OUT_EP,USB_SNG_BUF,BULK_OUT_RX_ADDRESS);
-
- /* Open EP IN */
- DCD_EP_Open(pdev,
- CDC_IN_EP,
- CDC_DATA_IN_PACKET_SIZE,
- USB_EP_BULK);
-
- /* Open EP OUT */
- DCD_EP_Open(pdev,
- CDC_OUT_EP,
- CDC_DATA_OUT_PACKET_SIZE,
- USB_EP_BULK);
-
- /* Open Command IN EP */
- DCD_EP_Open(pdev,
- CDC_CMD_EP,
- CDC_CMD_PACKET_SZE,
- USB_EP_INT);
-
-
-
- /* Initialize the Interface physical components */
- APP_FOPS.pIf_Init();
-
- /* Prepare Out endpoint to receive next packet */
- DCD_EP_PrepareRx(pdev,
- CDC_OUT_EP,
- (uint8_t*)(USB_Rx_Buffer),
- CDC_DATA_OUT_PACKET_SIZE);
-
- return USBD_OK;
-}
-
-/**
- * @brief usbd_cdc_Init
- * DeInitialize the CDC layer
- * @param pdev: device instance
- * @param cfgidx: Configuration index
- * @retval status
- */
-uint8_t usbd_cdc_DeInit (void *pdev,
- uint8_t cfgidx)
-{
- /* Open EP IN */
- DCD_EP_Close(pdev,
- CDC_IN_EP);
-
- /* Open EP OUT */
- DCD_EP_Close(pdev,
- CDC_OUT_EP);
-
- /* Open Command IN EP */
- DCD_EP_Close(pdev,
- CDC_CMD_EP);
-
- /* Restore default state of the Interface physical components */
- APP_FOPS.pIf_DeInit();
-
- return USBD_OK;
-}
-
-/**
- * @brief usbd_cdc_Setup
- * Handle the CDC specific requests
- * @param pdev: instance
- * @param req: usb requests
- * @retval status
- */
-uint8_t usbd_cdc_Setup (void *pdev,
- USB_SETUP_REQ *req)
-{
- uint16_t len=USB_CDC_DESC_SIZ;
- uint8_t *pbuf= (uint8_t*)usbd_cdc_CfgDesc + 9;
-
- switch (req->bmRequest & USB_REQ_TYPE_MASK)
- {
- /* CDC Class Requests -------------------------------*/
- case USB_REQ_TYPE_CLASS :
- /* Check if the request is a data setup packet */
- if (req->wLength)
- {
- /* Check if the request is Device-to-Host */
- if (req->bmRequest & 0x80)
- {
- /* Get the data to be sent to Host from interface layer */
- APP_FOPS.pIf_Ctrl(req->bRequest, CmdBuff, req->wLength);
-
- /* Send the data to the host */
- USBD_CtlSendData (pdev,
- CmdBuff,
- req->wLength);
- }
- else /* Host-to-Device requeset */
- {
- /* Set the value of the current command to be processed */
- cdcCmd = req->bRequest;
- cdcLen = req->wLength;
-
- /* Prepare the reception of the buffer over EP0
- Next step: the received data will be managed in usbd_cdc_EP0_TxSent()
- function. */
- USBD_CtlPrepareRx (pdev,
- CmdBuff,
- req->wLength);
- }
- }
- else /* No Data request */
- {
- /* Transfer the command to the interface layer */
- APP_FOPS.pIf_Ctrl(req->bRequest, NULL, 0);
- }
-
- return USBD_OK;
-
- default:
- USBD_CtlError (pdev, req);
- return USBD_FAIL;
-
-
-
- /* Standard Requests -------------------------------*/
- case USB_REQ_TYPE_STANDARD:
- switch (req->bRequest)
- {
- case USB_REQ_GET_DESCRIPTOR:
- if( (req->wValue >> 8) == CDC_DESCRIPTOR_TYPE)
- {
- pbuf = (uint8_t*)usbd_cdc_CfgDesc + 9 + (9 * USBD_ITF_MAX_NUM);
- len = MIN(USB_CDC_DESC_SIZ , req->wLength);
- }
-
- USBD_CtlSendData (pdev,
- pbuf,
- len);
- break;
-
- case USB_REQ_GET_INTERFACE :
- USBD_CtlSendData (pdev,
- (uint8_t *)&usbd_cdc_AltSet,
- 1);
- break;
-
- case USB_REQ_SET_INTERFACE :
- if ((uint8_t)(req->wValue) < USBD_ITF_MAX_NUM)
- {
- usbd_cdc_AltSet = (uint8_t)(req->wValue);
- }
- else
- {
- /* Call the error management function (command will be nacked */
- USBD_CtlError (pdev, req);
- }
- break;
- }
- }
- return USBD_OK;
-}
-
-/**
- * @brief usbd_cdc_EP0_RxReady
- * Data received on control endpoint
- * @param pdev: device device instance
- * @retval status
- */
-uint8_t usbd_cdc_EP0_RxReady (void *pdev)
-{
- if (cdcCmd != NO_CMD)
- {
- /* Process the data */
- APP_FOPS.pIf_Ctrl(cdcCmd, CmdBuff, cdcLen);
-
- /* Reset the command variable to default value */
- cdcCmd = NO_CMD;
- }
-
- return USBD_OK;
-}
-
-/**
- * @brief usbd_audio_DataIn
- * Data sent on non-control IN endpoint
- * @param pdev: device instance
- * @param epnum: endpoint number
- * @retval status
- */
-uint8_t usbd_cdc_DataIn (void *pdev, uint8_t epnum)
-{
- uint16_t USB_Tx_ptr;
- uint16_t USB_Tx_length;
-
- if (USB_Tx_State == 1)
- {
- if (APP_Rx_length == 0)
- {
- if (last_packet ==1)
- {
- last_packet =0;
-
- /*Send zero-length packet*/
- DCD_EP_Tx (pdev, CDC_IN_EP, 0, 0);
- }
- else
- {
- USB_Tx_State = 0;
- }
- }
- else
- {
- if (APP_Rx_length > CDC_DATA_IN_PACKET_SIZE){
- USB_Tx_ptr = APP_Rx_ptr_out;
- USB_Tx_length = CDC_DATA_IN_PACKET_SIZE;
-
- APP_Rx_ptr_out += CDC_DATA_IN_PACKET_SIZE;
- APP_Rx_length -= CDC_DATA_IN_PACKET_SIZE;
- }
- else
- {
- USB_Tx_ptr = APP_Rx_ptr_out;
- USB_Tx_length = APP_Rx_length;
-
- APP_Rx_ptr_out += APP_Rx_length;
- APP_Rx_length = 0;
- if (APP_Rx_length == CDC_DATA_IN_PACKET_SIZE) last_packet = 1;
- }
-
- /* Prepare the available data buffer to be sent on IN endpoint */
- DCD_EP_Tx (pdev,
- CDC_IN_EP,
- (uint8_t*)&APP_Rx_Buffer[USB_Tx_ptr],
- USB_Tx_length);
- }
- }
-
- return USBD_OK;
-}
-
-/**
- * @brief usbd_cdc_DataOut
- * Data received on non-control Out endpoint
- * @param pdev: device instance
- * @param epnum: endpoint number
- * @retval status
- */
-uint8_t usbd_cdc_DataOut (void *pdev, uint8_t epnum)
-{
- uint16_t USB_Rx_Cnt;
-
- /* Get the received data buffer and update the counter */
- USB_Rx_Cnt = ((USB_CORE_HANDLE*)pdev)->dev.out_ep[epnum].xfer_count;
-
- /* USB data will be immediately processed, this allow next USB traffic being
- NAKed till the end of the application Xfer */
- APP_FOPS.pIf_DataRx(USB_Rx_Buffer, USB_Rx_Cnt);
-
- /* Prepare Out endpoint to receive next packet */
- DCD_EP_PrepareRx(pdev,
- CDC_OUT_EP,
- (uint8_t*)(USB_Rx_Buffer),
- CDC_DATA_OUT_PACKET_SIZE);
-
- return USBD_OK;
-}
-
-/**
- * @brief usbd_CDC_SOF
- * Start Of Frame event management
- * @param pdev: instance
- * @param epnum: endpoint number
- * @retval status
- */
-uint8_t usbd_cdc_SOF (void *pdev)
-{
- static uint32_t FrameCount = 0;
-
- if (FrameCount++ == CDC_IN_FRAME_INTERVAL)
- {
- /* Reset the frame counter */
- FrameCount = 0;
-
- /* Check the data to be sent through IN pipe */
- Handle_USBAsynchXfer(pdev);
- }
-
- return USBD_OK;
-}
-
-/**
- * @brief Handle_USBAsynchXfer
- * Send data to USB
- * @param pdev: instance
- * @retval None
- */
-static void Handle_USBAsynchXfer (void *pdev)
-{
- uint16_t USB_Tx_ptr;
- uint16_t USB_Tx_length;
-
- if(USB_Tx_State != 1)
- {
- if (APP_Rx_ptr_out == APP_RX_DATA_SIZE)
- {
- APP_Rx_ptr_out = 0;
- }
-
- if(APP_Rx_ptr_out == APP_Rx_ptr_in)
- {
- USB_Tx_State = 0;
- return;
- }
-
- if(APP_Rx_ptr_out > APP_Rx_ptr_in) /* rollback */
- {
- APP_Rx_length = APP_RX_DATA_SIZE - APP_Rx_ptr_out;
-
- }
- else
- {
- APP_Rx_length = APP_Rx_ptr_in - APP_Rx_ptr_out;
-
- }
-
- if (APP_Rx_length > CDC_DATA_IN_PACKET_SIZE)
- {
- USB_Tx_ptr = APP_Rx_ptr_out;
- USB_Tx_length = CDC_DATA_IN_PACKET_SIZE;
-
- APP_Rx_ptr_out += CDC_DATA_IN_PACKET_SIZE;
- APP_Rx_length -= CDC_DATA_IN_PACKET_SIZE;
- }
- else
- {
- USB_Tx_ptr = APP_Rx_ptr_out;
- USB_Tx_length = APP_Rx_length;
-
- APP_Rx_ptr_out += APP_Rx_length;
- APP_Rx_length = 0;
- if (USB_Tx_length == CDC_DATA_IN_PACKET_SIZE) last_packet = 1; //IBA
- if (APP_Rx_ptr_in == 64) APP_Rx_ptr_in=0;
- }
- USB_Tx_State = 1;
-
- DCD_EP_Tx (pdev,
- CDC_IN_EP,
- (uint8_t*)&APP_Rx_Buffer[USB_Tx_ptr],
- USB_Tx_length);
- }
-
-}
-
-/**
- * @brief USBD_cdc_GetCfgDesc
- * Return configuration descriptor
- * @param speed : current device speed
- * @param length : pointer data length
- * @retval pointer to descriptor buffer
- */
-static uint8_t *USBD_cdc_GetCfgDesc (uint8_t speed, uint16_t *length)
-{
- *length = sizeof (usbd_cdc_CfgDesc);
- return (uint8_t*)usbd_cdc_CfgDesc;
-}
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/cdc/src/usbd_cdc_if_template.c b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/cdc/src/usbd_cdc_if_template.c
deleted file mode 100644
index 76ddec55b62d697d9742ae634782d83c4d0f4927..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/cdc/src/usbd_cdc_if_template.c
+++ /dev/null
@@ -1,203 +0,0 @@
-/**
- ******************************************************************************
- * @file usbd_cdc_if_template.c
- * @author MCD Application Team
- * @version V1.0.1
- * @date 31-January-2014
- * @brief Generic media access Layer.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_cdc_if_template.h"
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* These are external variables imported from CDC core to be used for IN
- transfer management. */
-extern uint8_t APP_Rx_Buffer []; /* Write CDC received data in this buffer.
- These data will be sent over USB IN endpoint
- in the CDC core functions. */
-extern uint32_t APP_Rx_ptr_in; /* Increment this pointer or roll it back to
- start address when writing received data
- in the buffer APP_Rx_Buffer. */
-
-/* Private function prototypes -----------------------------------------------*/
-static uint16_t TEMPLATE_Init (void);
-static uint16_t TEMPLATE_DeInit (void);
-static uint16_t TEMPLATE_Ctrl (uint32_t Cmd, uint8_t* Buf, uint32_t Len);
-static uint16_t TEMPLATE_DataTx (uint8_t* Buf, uint32_t Len);
-static uint16_t TEMPLATE_DataRx (uint8_t* Buf, uint32_t Len);
-
-CDC_IF_Prop_TypeDef TEMPLATE_fops =
-{
- TEMPLATE_Init,
- TEMPLATE_DeInit,
- TEMPLATE_Ctrl,
- TEMPLATE_DataTx,
- TEMPLATE_DataRx
-};
-
-/* Private functions ---------------------------------------------------------*/
-
-/**
- * @brief TEMPLATE_Init
- * Initializes the CDC media low layer
- * @param None
- * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL
- */
-static uint16_t TEMPLATE_Init(void)
-{
- /*
- Add your initialization code here
- */
- return USBD_OK;
-}
-
-/**
- * @brief TEMPLATE_DeInit
- * DeInitializes the CDC media low layer
- * @param None
- * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL
- */
-static uint16_t TEMPLATE_DeInit(void)
-{
- /*
- Add your deinitialization code here
- */
- return USBD_OK;
-}
-
-
-/**
- * @brief TEMPLATE_Ctrl
- * Manage the CDC class requests
- * @param Cmd: Command code
- * @param Buf: Buffer containing command data (request parameters)
- * @param Len: Number of data to be sent (in bytes)
- * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL
- */
-static uint16_t TEMPLATE_Ctrl (uint32_t Cmd, uint8_t* Buf, uint32_t Len)
-{
- switch (Cmd)
- {
- case SEND_ENCAPSULATED_COMMAND:
- /* Add your code here */
- break;
-
- case GET_ENCAPSULATED_RESPONSE:
- /* Add your code here */
- break;
-
- case SET_COMM_FEATURE:
- /* Add your code here */
- break;
-
- case GET_COMM_FEATURE:
- /* Add your code here */
- break;
-
- case CLEAR_COMM_FEATURE:
- /* Add your code here */
- break;
-
- case SET_LINE_CODING:
- /* Add your code here */
- break;
-
- case GET_LINE_CODING:
- /* Add your code here */
- break;
-
- case SET_CONTROL_LINE_STATE:
- /* Add your code here */
- break;
-
- case SEND_BREAK:
- /* Add your code here */
- break;
-
- default:
- break;
- }
-
- return USBD_OK;
-}
-
-/**
- * @brief TEMPLATE_DataTx
- * CDC received data to be send over USB IN endpoint are managed in
- * this function.
- * @param Buf: Buffer of data to be sent
- * @param Len: Number of data to be sent (in bytes)
- * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL
- */
-static uint16_t TEMPLATE_DataTx (uint8_t* Buf, uint32_t Len)
-{
-
- /* Get the data to be sent */
- for (i = 0; i < Len; i++)
- {
- /* APP_Rx_Buffer[APP_Rx_ptr_in] = XXX_ReceiveData(XXX); */
- }
-
- /* Increment the in pointer */
- APP_Rx_ptr_in++;
-
- /* To avoid buffer overflow */
- if(APP_Rx_ptr_in == APP_RX_DATA_SIZE)
- {
- APP_Rx_ptr_in = 0;
- }
-
- return USBD_OK;
-}
-
-/**
- * @brief TEMPLATE_DataRx
- * Data received over USB OUT endpoint are sent over CDC interface
- * through this function.
- *
- * @note
- * This function will block any OUT packet reception on USB endpoint
- * untill exiting this function. If you exit this function before transfer
- * is complete on CDC interface (ie. using DMA controller) it will result
- * in receiving more data while previous ones are still not sent.
- *
- * @param Buf: Buffer of data to be received
- * @param Len: Number of data received (in bytes)
- * @retval Result of the operation: USBD_OK if all operations are OK else USBD_FAIL
- */
-static uint16_t TEMPLATE_DataRx (uint8_t* Buf, uint32_t Len)
-{
- uint32_t i;
-
- /* Send the received buffer */
- for (i = 0; i < Len; i++)
- {
- /* XXXX_SendData(XXXX, *(Buf + i) ); */
- }
-
- return USBD_OK;
-}
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/dfu/inc/usbd_dfu_core.h b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/dfu/inc/usbd_dfu_core.h
deleted file mode 100644
index 56bb040889f2fa6303f1b43ca777b7c6d0cf1668..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/dfu/inc/usbd_dfu_core.h
+++ /dev/null
@@ -1,142 +0,0 @@
-/**
- ******************************************************************************
- * @file usbd_dfu_core.h
- * @author MCD Application Team
- * @version V1.0.1
- * @date 31-January-2014
- * @brief header file for the usbd_dfu_core.c file.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __USB_DFU_CORE_H_
-#define __USB_DFU_CORE_H_
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_dfu_mal.h"
-#include "usbd_req.h"
-
-/* Exported defines ----------------------------------------------------------*/
-#define USB_DFU_CONFIG_DESC_SIZ (18 + (9 * USBD_ITF_MAX_NUM))
-#define USB_DFU_DESC_SIZ 9
-
-#define DFU_DESCRIPTOR_TYPE 0x21
-
-
-/*---------------------------------------------------------------------*/
-/* DFU definitions */
-/*---------------------------------------------------------------------*/
-/**************************************************/
-/* DFU Requests DFU states */
-/**************************************************/
-
-
-#define STATE_appIDLE 0x00
-#define STATE_appDETACH 0x01
-#define STATE_dfuIDLE 0x02
-#define STATE_dfuDNLOAD_SYNC 0x03
-#define STATE_dfuDNBUSY 0x04
-#define STATE_dfuDNLOAD_IDLE 0x05
-#define STATE_dfuMANIFEST_SYNC 0x06
-#define STATE_dfuMANIFEST 0x07
-#define STATE_dfuMANIFEST_WAIT_RESET 0x08
-#define STATE_dfuUPLOAD_IDLE 0x09
-#define STATE_dfuERROR 0x0A
-
-/**************************************************/
-/* DFU Requests DFU status */
-/**************************************************/
-
-#define STATUS_OK 0x00
-#define STATUS_ERRTARGET 0x01
-#define STATUS_ERRFILE 0x02
-#define STATUS_ERRWRITE 0x03
-#define STATUS_ERRERASE 0x04
-#define STATUS_ERRCHECK_ERASED 0x05
-#define STATUS_ERRPROG 0x06
-#define STATUS_ERRVERIFY 0x07
-#define STATUS_ERRADDRESS 0x08
-#define STATUS_ERRNOTDONE 0x09
-#define STATUS_ERRFIRMWARE 0x0A
-#define STATUS_ERRVENDOR 0x0B
-#define STATUS_ERRUSBR 0x0C
-#define STATUS_ERRPOR 0x0D
-#define STATUS_ERRUNKNOWN 0x0E
-#define STATUS_ERRSTALLEDPKT 0x0F
-
-/**************************************************/
-/* DFU Requests DFU states Manifestation State */
-/**************************************************/
-
-#define Manifest_complete 0x00
-#define Manifest_In_Progress 0x01
-
-
-/**************************************************/
-/* Special Commands with Download Request */
-/**************************************************/
-
-#define CMD_GETCOMMANDS 0x00
-#define CMD_SETADDRESSPOINTER 0x21
-#define CMD_ERASE 0x41
-
-/**************************************************/
-/* Other defines */
-/**************************************************/
-/* Bit Detach capable = bit 3 in bmAttributes field */
-#define DFU_DETACH_MASK (uint8_t)(1 << 4)
-
-/* Exported types ------------------------------------------------------------*/
-/**************************************************/
-/* DFU Requests */
-/**************************************************/
-
-typedef enum _DFU_REQUESTS {
- DFU_DETACH = 0,
- DFU_DNLOAD = 1,
- DFU_UPLOAD,
- DFU_GETSTATUS,
- DFU_CLRSTATUS,
- DFU_GETSTATE,
- DFU_ABORT
-} DFU_REQUESTS;
-
-typedef void (*pFunction)(void);
-
-/* Exported macros -----------------------------------------------------------*/
-/********** Descriptor of DFU interface 0 Alternate setting n ****************/
-#define USBD_DFU_IF_DESC(n) 0x09, /* bLength: Interface Descriptor size */ \
- USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ \
- 0x00, /* bInterfaceNumber: Number of Interface */ \
- (n), /* bAlternateSetting: Alternate setting */ \
- 0x00, /* bNumEndpoints*/ \
- 0xFE, /* bInterfaceClass: Application Specific Class Code */ \
- 0x01, /* bInterfaceSubClass : Device Firmware Upgrade Code */ \
- 0x02, /* nInterfaceProtocol: DFU mode protocol */ \
- USBD_IDX_INTERFACE_STR + (n) + 1 /* iInterface: Index of string descriptor */ \
- /* 18 */
-
-/* Exported variables --------------------------------------------------------*/
-extern USBD_Class_cb_TypeDef DFU_cb;
-
-/* Exported functions ------------------------------------------------------- */
-
-#endif /* __USB_DFU_CORE_H_ */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/dfu/inc/usbd_dfu_mal.h b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/dfu/inc/usbd_dfu_mal.h
deleted file mode 100644
index c0f1d4867d81d8bf30186768570140884e177e57..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/dfu/inc/usbd_dfu_mal.h
+++ /dev/null
@@ -1,78 +0,0 @@
-/**
- ******************************************************************************
- * @file usbd_dfu_mal.h
- * @author MCD Application Team
- * @version V1.0.1
- * @date 31-January-2014
- * @brief Header for usbd_dfu_mal.c file.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __DFU_MAL_H
-#define __DFU_MAL_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_conf.h"
-#include "usbd_dfu_core.h"
-
-/* Exported types ------------------------------------------------------------*/
-typedef struct _DFU_MAL_PROP
-{
- const uint8_t* pStrDesc;
- uint16_t (*pMAL_Init) (void);
- uint16_t (*pMAL_DeInit) (void);
- uint16_t (*pMAL_Erase) (uint32_t Add);
- uint16_t (*pMAL_Write) (uint32_t Add, uint32_t Len);
- uint8_t *(*pMAL_Read) (uint32_t Add, uint32_t Len);
- uint16_t (*pMAL_CheckAdd) (uint32_t Add);
- const uint32_t EraseTiming;
- const uint32_t WriteTiming;
-}
-DFU_MAL_Prop_TypeDef;
-
-
-/* Exported defines --------------------------------------------------------*/
-#define MAL_OK 0
-#define MAL_FAIL 1
-
-/* Exported macro ------------------------------------------------------------*/
-#define _1st_BYTE(x) (uint8_t)((x)&0xFF) /* 1st addressing cycle */
-#define _2nd_BYTE(x) (uint8_t)(((x)&0xFF00)>>8) /* 2nd addressing cycle */
-#define _3rd_BYTE(x) (uint8_t)(((x)&0xFF0000)>>16) /* 3rd addressing cycle */
-#define _4th_BYTE(x) (uint8_t)(((x)&0xFF000000)>>24) /* 4th addressing cycle */
-
-#define SET_POLLING_TIMING(x) buffer[1] = _1st_BYTE(x);\
- buffer[2] = _2nd_BYTE(x);\
- buffer[3] = _3rd_BYTE(x);
-
-/* Exported functions ------------------------------------------------------- */
-uint16_t MAL_Init (void);
-uint16_t MAL_DeInit (void);
-uint16_t MAL_Erase (uint32_t SectorAddress);
-uint16_t MAL_Write (uint32_t SectorAddress, uint32_t DataLength);
-uint8_t *MAL_Read (uint32_t SectorAddress, uint32_t DataLength);
-uint16_t MAL_GetStatus(uint32_t SectorAddress ,uint8_t Cmd, uint8_t *buffer);
-
-extern uint8_t MAL_Buffer[XFERSIZE]; /* RAM Buffer for Downloaded Data */
-
-#endif /* __DFU_MAL_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/dfu/inc/usbd_flash_if.h b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/dfu/inc/usbd_flash_if.h
deleted file mode 100644
index a15924072b542788e524a29414b2b3f90b66a9da..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/dfu/inc/usbd_flash_if.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/**
- ******************************************************************************
- * @file usbd_flash_if.h
- * @author MCD Application Team
- * @version V1.0.1
- * @date 31-January-2014
- * @brief Header for usbd_flash_if.c file.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __FLASH_IF_MAL_H
-#define __FLASH_IF_MAL_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_dfu_mal.h"
-
-/* Exported defines ----------------------------------------------------------*/
-#define FLASH_START_ADD 0x08000000
-
-#define FLASH_END_ADD 0x08040000
-#define FLASH_IF_STRING (uint8_t*) "@Internal Flash /0x08000000/12*001Ka,116*001Kg"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported variables --------------------------------------------------------*/
-extern DFU_MAL_Prop_TypeDef DFU_Flash_cb;
-
-/* Exported functions ------------------------------------------------------- */
-
-#endif /* __FLASH_IF_MAL_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/dfu/inc/usbd_mem_if_template.h b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/dfu/inc/usbd_mem_if_template.h
deleted file mode 100644
index afdb4727319515e8bef9cc15558f1037f018a1f2..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/dfu/inc/usbd_mem_if_template.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/**
- ******************************************************************************
- * @file usbd_mem_if_template.h
- * @author MCD Application Team
- * @version V1.0.1
- * @date 31-January-2014
- * @brief Header for usbd_mem_if_template.c file.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __MEM_IF_MAL_H
-#define __MEM_IF_MAL_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "usb_conf.h"
-#include "usbd_dfu_mal.h"
-
-/* Exported defines ----------------------------------------------------------*/
-#define MEM_START_ADD 0x00000000 /* Dummy start address */
-#define MEM_END_ADD (uint32_t)(MEM_START_ADD + (5 * 1024)) /* Dummy Size = 5KB */
-
-#define MEM_IF_STRING "@Dummy Memory /0x00000000/01*002Kg,03*001Kg"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported variables --------------------------------------------------------*/
-extern DFU_MAL_Prop_TypeDef DFU_Mem_cb;
-
-/* Exported functions ------------------------------------------------------- */
-
-#endif /* __MEM_IF_MAL_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/dfu/src/usbd_dfu_core.c b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/dfu/src/usbd_dfu_core.c
deleted file mode 100644
index a6f47ab97aee9b7512022d9efeb7ef673a6b7835..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/dfu/src/usbd_dfu_core.c
+++ /dev/null
@@ -1,842 +0,0 @@
-/**
- ******************************************************************************
- * @file usbd_dfu_core.c
- * @author MCD Application Team
- * @version V1.0.1
- * @date 31-January-2014
- * @brief This file provides the high layer firmware functions to manage the
- * following functionalities of the USB DFU Class:
- * - Initialization and Configuration of high and low layer
- * - Enumeration as DFU Device (and enumeration for each implemented memory interface)
- * - Transfers to/from memory interfaces
- * - Easy-to-customize "plug-in-like" modules for adding/removing memory interfaces.
- * - Error management
- *
- * @verbatim
- *
- * ===================================================================
- * DFU Class Driver Description
- * ===================================================================
- * This driver manages the DFU class V1.1 following the "Device Class Specification for
- * Device Firmware Upgrade Version 1.1 Aug 5, 2004".
- * This driver implements the following aspects of the specification:
- * - Device descriptor management
- * - Configuration descriptor management
- * - Enumeration as DFU device (in DFU mode only)
- * - Requests management (supporting ST DFU sub-protocol)
- * - Memory operations management (Download/Upload/Erase/Detach/GetState/GetStatus)
- * - DFU state machine implementation.
- *
- * @note
- * ST DFU sub-protocol is compliant with DFU protocol and use sub-requests to manage
- * memory addressing, commands processing, specific memories operations (ie. Erase) ...
- * As required by the DFU specification, only endpoint 0 is used in this application.
- * Other endpoints and functions may be added to the application (ie. DFU ...)
- *
- * These aspects may be enriched or modified for a specific user application.
- *
- * This driver doesn't implement the following aspects of the specification
- * (but it is possible to manage these features with some modifications on this driver):
- * - Manifestation Tolerant mode
- *
- * @endverbatim
- *
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_dfu_core.h"
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-uint8_t usbd_dfu_OtherCfgDesc[USB_DFU_CONFIG_DESC_SIZ] ;
-
-/* The list of Interface String descriptor pointers is defined in usbd_dfu_mal.c
- file. This list can be updated whenever a memory has to be added or removed */
-extern const uint8_t* usbd_dfu_StringDesc[];
-
-/* State Machine variables */
-uint8_t DeviceState;
-uint8_t DeviceStatus[6];
-uint32_t Manifest_State = Manifest_complete;
-/* Data Management variables */
-static uint32_t wBlockNum = 0, wlength = 0;
-static uint32_t Pointer = APP_DEFAULT_ADD; /* Base Address to Erase, Program or Read */
-static __IO uint32_t usbd_dfu_AltSet = 0;
-
-extern uint8_t MAL_Buffer[];
-
-/*********************************************
- DFU Device library callbacks
- *********************************************/
-static uint8_t usbd_dfu_Init (void *pdev,
- uint8_t cfgidx);
-
-static uint8_t usbd_dfu_DeInit (void *pdev,
- uint8_t cfgidx);
-
-static uint8_t usbd_dfu_Setup (void *pdev,
- USB_SETUP_REQ *req);
-
-static uint8_t EP0_TxSent (void *pdev);
-
-static uint8_t EP0_RxReady (void *pdev);
-
-
-static uint8_t *USBD_DFU_GetCfgDesc (uint8_t speed,
- uint16_t *length);
-
-
-static uint8_t* USBD_DFU_GetUsrStringDesc (uint8_t speed,
- uint8_t index ,
- uint16_t *length);
-
-
-/* DFU interface class callbacks structure */
-USBD_Class_cb_TypeDef DFU_cb =
-{
- usbd_dfu_Init,
- usbd_dfu_DeInit,
- usbd_dfu_Setup,
- EP0_TxSent,
- EP0_RxReady,
- NULL, /* DataIn, */
- NULL, /* DataOut, */
- NULL, /*SOF */
- USBD_DFU_GetCfgDesc,
- USBD_DFU_GetUsrStringDesc,
-};
-
-/* USB DFU device Configuration Descriptor */
-const uint8_t usbd_dfu_CfgDesc[USB_DFU_CONFIG_DESC_SIZ] =
-{
- 0x09, /* bLength: Configuration Descriptor size */
- USB_CONFIGURATION_DESCRIPTOR_TYPE, /* bDescriptorType: Configuration */
- USB_DFU_CONFIG_DESC_SIZ,
- /* wTotalLength: Bytes returned */
- 0x00,
- 0x01, /*bNumInterfaces: 1 interface*/
- 0x01, /*bConfigurationValue: Configuration value*/
- 0x02, /*iConfiguration: Index of string descriptor describing the configuration*/
- 0xC0, /*bmAttributes: bus powered and Supports Remote Wakeup */
- 0x32, /*MaxPower 100 mA: this current is used for detecting Vbus*/
- /* 09 */
-
- /********** Descriptor of DFU interface 0 Alternate setting 0 **************/
- USBD_DFU_IF_DESC(0), /* This interface is mandatory for all devices */
-
-#if (USBD_ITF_MAX_NUM > 1)
- /********** Descriptor of DFU interface 0 Alternate setting 1 **************/
- USBD_DFU_IF_DESC(1),
-#endif /* (USBD_ITF_MAX_NUM > 1) */
-
-#if (USBD_ITF_MAX_NUM > 2)
- /********** Descriptor of DFU interface 0 Alternate setting 2 **************/
- USBD_DFU_IF_DESC(2),
-#endif /* (USBD_ITF_MAX_NUM > 2) */
-
-#if (USBD_ITF_MAX_NUM > 3)
- /********** Descriptor of DFU interface 0 Alternate setting 3 **************/
- USBD_DFU_IF_DESC(3),
-#endif /* (USBD_ITF_MAX_NUM > 3) */
-
-#if (USBD_ITF_MAX_NUM > 4)
- /********** Descriptor of DFU interface 0 Alternate setting 4 **************/
- USBD_DFU_IF_DESC(4),
-#endif /* (USBD_ITF_MAX_NUM > 4) */
-
-#if (USBD_ITF_MAX_NUM > 5)
- /********** Descriptor of DFU interface 0 Alternate setting 5 **************/
- USBD_DFU_IF_DESC(5),
-#endif /* (USBD_ITF_MAX_NUM > 5) */
-
-#if (USBD_ITF_MAX_NUM > 6)
-#error "ERROR: usbd_dfu_core.c: Modify the file to support more descriptors!"
-#endif /* (USBD_ITF_MAX_NUM > 6) */
-
- /******************** DFU Functional Descriptor********************/
- 0x09, /*blength = 9 Bytes*/
- DFU_DESCRIPTOR_TYPE, /* DFU Functional Descriptor*/
- 0x0B, /*bmAttribute
- bitCanDnload = 1 (bit 0)
- bitCanUpload = 1 (bit 1)
- bitManifestationTolerant = 0 (bit 2)
- bitWillDetach = 1 (bit 3)
- Reserved (bit4-6)
- bitAcceleratedST = 0 (bit 7)*/
- 0xFF, /*DetachTimeOut= 255 ms*/
- 0x00,
- TRANSFER_SIZE_BYTES(XFERSIZE), /* TransferSize = 1024 Byte*/
- 0x1A, /* bcdDFUVersion*/
- 0x01
- /***********************************************************/
- /* 9*/
-} ;
-/* Private function prototypes -----------------------------------------------*/
-
-/*********************************************
- DFU Requests management functions
- *********************************************/
-static void DFU_Req_DETACH (void *pdev,
- USB_SETUP_REQ *req);
-
-static void DFU_Req_DNLOAD (void *pdev,
- USB_SETUP_REQ *req);
-
-static void DFU_Req_UPLOAD (void *pdev,
- USB_SETUP_REQ *req);
-
-static void DFU_Req_GETSTATUS (void *pdev);
-
-static void DFU_Req_CLRSTATUS (void *pdev);
-
-static void DFU_Req_GETSTATE (void *pdev);
-
-static void DFU_Req_ABORT (void *pdev);
-
-static void DFU_LeaveDFUMode (void *pdev);
-
-/* Private function ----------------------------------------------------------*/
-
-/**
- * @brief usbd_dfu_Init
- * Initializes the DFU interface.
- * @param pdev: device instance
- * @param cfgidx: Configuration index
- * @retval status
- */
-static uint8_t usbd_dfu_Init (void *pdev,
- uint8_t cfgidx)
-{
- /* Initialize the MAL(Media Access Layer) */
- MAL_Init();
-
- /* Initialize the state of the DFU interface */
- DeviceState = STATE_dfuIDLE;
- DeviceStatus[0] = STATUS_OK;
- DeviceStatus[4] = DeviceState;
-
- return USBD_OK;
-}
-
-/**
- * @brief usbd_dfu_Init
- * De-initializes the DFU layer.
- * @param pdev: device instance
- * @param cfgidx: Configuration index
- * @retval status
- */
-static uint8_t usbd_dfu_DeInit (void *pdev,
- uint8_t cfgidx)
-{
- /* Restore default state */
- DeviceState = STATE_dfuIDLE;
- DeviceStatus[0] = STATUS_OK;
- DeviceStatus[4] = DeviceState;
- wBlockNum = 0;
- wlength = 0;
-
- /* DeInitilialize the MAL(Media Access Layer) */
- MAL_DeInit();
-
- return USBD_OK;
-}
-
-/**
- * @brief usbd_dfu_Setup
- * Handles the DFU request parsing.
- * @param pdev: instance
- * @param req: usb requests
- * @retval status
- */
-static uint8_t usbd_dfu_Setup (void *pdev,
- USB_SETUP_REQ *req)
-{
- uint16_t len = 0;
- uint8_t *pbuf = NULL;
-
- switch (req->bmRequest & USB_REQ_TYPE_MASK)
- {
- /* DFU Class Requests -------------------------------*/
- case USB_REQ_TYPE_CLASS :
- switch (req->bRequest)
- {
- case DFU_DNLOAD:
- DFU_Req_DNLOAD(pdev, req);
- break;
-
- case DFU_UPLOAD:
- DFU_Req_UPLOAD(pdev, req);
- break;
-
- case DFU_GETSTATUS:
- DFU_Req_GETSTATUS(pdev);
- break;
-
- case DFU_CLRSTATUS:
- DFU_Req_CLRSTATUS(pdev);
- break;
-
- case DFU_GETSTATE:
- DFU_Req_GETSTATE(pdev);
- break;
-
- case DFU_ABORT:
- DFU_Req_ABORT(pdev);
- break;
-
- case DFU_DETACH:
- DFU_Req_DETACH(pdev, req);
- break;
-
- default:
- USBD_CtlError (pdev, req);
- return USBD_FAIL;
- }
- break;
-
- /* Standard Requests -------------------------------*/
- case USB_REQ_TYPE_STANDARD:
- switch (req->bRequest)
- {
- case USB_REQ_GET_DESCRIPTOR:
- if( (req->wValue >> 8) == DFU_DESCRIPTOR_TYPE)
- {
- pbuf = (uint8_t*)usbd_dfu_CfgDesc + 9 + (9 * USBD_ITF_MAX_NUM);
- len = MIN(USB_DFU_DESC_SIZ , req->wLength);
- }
-
- USBD_CtlSendData (pdev,
- pbuf,
- len);
- break;
-
- case USB_REQ_GET_INTERFACE :
- USBD_CtlSendData (pdev,
- (uint8_t *)&usbd_dfu_AltSet,
- 1);
- break;
-
- case USB_REQ_SET_INTERFACE :
- if ((uint8_t)(req->wValue) < USBD_ITF_MAX_NUM)
- {
- usbd_dfu_AltSet = (uint8_t)(req->wValue);
- }
- else
- {
- /* Call the error management function (command will be nacked */
- USBD_CtlError (pdev, req);
- }
- break;
- }
- }
- return USBD_OK;
-}
-
-/**
- * @brief EP0_TxSent
- * Handles the DFU control endpoint data IN stage.
- * @param pdev: device instance
- * @retval status
- */
-static uint8_t EP0_TxSent (void *pdev)
-{
- uint32_t Addr;
- USB_SETUP_REQ req;
-
- if (DeviceState == STATE_dfuDNBUSY)
- {
- /* Decode the Special Command*/
- if (wBlockNum == 0)
- {
- if ((MAL_Buffer[0] == CMD_GETCOMMANDS) && (wlength == 1))
- {}
- else if (( MAL_Buffer[0] == CMD_SETADDRESSPOINTER ) && (wlength == 5))
- {
- Pointer = MAL_Buffer[1];
- Pointer += MAL_Buffer[2] << 8;
- Pointer += MAL_Buffer[3] << 16;
- Pointer += MAL_Buffer[4] << 24;
- }
- else if (( MAL_Buffer[0] == CMD_ERASE ) && (wlength == 5))
- {
- Pointer = MAL_Buffer[1];
- Pointer += MAL_Buffer[2] << 8;
- Pointer += MAL_Buffer[3] << 16;
- Pointer += MAL_Buffer[4] << 24;
- MAL_Erase(Pointer);
- }
- else
- {
- /* Reset the global length and block number */
- wlength = 0;
- wBlockNum = 0;
- /* Call the error management function (command will be nacked) */
- req.bmRequest = 0;
- req.wLength = 1;
- USBD_CtlError (pdev, &req);
- }
- }
- /* Regular Download Command */
- else if (wBlockNum > 1)
- {
- /* Decode the required address */
- Addr = ((wBlockNum - 2) * XFERSIZE) + Pointer;
-
- /* Preform the write operation */
- MAL_Write(Addr, wlength);
- }
- /* Reset the global length and block number */
- wlength = 0;
- wBlockNum = 0;
-
- /* Update the state machine */
- DeviceState = STATE_dfuDNLOAD_SYNC;
- DeviceStatus[4] = DeviceState;
- DeviceStatus[1] = 0;
- DeviceStatus[2] = 0;
- DeviceStatus[3] = 0;
- return USBD_OK;
- }
- else if (DeviceState == STATE_dfuMANIFEST)/* Manifestation in progress*/
- {
- /* Start leaving DFU mode */
- DFU_LeaveDFUMode(pdev);
- }
-
- return USBD_OK;
-}
-
-/**
- * @brief EP0_RxReady
- * Handles the DFU control endpoint data OUT stage.
- * @param pdev: device instance
- * @retval status
- */
-static uint8_t EP0_RxReady (void *pdev)
-{
- return USBD_OK;
-}
-
-
-/******************************************************************************
- DFU Class requests management
-******************************************************************************/
-/**
- * @brief DFU_Req_DETACH
- * Handles the DFU DETACH request.
- * @param pdev: device instance
- * @param req: pointer to the request structure.
- * @retval None.
- */
-static void DFU_Req_DETACH(void *pdev, USB_SETUP_REQ *req)
-{
- if (DeviceState == STATE_dfuIDLE || DeviceState == STATE_dfuDNLOAD_SYNC
- || DeviceState == STATE_dfuDNLOAD_IDLE || DeviceState == STATE_dfuMANIFEST_SYNC
- || DeviceState == STATE_dfuUPLOAD_IDLE )
- {
- /* Update the state machine */
- DeviceState = STATE_dfuIDLE;
- DeviceStatus[0] = STATUS_OK;
- DeviceStatus[1] = 0;
- DeviceStatus[2] = 0;
- DeviceStatus[3] = 0; /*bwPollTimeout=0ms*/
- DeviceStatus[4] = DeviceState;
- DeviceStatus[5] = 0; /*iString*/
- wBlockNum = 0;
- wlength = 0;
- }
-
- /* Check the detach capability in the DFU functional descriptor */
- if ((usbd_dfu_CfgDesc[12 + (9 * USBD_ITF_MAX_NUM)]) & DFU_DETACH_MASK)
- {
- /* Perform an Attach-Detach operation on USB bus */
- DCD_DevDisconnect (pdev);
- DCD_DevConnect (pdev);
- }
- else
- {
- /* Wait for the period of time specified in Detach request */
- USB_BSP_mDelay (req->wValue);
- }
-}
-
-/**
- * @brief DFU_Req_DNLOAD
- * Handles the DFU DNLOAD request.
- * @param pdev: device instance
- * @param req: pointer to the request structure
- * @retval None
- */
-static void DFU_Req_DNLOAD(void *pdev, USB_SETUP_REQ *req)
-{
- /* Data setup request */
- if (req->wLength > 0)
- {
- if ((DeviceState == STATE_dfuIDLE) || (DeviceState == STATE_dfuDNLOAD_IDLE))
- {
- /* Update the global length and block number */
- wBlockNum = req->wValue;
- wlength = req->wLength;
-
- /* Update the state machine */
- DeviceState = STATE_dfuDNLOAD_SYNC;
- DeviceStatus[4] = DeviceState;
-
- /* Prepare the reception of the buffer over EP0 */
- USBD_CtlPrepareRx (pdev,
- (uint8_t*)MAL_Buffer,
- wlength);
- }
- /* Unsupported state */
- else
- {
- /* Call the error management function (command will be nacked */
- USBD_CtlError (pdev, req);
- }
- }
- /* 0 Data DNLOAD request */
- else
- {
- /* End of DNLOAD operation*/
- if (DeviceState == STATE_dfuDNLOAD_IDLE || DeviceState == STATE_dfuIDLE )
- {
- Manifest_State = Manifest_In_Progress;
- DeviceState = STATE_dfuMANIFEST_SYNC;
- DeviceStatus[1] = 0;
- DeviceStatus[2] = 0;
- DeviceStatus[3] = 0;
- DeviceStatus[4] = DeviceState;
- }
- else
- {
- /* Call the error management function (command will be nacked */
- USBD_CtlError (pdev, req);
- }
- }
-}
-
-/**
- * @brief DFU_Req_UPLOAD
- * Handles the DFU UPLOAD request.
- * @param pdev: instance
- * @param req: pointer to the request structure
- * @retval status
- */
-static void DFU_Req_UPLOAD(void *pdev, USB_SETUP_REQ *req)
-{
- uint8_t *Phy_Addr = NULL;
- uint32_t Addr = 0;
-
- /* Data setup request */
- if (req->wLength > 0)
- {
- if ((DeviceState == STATE_dfuIDLE) || (DeviceState == STATE_dfuUPLOAD_IDLE))
- {
- /* Update the global langth and block number */
- wBlockNum = req->wValue;
- wlength = req->wLength;
-
- /* DFU Get Command */
- if (wBlockNum == 0)
- {
- /* Update the state machine */
- DeviceState = (wlength > 3)? STATE_dfuIDLE:STATE_dfuUPLOAD_IDLE;
- DeviceStatus[4] = DeviceState;
- DeviceStatus[1] = 0;
- DeviceStatus[2] = 0;
- DeviceStatus[3] = 0;
-
- /* Store the values of all supported commands */
- MAL_Buffer[0] = CMD_GETCOMMANDS;
- MAL_Buffer[1] = CMD_SETADDRESSPOINTER;
- MAL_Buffer[2] = CMD_ERASE;
-
- /* Send the status data over EP0 */
- USBD_CtlSendData (pdev,
- (uint8_t *)(&(MAL_Buffer[0])),
- 3);
- }
- else if (wBlockNum > 1)
- {
- DeviceState = STATE_dfuUPLOAD_IDLE ;
- DeviceStatus[4] = DeviceState;
- DeviceStatus[1] = 0;
- DeviceStatus[2] = 0;
- DeviceStatus[3] = 0;
- Addr = ((wBlockNum - 2) * XFERSIZE) + Pointer; /* Change is Accelerated*/
-
- /* Return the physical address where data are stored */
- Phy_Addr = MAL_Read(Addr, wlength);
-
- /* Send the status data over EP0 */
- USBD_CtlSendData (pdev,
- Phy_Addr,
- wlength);
- }
- else /* unsupported wBlockNum */
- {
- DeviceState = STATUS_ERRSTALLEDPKT;
- DeviceStatus[4] = DeviceState;
- DeviceStatus[1] = 0;
- DeviceStatus[2] = 0;
- DeviceStatus[3] = 0;
-
- /* Call the error management function (command will be nacked */
- USBD_CtlError (pdev, req);
- }
- }
- /* Unsupported state */
- else
- {
- wlength = 0;
- wBlockNum = 0;
- /* Call the error management function (command will be nacked */
- USBD_CtlError (pdev, req);
- }
- }
- /* No Data setup request */
- else
- {
- DeviceState = STATE_dfuIDLE;
- DeviceStatus[1] = 0;
- DeviceStatus[2] = 0;
- DeviceStatus[3] = 0;
- DeviceStatus[4] = DeviceState;
- }
-}
-
-/**
- * @brief DFU_Req_GETSTATUS
- * Handles the DFU GETSTATUS request.
- * @param pdev: instance
- * @retval status
- */
-static void DFU_Req_GETSTATUS(void *pdev)
-{
- switch (DeviceState)
- {
- case STATE_dfuDNLOAD_SYNC:
- if (wlength != 0)
- {
- DeviceState = STATE_dfuDNBUSY;
- DeviceStatus[4] = DeviceState;
- if ((wBlockNum == 0) && (MAL_Buffer[0] == CMD_ERASE))
- {
- MAL_GetStatus(Pointer, 0, DeviceStatus);
- }
- else
- {
- MAL_GetStatus(Pointer, 1, DeviceStatus);
- }
- }
- else /* (wlength==0)*/
- {
- DeviceState = STATE_dfuDNLOAD_IDLE;
- DeviceStatus[4] = DeviceState;
- DeviceStatus[1] = 0;
- DeviceStatus[2] = 0;
- DeviceStatus[3] = 0;
- }
- break;
-
- case STATE_dfuMANIFEST_SYNC :
- if (Manifest_State == Manifest_In_Progress)
- {
- DeviceState = STATE_dfuMANIFEST;
- DeviceStatus[4] = DeviceState;
- DeviceStatus[1] = 1; /*bwPollTimeout = 1ms*/
- DeviceStatus[2] = 0;
- DeviceStatus[3] = 0;
- //break;
- }
- else if ((Manifest_State == Manifest_complete) && \
- ((usbd_dfu_CfgDesc[(11 + (9 * USBD_ITF_MAX_NUM))]) & 0x04))
- {
- DeviceState = STATE_dfuIDLE;
- DeviceStatus[4] = DeviceState;
- DeviceStatus[1] = 0;
- DeviceStatus[2] = 0;
- DeviceStatus[3] = 0;
- //break;
- }
- break;
-
- default :
- break;
- }
-
- /* Send the status data over EP0 */
- USBD_CtlSendData (pdev,
- (uint8_t *)(&(DeviceStatus[0])),
- 6);
-}
-
-/**
- * @brief DFU_Req_CLRSTATUS
- * Handles the DFU CLRSTATUS request.
- * @param pdev: device instance
- * @retval status
- */
-static void DFU_Req_CLRSTATUS(void *pdev)
-{
- if (DeviceState == STATE_dfuERROR)
- {
- DeviceState = STATE_dfuIDLE;
- DeviceStatus[0] = STATUS_OK;/*bStatus*/
- DeviceStatus[1] = 0;
- DeviceStatus[2] = 0;
- DeviceStatus[3] = 0; /*bwPollTimeout=0ms*/
- DeviceStatus[4] = DeviceState;/*bState*/
- DeviceStatus[5] = 0;/*iString*/
- }
- else
- { /*State Error*/
- DeviceState = STATE_dfuERROR;
- DeviceStatus[0] = STATUS_ERRUNKNOWN;/*bStatus*/
- DeviceStatus[1] = 0;
- DeviceStatus[2] = 0;
- DeviceStatus[3] = 0; /*bwPollTimeout=0ms*/
- DeviceStatus[4] = DeviceState;/*bState*/
- DeviceStatus[5] = 0;/*iString*/
- }
-}
-
-/**
- * @brief DFU_Req_GETSTATE
- * Handles the DFU GETSTATE request.
- * @param pdev: device instance
- * @retval None
- */
-static void DFU_Req_GETSTATE(void *pdev)
-{
- /* Return the current state of the DFU interface */
- USBD_CtlSendData (pdev,
- &DeviceState,
- 1);
-}
-
-/**
- * @brief DFU_Req_ABORT
- * Handles the DFU ABORT request.
- * @param pdev: device instance
- * @retval None
- */
-static void DFU_Req_ABORT(void *pdev)
-{
- if (DeviceState == STATE_dfuIDLE || DeviceState == STATE_dfuDNLOAD_SYNC
- || DeviceState == STATE_dfuDNLOAD_IDLE || DeviceState == STATE_dfuMANIFEST_SYNC
- || DeviceState == STATE_dfuUPLOAD_IDLE )
- {
- DeviceState = STATE_dfuIDLE;
- DeviceStatus[0] = STATUS_OK;
- DeviceStatus[1] = 0;
- DeviceStatus[2] = 0;
- DeviceStatus[3] = 0; /*bwPollTimeout=0ms*/
- DeviceStatus[4] = DeviceState;
- DeviceStatus[5] = 0; /*iString*/
- wBlockNum = 0;
- wlength = 0;
- }
-}
-
-/**
- * @brief DFU_LeaveDFUMode
- * Handles the sub-protocol DFU leave DFU mode request (leaves DFU mode
- * and resets device to jump to user loaded code).
- * @param pdev: device instance
- * @retval None
- */
-void DFU_LeaveDFUMode(void *pdev)
-{
- Manifest_State = Manifest_complete;
-
- if ((usbd_dfu_CfgDesc[(11 + (9 * USBD_ITF_MAX_NUM))]) & 0x04)
- {
- DeviceState = STATE_dfuMANIFEST_SYNC;
- DeviceStatus[4] = DeviceState;
- DeviceStatus[1] = 0;
- DeviceStatus[2] = 0;
- DeviceStatus[3] = 0;
- return;
- }
- else
- {
- DeviceState = STATE_dfuMANIFEST_WAIT_RESET;
- DeviceStatus[4] = DeviceState;
- DeviceStatus[1] = 0;
- DeviceStatus[2] = 0;
- DeviceStatus[3] = 0;
-
- /* Disconnect the USB device */
- DCD_DevDisconnect (pdev);
-
- /* DeInitilialize the MAL(Media Access Layer) */
- MAL_DeInit();
-
- /* Generate system reset to allow jumping to the user code */
- NVIC_SystemReset();
-
- /* This instruction will not be reached (system reset) */
- return;
- }
-}
-
-/**
- * @brief USBD_DFU_GetCfgDesc
- * Returns configuration descriptor
- * @param speed : current device speed
- * @param length : pointer data length
- * @retval pointer to descriptor buffer
- */
-static uint8_t *USBD_DFU_GetCfgDesc (uint8_t speed, uint16_t *length)
-{
- *length = sizeof (usbd_dfu_CfgDesc);
- return (uint8_t*)usbd_dfu_CfgDesc;
-}
-
-/**
- * @brief USBD_DFU_GetUsrStringDesc
- * Manages the transfer of memory interfaces string descriptors.
- * @param speed : current device speed
- * @param index: descriptor index
- * @param length : pointer data length
- * @retval pointer to the descriptor table or NULL if the descriptor is not supported.
- */
-static uint8_t* USBD_DFU_GetUsrStringDesc (uint8_t speed, uint8_t index , uint16_t *length)
-{
- /* Check if the requested string interface is supported */
- if (index <= (USBD_IDX_INTERFACE_STR + USBD_ITF_MAX_NUM))
- {
-
-
- USBD_GetString ((uint8_t *)usbd_dfu_StringDesc[index - USBD_IDX_INTERFACE_STR - 1], USBD_StrDesc, length);
- return USBD_StrDesc;
- }
- /* Not supported Interface Descriptor index */
- else
- {
- return NULL;
- }
-}
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/dfu/src/usbd_dfu_mal.c b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/dfu/src/usbd_dfu_mal.c
deleted file mode 100644
index c1c4d2b9d0792b5eeafb6978f91699e332cf44d2..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/dfu/src/usbd_dfu_mal.c
+++ /dev/null
@@ -1,256 +0,0 @@
-/**
- ******************************************************************************
- * @file usbd_dfu_mal.c
- * @author MCD Application Team
- * @version V1.0.1
- * @date 31-January-2014
- * @brief Generic media access Layer.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_dfu_mal.h"
-#include "usbd_flash_if.h"
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-
-/* Global Memories callback and string descriptors reference tables.
- To add a new memory, modify the value of MAX_USED_MEDIA in usbd_dfu_mal.h
- and add the pointer to the callback structure in this table.
- Then add the pointer to the memory string descriptor in usbd_dfu_StringDesc table.
- No other operation is required. */
-DFU_MAL_Prop_TypeDef* tMALTab[MAX_USED_MEDIA] = {
- &DFU_Flash_cb
-};
-
-const uint8_t* usbd_dfu_StringDesc[MAX_USED_MEDIA] = {
- FLASH_IF_STRING
-};
-
-/* RAM Buffer for Downloaded Data */
-uint8_t MAL_Buffer[XFERSIZE] ;
-
-/* Private function prototypes -----------------------------------------------*/
-static uint8_t MAL_CheckAdd (uint32_t Add);
-
-/* Private functions ---------------------------------------------------------*/
-
-/**
- * @brief MAL_Init
- * Initializes the Media on the STM32
- * @param None
- * @retval Result of the operation (MAL_OK in all cases)
- */
-uint16_t MAL_Init(void)
-{
- uint32_t memIdx = 0;
-
- /* Init all supported memories */
- for(memIdx = 0; memIdx < MAX_USED_MEDIA; memIdx++)
- {
- /* If the check address is positive, exit with the memory index */
- if (tMALTab[memIdx]->pMAL_Init != NULL)
- {
- tMALTab[memIdx]->pMAL_Init();
- }
- }
-
- return MAL_OK;
-}
-
-/**
- * @brief MAL_DeInit
- * DeInitializes the Media on the STM32
- * @param None
- * @retval Result of the operation (MAL_OK in all cases)
- */
-uint16_t MAL_DeInit(void)
-{
- uint32_t memIdx = 0;
-
- /* Init all supported memories */
- for(memIdx = 0; memIdx < MAX_USED_MEDIA; memIdx++)
- {
- /* Check if the command is supported */
- if (tMALTab[memIdx]->pMAL_DeInit != NULL)
- {
- tMALTab[memIdx]->pMAL_DeInit();
- }
- }
-
- return MAL_OK;
-}
-
-/**
- * @brief MAL_Erase
- * Erase a sector of memory.
- * @param Add: Sector address/code
- * @retval Result of the operation: MAL_OK if all operations are OK else MAL_FAIL
- */
-uint16_t MAL_Erase(uint32_t Add)
-{
- uint32_t memIdx = MAL_CheckAdd(Add);
-
- /* Check if the area is protected */
- if (DFU_MAL_IS_PROTECTED_AREA(Add))
- {
- return MAL_FAIL;
- }
-
- if (memIdx < MAX_USED_MEDIA)
- {
- /* Check if the command is supported */
- if (tMALTab[memIdx]->pMAL_Erase != NULL)
- {
- return tMALTab[memIdx]->pMAL_Erase(Add);
- }
- else
- {
- return MAL_FAIL;
- }
- }
- else
- {
- return MAL_FAIL;
- }
-}
-
-/**
- * @brief MAL_Write
- * Write sectors of memory.
- * @param Add: Sector address/code
- * @param Len: Number of data to be written (in bytes)
- * @retval Result of the operation: MAL_OK if all operations are OK else MAL_FAIL
- */
-uint16_t MAL_Write (uint32_t Add, uint32_t Len)
-{
- uint32_t memIdx = MAL_CheckAdd(Add);
-
- /* Check if the area is protected */
- if (DFU_MAL_IS_PROTECTED_AREA(Add))
- {
- return MAL_FAIL;
- }
-
- if (memIdx < MAX_USED_MEDIA)
- {
- /* Check if the command is supported */
- if (tMALTab[memIdx]->pMAL_Write != NULL)
- {
- return tMALTab[memIdx]->pMAL_Write(Add, Len);
- }
- else
- {
- return MAL_FAIL;
- }
- }
- else
- {
- return MAL_FAIL;
- }
-}
-
-/**
- * @brief MAL_Read
- * Read sectors of memory.
- * @param Add: Sector address/code
- * @param Len: Number of data to be written (in bytes)
- * @retval Buffer pointer
- */
-uint8_t *MAL_Read (uint32_t Add, uint32_t Len)
-{
- uint32_t memIdx = MAL_CheckAdd(Add);
-
- if (memIdx < MAX_USED_MEDIA)
- {
- /* Check if the command is supported */
- if (tMALTab[memIdx]->pMAL_Read != NULL)
- {
- return tMALTab[memIdx]->pMAL_Read(Add, Len);
- }
- else
- {
- return MAL_Buffer;
- }
- }
- else
- {
- return MAL_Buffer;
- }
-}
-
-/**
- * @brief MAL_GetStatus
- * Get the status of a given memory.
- * @param Add: Sector address/code (allow to determine which memory will be addressed)
- * @param Cmd: 0 for erase and 1 for write
- * @param buffer: pointer to the buffer where the status data will be stored.
- * @retval Buffer pointer
- */
-uint16_t MAL_GetStatus(uint32_t Add , uint8_t Cmd, uint8_t *buffer)
-{
- uint32_t memIdx = MAL_CheckAdd(Add);
-
- if (memIdx < MAX_USED_MEDIA)
- {
- if (Cmd & 0x01)
- {
- SET_POLLING_TIMING(tMALTab[memIdx]->EraseTiming);
- }
- else
- {
- SET_POLLING_TIMING(tMALTab[memIdx]->WriteTiming);
- }
-
- return MAL_OK;
- }
- else
- {
- return MAL_FAIL;
- }
-}
-
-/**
- * @brief MAL_CheckAdd
- * Determine which memory should be managed.
- * @param Add: Sector address/code (allow to determine which memory will be addressed)
- * @retval Index of the addressed memory.
- */
-static uint8_t MAL_CheckAdd(uint32_t Add)
-{
- uint32_t memIdx = 0;
-
- /* Check with all supported memories */
- for(memIdx = 0; memIdx < MAX_USED_MEDIA; memIdx++)
- {
- /* If the check address is positive, exit with the memory index */
- if (tMALTab[memIdx]->pMAL_CheckAdd(Add) == MAL_OK)
- {
- return memIdx;
- }
- }
- /* If no memory found, return MAX_USED_MEDIA */
- return (MAX_USED_MEDIA);
-}
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/dfu/src/usbd_flash_if.c b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/dfu/src/usbd_flash_if.c
deleted file mode 100644
index 9d45c19b37fb700dfb92a9d1c44f2c4fc4030a26..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/dfu/src/usbd_flash_if.c
+++ /dev/null
@@ -1,164 +0,0 @@
-/**
- ******************************************************************************
- * @file usbd_flash_if.c
- * @author MCD Application Team
- * @version V1.0.1
- * @date 31-January-2014
- * @brief Specific media access Layer for internal flash.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_flash_if.h"
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-
-/* Private function prototypes -----------------------------------------------*/
-uint16_t FLASH_If_Init(void);
-uint16_t FLASH_If_Erase (uint32_t Add);
-uint16_t FLASH_If_Write (uint32_t Add, uint32_t Len);
-uint8_t *FLASH_If_Read (uint32_t Add, uint32_t Len);
-uint16_t FLASH_If_DeInit(void);
-uint16_t FLASH_If_CheckAdd(uint32_t Add);
-
-
-/* Private variables ---------------------------------------------------------*/
-DFU_MAL_Prop_TypeDef DFU_Flash_cb =
-{
- FLASH_IF_STRING,
- FLASH_If_Init,
- FLASH_If_DeInit,
- FLASH_If_Erase,
- FLASH_If_Write,
- FLASH_If_Read,
- FLASH_If_CheckAdd,
- 40, /* Erase Time in ms : extracted from flash memory datasheet Maximum
- timming value for Sector Erase*/
- 60 /* Programming Time in ms (60us * RAM Buffer size (1024 Bytes)
- extracted from flash memory datasheet Maximum timming value for 1024 bytes
- Write)*/
-};
-
-/* Private functions ---------------------------------------------------------*/
-
-/**
- * @brief FLASH_If_Init
- * Memory initialization routine.
- * @param None
- * @retval MAL_OK if operation is successful, MAL_FAIL else.
-*/
-uint16_t FLASH_If_Init(void)
-{
- /* Unlock the internal flash */
- FLASH_Unlock();
-
- return MAL_OK;
-}
-
-/**
- * @brief FLASH_If_DeInit
- * Memory deinitialization routine.
- * @param None
- * @retval MAL_OK if operation is successful, MAL_FAIL else.
- */
-uint16_t FLASH_If_DeInit(void)
-{
- /* Lock the internal flash */
- FLASH_Lock();
-
- return MAL_OK;
-}
-
-/**
- * @brief FLASH_If_Erase
- * Erase sector.
- * @param Add: Address to be written to.
- * @retval MAL_OK if operation is successful, MAL_FAIL else.
- */
-uint16_t FLASH_If_Erase(uint32_t Add)
-{
- /* Call the standard Flash erase function */
- FLASH_ErasePage(Add);
-
- return MAL_OK;
-}
-
-/**
- * @brief FLASH_If_Write
- * Memory write routine.
- * @param Add: Address to be written to.
- * @param Len: Number of data to be written (in bytes).
- * @retval MAL_OK if operation is successful, MAL_FAIL else.
- */
-uint16_t FLASH_If_Write(uint32_t Add, uint32_t Len)
-{
- uint32_t idx = 0;
-
- if (Len & 0x3) /* Not an aligned data */
- {
- for (idx = Len; idx < ((Len & 0xFFFC) + 4); idx++)
- {
- MAL_Buffer[idx] = 0xFF;
- }
- }
-
- /* Data received are Word multiple */
- for (idx = 0; idx < Len; idx = idx + 4)
- {
- FLASH_ProgramWord(Add, *(uint32_t *)(MAL_Buffer + idx));
- Add += 4;
- }
- return MAL_OK;
-}
-
-/**
- * @brief FLASH_If_Read
- * Memory read routine.
- * @param Add: Address to be read from.
- * @param Len: Number of data to be read (in bytes).
- * @retval Pointer to the physical address where data should be read.
- */
-uint8_t *FLASH_If_Read (uint32_t Add, uint32_t Len)
-{
- return (uint8_t *)(Add);
-}
-
-/**
- * @brief FLASH_If_CheckAdd
- * Check if the address is an allowed address for this memory.
- * @param Add: Address to be checked.
- * @param Len: Number of data to be read (in bytes).
- * @retval MAL_OK if the address is allowed, MAL_FAIL else.
- */
-uint16_t FLASH_If_CheckAdd(uint32_t Add)
-{
- if ((Add >= FLASH_START_ADD) && (Add < FLASH_END_ADD))
- {
- return MAL_OK;
- }
- else
- {
- return MAL_FAIL;
- }
-}
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/dfu/src/usbd_mem_if_template.c b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/dfu/src/usbd_mem_if_template.c
deleted file mode 100644
index 2bf838ebd34051a12154f806d7e5075d08e31c2b..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/dfu/src/usbd_mem_if_template.c
+++ /dev/null
@@ -1,137 +0,0 @@
-/**
- ******************************************************************************
- * @file usbd_mem_if_template.c
- * @author MCD Application Team
- * @version V1.0.1
- * @date 31-January-2014
- * @brief Specific media access Layer for a template memory. This file is
- provided as template example showing how to implement a new memory
- interface based on pre-defined API.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_mem_if_template.h"
-#include "usbd_dfu_mal.h"
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-uint16_t MEM_If_Init(void);
-uint16_t MEM_If_Erase (uint32_t Add);
-uint16_t MEM_If_Write (uint32_t Add, uint32_t Len);
-uint8_t *MEM_If_Read (uint32_t Add, uint32_t Len);
-uint16_t MEM_If_DeInit(void);
-uint16_t MEM_If_CheckAdd(uint32_t Add);
-
-/* Private variables ---------------------------------------------------------*/
-DFU_MAL_Prop_TypeDef DFU_Mem_cb =
- {
- MEM_IF_STRING,
- MEM_If_Init,
- MEM_If_DeInit,
- MEM_If_Erase,
- MEM_If_Write,
- MEM_If_Read,
- MEM_If_CheckAdd,
- 10, /* Erase Time in ms */
- 10 /* Programming Time in ms */
- };
-
-/* Private functions ---------------------------------------------------------*/
-
-/**
- * @brief MEM_If_Init
- * Memory initialization routine.
- * @param None
- * @retval MAL_OK if operation is successful, MAL_FAIL else.
- */
-uint16_t MEM_If_Init(void)
-{
- return MAL_OK;
-}
-
-/**
- * @brief MEM_If_DeInit
- * Memory deinitialization routine.
- * @param None
- * @retval MAL_OK if operation is successful, MAL_FAIL else.
- */
-uint16_t MEM_If_DeInit(void)
-{
- return MAL_OK;
-}
-
-/**
- * @brief MEM_If_Erase
- * Erase sector.
- * @param Add: Address of sector to be erased.
- * @retval MAL_OK if operation is successful, MAL_FAIL else.
- */
-uint16_t MEM_If_Erase(uint32_t Add)
-{
- return MAL_OK;
-}
-
-/**
- * @brief MEM_If_Write
- * Memory write routine.
- * @param Add: Address to be written to.
- * @param Len: Number of data to be written (in bytes).
- * @retval MAL_OK if operation is successful, MAL_FAIL else.
- */
-uint16_t MEM_If_Write(uint32_t Add, uint32_t Len)
-{
- return MAL_OK;
-}
-
-/**
- * @brief MEM_If_Read
- * Memory read routine.
- * @param Add: Address to be read from.
- * @param Len: Number of data to be read (in bytes).
- * @retval Pointer to the physical address where data should be read.
- */
-uint8_t *MEM_If_Read (uint32_t Add, uint32_t Len)
-{
- /* Return a valid address to avoid HardFault */
- return (uint8_t*)(MAL_Buffer);
-}
-
-/**
- * @brief MEM_If_CheckAdd
- * Check if the address is an allowed address for this memory.
- * @param Add: Address to be checked.
- * @param Len: Number of data to be read (in bytes).
- * @retval MAL_OK if the address is allowed, MAL_FAIL else.
- */
-uint16_t MEM_If_CheckAdd(uint32_t Add)
-{
- if ((Add >= MEM_START_ADD) && (Add < MEM_END_ADD))
- {
- return MAL_OK;
- }
- else
- {
- return MAL_FAIL;
- }
-}
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/hid/inc/usbd_custom_hid_core.h b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/hid/inc/usbd_custom_hid_core.h
deleted file mode 100644
index abe3f9979b9a5ba762b727631f99b35aee8683be..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/hid/inc/usbd_custom_hid_core.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/**
- ******************************************************************************
- * @file usbd_hid_core.h
- * @author MCD Application Team
- * @version V1.0.1
- * @date 31-January-2014
- * @brief header file for the usbd_hid_core.c file.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __USB_HID_CORE_H_
-#define __USB_HID_CORE_H_
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_req.h"
-
-/* Exported defines ----------------------------------------------------------*/
-#define USB_HID_CONFIG_DESC_SIZ 34
-#define USB_HID_DESC_SIZ 9
-#define HID_MOUSE_REPORT_DESC_SIZE 74
-
-#define HID_DESCRIPTOR_TYPE 0x21
-#define HID_REPORT_DESC 0x22
-
-
-#define HID_REQ_SET_PROTOCOL 0x0B
-#define HID_REQ_GET_PROTOCOL 0x03
-
-#define HID_REQ_SET_IDLE 0x0A
-#define HID_REQ_GET_IDLE 0x02
-
-#define HID_REQ_SET_REPORT 0x09
-#define HID_REQ_GET_REPORT 0x01
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported macros -----------------------------------------------------------*/
-/* Exported variables --------------------------------------------------------*/
-extern USBD_Class_cb_TypeDef USBD_HID_cb;
-
-/* Exported functions ------------------------------------------------------- */
-
-uint8_t USBD_HID_SendReport (USB_CORE_HANDLE *pdev,
- uint8_t *report,
- uint16_t len);
-
-#endif /* __USB_HID_CORE_H_ */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/hid/inc/usbd_hid_core.h b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/hid/inc/usbd_hid_core.h
deleted file mode 100644
index aa560243a458f7b128aee46e0eca8ab107a3d3b9..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/hid/inc/usbd_hid_core.h
+++ /dev/null
@@ -1,64 +0,0 @@
-/**
- ******************************************************************************
- * @file usbd_hid_core.h
- * @author MCD Application Team
- * @version V1.0.1
- * @date 31-January-2014
- * @brief header file for the usbd_hid_core.c file.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __USB_HID_CORE_H_
-#define __USB_HID_CORE_H_
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_req.h"
-
-/* Exported defines ----------------------------------------------------------*/
-#define USB_HID_CONFIG_DESC_SIZ 34
-#define USB_HID_DESC_SIZ 9
-#define HID_MOUSE_REPORT_DESC_SIZE 74
-
-#define HID_DESCRIPTOR_TYPE 0x21
-#define HID_REPORT_DESC 0x22
-
-
-#define HID_REQ_SET_PROTOCOL 0x0B
-#define HID_REQ_GET_PROTOCOL 0x03
-
-#define HID_REQ_SET_IDLE 0x0A
-#define HID_REQ_GET_IDLE 0x02
-
-#define HID_REQ_SET_REPORT 0x09
-#define HID_REQ_GET_REPORT 0x01
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported macros -----------------------------------------------------------*/
-/* Exported variables --------------------------------------------------------*/
-extern USBD_Class_cb_TypeDef USBD_HID_cb;
-
-/* Exported functions ------------------------------------------------------- */
-
-uint8_t USBD_HID_SendReport (USB_CORE_HANDLE *pdev,
- uint8_t *report,
- uint16_t len);
-#endif /* __USB_HID_CORE_H_ */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/hid/src/usbd_custom_hid_core.c b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/hid/src/usbd_custom_hid_core.c
deleted file mode 100644
index 81e9dad67530080bced792fd9b005ff6fbc281ae..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/hid/src/usbd_custom_hid_core.c
+++ /dev/null
@@ -1,622 +0,0 @@
-/**
- ******************************************************************************
- * @file usbd_hid_core.c
- * @author MCD Application Team
- * @version V1.0.1
- * @date 31-January-2014
- * @brief This file provides the HID core functions.
- *
- * @verbatim
- *
- * ===================================================================
- * HID Class Description
- * ===================================================================
- * This module manages the HID class V1.11 following the "Device Class Definition
- * for Human Interface Devices (HID) Version 1.11 Jun 27, 2001".
- * This driver implements the following aspects of the specification:
- * - The Boot Interface Subclass
- * - The Mouse protocol
- * - Usage Page : Generic Desktop
- * - Usage : Custom
- * - Collection : Application
- *
- *
- * @endverbatim
- *
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_custom_hid_core.h"
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-uint8_t USBD_HID_Init (void *pdev,
- uint8_t cfgidx);
-
-uint8_t USBD_HID_DeInit (void *pdev,
- uint8_t cfgidx);
-
-uint8_t USBD_HID_Setup (void *pdev,
- USB_SETUP_REQ *req);
-
-uint8_t *USBD_HID_GetCfgDesc (uint8_t speed, uint16_t *length);
-
-
-uint8_t USBD_HID_DataIn (void *pdev, uint8_t epnum);
-
-
-uint8_t USBD_HID_DataOut (void *pdev, uint8_t epnum);
-
-
-uint8_t USBD_HID_EP0_RxReady (void *pdev);
-
-USBD_Class_cb_TypeDef USBD_HID_cb =
-{
- USBD_HID_Init,
- USBD_HID_DeInit,
- USBD_HID_Setup,
- NULL, /*EP0_TxSent*/
- USBD_HID_EP0_RxReady, /*EP0_RxReady*/ /* STATUS STAGE IN */
- USBD_HID_DataIn, /*DataIn*/
- USBD_HID_DataOut, /*DataOut*/
- NULL, /*SOF */
- USBD_HID_GetCfgDesc,
-};
-
-
-
-uint8_t Report_buf[2];
-uint8_t USBD_HID_Report_ID=0;
-uint8_t flag = 0;
-extern uint8_t PrevXferDone;
-
-static uint32_t USBD_HID_AltSet = 0;
-
-static uint32_t USBD_HID_Protocol = 0;
-
-static uint32_t USBD_HID_IdleState = 0;
-
-/* USB HID device Configuration Descriptor */
-const uint8_t USBD_HID_CfgDesc[CUSTOMHID_SIZ_CONFIG_DESC] =
-{
- 0x09, /* bLength: Configuration Descriptor size */
- USB_CONFIGURATION_DESCRIPTOR_TYPE, /* bDescriptorType: Configuration */
- CUSTOMHID_SIZ_CONFIG_DESC,
- /* wTotalLength: Bytes returned */
- 0x00,
- 0x01, /*bNumInterfaces: 1 interface*/
- 0x01, /*bConfigurationValue: Configuration value*/
- 0x00, /*iConfiguration: Index of string descriptor describing
- the configuration*/
- 0xC0, /*bmAttributes: bus powered and Support Remote Wake-up */
- 0x32, /*MaxPower 100 mA: this current is used for detecting Vbus*/
-
- /************** Descriptor of Custom HID interface ****************/
- /* 09 */
- 0x09, /*bLength: Interface Descriptor size*/
- USB_INTERFACE_DESCRIPTOR_TYPE,/*bDescriptorType: Interface descriptor type*/
- 0x00, /*bInterfaceNumber: Number of Interface*/
- 0x00, /*bAlternateSetting: Alternate setting*/
- 0x02, /*bNumEndpoints*/
- 0x03, /*bInterfaceClass: HID*/
- 0x00, /*bInterfaceSubClass : 1=BOOT, 0=no boot*/
- 0x00, /*nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse*/
- 0, /*iInterface: Index of string descriptor*/
- /******************** Descriptor of Custom HID ********************/
- /* 18 */
- 0x09, /*bLength: HID Descriptor size*/
- HID_DESCRIPTOR_TYPE, /*bDescriptorType: HID*/
- 0x11, /*bcdHID: HID Class Spec release number*/
- 0x01,
- 0x00, /*bCountryCode: Hardware target country*/
- 0x01, /*bNumDescriptors: Number of HID class descriptors to follow*/
- 0x22, /*bDescriptorType*/
- CUSTOMHID_SIZ_REPORT_DESC,/*wItemLength: Total length of Report descriptor*/
- 0x00,
- /******************** Descriptor of Custom HID endpoints ***********/
- /* 27 */
- 0x07, /* bLength: Endpoint Descriptor size */
- USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: */
-
- HID_IN_EP, /* bEndpointAddress: Endpoint Address (IN) */
- 0x03, /* bmAttributes: Interrupt endpoint */
- HID_IN_PACKET, /* wMaxPacketSize: 2 Bytes max */
- 0x00,
- 0x20, /* bInterval: Polling Interval (32 ms) */
- /* 34 */
-
- 0x07, /* bLength: Endpoint Descriptor size */
- USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: */
- /* Endpoint descriptor type */
- HID_OUT_EP, /* bEndpointAddress: */
- /* Endpoint Address (OUT) */
- 0x03, /* bmAttributes: Interrupt endpoint */
- HID_OUT_PACKET, /* wMaxPacketSize: 2 Bytes max */
- 0x00,
- 0x20, /* bInterval: Polling Interval (20 ms) */
- /* 41 */
-} ;
-
-const uint8_t CustomHID_ReportDescriptor[CUSTOMHID_SIZ_REPORT_DESC] =
-{
- 0x06, 0xFF, 0x00, /* USAGE_PAGE (Vendor Page: 0xFF00) */
- 0x09, 0x01, /* USAGE (Demo Kit) */
- 0xa1, 0x01, /* COLLECTION (Application) */
- /* 6 */
-
- /* Led 1 */
- 0x85, 0x01, /* REPORT_ID (1) */
- 0x09, 0x01, /* USAGE (LED 1) */
- 0x15, 0x00, /* LOGICAL_MINIMUM (0) */
- 0x25, 0x01, /* LOGICAL_MAXIMUM (1) */
- 0x75, 0x08, /* REPORT_SIZE (8) */
- 0x95, 0x01, /* REPORT_COUNT (1) */
- 0xB1, 0x82, /* FEATURE (Data,Var,Abs,Vol) */
-
- 0x85, 0x01, /* REPORT_ID (1) */
- 0x09, 0x01, /* USAGE (LED 1) */
- 0x91, 0x82, /* OUTPUT (Data,Var,Abs,Vol) */
- /* 26 */
-
- /* Led 2 */
- 0x85, 0x02, /* REPORT_ID 2 */
- 0x09, 0x02, /* USAGE (LED 2) */
- 0x15, 0x00, /* LOGICAL_MINIMUM (0) */
- 0x25, 0x01, /* LOGICAL_MAXIMUM (1) */
- 0x75, 0x08, /* REPORT_SIZE (8) */
- 0x95, 0x01, /* REPORT_COUNT (1) */
- 0xB1, 0x82, /* FEATURE (Data,Var,Abs,Vol) */
-
- 0x85, 0x02, /* REPORT_ID (2) */
- 0x09, 0x02, /* USAGE (LED 2) */
- 0x91, 0x82, /* OUTPUT (Data,Var,Abs,Vol) */
- /* 46 */
-
- /* Led 3 */
- 0x85, 0x03, /* REPORT_ID (3) */
- 0x09, 0x03, /* USAGE (LED 3) */
- 0x15, 0x00, /* LOGICAL_MINIMUM (0) */
- 0x25, 0x01, /* LOGICAL_MAXIMUM (1) */
- 0x75, 0x08, /* REPORT_SIZE (8) */
- 0x95, 0x01, /* REPORT_COUNT (1) */
- 0xB1, 0x82, /* FEATURE (Data,Var,Abs,Vol) */
-
- 0x85, 0x03, /* REPORT_ID (3) */
- 0x09, 0x03, /* USAGE (LED 3) */
- 0x91, 0x82, /* OUTPUT (Data,Var,Abs,Vol) */
- /* 66 */
-
- /* Led 4 */
- 0x85, 0x04, /* REPORT_ID 4) */
- 0x09, 0x04, /* USAGE (LED 4) */
- 0x15, 0x00, /* LOGICAL_MINIMUM (0) */
- 0x25, 0x01, /* LOGICAL_MAXIMUM (1) */
- 0x75, 0x08, /* REPORT_SIZE (8) */
- 0x95, 0x01, /* REPORT_COUNT (1) */
- 0xB1, 0x82, /* FEATURE (Data,Var,Abs,Vol) */
-
- 0x85, 0x04, /* REPORT_ID (4) */
- 0x09, 0x04, /* USAGE (LED 4) */
- 0x91, 0x82, /* OUTPUT (Data,Var,Abs,Vol) */
- /* 86 */
-
- /* key Push Button */
- 0x85, 0x05, /* REPORT_ID (5) */
- 0x09, 0x05, /* USAGE (Push Button) */
- 0x15, 0x00, /* LOGICAL_MINIMUM (0) */
- 0x25, 0x01, /* LOGICAL_MAXIMUM (1) */
- 0x75, 0x01, /* REPORT_SIZE (1) */
- 0x81, 0x82, /* INPUT (Data,Var,Abs,Vol) */
-
- 0x09, 0x05, /* USAGE (Push Button) */
- 0x75, 0x01, /* REPORT_SIZE (1) */
- 0xb1, 0x82, /* FEATURE (Data,Var,Abs,Vol) */
-
- 0x75, 0x07, /* REPORT_SIZE (7) */
- 0x81, 0x83, /* INPUT (Cnst,Var,Abs,Vol) */
- 0x85, 0x05, /* REPORT_ID (2) */
-
- 0x75, 0x07, /* REPORT_SIZE (7) */
- 0xb1, 0x83, /* FEATURE (Cnst,Var,Abs,Vol) */
- /* 114 */
-
- /* Tamper Push Button */
- 0x85, 0x06, /* REPORT_ID (6) */
- 0x09, 0x06, /* USAGE (Tamper Push Button) */
- 0x15, 0x00, /* LOGICAL_MINIMUM (0) */
- 0x25, 0x01, /* LOGICAL_MAXIMUM (1) */
- 0x75, 0x01, /* REPORT_SIZE (1) */
- 0x81, 0x82, /* INPUT (Data,Var,Abs,Vol) */
-
- 0x09, 0x06, /* USAGE (Tamper Push Button) */
- 0x75, 0x01, /* REPORT_SIZE (1) */
- 0xb1, 0x82, /* FEATURE (Data,Var,Abs,Vol) */
-
- 0x75, 0x07, /* REPORT_SIZE (7) */
- 0x81, 0x83, /* INPUT (Cnst,Var,Abs,Vol) */
- 0x85, 0x06, /* REPORT_ID (6) */
-
- 0x75, 0x07, /* REPORT_SIZE (7) */
- 0xb1, 0x83, /* FEATURE (Cnst,Var,Abs,Vol) */
- /* 142 */
-
- /* ADC IN */
- 0x85, 0x07, /* REPORT_ID (7) */
- 0x09, 0x07, /* USAGE (ADC IN) */
- 0x15, 0x00, /* LOGICAL_MINIMUM (0) */
- 0x26, 0xff, 0x00, /* LOGICAL_MAXIMUM (255) */
- 0x75, 0x08, /* REPORT_SIZE (8) */
- 0x81, 0x82, /* INPUT (Data,Var,Abs,Vol) */
- 0x85, 0x07, /* REPORT_ID (7) */
- 0x09, 0x07, /* USAGE (ADC in) */
- 0xb1, 0x82, /* FEATURE (Data,Var,Abs,Vol) */
- /* 161 */
-
- 0xc0 /* END_COLLECTION */
-}; /* CustomHID_ReportDescriptor */
-
-/* Private function ----------------------------------------------------------*/
-/**
- * @brief USBD_HID_Init
- * Initialize the HID interface
- * @param pdev: device instance
- * @param cfgidx: Configuration index
- * @retval status
- */
-uint8_t USBD_HID_Init (void *pdev,
- uint8_t cfgidx)
-{
- DCD_PMA_Config(pdev , HID_IN_EP,USB_SNG_BUF,HID_IN_TX_ADDRESS);
- DCD_PMA_Config(pdev , HID_OUT_EP,USB_SNG_BUF,HID_OUT_RX_ADDRESS);
-
- /* Open EP IN */
- DCD_EP_Open(pdev,
- HID_IN_EP,
- HID_IN_PACKET,
- USB_EP_INT);
-
- /* Open EP OUT */
- DCD_EP_Open(pdev,
- HID_OUT_EP,
- HID_OUT_PACKET,
- USB_EP_INT);
-
- /*Receive Data*/
- DCD_EP_PrepareRx(pdev,HID_OUT_EP,Report_buf,2);
-
- return USBD_OK;
-}
-
-/**
- * @brief USBD_HID_Init
- * DeInitialize the HID layer
- * @param pdev: device instance
- * @param cfgidx: Configuration index
- * @retval status
- */
-uint8_t USBD_HID_DeInit (void *pdev,
- uint8_t cfgidx)
-{
- /* Close HID EPs */
- DCD_EP_Close (pdev , HID_IN_EP);
- DCD_EP_Close (pdev , HID_OUT_EP);
-
- return USBD_OK;
-}
-
-/**
- * @brief USBD_HID_Setup
- * Handle the HID specific requests
- * @param pdev: instance
- * @param req: usb requests
- * @retval status
- */
-uint8_t USBD_HID_Setup (void *pdev,
- USB_SETUP_REQ *req)
-{
- uint8_t USBD_HID_Report_LENGTH=0;
- uint16_t len = 0;
- uint8_t *pbuf = NULL;
-
-
- switch (req->bmRequest & USB_REQ_TYPE_MASK)
- {
- case USB_REQ_TYPE_CLASS :
- switch (req->bRequest)
- {
- case HID_REQ_SET_PROTOCOL:
- USBD_HID_Protocol = (uint8_t)(req->wValue);
- break;
-
- case HID_REQ_GET_PROTOCOL:
- USBD_CtlSendData (pdev,
- (uint8_t *)&USBD_HID_Protocol,
- 1);
- break;
-
- case HID_REQ_SET_IDLE:
- USBD_HID_IdleState = (uint8_t)(req->wValue >> 8);
- break;
-
- case HID_REQ_GET_IDLE:
- USBD_CtlSendData (pdev,
- (uint8_t *)&USBD_HID_IdleState,
- 1);
- break;
-
- case HID_REQ_SET_REPORT:
- flag = 1;
- USBD_HID_Report_ID = (uint8_t)(req->wValue);
- USBD_HID_Report_LENGTH = (uint8_t)(req->wLength);
- USBD_CtlPrepareRx (pdev, Report_buf, USBD_HID_Report_LENGTH);
-
- break;
-
- default:
- USBD_CtlError (pdev, req);
- return USBD_FAIL;
- }
- break;
-
- case USB_REQ_TYPE_STANDARD:
- switch (req->bRequest)
- {
- case USB_REQ_GET_DESCRIPTOR:
- if( req->wValue >> 8 == HID_REPORT_DESC)
- {
- len = MIN(CUSTOMHID_SIZ_REPORT_DESC , req->wLength);
- pbuf = (uint8_t*)CustomHID_ReportDescriptor;
- }
- else if( req->wValue >> 8 == HID_DESCRIPTOR_TYPE)
- {
- pbuf = (uint8_t*)USBD_HID_CfgDesc + 0x12;
- len = MIN(USB_HID_DESC_SIZ , req->wLength);
- }
-
- USBD_CtlSendData (pdev,
- pbuf,
- len);
-
- break;
-
- case USB_REQ_GET_INTERFACE :
- USBD_CtlSendData (pdev,
- (uint8_t *)&USBD_HID_AltSet,
- 1);
- break;
-
- case USB_REQ_SET_INTERFACE :
- USBD_HID_AltSet = (uint8_t)(req->wValue);
- break;
- }
- }
- return USBD_OK;
-}
-
-/**
- * @brief USBD_HID_SendReport
- * Send HID Report
- * @param pdev: device instance
- * @param buff: pointer to report
- * @retval status
- */
-uint8_t USBD_HID_SendReport (USB_CORE_HANDLE *pdev,
- uint8_t *report,
- uint16_t len)
-{
- /* Check if USB is configured */
- if (pdev->dev.device_status == USB_CONFIGURED )
- {
- DCD_EP_Tx (pdev, HID_IN_EP, report, len);
- }
- return USBD_OK;
-}
-
-/**
- * @brief USBD_HID_GetCfgDesc
- * return configuration descriptor
- * @param speed : current device speed
- * @param length : pointer data length
- * @retval pointer to descriptor buffer
- */
-uint8_t *USBD_HID_GetCfgDesc (uint8_t speed, uint16_t *length)
-{
- *length = sizeof (USBD_HID_CfgDesc);
- return (uint8_t*)USBD_HID_CfgDesc;
-}
-
-/**
- * @brief USBD_HID_DataIn
- * handle data IN Stage
- * @param pdev: device instance
- * @param epnum: endpoint index
- * @retval status
- */
-uint8_t USBD_HID_DataIn (void *pdev,
- uint8_t epnum)
-{
- if (epnum == 1) PrevXferDone = 1;
-
- return USBD_OK;
-}
-
-/**
- * @brief USBD_HID_DataOut
- * handle data IN Stage
- * @param pdev: device instance
- * @param epnum: endpoint index
- * @retval status
- */
-uint8_t USBD_HID_DataOut (void *pdev,
- uint8_t epnum)
-{
-
- BitAction Led_State;
- if (epnum == 1)
- {
- if (Report_buf[1] == 0)
- {
- Led_State = Bit_RESET;
- }
- else
- {
- Led_State = Bit_SET;
- }
-
- switch (Report_buf[0])
- {
- case 1: /* Led 1 */
- if (Led_State != Bit_RESET)
- {
- STM_EVAL_LEDOn(LED1);
- }
- else
- {
- STM_EVAL_LEDOff(LED1);
- }
- break;
-
- case 2: /* Led 2 */
- if (Led_State != Bit_RESET)
- {
- STM_EVAL_LEDOn(LED2);
- }
- else
- {
- STM_EVAL_LEDOff(LED2);
- }
- break;
- case 3: /* Led 3 */
- if (Led_State != Bit_RESET)
- {
- STM_EVAL_LEDOn(LED3);
- }
- else
- {
- STM_EVAL_LEDOff(LED3);
- }
- break;
- case 4: /* Led 4 */
- if (Led_State != Bit_RESET)
- {
- STM_EVAL_LEDOn(LED4);
- }
- else
- {
- STM_EVAL_LEDOff(LED4);
- }
- break;
- default:
- STM_EVAL_LEDOff(LED1);
- STM_EVAL_LEDOff(LED2);
- STM_EVAL_LEDOff(LED3);
- STM_EVAL_LEDOff(LED4);
- break;
- }
- }
-
- DCD_EP_PrepareRx(pdev,HID_IN_EP,Report_buf,2);
-
- return USBD_OK;
-}
-
-/**
- * @brief USBD_HID_EP0_RxReady
- * Handles control request data.
- * @param pdev: device instance
- * @param epnum: endpoint index
- * @retval status
- */
-
-uint8_t USBD_HID_EP0_RxReady(void *pdev)
-{
- BitAction Led_State;
-
- if (flag == 1)
- {
- flag = 0;
- if (Report_buf[1] == 0)
- {
- Led_State = Bit_RESET;
- }
- else
- {
- Led_State = Bit_SET;
- }
-
- switch (Report_buf[0])
- {
- case 1: /* Led 1 */
- if (Led_State != Bit_RESET)
- {
- STM_EVAL_LEDOn(LED1);
- }
- else
- {
- STM_EVAL_LEDOff(LED1);
- }
- break;
-
- case 2: /* Led 2 */
- if (Led_State != Bit_RESET)
- {
- STM_EVAL_LEDOn(LED2);
- }
- else
- {
- STM_EVAL_LEDOff(LED2);
- }
- break;
- case 3: /* Led 3 */
- if (Led_State != Bit_RESET)
- {
- STM_EVAL_LEDOn(LED3);
- }
- else
- {
- STM_EVAL_LEDOff(LED3);
- }
- break;
- case 4: /* Led 4 */
- if (Led_State != Bit_RESET)
- {
- STM_EVAL_LEDOn(LED4);
- }
- else
- {
- STM_EVAL_LEDOff(LED4);
- }
- break;
- default:
- STM_EVAL_LEDOff(LED1);
- STM_EVAL_LEDOff(LED2);
- STM_EVAL_LEDOff(LED3);
- STM_EVAL_LEDOff(LED4);
- break;
- }
- }
- return USBD_OK;
-}
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/hid/src/usbd_hid_core.c b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/hid/src/usbd_hid_core.c
deleted file mode 100644
index a108423137ecb6e80f94844b632d214b0a3ef6cf..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/hid/src/usbd_hid_core.c
+++ /dev/null
@@ -1,342 +0,0 @@
-/**
- ******************************************************************************
- * @file usbd_hid_core.c
- * @author MCD Application Team
- * @version V1.0.1
- * @date 31-January-2014
- * @brief This file provides the HID core functions.
- *
- * @verbatim
- *
- * ===================================================================
- * HID Class Description
- * ===================================================================
- * This module manages the HID class V1.11 following the "Device Class Definition
- * for Human Interface Devices (HID) Version 1.11 Jun 27, 2001".
- * This driver implements the following aspects of the specification:
- * - The Boot Interface Subclass
- * - The Mouse protocol
- * - Usage Page : Generic Desktop
- * - Usage : Joystick
- * - Collection : Application
- *
- *
- * @endverbatim
- *
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_hid_core.h"
-
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-static uint8_t USBD_HID_Init (void *pdev,
- uint8_t cfgidx);
-
-static uint8_t USBD_HID_DeInit (void *pdev,
- uint8_t cfgidx);
-
-static uint8_t USBD_HID_Setup (void *pdev,
- USB_SETUP_REQ *req);
-
-static uint8_t *USBD_HID_GetCfgDesc (uint8_t speed, uint16_t *length);
-
-USBD_Class_cb_TypeDef USBD_HID_cb =
-{
- USBD_HID_Init,
- USBD_HID_DeInit,
- USBD_HID_Setup,
- NULL, /*EP0_TxSent*/
- NULL, /*EP0_RxReady*/
- NULL, /*DataIn*/
- NULL, /*DataOut*/
- NULL, /*SOF */
- USBD_HID_GetCfgDesc,
-};
-
-static uint32_t USBD_HID_AltSet = 0;
-
-static uint32_t USBD_HID_Protocol = 0;
-
-static uint32_t USBD_HID_IdleState = 0;
-
-/* USB HID device Configuration Descriptor */
-const uint8_t USBD_HID_CfgDesc[USB_HID_CONFIG_DESC_SIZ] =
-{
- 0x09, /* bLength: Configuration Descriptor size */
- USB_CONFIGURATION_DESCRIPTOR_TYPE, /* bDescriptorType: Configuration */
- USB_HID_CONFIG_DESC_SIZ,
- /* wTotalLength: Bytes returned */
- 0x00,
- 0x01, /*bNumInterfaces: 1 interface*/
- 0x01, /*bConfigurationValue: Configuration value*/
- 0x00, /*iConfiguration: Index of string descriptor describing
- the configuration*/
- 0xE0, /*bmAttributes: bus powered and Support Remote Wake-up */
- 0x32, /*MaxPower 100 mA: this current is used for detecting Vbus*/
-
- /************** Descriptor of Joystick Mouse interface ****************/
- /* 09 */
- 0x09, /*bLength: Interface Descriptor size*/
- USB_INTERFACE_DESCRIPTOR_TYPE,/*bDescriptorType: Interface descriptor type*/
- 0x00, /*bInterfaceNumber: Number of Interface*/
- 0x00, /*bAlternateSetting: Alternate setting*/
- 0x01, /*bNumEndpoints*/
- 0x03, /*bInterfaceClass: HID*/
- 0x01, /*bInterfaceSubClass : 1=BOOT, 0=no boot*/
- 0x02, /*nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse*/
- 0, /*iInterface: Index of string descriptor*/
- /******************** Descriptor of Joystick Mouse HID ********************/
- /* 18 */
- 0x09, /*bLength: HID Descriptor size*/
- HID_DESCRIPTOR_TYPE, /*bDescriptorType: HID*/
- 0x11, /*bcdHID: HID Class Spec release number*/
- 0x01,
- 0x00, /*bCountryCode: Hardware target country*/
- 0x01, /*bNumDescriptors: Number of HID class descriptors to follow*/
- 0x22, /*bDescriptorType*/
- HID_MOUSE_REPORT_DESC_SIZE,/*wItemLength: Total length of Report descriptor*/
- 0x00,
- /******************** Descriptor of Mouse endpoint ********************/
- /* 27 */
- 0x07, /*bLength: Endpoint Descriptor size*/
- USB_ENDPOINT_DESCRIPTOR_TYPE, /*bDescriptorType:*/
-
- HID_IN_EP, /*bEndpointAddress: Endpoint Address (IN)*/
- 0x03, /*bmAttributes: Interrupt endpoint*/
- HID_IN_PACKET, /*wMaxPacketSize: 4 Byte max */
- 0x00,
- 0x0A, /*bInterval: Polling Interval (10 ms)*/
- /* 34 */
-} ;
-
-const uint8_t HID_MOUSE_ReportDesc[HID_MOUSE_REPORT_DESC_SIZE] =
-{
- 0x05, 0x01,
- 0x09, 0x02,
- 0xA1, 0x01,
- 0x09, 0x01,
-
- 0xA1, 0x00,
- 0x05, 0x09,
- 0x19, 0x01,
- 0x29, 0x03,
-
- 0x15, 0x00,
- 0x25, 0x01,
- 0x95, 0x03,
- 0x75, 0x01,
-
- 0x81, 0x02,
- 0x95, 0x01,
- 0x75, 0x05,
- 0x81, 0x01,
-
- 0x05, 0x01,
- 0x09, 0x30,
- 0x09, 0x31,
- 0x09, 0x38,
-
- 0x15, 0x81,
- 0x25, 0x7F,
- 0x75, 0x08,
- 0x95, 0x03,
-
- 0x81, 0x06,
- 0xC0, 0x09,
- 0x3c, 0x05,
- 0xff, 0x09,
-
- 0x01, 0x15,
- 0x00, 0x25,
- 0x01, 0x75,
- 0x01, 0x95,
-
- 0x02, 0xb1,
- 0x22, 0x75,
- 0x06, 0x95,
- 0x01, 0xb1,
-
- 0x01, 0xc0
-};
-
-/* Private function ----------------------------------------------------------*/
-/**
- * @brief USBD_HID_Init
- * Initialize the HID interface
- * @param pdev: device instance
- * @param cfgidx: Configuration index
- * @retval status
- */
-static uint8_t USBD_HID_Init (void *pdev,
- uint8_t cfgidx)
-{
- DCD_PMA_Config(pdev , HID_IN_EP,USB_SNG_BUF,HID_IN_TX_ADDRESS);
-
- /* Open EP IN */
- DCD_EP_Open(pdev,
- HID_IN_EP,
- HID_IN_PACKET,
- USB_EP_INT);
-
- /* Open EP OUT */
- DCD_EP_Open(pdev,
- HID_OUT_EP,
- HID_OUT_PACKET,
- USB_EP_INT);
-
- return USBD_OK;
-}
-
-/**
- * @brief USBD_HID_Init
- * DeInitialize the HID layer
- * @param pdev: device instance
- * @param cfgidx: Configuration index
- * @retval status
- */
-static uint8_t USBD_HID_DeInit (void *pdev,
- uint8_t cfgidx)
-{
- /* Close HID EPs */
- DCD_EP_Close (pdev , HID_IN_EP);
- DCD_EP_Close (pdev , HID_OUT_EP);
-
-
- return USBD_OK;
-}
-
-/**
- * @brief USBD_HID_Setup
- * Handle the HID specific requests
- * @param pdev: instance
- * @param req: usb requests
- * @retval status
- */
-static uint8_t USBD_HID_Setup (void *pdev,
- USB_SETUP_REQ *req)
-{
- uint16_t len = 0;
- uint8_t *pbuf = NULL;
-
- switch (req->bmRequest & USB_REQ_TYPE_MASK)
- {
- case USB_REQ_TYPE_CLASS :
- switch (req->bRequest)
- {
- case HID_REQ_SET_PROTOCOL:
- USBD_HID_Protocol = (uint8_t)(req->wValue);
- break;
-
- case HID_REQ_GET_PROTOCOL:
- USBD_CtlSendData (pdev,
- (uint8_t *)&USBD_HID_Protocol,
- 1);
- break;
-
- case HID_REQ_SET_IDLE:
- USBD_HID_IdleState = (uint8_t)(req->wValue >> 8);
- break;
-
- case HID_REQ_GET_IDLE:
- USBD_CtlSendData (pdev,
- (uint8_t *)&USBD_HID_IdleState,
- 1);
- break;
-
- default:
- USBD_CtlError (pdev, req);
- return USBD_FAIL;
- }
- break;
-
- case USB_REQ_TYPE_STANDARD:
- switch (req->bRequest)
- {
- case USB_REQ_GET_DESCRIPTOR:
- if( req->wValue >> 8 == HID_REPORT_DESC)
- {
- len = MIN(HID_MOUSE_REPORT_DESC_SIZE , req->wLength);
- pbuf = (uint8_t *)HID_MOUSE_ReportDesc;
- }
- else if( req->wValue >> 8 == HID_DESCRIPTOR_TYPE)
- {
- pbuf = (uint8_t *)USBD_HID_CfgDesc + 0x12;
- len = MIN(USB_HID_DESC_SIZ , req->wLength);
- }
-
- USBD_CtlSendData (pdev,
- pbuf,
- len);
-
- break;
-
- case USB_REQ_GET_INTERFACE :
- USBD_CtlSendData (pdev,
- (uint8_t *)&USBD_HID_AltSet,
- 1);
- break;
-
- case USB_REQ_SET_INTERFACE :
- USBD_HID_AltSet = (uint8_t)(req->wValue);
- break;
- }
- }
- return USBD_OK;
-}
-
-/**
- * @brief USBD_HID_SendReport
- * Send HID Report
- * @param pdev: device instance
- * @param buff: pointer to report
- * @retval status
- */
-uint8_t USBD_HID_SendReport (USB_CORE_HANDLE *pdev,
- uint8_t *report,
- uint16_t len)
-{
- /* Check if USB is configured */
- if (pdev->dev.device_status == USB_CONFIGURED )
- {
- DCD_EP_Tx (pdev, HID_IN_EP, report, len);
- }
- return USBD_OK;
-}
-
-/**
- * @brief USBD_HID_GetCfgDesc
- * return configuration descriptor
- * @param speed : current device speed
- * @param length : pointer data length
- * @retval pointer to descriptor buffer
- */
-static uint8_t *USBD_HID_GetCfgDesc (uint8_t speed, uint16_t *length)
-{
- *length = sizeof (USBD_HID_CfgDesc);
- return (uint8_t *)USBD_HID_CfgDesc;
-}
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/hid_cdc_wrapper/inc/usbd_hid_cdc_wrapper.h b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/hid_cdc_wrapper/inc/usbd_hid_cdc_wrapper.h
deleted file mode 100644
index 7f9358e556b26f3f54eb4e74468383c697227aa1..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/hid_cdc_wrapper/inc/usbd_hid_cdc_wrapper.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/**
- ******************************************************************************
- * @file usbd_hid_cdc_wrapper.h
- * @author MCD Application Team
- * @version V1.0.1
- * @date 31-January-2014
- * @brief header file for the usbd_hid_cdc_wrapper.c file.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __USB_HID_CDC_WRAPPER_H_
-#define __USB_HID_CDC_WRAPPER_H_
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_custom_hid_core.h"
-#include "usbd_cdc_core.h"
-
-/* Exported defines ----------------------------------------------------------*/
-#define HID_INTERFACE 0x0
-#define CDC_COM_INTERFACE 0x1
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported macros -----------------------------------------------------------*/
-#define USB_HID_CDC_CONFIG_DESC_SIZ (CUSTOMHID_SIZ_CONFIG_DESC -9 + USB_CDC_CONFIG_DESC_SIZ + 8)
-
-/* Exported variables --------------------------------------------------------*/
-extern USBD_Class_cb_TypeDef USBD_HID_CDC_cb;
-
-/* Exported functions ------------------------------------------------------- */
-
-#endif /* __USB_HID_CDC_WRAPPER_H_ */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/hid_cdc_wrapper/src/usbd_hid_cdc_wrapper.c b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/hid_cdc_wrapper/src/usbd_hid_cdc_wrapper.c
deleted file mode 100644
index f17ec255c2ff688ef6fbe0328a1ae54e41fc65d8..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/hid_cdc_wrapper/src/usbd_hid_cdc_wrapper.c
+++ /dev/null
@@ -1,404 +0,0 @@
-/**
- ******************************************************************************
- * @file usbd_cdc_hid_wrapper.c
- * @author MCD Application Team
- * @version V1.0.1
- * @date 31-January-2014
- * @brief This file calls to the separate CDC and HID class layer handlers.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- *******************************************************************************/
- /*
- * ===================================================================
- * composite CDC_HID
- * =================================================================== */
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_hid_cdc_wrapper.h"
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* USBD_CDC_HID_Private_Variables */
-static uint8_t USBD_HID_CDC_Init (void *pdev , uint8_t cfgidx);
-static uint8_t USBD_HID_CDC_DeInit (void *pdev , uint8_t cfgidx);
-
-/* Control Endpoints*/
-static uint8_t USBD_HID_CDC_Setup (void *pdev , USB_SETUP_REQ *req);
-static uint8_t USBD_HID_CDC_EP0_RxReady (void *pdev);
-/* Class Specific Endpoints*/
-static uint8_t USBD_HID_CDC_DataIn (void *pdev , uint8_t epnum);
-static uint8_t USBD_HID_CDC_DataOut (void *pdev , uint8_t epnum);
-static uint8_t USBD_HID_CDC_SOF (void *pdev);
-
-static uint8_t* USBD_HID_CDC_GetConfigDescriptor( uint8_t speed , uint16_t *length);
-
-/* HID_CDC_CORE_Private_Variables */
-USBD_Class_cb_TypeDef USBD_HID_CDC_cb =
-{
- USBD_HID_CDC_Init,
- USBD_HID_CDC_DeInit,
- USBD_HID_CDC_Setup,
- NULL,
- USBD_HID_CDC_EP0_RxReady,
- USBD_HID_CDC_DataIn,
- USBD_HID_CDC_DataOut,
- USBD_HID_CDC_SOF,
- USBD_HID_CDC_GetConfigDescriptor,
-};
-
-/* USB CDC_HID device Configuration Descriptor */
-const uint8_t USBD_HID_CDC_CfgDesc[USB_HID_CDC_CONFIG_DESC_SIZ] =
-{
- 0x09, /* bLength: Configuration Descriptor size */
- USB_CONFIGURATION_DESCRIPTOR_TYPE, /* bDescriptorType: Configuration */
- USB_HID_CDC_CONFIG_DESC_SIZ,
- /* wTotalLength: Bytes returned */
- 0x00,
- 0x03, /*bNumInterfaces: 3 interfaces (2 for CDC, 1 for HID)*/
- 0x01, /*bConfigurationValue: Configuration value*/
- 0x00, /*iConfiguration: Index of string descriptor describing
- the configuration*/
- 0xE0, /*bmAttributes: bus powered and Support Remote Wake-up */
- 0x32, /*MaxPower 100 mA: this current is used for detecting Vbus*/
-
- /************** Descriptor of CUSTOM HID interface ****************/
- /* 09 */
- 0x09, /*bLength: Interface Descriptor size*/
- USB_INTERFACE_DESCRIPTOR_TYPE,/*bDescriptorType: Interface descriptor type*/
- HID_INTERFACE, /*bInterfaceNumber: Number of Interface*/
- 0x00, /*bAlternateSetting: Alternate setting*/
- 0x02, /*bNumEndpoints*/
- 0x03, /*bInterfaceClass: HID*/
- 0x00, /*bInterfaceSubClass : 1=BOOT, 0=no boot*/
- 0x00, /*nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse*/
- 0, /*iInterface: Index of string descriptor*/
- /******************** Descriptor of CUSTOM HID **************************/
- /* 18 */
- 0x09, /*bLength: HID Descriptor size*/
- HID_DESCRIPTOR_TYPE, /*bDescriptorType: HID*/
- 0x11, /*bcdHID: HID Class Spec release number*/
- 0x01,
- 0x00, /*bCountryCode: Hardware target country*/
- 0x01, /*bNumDescriptors: Number of HID class descriptors to follow*/
- 0x22, /*bDescriptorType*/
- CUSTOMHID_SIZ_REPORT_DESC,/*wItemLength: Total length of Report descriptor*/
- 0x00,
- /******************** Descriptor of CUSTOM HID endpoint *********************/
- /* 27 */
- 0x07, /*bLength: Endpoint Descriptor size*/
- USB_ENDPOINT_DESCRIPTOR_TYPE, /*bDescriptorType:*/
-
- HID_IN_EP, /*bEndpointAddress: Endpoint Address (IN)*/
- 0x03, /*bmAttributes: Interrupt endpoint*/
- HID_IN_PACKET, /*wMaxPacketSize: 2 Byte max */
- 0x00,
- 0x20, /*bInterval: Polling Interval (32 ms)*/
- /* 34 */
-
- 0x07, /* bLength: Endpoint Descriptor size */
- USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: */
- /* Endpoint descriptor type */
- HID_OUT_EP, /* bEndpointAddress: */
- /* Endpoint Address (OUT) */
- 0x03, /* bmAttributes: Interrupt endpoint */
- HID_OUT_PACKET, /* wMaxPacketSize: 2 Bytes max */
- 0x00,
- 0x20, /* bInterval: Polling Interval (20 ms) */
- /* 41 */
-
- /******** IAD should be positioned just before the CDC interfaces ******
- IAD to associate the two CDC interfaces */
-
- 0x08, /* bLength */
- 0x0B, /* bDescriptorType */
- 0x01, /* bFirstInterface */
- 0x02, /* bInterfaceCount */
- 0x02, /* bFunctionClass */
- 0x02, /* bFunctionSubClass */
- 0x01, /* bFunctionProtocol */
- 0x00, /* iFunction (Index of string descriptor describing this function) */
-
- /*************************** CDC interfaces *******************************/
-
- /*Interface Descriptor */
- 0x09, /* bLength: Interface Descriptor size */
- USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType: Interface */
- /* Interface descriptor type */
- CDC_COM_INTERFACE, /* bInterfaceNumber: Number of Interface */
- 0x00, /* bAlternateSetting: Alternate setting */
- 0x01, /* bNumEndpoints: One endpoints used */
- 0x02, /* bInterfaceClass: Communication Interface Class */
- 0x02, /* bInterfaceSubClass: Abstract Control Model */
- 0x01, /* bInterfaceProtocol: Common AT commands */
- 0x01, /* iInterface: */
-
- /*Header Functional Descriptor*/
- 0x05, /* bLength: Endpoint Descriptor size */
- 0x24, /* bDescriptorType: CS_INTERFACE */
- 0x00, /* bDescriptorSubtype: Header Func Desc */
- 0x10, /* bcdCDC: spec release number */
- 0x01,
-
- /*Call Management Functional Descriptor*/
- 0x05, /* bFunctionLength */
- 0x24, /* bDescriptorType: CS_INTERFACE */
- 0x01, /* bDescriptorSubtype: Call Management Func Desc */
- 0x00, /* bmCapabilities: D0+D1 */
- 0x02, /* bDataInterface: 2 */
-
- /*ACM Functional Descriptor*/
- 0x04, /* bFunctionLength */
- 0x24, /* bDescriptorType: CS_INTERFACE */
- 0x02, /* bDescriptorSubtype: Abstract Control Management desc */
- 0x02, /* bmCapabilities */
-
- /*Union Functional Descriptor*/
- 0x05, /* bFunctionLength */
- 0x24, /* bDescriptorType: CS_INTERFACE */
- 0x06, /* bDescriptorSubtype: Union func desc */
- 0x01, /* bMasterInterface: Communication class interface */
- 0x02, /* bSlaveInterface0: Data Class Interface */
-
- /*Endpoint 2 Descriptor*/
- 0x07, /* bLength: Endpoint Descriptor size */
- USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: Endpoint */
- CDC_CMD_EP, /* bEndpointAddress */
- 0x03, /* bmAttributes: Interrupt */
- LOBYTE(CDC_CMD_PACKET_SZE), /* wMaxPacketSize: */
- HIBYTE(CDC_CMD_PACKET_SZE),
- 0xFF, /* bInterval: */
-
- /*---------------------------------------------------------------------------*/
-
- /*Data class interface descriptor*/
- 0x09, /* bLength: Endpoint Descriptor size */
- USB_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType: */
- 0x02, /* bInterfaceNumber: Number of Interface */
- 0x00, /* bAlternateSetting: Alternate setting */
- 0x02, /* bNumEndpoints: Two endpoints used */
- 0x0A, /* bInterfaceClass: CDC */
- 0x00, /* bInterfaceSubClass: */
- 0x00, /* bInterfaceProtocol: */
- 0x00, /* iInterface: */
-
- /*Endpoint OUT Descriptor*/
- 0x07, /* bLength: Endpoint Descriptor size */
- USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: Endpoint */
- CDC_OUT_EP, /* bEndpointAddress */
- 0x02, /* bmAttributes: Bulk */
- 0x40, /* wMaxPacketSize: */
- 0x00,
- 0x00, /* bInterval: ignore for Bulk transfer */
-
- /*Endpoint IN Descriptor*/
- 0x07, /* bLength: Endpoint Descriptor size */
- USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: Endpoint */
- CDC_IN_EP, /* bEndpointAddress */
- 0x02, /* bmAttributes: Bulk */
- 0x40, /* wMaxPacketSize: */
- 0x00,
- 0x00, /* bInterval */
-
-}; /* USBD_HID_CDC_CfgDesc */
-
-/* Private function prototypes -----------------------------------------------*/
-/*********************************************
- CDC Device library callbacks
-*********************************************/
-extern uint8_t usbd_cdc_Init (void *pdev, uint8_t cfgidx);
-extern uint8_t usbd_cdc_DeInit (void *pdev, uint8_t cfgidx);
-extern uint8_t usbd_cdc_Setup (void *pdev, USB_SETUP_REQ *req);
-extern uint8_t usbd_cdc_EP0_RxReady (void *pdev);
-extern uint8_t usbd_cdc_DataIn (void *pdev, uint8_t epnum);
-extern uint8_t usbd_cdc_DataOut (void *pdev, uint8_t epnum);
-extern uint8_t usbd_cdc_SOF (void *pdev);
-
-/*********************************************
- HID Device library callbacks
-*********************************************/
-extern uint8_t USBD_HID_Init (void *pdev, uint8_t cfgidx);
-extern uint8_t USBD_HID_DeInit (void *pdev, uint8_t cfgidx);
-extern uint8_t USBD_HID_Setup (void *pdev, USB_SETUP_REQ *req);
-extern uint8_t *USBD_HID_GetCfgDesc (uint8_t speed, uint16_t *length);
-extern uint8_t USBD_HID_DataIn (void *pdev, uint8_t epnum);
-extern uint8_t USBD_HID_DataOut (void *pdev, uint8_t epnum);
-extern uint8_t USBD_HID_EP0_RxReady (void *pdev);
-
-/* Private function ----------------------------------------------------------*/
-/**
- * @brief USBD_HID_CDC_Init
- * Initialize the HID & CDC interfaces
- * @param pdev: device instance
- * @param cfgidx: Configuration index
- * @retval status
- */
-static uint8_t USBD_HID_CDC_Init (void *pdev,
- uint8_t cfgidx)
-{
- /* HID initialization */
- USBD_HID_Init (pdev,cfgidx);
-
- /* CDC initialization */
- usbd_cdc_Init (pdev,cfgidx);
-
- return USBD_OK;
-
-}
-
-/**
- * @brief USBD_HID_Init
- * DeInitialize the HID/CDC interfaces
- * @param pdev: device instance
- * @param cfgidx: Configuration index
- * @retval status
- */
-static uint8_t USBD_HID_CDC_DeInit (void *pdev,
- uint8_t cfgidx)
-{
- /* HID De-initialization */
- USBD_HID_DeInit (pdev,cfgidx);
-
- /* CDC De-initialization */
- usbd_cdc_DeInit (pdev,cfgidx);
-
-
- return USBD_OK;
-}
-
-/**
- * @brief USBD_HID_Setup
- * Handle the HID specific requests
- * @param pdev: instance
- * @param req: usb requests
- * @retval status
- */
-static uint8_t USBD_HID_CDC_Setup (void *pdev,
- USB_SETUP_REQ *req)
-{
- switch (req->bmRequest & USB_REQ_RECIPIENT_MASK)
- {
- case USB_REQ_RECIPIENT_INTERFACE:
- if (req->wIndex == HID_INTERFACE)
- {
- return (USBD_HID_Setup (pdev, req));
- }
- else
- {
- return (usbd_cdc_Setup(pdev, req));
- }
- case USB_REQ_RECIPIENT_ENDPOINT:
- if ((req->wIndex == HID_IN_EP) || (req->wIndex == HID_OUT_EP))
- {
- return (USBD_HID_Setup (pdev, req));
- }
- else
- {
- return (usbd_cdc_Setup(pdev, req));
- }
- }
- return USBD_OK;
-}
-
-/**
- * @brief USBD_HID_CDC_GetCfgDesc
- * return configuration descriptor
- * @param speed : current device speed
- * @param length : pointer data length
- * @retval pointer to descriptor buffer
- */
-uint8_t *USBD_HID_CDC_GetConfigDescriptor (uint8_t speed, uint16_t *length)
-{
- *length = sizeof (USBD_HID_CDC_CfgDesc);
- return (uint8_t*)USBD_HID_CDC_CfgDesc;
-}
-
-/**
- * @brief USBD_HID_CDC_DataIn
- * handle data IN Stage
- * @param pdev: device instance
- * @param epnum: endpoint index
- * @retval status
- */
-static uint8_t USBD_HID_CDC_DataIn (void *pdev,
- uint8_t epnum)
-{
- /*DataIN can be for CDC or HID */
-
- if (epnum == (CDC_IN_EP&~0x80) )
- {
- return (usbd_cdc_DataIn(pdev, epnum));
- }
- else
- {
- return (USBD_HID_DataIn(pdev, epnum));
- }
-}
-
-/**
- * @brief USBD_HID_CDC_DataOut
- * handle data OUT Stage
- * @param pdev: device instance
- * @param epnum: endpoint index
- * @retval status
- */
-uint8_t USBD_HID_CDC_DataOut(void *pdev , uint8_t epnum)
-{
- /*DataOut can be for CDC or HID */
-
- if (epnum == (CDC_OUT_EP&~0x80) )
- {
- return (usbd_cdc_DataOut(pdev, epnum));
- }
- else
- {
- return (USBD_HID_DataOut(pdev, epnum));
- }
-}
-
-/**
- * @brief USBD_HID_CDC_SOF
- * handle SOF processing
- * @param pdev: device instance
- * @param epnum: endpoint index
- * @retval status
- */
-
-uint8_t USBD_HID_CDC_SOF (void *pdev)
-{
- /*SOF processing needed for CDC */
- return (usbd_cdc_SOF(pdev));
-}
-
-/**
- * @brief USBD_HID_CDC_EP0_RxReady
- * handle RxReady processing
- * @param pdev: device istance
- * @param epnum: endpoint index
- * @retval status
- */
-static uint8_t USBD_HID_CDC_EP0_RxReady (void *pdev)
-{
- /* RxReady processing needed for CDC or HID */
- (usbd_cdc_EP0_RxReady(pdev));
- (USBD_HID_EP0_RxReady(pdev));
- return USBD_OK;
-}
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/hid_msc_wrapper/inc/usbd_hid_msc_wrapper.h b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/hid_msc_wrapper/inc/usbd_hid_msc_wrapper.h
deleted file mode 100644
index e3e60f2c04b9da6d126b76c8f039accfcf5a0789..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/hid_msc_wrapper/inc/usbd_hid_msc_wrapper.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/**
- ******************************************************************************
- * @file usbd_msc_hid_wrapper.h
- * @author MCD Application Team
- * @version V1.0.1
- * @date 31-January-2014
- * @brief header file for the usbd_msc_hid_wrapper.c file.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __USB_HID_MSC_WRAPPER_H_
-#define __USB_HID_MSC_WRAPPER_H_
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_ioreq.h"
-
-/* Exported defines ----------------------------------------------------------*/
-#define HID_INTERFACE 0x0
-#define MSC_INTERFACE 0x1
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported macros -----------------------------------------------------------*/
-#define USB_HID_MSC_CONFIG_DESC_SIZ (CUSTOMHID_SIZ_CONFIG_DESC -9 + USB_MSC_CONFIG_DESC_SIZ)
-
-/* Exported variables --------------------------------------------------------*/
-extern USBD_Class_cb_TypeDef USBD_HID_MSC_cb;
-
-/* Exported functions ------------------------------------------------------- */
-
-
-#endif /* __USB_HID_MSC_WRAPPER_H_ */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/hid_msc_wrapper/src/usbd_hid_msc_wrapper.c b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/hid_msc_wrapper/src/usbd_hid_msc_wrapper.c
deleted file mode 100644
index 1344329634eaef460b40f895973f44919a261ebf..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/hid_msc_wrapper/src/usbd_hid_msc_wrapper.c
+++ /dev/null
@@ -1,326 +0,0 @@
-/**
- ******************************************************************************
- * @file usbd_msc_hid_wrapper.c
- * @author MCD Application Team
- * @version V1.0.1
- * @date 31-January-2014
- * @brief This file calls to the separate MSC and HID class layer handlers.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- *****************************************************************************/
- /*
- * ===================================================================
- * composite MSC_HID
- * =================================================================== */
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_hid_msc_wrapper.h"
-#include "usbd_custom_hid_core.h"
-#include "usbd_msc_core.h"
-#include "usbd_desc.h"
-#include "usbd_req.h"
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-static uint8_t USBD_HID_MSC_Init (void *pdev , uint8_t cfgidx);
-static uint8_t USBD_HID_MSC_DeInit (void *pdev , uint8_t cfgidx);
-
-/* Control Endpoints*/
-static uint8_t USBD_HID_MSC_Setup (void *pdev , USB_SETUP_REQ *req);
-static uint8_t USBD_HID_MSC_EP0_RxReady (void *pdev);
-
-/* Class Specific Endpoints*/
-static uint8_t USBD_HID_MSC_DataIn (void *pdev , uint8_t epnum);
-static uint8_t USBD_HID_MSC_DataOut (void *pdev , uint8_t epnum);
-
-static uint8_t* USBD_HID_MSC_GetConfigDescriptor( uint8_t speed , uint16_t *length);
-
-USBD_Class_cb_TypeDef USBD_HID_MSC_cb =
-{
- USBD_HID_MSC_Init,
- USBD_HID_MSC_DeInit,
- USBD_HID_MSC_Setup,
- NULL,
- USBD_HID_MSC_EP0_RxReady,
- USBD_HID_MSC_DataIn,
- USBD_HID_MSC_DataOut,
- NULL,
- USBD_HID_MSC_GetConfigDescriptor,
-};
-
-
-/* USB MSC_HID device Configuration Descriptor */
-const uint8_t USBD_HID_MSC_CfgDesc[USB_HID_MSC_CONFIG_DESC_SIZ] =
-{
- 0x09, /* bLength: Configuration Descriptor size */
- USB_CONFIGURATION_DESCRIPTOR_TYPE, /* bDescriptorType: Configuration */
- USB_HID_MSC_CONFIG_DESC_SIZ,
- /* wTotalLength: Bytes returned */
- 0x00,
- 0x02, /*bNumInterfaces: 2 interfaces (1 for MSC, 1 for HID)*/
- 0x01, /*bConfigurationValue: Configuration value*/
- 0x00, /*iConfiguration: Index of string descriptor describing
- the configuration*/
- 0xE0, /*bmAttributes: bus powered and Support Remote Wake-up */
- 0x32, /*MaxPower 100 mA: this current is used for detecting Vbus*/
-
- /************** Descriptor of CUSTOM HID interface ****************/
- /* 09 */
- 0x09, /*bLength: Interface Descriptor size*/
- USB_INTERFACE_DESCRIPTOR_TYPE,/*bDescriptorType: Interface descriptor type*/
- HID_INTERFACE, /*bInterfaceNumber: Number of Interface*/
- 0x00, /*bAlternateSetting: Alternate setting*/
- 0x02, /*bNumEndpoints*/
- 0x03, /*bInterfaceClass: HID*/
- 0x00, /*bInterfaceSubClass : 1=BOOT, 0=no boot*/
- 0x00, /*nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse*/
- 0, /*iInterface: Index of string descriptor*/
- /******************** Descriptor of CUSTOM HID **************************/
- /* 18 */
- 0x09, /*bLength: HID Descriptor size*/
- HID_DESCRIPTOR_TYPE, /*bDescriptorType: HID*/
- 0x11, /*bcdHID: HID Class Spec release number*/
- 0x01,
- 0x00, /*bCountryCode: Hardware target country*/
- 0x01, /*bNumDescriptors: Number of HID class descriptors to follow*/
- 0x22, /*bDescriptorType*/
- CUSTOMHID_SIZ_REPORT_DESC,/*wItemLength: Total length of Report descriptor*/
- 0x00,
- /******************** Descriptor of CUSTOM HID endpoint *********************/
- /* 27 */
- 0x07, /*bLength: Endpoint Descriptor size*/
- USB_ENDPOINT_DESCRIPTOR_TYPE, /*bDescriptorType:*/
-
- HID_IN_EP, /*bEndpointAddress: Endpoint Address (IN)*/
- 0x03, /*bmAttributes: Interrupt endpoint*/
- HID_IN_PACKET, /*wMaxPacketSize: 2 Byte max */
- 0x00,
- 0x20, /*bInterval: Polling Interval (32 ms)*/
- /* 34 */
-
- 0x07, /* bLength: Endpoint Descriptor size */
- USB_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType: */
- /* Endpoint descriptor type */
- HID_OUT_EP, /* bEndpointAddress: */
- /* Endpoint Address (OUT) */
- 0x03, /* bmAttributes: Interrupt endpoint */
- HID_OUT_PACKET, /* wMaxPacketSize: 2 Bytes max */
- 0x00,
- 0x20, /* bInterval: Polling Interval (20 ms) */
- /* 41 */
-
- /******************** Mass Storage interface ********************/
- 0x09, /* bLength: Interface Descriptor size */
- 0x04, /* bDescriptorType: */
- MSC_INTERFACE, /* bInterfaceNumber: Number of Interface */
- 0x00, /* bAlternateSetting: Alternate setting */
- 0x02, /* bNumEndpoints*/
- 0x08, /* bInterfaceClass: MSC Class */
- 0x06, /* bInterfaceSubClass : SCSI transparent*/
- 0x50, /* nInterfaceProtocol */
- 0X01, /* iInterface: */
- /******************** Mass Storage Endpoints ********************/
- 0x07, /*Endpoint descriptor length = 7*/
- 0x05, /*Endpoint descriptor type */
- MSC_IN_EP, /*Endpoint address (IN, address 2) */
- 0x02, /*Bulk endpoint type */
- LOBYTE(MSC_MAX_PACKET),
- HIBYTE(MSC_MAX_PACKET),
- 0x00, /*Polling interval in milliseconds */
-
- 0x07, /*Endpoint descriptor length = 7 */
- 0x05, /*Endpoint descriptor type */
- MSC_OUT_EP, /*Endpoint address (OUT, address 2) */
- 0x02, /*Bulk endpoint type */
- LOBYTE(MSC_MAX_PACKET),
- HIBYTE(MSC_MAX_PACKET),
- 0x00 /*Polling interval in milliseconds*/
-
-}; /* USBD_HID_MSC_CfgDesc */
-
-/* Private function prototypes -----------------------------------------------*/
-/*********************************************
- MSC Device library callbacks
-*********************************************/
-extern uint8_t USBD_MSC_Init (void *pdev, uint8_t cfgidx);
-extern uint8_t USBD_MSC_DeInit (void *pdev, uint8_t cfgidx);
-extern uint8_t USBD_MSC_Setup (void *pdev, USB_SETUP_REQ *req);
-extern uint8_t USBD_MSC_DataIn (void *pdev, uint8_t epnum);
-extern uint8_t USBD_MSC_DataOut (void *pdev, uint8_t epnum);
-extern uint8_t *USBD_MSC_GetCfgDesc (uint8_t speed, uint16_t *length);
-extern uint8_t USBD_MSC_CfgDesc[USB_MSC_CONFIG_DESC_SIZ];
-
-/*********************************************
- HID Device library callbacks
-*********************************************/
-extern uint8_t USBD_HID_Init (void *pdev, uint8_t cfgidx);
-extern uint8_t USBD_HID_DeInit (void *pdev, uint8_t cfgidx);
-extern uint8_t USBD_HID_Setup (void *pdev, USB_SETUP_REQ *req);
-extern uint8_t *USBD_HID_GetCfgDesc (uint8_t speed, uint16_t *length);
-extern uint8_t USBD_HID_DataIn (void *pdev, uint8_t epnum);
-extern uint8_t USBD_HID_DataOut (void *pdev, uint8_t epnum);
-extern uint8_t USBD_HID_EP0_RxReady (void *pdev);
-
-/* Private functions ---------------------------------------------------------*/
-
-/**
- * @brief USBD_HID_MSC_Init
- * Initialize the HID & MSC interfaces
- * @param pdev: device instance
- * @param cfgidx: Configuration index
- * @retval status
- */
-static uint8_t USBD_HID_MSC_Init (void *pdev,
- uint8_t cfgidx)
-{
- /* HID initialization */
- USBD_HID_Init (pdev,cfgidx);
-
- /* MSC initialization */
- USBD_MSC_Init (pdev,cfgidx);
-
- return USBD_OK;
-
-}
-
-/**
- * @brief USBD_HID_Init
- * DeInitialize the HID/CDC interfaces
- * @param pdev: device instance
- * @param cfgidx: Configuration index
- * @retval status
- */
-static uint8_t USBD_HID_MSC_DeInit (void *pdev,
- uint8_t cfgidx)
-{
- /* HID De-initialization */
- USBD_HID_DeInit (pdev,cfgidx);
-
- /* CDC De-initialization */
- USBD_MSC_DeInit (pdev,cfgidx);
-
-
- return USBD_OK;
-}
-
-/**
- * @brief USBD_HID_Setup
- * Handle the HID specific requests
- * @param pdev: instance
- * @param req: usb requests
- * @retval status
- */
-static uint8_t USBD_HID_MSC_Setup (void *pdev,
- USB_SETUP_REQ *req)
-{
- switch (req->bmRequest & USB_REQ_RECIPIENT_MASK)
- {
- case USB_REQ_RECIPIENT_INTERFACE:
- if (req->wIndex == HID_INTERFACE)
- {
- return (USBD_HID_Setup (pdev, req));
- }
- else
- {
- return (USBD_MSC_Setup(pdev, req));
- }
- case USB_REQ_RECIPIENT_ENDPOINT:
- if ((req->wIndex == HID_IN_EP) || (req->wIndex == HID_OUT_EP))
- {
- return (USBD_HID_Setup (pdev, req));
- }
- else
- {
- return (USBD_MSC_Setup(pdev, req));
- }
- }
- return USBD_OK;
-}
-
-/**
- * @brief USBD_HID_MSC_GetCfgDesc
- * return configuration descriptor
- * @param speed : current device speed
- * @param length : pointer data length
- * @retval pointer to descriptor buffer
- */
-uint8_t *USBD_HID_MSC_GetConfigDescriptor (uint8_t speed, uint16_t *length)
-{
- *length = sizeof (USBD_HID_MSC_CfgDesc);
- return (uint8_t*)USBD_HID_MSC_CfgDesc;
-}
-
-/**
- * @brief USBD_HID_MSC_DataIn
- * handle data IN Stage
- * @param pdev: device instance
- * @param epnum: endpoint index
- * @retval status
- */
-static uint8_t USBD_HID_MSC_DataIn (void *pdev,
- uint8_t epnum)
-{
- /*DataIN can be for MSC or HID */
-
- if (epnum == (MSC_IN_EP&~0x80) )
- {
- return (USBD_MSC_DataIn(pdev, epnum));
- }
- else
- {
- return (USBD_HID_DataIn(pdev, epnum));
- }
-}
-
-/**
- * @brief USBD_HID_MSC_DataOut
- * handle data OUT Stage
- * @param pdev: device instance
- * @param epnum: endpoint index
- * @retval status
- */
-static uint8_t USBD_HID_MSC_DataOut(void *pdev , uint8_t epnum)
-{
- /*DataOut can be for MSC or HID */
-
- if (epnum == (MSC_OUT_EP&~0x80) )
- {
- return (USBD_MSC_DataOut(pdev, epnum));
- }
- else
- {
- return (USBD_HID_DataOut(pdev, epnum));
- }
-}
-
-/**
- * @brief USBD_HID_MSC_EP0_RxReady
- * handle RxReady processing
- * @param pdev: device instance
- * @param epnum: endpoint index
- * @retval status
- */
-uint8_t USBD_HID_MSC_EP0_RxReady (void *pdev)
-{
- /*RxReady processing needed for Custom HID only*/
- return (USBD_HID_EP0_RxReady(pdev));
-}
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/msc/inc/usbd_msc_bot.h b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/msc/inc/usbd_msc_bot.h
deleted file mode 100644
index a76b96d5a006d91cb9b8fb3e9581dcf6e1565f72..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/msc/inc/usbd_msc_bot.h
+++ /dev/null
@@ -1,116 +0,0 @@
-/**
- ******************************************************************************
- * @file usbd_msc_bot.h
- * @author MCD Application Team
- * @version V1.0.1
- * @date 31-January-2014
- * @brief header for the usbd_msc_bot.c file
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __USBD_MSC_BOT_H
-#define __USBD_MSC_BOT_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_core.h"
-#include "usbd_msc_scsi.h"
-#include "usbd_ioreq.h"
-#include "usbd_msc_mem.h"
-
-/* Exported defines ----------------------------------------------------------*/
-#define BOT_IDLE 0 /* Idle state */
-#define BOT_DATA_OUT 1 /* Data Out state */
-#define BOT_DATA_IN 2 /* Data In state */
-#define BOT_LAST_DATA_IN 3 /* Last Data In Last */
-#define BOT_SEND_DATA 4 /* Send Immediate data */
-
-#define BOT_CBW_SIGNATURE 0x43425355
-#define BOT_CSW_SIGNATURE 0x53425355
-#define BOT_CBW_LENGTH 31
-#define BOT_CSW_LENGTH 13
-
-/* CSW Status Definitions */
-#define CSW_CMD_PASSED 0x00
-#define CSW_CMD_FAILED 0x01
-#define CSW_PHASE_ERROR 0x02
-
-/* BOT Status */
-#define BOT_STATE_NORMAL 0
-#define BOT_STATE_RECOVERY 1
-#define BOT_STATE_ERROR 2
-
-
-#define DIR_IN 0
-#define DIR_OUT 1
-#define BOTH_DIR 2
-
-/* Exported types ------------------------------------------------------------*/
-typedef struct _MSC_BOT_CBW
-{
- uint32_t dSignature;
- uint32_t dTag;
- uint32_t dDataLength;
- uint8_t bmFlags;
- uint8_t bLUN;
- uint8_t bCBLength;
- uint8_t CB[16];
-}
-MSC_BOT_CBW_TypeDef;
-
-
-typedef struct _MSC_BOT_CSW
-{
- uint32_t dSignature;
- uint32_t dTag;
- uint32_t dDataResidue;
- uint8_t bStatus;
-}
-MSC_BOT_CSW_TypeDef;
-
-/* Exported macros -----------------------------------------------------------*/
-/* Exported variables --------------------------------------------------------*/
-extern uint8_t MSC_BOT_Data[];
-extern uint16_t MSC_BOT_DataLen;
-extern uint8_t MSC_BOT_State;
-extern uint8_t MSC_BOT_BurstMode;
-extern MSC_BOT_CBW_TypeDef MSC_BOT_cbw;
-extern MSC_BOT_CSW_TypeDef MSC_BOT_csw;
-
-/* Exported functions ------------------------------------------------------- */
-void MSC_BOT_Init (USB_CORE_HANDLE *pdev);
-void MSC_BOT_Reset (USB_CORE_HANDLE *pdev);
-void MSC_BOT_DeInit (USB_CORE_HANDLE *pdev);
-void MSC_BOT_DataIn (USB_CORE_HANDLE *pdev,
- uint8_t epnum);
-
-void MSC_BOT_DataOut (USB_CORE_HANDLE *pdev,
- uint8_t epnum);
-
-void MSC_BOT_SendCSW (USB_CORE_HANDLE *pdev,
- uint8_t CSW_Status);
-
-void MSC_BOT_CplClrFeature (USB_CORE_HANDLE *pdev,
- uint8_t epnum);
-
-#endif /* __USBD_MSC_BOT_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/msc/inc/usbd_msc_core.h b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/msc/inc/usbd_msc_core.h
deleted file mode 100644
index 9ffc4a9070b43f57281777310d8cd747801e6a3d..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/msc/inc/usbd_msc_core.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/**
- ******************************************************************************
- * @file usbd_msc_core.h
- * @author MCD Application Team
- * @version V1.0.1
- * @date 31-January-2014
- * @brief header for the usbd_msc_core.c file
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef _USB_MSC_CORE_H_
-#define _USB_MSC_CORE_H_
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_req.h"
-#include "usbd_msc_bot.h"
-
-/* Exported defines ----------------------------------------------------------*/
-#define BOT_GET_MAX_LUN 0xFE
-#define BOT_RESET 0xFF
-#define USB_MSC_CONFIG_DESC_SIZ 32
-
-#define MSC_EPIN_SIZE MSC_MAX_PACKET
-#define MSC_EPOUT_SIZE MSC_MAX_PACKET
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported macros -----------------------------------------------------------*/
-/* Exported variables --------------------------------------------------------*/
-extern USBD_Class_cb_TypeDef USBD_MSC_cb;
-
-/* Exported functions ------------------------------------------------------- */
-
-#endif /* _USB_MSC_CORE_H_ */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/msc/inc/usbd_msc_data.h b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/msc/inc/usbd_msc_data.h
deleted file mode 100644
index 47885ed462334eac784a1288ae848428e822538e..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/msc/inc/usbd_msc_data.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/**
- ******************************************************************************
- * @file usbd_msc_data.h
- * @author MCD Application Team
- * @version V1.0.1
- * @date 31-January-2014
- * @brief header for the usbd_msc_data.c file
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-
-#ifndef _USBD_MSC_DATA_H_
-#define _USBD_MSC_DATA_H_
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_conf.h"
-
-/* Exported defines ----------------------------------------------------------*/
-#define MODE_SENSE6_LEN 8
-#define MODE_SENSE10_LEN 8
-#define LENGTH_INQUIRY_PAGE00 7
-#define LENGTH_FORMAT_CAPACITIES 20
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported macros -----------------------------------------------------------*/
-/* Exported variables --------------------------------------------------------*/
-extern const uint8_t MSC_Page00_Inquiry_Data[];
-extern const uint8_t MSC_Mode_Sense6_data[];
-extern const uint8_t MSC_Mode_Sense10_data[];
-
-/* Exported functions ------------------------------------------------------- */
-
-#endif /* _USBD_MSC_DATA_H_ */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/msc/inc/usbd_msc_mem.h b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/msc/inc/usbd_msc_mem.h
deleted file mode 100644
index 0b6bc74b45f6cd0676837c8a747187cccde6d65e..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/msc/inc/usbd_msc_mem.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/**
- ******************************************************************************
- * @file usbd_msc_mem.h
- * @author MCD Application Team
- * @version V1.0.1
- * @date 31-January-2014
- * @brief header for the STORAGE DISK file file
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __USBD_MEM_H
-#define __USBD_MEM_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_def.h"
-
-/* Exported defines ----------------------------------------------------------*/
-#define USBD_STD_INQUIRY_LENGTH 36
-
-/* Exported types ------------------------------------------------------------*/
-typedef struct _USBD_STORAGE
-{
- int8_t (* Init) (uint8_t lun);
- int8_t (* GetCapacity) (uint8_t lun, uint32_t *block_num, uint32_t *block_size);
- int8_t (* IsReady) (uint8_t lun);
- int8_t (* IsWriteProtected) (uint8_t lun);
- int8_t (* Read) (uint8_t lun, uint8_t *buf, uint32_t blk_addr, uint16_t blk_len);
- int8_t (* Write)(uint8_t lun, uint8_t *buf, uint32_t blk_addr, uint16_t blk_len);
- int8_t (* GetMaxLun)(void);
- int8_t *pInquiry;
-
-}USBD_STORAGE_cb_TypeDef;
-
-/* Exported macros -----------------------------------------------------------*/
-/* Exported variables --------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-extern USBD_STORAGE_cb_TypeDef *USBD_STORAGE_fops;
-
-
-#endif /* __USBD_MEM_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/msc/inc/usbd_msc_scsi.h b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/msc/inc/usbd_msc_scsi.h
deleted file mode 100644
index ca6dded6f40e483c964165ea7a9de1b0993a498d..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/msc/inc/usbd_msc_scsi.h
+++ /dev/null
@@ -1,145 +0,0 @@
-/**
- ******************************************************************************
- * @file usbd_msc_scsi.h
- * @author MCD Application Team
- * @version V1.0.1
- * @date 31-January-2014
- * @brief header for the usbd_msc_scsi.c file
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __USBD_MSC_SCSI_H
-#define __USBD_MSC_SCSI_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_msc_data.h"
-#include "usbd_msc_bot.h"
-
-/* Exported defines ----------------------------------------------------------*/
-#define SENSE_LIST_DEEPTH 4
-
-/* SCSI Commands */
-#define SCSI_FORMAT_UNIT 0x04
-#define SCSI_INQUIRY 0x12
-#define SCSI_MODE_SELECT6 0x15
-#define SCSI_MODE_SELECT10 0x55
-#define SCSI_MODE_SENSE6 0x1A
-#define SCSI_MODE_SENSE10 0x5A
-#define SCSI_ALLOW_MEDIUM_REMOVAL 0x1E
-#define SCSI_READ6 0x08
-#define SCSI_READ10 0x28
-#define SCSI_READ12 0xA8
-#define SCSI_READ16 0x88
-
-#define SCSI_READ_CAPACITY10 0x25
-#define SCSI_READ_CAPACITY16 0x9E
-
-#define SCSI_REQUEST_SENSE 0x03
-#define SCSI_START_STOP_UNIT 0x1B
-#define SCSI_TEST_UNIT_READY 0x00
-#define SCSI_WRITE6 0x0A
-#define SCSI_WRITE10 0x2A
-#define SCSI_WRITE12 0xAA
-#define SCSI_WRITE16 0x8A
-
-#define SCSI_VERIFY10 0x2F
-#define SCSI_VERIFY12 0xAF
-#define SCSI_VERIFY16 0x8F
-
-#define SCSI_SEND_DIAGNOSTIC 0x1D
-#define SCSI_READ_FORMAT_CAPACITIES 0x23
-
-#define NO_SENSE 0
-#define RECOVERED_ERROR 1
-#define NOT_READY 2
-#define MEDIUM_ERROR 3
-#define HARDWARE_ERROR 4
-#define ILLEGAL_REQUEST 5
-#define UNIT_ATTENTION 6
-#define DATA_PROTECT 7
-#define BLANK_CHECK 8
-#define VENDOR_SPECIFIC 9
-#define COPY_ABORTED 10
-#define ABORTED_COMMAND 11
-#define VOLUME_OVERFLOW 13
-#define MISCOMPARE 14
-
-
-#define INVALID_CDB 0x20
-#define INVALID_FIELED_IN_COMMAND 0x24
-#define PARAMETER_LIST_LENGTH_ERROR 0x1A
-#define INVALID_FIELD_IN_PARAMETER_LIST 0x26
-#define ADDRESS_OUT_OF_RANGE 0x21
-#define MEDIUM_NOT_PRESENT 0x3A
-#define MEDIUM_HAVE_CHANGED 0x28
-#define WRITE_PROTECTED 0x27
-#define UNRECOVERED_READ_ERROR 0x11
-#define WRITE_FAULT 0x03
-
-#define READ_FORMAT_CAPACITY_DATA_LEN 0x0C
-#define READ_CAPACITY10_DATA_LEN 0x08
-#define MODE_SENSE10_DATA_LEN 0x08
-#define MODE_SENSE6_DATA_LEN 0x04
-#define REQUEST_SENSE_DATA_LEN 0x12
-#define STANDARD_INQUIRY_DATA_LEN 0x24
-#define BLKVFY 0x04
-
-/* Exported types ------------------------------------------------------------*/
-typedef struct _SENSE_ITEM {
- char Skey;
- union {
- struct _ASCs {
- char ASC;
- char ASCQ;
- }b;
- unsigned int ASC;
- char *pData;
- } w;
-} SCSI_Sense_TypeDef;
-
-/* Exported macros -----------------------------------------------------------*/
-/* Exported variables --------------------------------------------------------*/
-extern uint8_t Page00_Inquiry_Data[];
-extern uint8_t Standard_Inquiry_Data[];
-extern uint8_t Standard_Inquiry_Data2[];
-extern uint8_t Mode_Sense6_data[];
-extern uint8_t Mode_Sense10_data[];
-extern uint8_t Scsi_Sense_Data[];
-extern uint8_t ReadCapacity10_Data[];
-extern uint8_t ReadFormatCapacity_Data [];
-
-extern SCSI_Sense_TypeDef SCSI_Sense [SENSE_LIST_DEEPTH];
-extern uint8_t SCSI_Sense_Head;
-extern uint8_t SCSI_Sense_Tail;
-/* Exported functions ------------------------------------------------------- */
-int8_t SCSI_ProcessCmd(USB_CORE_HANDLE *pdev,
- uint8_t lun,
- uint8_t *cmd);
-
-void SCSI_SenseCode(uint8_t lun,
- uint8_t sKey,
- uint8_t ASC);
-
-
-#endif /* __USBD_MSC_SCSI_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/msc/src/usbd_msc_bot.c b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/msc/src/usbd_msc_bot.c
deleted file mode 100644
index a362446edf6cf4c8239a170f615657a6253389e9..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/msc/src/usbd_msc_bot.c
+++ /dev/null
@@ -1,319 +0,0 @@
-/**
- ******************************************************************************
- * @file usbd_msc_bot.c
- * @author MCD Application Team
- * @version V1.0.1
- * @date 31-January-2014
- * @brief This file provides all the BOT protocol core functions.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_msc_bot.h"
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-uint16_t MSC_BOT_DataLen;
-uint8_t MSC_BOT_State;
-uint8_t MSC_BOT_Status;
-
-uint8_t MSC_BOT_Data[MSC_MEDIA_PACKET] ;
-
-MSC_BOT_CBW_TypeDef MSC_BOT_cbw ;
-
-MSC_BOT_CSW_TypeDef MSC_BOT_csw ;
-
-/* Private function prototypes -----------------------------------------------*/
-static void MSC_BOT_CBW_Decode (USB_CORE_HANDLE *pdev);
-
-static void MSC_BOT_SendData (USB_CORE_HANDLE *pdev,
- uint8_t* pbuf,
- uint16_t len);
-
-static void MSC_BOT_Abort(USB_CORE_HANDLE *pdev);
-
-/* Private functions ---------------------------------------------------------*/
-/**
- * @brief MSC_BOT_Init
- * Initialize the BOT Process
- * @param pdev: device instance
- * @retval None
- */
-void MSC_BOT_Init (USB_CORE_HANDLE *pdev)
-{
- MSC_BOT_State = BOT_IDLE;
- MSC_BOT_Status = BOT_STATE_NORMAL;
- USBD_STORAGE_fops->Init(0);
-
- /* Prepare EP to Receive First BOT Cmd */
- DCD_EP_PrepareRx (pdev,
- MSC_OUT_EP,
- (uint8_t *)&MSC_BOT_cbw,
- BOT_CBW_LENGTH);
-}
-
-/**
- * @brief MSC_BOT_Reset
- * Reset the BOT Machine
- * @param pdev: device instance
- * @retval None
- */
-void MSC_BOT_Reset (USB_CORE_HANDLE *pdev)
-{
- MSC_BOT_State = BOT_IDLE;
- MSC_BOT_Status = BOT_STATE_RECOVERY;
- /* Prepare EP to Receive First BOT Cmd */
- DCD_EP_PrepareRx (pdev,
- MSC_OUT_EP,
- (uint8_t *)&MSC_BOT_cbw,
- BOT_CBW_LENGTH);
-}
-
-/**
- * @brief MSC_BOT_DeInit
- * Uninitialize the BOT Machine
- * @param pdev: device instance
- * @retval None
- */
-void MSC_BOT_DeInit (USB_CORE_HANDLE *pdev)
-{
- MSC_BOT_State = BOT_IDLE;
-}
-
-/**
- * @brief MSC_BOT_DataIn
- * Handle BOT IN data stage
- * @param pdev: device instance
- * @param epnum: endpoint index
- * @retval None
- */
-void MSC_BOT_DataIn (USB_CORE_HANDLE *pdev,
- uint8_t epnum)
-{
-
- switch (MSC_BOT_State)
- {
- case BOT_DATA_IN:
- if(SCSI_ProcessCmd(pdev,
- MSC_BOT_cbw.bLUN,
- &MSC_BOT_cbw.CB[0]) < 0)
- {
- MSC_BOT_SendCSW (pdev, CSW_CMD_FAILED);
- }
- break;
-
- case BOT_SEND_DATA:
- case BOT_LAST_DATA_IN:
- MSC_BOT_SendCSW (pdev, CSW_CMD_PASSED);
-
- break;
-
- default:
- break;
- }
-}
-/**
- * @brief MSC_BOT_DataOut
- * Process MSC OUT data
- * @param pdev: device instance
- * @param epnum: endpoint index
- * @retval None
- */
-void MSC_BOT_DataOut (USB_CORE_HANDLE *pdev,
- uint8_t epnum)
-{
-
- switch (MSC_BOT_State)
- {
- case BOT_IDLE:
- MSC_BOT_CBW_Decode(pdev);
- break;
-
- case BOT_DATA_OUT:
-
- if(SCSI_ProcessCmd(pdev,
- MSC_BOT_cbw.bLUN,
- &MSC_BOT_cbw.CB[0]) < 0)
- {
- MSC_BOT_SendCSW (pdev, CSW_CMD_FAILED);
- }
-
- break;
-
- default:
- break;
- }
-
-}
-
-/**
- * @brief MSC_BOT_CBW_Decode
- * Decode the CBW command and set the BOT state machine accordingly
- * @param pdev: device instance
- * @retval None
- */
-static void MSC_BOT_CBW_Decode (USB_CORE_HANDLE *pdev)
-{
-
- MSC_BOT_csw.dTag = MSC_BOT_cbw.dTag;
- MSC_BOT_csw.dDataResidue = MSC_BOT_cbw.dDataLength;
-
- if ((USBD_GetRxCount (pdev ,MSC_OUT_EP) != BOT_CBW_LENGTH) ||
- (MSC_BOT_cbw.dSignature != BOT_CBW_SIGNATURE)||
- (MSC_BOT_cbw.bLUN > 1) ||
- (MSC_BOT_cbw.bCBLength < 1) ||
- (MSC_BOT_cbw.bCBLength > 16))
- {
-
- SCSI_SenseCode(MSC_BOT_cbw.bLUN,
- ILLEGAL_REQUEST,
- INVALID_CDB);
- MSC_BOT_Status = BOT_STATE_ERROR;
- MSC_BOT_Abort(pdev);
-
- }
- else
- {
- if(SCSI_ProcessCmd(pdev,
- MSC_BOT_cbw.bLUN,
- &MSC_BOT_cbw.CB[0]) < 0)
- {
- MSC_BOT_Abort(pdev);
- }
- /*Burst xfer handled internally*/
- else if ((MSC_BOT_State != BOT_DATA_IN) &&
- (MSC_BOT_State != BOT_DATA_OUT) &&
- (MSC_BOT_State != BOT_LAST_DATA_IN))
- {
- if (MSC_BOT_DataLen > 0)
- {
- MSC_BOT_SendData(pdev,
- MSC_BOT_Data,
- MSC_BOT_DataLen);
- }
- else if (MSC_BOT_DataLen == 0)
- {
- MSC_BOT_SendCSW (pdev,
- CSW_CMD_PASSED);
- }
- }
- }
-}
-
-/**
- * @brief MSC_BOT_SendData
- * Send the requested data
- * @param pdev: device instance
- * @param buf: pointer to data buffer
- * @param len: Data Length
- * @retval None
- */
-static void MSC_BOT_SendData(USB_CORE_HANDLE *pdev,
- uint8_t* buf,
- uint16_t len)
-{
-
- len = MIN (MSC_BOT_cbw.dDataLength, len);
- MSC_BOT_csw.dDataResidue -= len;
- MSC_BOT_csw.bStatus = CSW_CMD_PASSED;
- MSC_BOT_State = BOT_SEND_DATA;
-
- DCD_EP_Tx (pdev, MSC_IN_EP, buf, len);
-}
-
-/**
- * @brief MSC_BOT_SendCSW
- * Send the Command Status Wrapper
- * @param pdev: device instance
- * @param status : CSW status
- * @retval None
- */
-void MSC_BOT_SendCSW (USB_CORE_HANDLE *pdev,
- uint8_t CSW_Status)
-{
- MSC_BOT_csw.dSignature = BOT_CSW_SIGNATURE;
- MSC_BOT_csw.bStatus = CSW_Status;
- MSC_BOT_State = BOT_IDLE;
-
- DCD_EP_Tx (pdev,
- MSC_IN_EP,
- (uint8_t *)&MSC_BOT_csw,
- BOT_CSW_LENGTH);
-
- /* Prepare EP to Receive next Cmd */
- DCD_EP_PrepareRx (pdev,
- MSC_OUT_EP,
- (uint8_t *)&MSC_BOT_cbw,
- BOT_CBW_LENGTH);
-
-}
-
-/**
- * @brief MSC_BOT_Abort
- * Abort the current transfer
- * @param pdev: device instance
- * @retval status
- */
-
-static void MSC_BOT_Abort (USB_CORE_HANDLE *pdev)
-{
-
- if ((MSC_BOT_cbw.bmFlags == 0) &&
- (MSC_BOT_cbw.dDataLength != 0) &&
- (MSC_BOT_Status == BOT_STATE_NORMAL) )
- {
- DCD_EP_Stall(pdev, MSC_OUT_EP );
- }
- DCD_EP_Stall(pdev, MSC_IN_EP);
-
- if(MSC_BOT_Status == BOT_STATE_ERROR)
- {
- DCD_EP_PrepareRx (pdev,
- MSC_OUT_EP,
- (uint8_t *)&MSC_BOT_cbw,
- BOT_CBW_LENGTH);
- }
-}
-
-/**
- * @brief MSC_BOT_CplClrFeature
- * Complete the clear feature request
- * @param pdev: device instance
- * @param epnum: endpoint index
- * @retval None
- */
-
-void MSC_BOT_CplClrFeature (USB_CORE_HANDLE *pdev, uint8_t epnum)
-{
- if(MSC_BOT_Status == BOT_STATE_ERROR )/* Bad CBW Signature */
- {
- DCD_EP_Stall(pdev, MSC_IN_EP);
- MSC_BOT_Status = BOT_STATE_NORMAL;
- }
- else if(((epnum & 0x80) == 0x80) && ( MSC_BOT_Status != BOT_STATE_RECOVERY))
- {
- MSC_BOT_SendCSW (pdev, CSW_CMD_FAILED);
- }
-
-}
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/msc/src/usbd_msc_core.c b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/msc/src/usbd_msc_core.c
deleted file mode 100644
index b5c4169ffc81b1e64630291f4209ec896295a91f..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/msc/src/usbd_msc_core.c
+++ /dev/null
@@ -1,310 +0,0 @@
-/**
- ******************************************************************************
- * @file usbd_msc_core.c
- * @author MCD Application Team
- * @version V1.0.1
- * @date 31-January-2014
- * @brief This file provides all the MSC core functions.
- *
- * @verbatim
- *
- * ===================================================================
- * MSC Class Description
- * ===================================================================
- * This module manages the MSC class V1.0 following the "Universal
- * Serial Bus Mass Storage Class (MSC) Bulk-Only Transport (BOT) Version 1.0
- * Sep. 31, 1999".
- * This driver implements the following aspects of the specification:
- * - Bulk-Only Transport protocol
- * - Subclass : SCSI transparent command set (ref. SCSI Primary Commands - 3 (SPC-3))
- *
- * @endverbatim
- *
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_msc_core.h"
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-uint8_t USBD_MSC_Init (void *pdev,
- uint8_t cfgidx);
-
-uint8_t USBD_MSC_DeInit (void *pdev,
- uint8_t cfgidx);
-
-uint8_t USBD_MSC_Setup (void *pdev,
- USB_SETUP_REQ *req);
-
-uint8_t USBD_MSC_DataIn (void *pdev,
- uint8_t epnum);
-
-
-uint8_t USBD_MSC_DataOut (void *pdev,
- uint8_t epnum);
-
-uint8_t *USBD_MSC_GetCfgDesc (uint8_t speed,
- uint16_t *length);
-
-USBD_Class_cb_TypeDef USBD_MSC_cb =
-{
- USBD_MSC_Init,
- USBD_MSC_DeInit,
- USBD_MSC_Setup,
- NULL, /*EP0_TxSent*/
- NULL, /*EP0_RxReady*/
- USBD_MSC_DataIn,
- USBD_MSC_DataOut,
- NULL, /*SOF */
- USBD_MSC_GetCfgDesc,
-};
-
-/* USB Mass storage device Configuration Descriptor */
-/* All Descriptors (Configuration, Interface, Endpoint, Class, Vendor */
-const uint8_t USBD_MSC_CfgDesc[USB_MSC_CONFIG_DESC_SIZ] =
-{
- 0x09, /* bLength: Configuration Descriptor size */
- USB_DESC_TYPE_CONFIGURATION, /* bDescriptorType: Configuration */
- USB_MSC_CONFIG_DESC_SIZ,
-
- 0x00,
- 0x01, /* bNumInterfaces: 1 interface */
- 0x01, /* bConfigurationValue: */
- 0x04, /* iConfiguration: */
- 0xC0, /* bmAttributes: */
- 0x32, /* MaxPower 100 mA */
-
- /******************** Mass Storage interface ********************/
- 0x09, /* bLength: Interface Descriptor size */
- 0x04, /* bDescriptorType: */
- 0x00, /* bInterfaceNumber: Number of Interface */
- 0x00, /* bAlternateSetting: Alternate setting */
- 0x02, /* bNumEndpoints*/
- 0x08, /* bInterfaceClass: MSC Class */
- 0x06, /* bInterfaceSubClass : SCSI transparent*/
- 0x50, /* nInterfaceProtocol */
- 0x05, /* iInterface: */
- /******************** Mass Storage Endpoints ********************/
- 0x07, /*Endpoint descriptor length = 7*/
- 0x05, /*Endpoint descriptor type */
- MSC_IN_EP, /*Endpoint address (IN, address 1) */
- 0x02, /*Bulk endpoint type */
- LOBYTE(MSC_MAX_PACKET),
- HIBYTE(MSC_MAX_PACKET),
- 0x00, /*Polling interval in milliseconds */
- 0x07, /*Endpoint descriptor length = 7 */
- 0x05, /*Endpoint descriptor type */
- MSC_OUT_EP, /*Endpoint address (OUT, address 1) */
- 0x02, /*Bulk endpoint type */
- LOBYTE(MSC_MAX_PACKET),
- HIBYTE(MSC_MAX_PACKET),
- 0x00 /*Polling interval in milliseconds*/
-};
-static uint8_t USBD_MSC_MaxLun = 0;
-
-static uint8_t USBD_MSC_AltSet = 0;
-
-/* Private function ----------------------------------------------------------*/
-/**
- * @brief USBD_MSC_Init
- * Initialize the mass storage configuration
- * @param pdev: device instance
- * @param cfgidx: configuration index
- * @retval status
- */
-uint8_t USBD_MSC_Init (void *pdev,
- uint8_t cfgidx)
-{
- DCD_PMA_Config(pdev , MSC_IN_EP,USB_SNG_BUF,MSC_IN_TX_ADDRESS);
- DCD_PMA_Config(pdev , MSC_OUT_EP,USB_SNG_BUF,MSC_OUT_RX_ADDRESS);
-
- /* Open EP IN */
- DCD_EP_Open(pdev,
- MSC_IN_EP,
- MSC_EPIN_SIZE,
- USB_EP_BULK);
-
- /* Open EP OUT */
- DCD_EP_Open(pdev,
- MSC_OUT_EP,
- MSC_EPOUT_SIZE,
- USB_EP_BULK);
-
- /* Init the BOT layer */
- MSC_BOT_Init(pdev);
-
- return USBD_OK;
-}
-
-/**
- * @brief USBD_MSC_DeInit
- * DeInitilaize the mass storage configuration
- * @param pdev: device instance
- * @param cfgidx: configuration index
- * @retval status
- */
-uint8_t USBD_MSC_DeInit (void *pdev,
- uint8_t cfgidx)
-{
- /* Close MSC EPs */
- DCD_EP_Close (pdev , MSC_IN_EP);
- DCD_EP_Close (pdev , MSC_OUT_EP);
-
- /* Un Init the BOT layer */
- MSC_BOT_DeInit(pdev);
- return USBD_OK;
-}
-/**
- * @brief USBD_MSC_Setup
- * Handle the MSC specific requests
- * @param pdev: device instance
- * @param req: USB request
- * @retval status
- */
-uint8_t USBD_MSC_Setup (void *pdev, USB_SETUP_REQ *req)
-{
-
- switch (req->bmRequest & USB_REQ_TYPE_MASK)
- {
-
- /* Class request */
- case USB_REQ_TYPE_CLASS :
- switch (req->bRequest)
- {
- case BOT_GET_MAX_LUN :
-
- if((req->wValue == 0) &&
- (req->wLength == 1) &&
- ((req->bmRequest & 0x80) == 0x80))
- {
- USBD_MSC_MaxLun = USBD_STORAGE_fops->GetMaxLun();
- if(USBD_MSC_MaxLun > 0)
- {
- USBD_CtlSendData (pdev,
- &USBD_MSC_MaxLun,
- 1);
- }
- else
- {
- USBD_CtlError(pdev , req);
- return USBD_FAIL;
- }
- }
- else
- {
- USBD_CtlError(pdev , req);
- return USBD_FAIL;
- }
- break;
-
- case BOT_RESET :
- if((req->wValue == 0) &&
- (req->wLength == 0) &&
- ((req->bmRequest & 0x80) != 0x80))
- {
- MSC_BOT_Reset(pdev);
- }
- else
- {
- USBD_CtlError(pdev , req);
- return USBD_FAIL;
- }
- break;
-
- default:
- USBD_CtlError(pdev , req);
- return USBD_FAIL;
- }
- break;
- /* Interface & Endpoint request */
- case USB_REQ_TYPE_STANDARD:
- switch (req->bRequest)
- {
- case USB_REQ_GET_INTERFACE :
- USBD_CtlSendData (pdev,
- &USBD_MSC_AltSet,
- 1);
- break;
-
- case USB_REQ_SET_INTERFACE :
- USBD_MSC_AltSet = (uint8_t)(req->wValue);
- break;
-
- case USB_REQ_CLEAR_FEATURE:
-
- /* Handle BOT error */
- MSC_BOT_CplClrFeature(pdev, (uint8_t)req->wIndex);
- break;
-
- }
- break;
-
- default:
- break;
- }
- return USBD_OK;
-}
-
-/**
- * @brief USBD_MSC_DataIn
- * handle data IN Stage
- * @param pdev: device instance
- * @param epnum: endpoint index
- * @retval status
- */
-uint8_t USBD_MSC_DataIn (void *pdev,
- uint8_t epnum)
-{
- MSC_BOT_DataIn(pdev , epnum);
- return USBD_OK;
-}
-
-/**
- * @brief USBD_MSC_DataOut
- * handle data OUT Stage
- * @param pdev: device instance
- * @param epnum: endpoint index
- * @retval status
- */
-uint8_t USBD_MSC_DataOut (void *pdev,
- uint8_t epnum)
-{
- MSC_BOT_DataOut(pdev , epnum);
- return USBD_OK;
-}
-
-/**
- * @brief USBD_MSC_GetCfgDesc
- * return configuration descriptor
- * @param speed : current device speed
- * @param length : pointer data length
- * @retval pointer to descriptor buffer
- */
-uint8_t *USBD_MSC_GetCfgDesc (uint8_t speed, uint16_t *length)
-{
- *length = sizeof (USBD_MSC_CfgDesc);
- return (uint8_t *)USBD_MSC_CfgDesc;
-}
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/msc/src/usbd_msc_data.c b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/msc/src/usbd_msc_data.c
deleted file mode 100644
index 716248a195c292df9fdb9fb0758d4e97b633d05c..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/msc/src/usbd_msc_data.c
+++ /dev/null
@@ -1,71 +0,0 @@
-/**
- ******************************************************************************
- * @file usbd_msc_data.c
- * @author MCD Application Team
- * @version V1.0.1
- * @date 31-January-2014
- * @brief This file provides all the vital inquiry pages and sense data.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_msc_data.h"
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* USB Mass storage Page 0 Inquiry Data */
-const uint8_t MSC_Page00_Inquiry_Data[] = {//7
- 0x00,
- 0x00,
- 0x00,
- (LENGTH_INQUIRY_PAGE00 - 4),
- 0x00,
- 0x80,
- 0x83
-};
-/* USB Mass storage sense 6 Data */
-const uint8_t MSC_Mode_Sense6_data[] = {
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00
-};
-/* USB Mass storage sense 10 Data */
-const uint8_t MSC_Mode_Sense10_data[] = {
- 0x00,
- 0x06,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00
-};
-
-/* Private function prototypes -----------------------------------------------*/
-/* Private function ----------------------------------------------------------*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/msc/src/usbd_msc_scsi.c b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/msc/src/usbd_msc_scsi.c
deleted file mode 100644
index e7d2900a77050b5a44a351f85eff14636a6b3da8..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/msc/src/usbd_msc_scsi.c
+++ /dev/null
@@ -1,661 +0,0 @@
-/**
- ******************************************************************************
- * @file usbd_msc_scsi.c
- * @author MCD Application Team
- * @version V1.0.1
- * @date 31-January-2014
- * @brief This file provides all the USBD SCSI layer functions.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_msc_scsi.h"
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-SCSI_Sense_TypeDef SCSI_Sense [SENSE_LIST_DEEPTH];
-uint8_t SCSI_Sense_Head;
-uint8_t SCSI_Sense_Tail;
-
-uint32_t SCSI_blk_size;
-uint32_t SCSI_blk_nbr;
-
-uint32_t SCSI_blk_addr;
-uint32_t SCSI_blk_len;
-
-USB_CORE_HANDLE *cdev;
-
-/* Private function prototypes -----------------------------------------------*/
-static int8_t SCSI_TestUnitReady(uint8_t lun, uint8_t *params);
-static int8_t SCSI_Inquiry(uint8_t lun, uint8_t *params);
-static int8_t SCSI_ReadFormatCapacity(uint8_t lun, uint8_t *params);
-static int8_t SCSI_ReadCapacity10(uint8_t lun, uint8_t *params);
-static int8_t SCSI_RequestSense (uint8_t lun, uint8_t *params);
-static int8_t SCSI_StartStopUnit(uint8_t lun, uint8_t *params);
-static int8_t SCSI_ModeSense6 (uint8_t lun, uint8_t *params);
-static int8_t SCSI_ModeSense10 (uint8_t lun, uint8_t *params);
-static int8_t SCSI_Write10(uint8_t lun , uint8_t *params);
-static int8_t SCSI_Read10(uint8_t lun , uint8_t *params);
-static int8_t SCSI_Verify10(uint8_t lun, uint8_t *params);
-static int8_t SCSI_CheckAddressRange (uint8_t lun ,
- uint32_t blk_offset ,
- uint16_t blk_nbr);
-static int8_t SCSI_ProcessRead (uint8_t lun);
-
-static int8_t SCSI_ProcessWrite (uint8_t lun);
-
-/* Private function ----------------------------------------------------------*/
-/**
- * @brief SCSI_ProcessCmd
- * Process SCSI commands
- * @param pdev: device instance
- * @param lun: Logical unit number
- * @param params: Command parameters
- * @retval status
- */
-int8_t SCSI_ProcessCmd(USB_CORE_HANDLE *pdev,
- uint8_t lun,
- uint8_t *params)
-{
- cdev = pdev;
-
- switch (params[0])
- {
- case SCSI_TEST_UNIT_READY:
- return SCSI_TestUnitReady(lun, params);
-
- case SCSI_REQUEST_SENSE:
- return SCSI_RequestSense (lun, params);
- case SCSI_INQUIRY:
- return SCSI_Inquiry(lun, params);
-
- case SCSI_START_STOP_UNIT:
- return SCSI_StartStopUnit(lun, params);
-
- case SCSI_ALLOW_MEDIUM_REMOVAL:
- return SCSI_StartStopUnit(lun, params);
-
- case SCSI_MODE_SENSE6:
- return SCSI_ModeSense6 (lun, params);
-
- case SCSI_MODE_SENSE10:
- return SCSI_ModeSense10 (lun, params);
-
- case SCSI_READ_FORMAT_CAPACITIES:
- return SCSI_ReadFormatCapacity(lun, params);
-
- case SCSI_READ_CAPACITY10:
- return SCSI_ReadCapacity10(lun, params);
-
- case SCSI_READ10:
- return SCSI_Read10(lun, params);
-
- case SCSI_WRITE10:
- return SCSI_Write10(lun, params);
-
- case SCSI_VERIFY10:
- return SCSI_Verify10(lun, params);
-
- default:
- SCSI_SenseCode(lun,
- ILLEGAL_REQUEST,
- INVALID_CDB);
- return -1;
- }
-}
-
-
-/**
- * @brief SCSI_TestUnitReady
- * Process SCSI Test Unit Ready Command
- * @param lun: Logical unit number
- * @param params: Command parameters
- * @retval status
- */
-static int8_t SCSI_TestUnitReady(uint8_t lun, uint8_t *params)
-{
-
- /* case 9 : Hi > D0 */
- if (MSC_BOT_cbw.dDataLength != 0)
- {
- SCSI_SenseCode(MSC_BOT_cbw.bLUN,
- ILLEGAL_REQUEST,
- INVALID_CDB);
- return -1;
- }
-
- if(USBD_STORAGE_fops->IsReady(lun) !=0 )
- {
- SCSI_SenseCode(lun,
- NOT_READY,
- MEDIUM_NOT_PRESENT);
- return -1;
- }
- MSC_BOT_DataLen = 0;
- return 0;
-}
-
-/**
- * @brief SCSI_Inquiry
- * Process Inquiry command
- * @param lun: Logical unit number
- * @param params: Command parameters
- * @retval status
- */
-static int8_t SCSI_Inquiry(uint8_t lun, uint8_t *params)
-{
- uint8_t* pPage;
- uint16_t len;
-
- if (params[1] & 0x01)/*Evpd is set*/
- {
- pPage = (uint8_t *)MSC_Page00_Inquiry_Data;
- len = LENGTH_INQUIRY_PAGE00;
- }
- else
- {
-
- pPage = (uint8_t *)&USBD_STORAGE_fops->pInquiry[lun * USBD_STD_INQUIRY_LENGTH];
- len = pPage[4] + 5;
-
- if (params[4] <= len)
- {
- len = params[4];
- }
- }
- MSC_BOT_DataLen = len;
-
- while (len)
- {
- len--;
- MSC_BOT_Data[len] = pPage[len];
- }
- return 0;
-}
-
-/**
- * @brief SCSI_ReadCapacity10
- * Process Read Capacity 10 command
- * @param lun: Logical unit number
- * @param params: Command parameters
- * @retval status
- */
-static int8_t SCSI_ReadCapacity10(uint8_t lun, uint8_t *params)
-{
-
- if(USBD_STORAGE_fops->GetCapacity(lun, &SCSI_blk_nbr, &SCSI_blk_size) != 0)
- {
- SCSI_SenseCode(lun,
- NOT_READY,
- MEDIUM_NOT_PRESENT);
- return -1;
- }
- else
- {
-
- MSC_BOT_Data[0] = (uint8_t)((SCSI_blk_nbr - 1) >> 24);
- MSC_BOT_Data[1] = (uint8_t)((SCSI_blk_nbr - 1) >> 16);
- MSC_BOT_Data[2] = (uint8_t)((SCSI_blk_nbr - 1) >> 8);
- MSC_BOT_Data[3] = (uint8_t)(SCSI_blk_nbr - 1);
-
- MSC_BOT_Data[4] = (uint8_t)(SCSI_blk_size >> 24);
- MSC_BOT_Data[5] = (uint8_t)(SCSI_blk_size >> 16);
- MSC_BOT_Data[6] = (uint8_t)(SCSI_blk_size >> 8);
- MSC_BOT_Data[7] = (uint8_t)(SCSI_blk_size);
-
- MSC_BOT_DataLen = 8;
- return 0;
- }
-}
-/**
- * @brief SCSI_ReadFormatCapacity
- * Process Read Format Capacity command
- * @param lun: Logical unit number
- * @param params: Command parameters
- * @retval status
- */
-static int8_t SCSI_ReadFormatCapacity(uint8_t lun, uint8_t *params)
-{
-
- uint32_t blk_size;
- uint32_t blk_nbr;
- uint16_t i;
-
- for(i=0 ; i < 12 ; i++)
- {
- MSC_BOT_Data[i] = 0;
- }
-
- if(USBD_STORAGE_fops->GetCapacity(lun, &blk_nbr, &blk_size) != 0)
- {
- SCSI_SenseCode(lun,
- NOT_READY,
- MEDIUM_NOT_PRESENT);
- return (-1);
- }
- else
- {
- MSC_BOT_Data[3] = 0x08;
- MSC_BOT_Data[4] = (uint8_t)((blk_nbr - 1) >> 24);
- MSC_BOT_Data[5] = (uint8_t)((blk_nbr - 1) >> 16);
- MSC_BOT_Data[6] = (uint8_t)((blk_nbr - 1) >> 8);
- MSC_BOT_Data[7] = (uint8_t)(blk_nbr - 1);
-
- MSC_BOT_Data[8] = 0x02;
- MSC_BOT_Data[9] = (uint8_t)(blk_size >> 16);
- MSC_BOT_Data[10] = (uint8_t)(blk_size >> 8);
- MSC_BOT_Data[11] = (uint8_t)(blk_size);
-
- MSC_BOT_DataLen = 12;
- return 0;
- }
-}
-/**
- * @brief SCSI_ModeSense6
- * Process Mode Sense6 command
- * @param lun: Logical unit number
- * @param params: Command parameters
- * @retval status
- */
-static int8_t SCSI_ModeSense6 (uint8_t lun, uint8_t *params)
-{
-
- uint16_t len = 8 ;
- MSC_BOT_DataLen = len;
-
- while (len)
- {
- len--;
- MSC_BOT_Data[len] = MSC_Mode_Sense6_data[len];
- }
- return 0;
-}
-
-/**
- * @brief SCSI_ModeSense10
- * Process Mode Sense10 command
- * @param lun: Logical unit number
- * @param params: Command parameters
- * @retval status
- */
-static int8_t SCSI_ModeSense10 (uint8_t lun, uint8_t *params)
-{
- uint16_t len = 8;
-
- MSC_BOT_DataLen = len;
-
- while (len)
- {
- len--;
- MSC_BOT_Data[len] = MSC_Mode_Sense10_data[len];
- }
- return 0;
-}
-
-/**
- * @brief SCSI_RequestSense
- * Process Request Sense command
- * @param lun: Logical unit number
- * @param params: Command parameters
- * @retval status
- */
-
-static int8_t SCSI_RequestSense (uint8_t lun, uint8_t *params)
-{
- uint8_t i;
-
- for(i=0 ; i < REQUEST_SENSE_DATA_LEN ; i++)
- {
- MSC_BOT_Data[i] = 0;
- }
-
- MSC_BOT_Data[0] = 0x70;
- MSC_BOT_Data[7] = REQUEST_SENSE_DATA_LEN - 6;
-
- if((SCSI_Sense_Head != SCSI_Sense_Tail)) {
-
- MSC_BOT_Data[2] = SCSI_Sense[SCSI_Sense_Head].Skey;
- MSC_BOT_Data[12] = SCSI_Sense[SCSI_Sense_Head].w.b.ASCQ;
- MSC_BOT_Data[13] = SCSI_Sense[SCSI_Sense_Head].w.b.ASC;
- SCSI_Sense_Head++;
-
- if (SCSI_Sense_Head == SENSE_LIST_DEEPTH)
- {
- SCSI_Sense_Head = 0;
- }
- }
- MSC_BOT_DataLen = REQUEST_SENSE_DATA_LEN;
-
- if (params[4] <= REQUEST_SENSE_DATA_LEN)
- {
- MSC_BOT_DataLen = params[4];
- }
- return 0;
-}
-
-/**
- * @brief SCSI_SenseCode
- * Load the last error code in the error list
- * @param lun: Logical unit number
- * @param sKey: Sense Key
- * @param ASC: Additional Sense Key
- * @retval none
-
- */
-void SCSI_SenseCode(uint8_t lun, uint8_t sKey, uint8_t ASC)
-{
- SCSI_Sense[SCSI_Sense_Tail].Skey = sKey;
- SCSI_Sense[SCSI_Sense_Tail].w.ASC = ASC << 8;
- SCSI_Sense_Tail++;
- if (SCSI_Sense_Tail == SENSE_LIST_DEEPTH)
- {
- SCSI_Sense_Tail = 0;
- }
-}
-/**
- * @brief SCSI_StartStopUnit
- * Process Start Stop Unit command
- * @param lun: Logical unit number
- * @param params: Command parameters
- * @retval status
- */
-static int8_t SCSI_StartStopUnit(uint8_t lun, uint8_t *params)
-{
- MSC_BOT_DataLen = 0;
- return 0;
-}
-
-/**
- * @brief SCSI_Read10
- * Process Read10 command
- * @param lun: Logical unit number
- * @param params: Command parameters
- * @retval status
- */
-static int8_t SCSI_Read10(uint8_t lun , uint8_t *params)
-{
- if(MSC_BOT_State == BOT_IDLE) /* Idle */
- {
-
- /* case 10 : Ho <> Di */
-
- if ((MSC_BOT_cbw.bmFlags & 0x80) != 0x80)
- {
- SCSI_SenseCode(MSC_BOT_cbw.bLUN,
- ILLEGAL_REQUEST,
- INVALID_CDB);
- return -1;
- }
-
- if(USBD_STORAGE_fops->IsReady(lun) !=0 )
- {
- SCSI_SenseCode(lun,
- NOT_READY,
- MEDIUM_NOT_PRESENT);
- return -1;
- }
-
- SCSI_blk_addr = (params[2] << 24) | \
- (params[3] << 16) | \
- (params[4] << 8) | \
- params[5];
-
- SCSI_blk_len = (params[7] << 8) | \
- params[8];
-
-
-
- if( SCSI_CheckAddressRange(lun, SCSI_blk_addr, SCSI_blk_len) < 0)
- {
- return -1; /* error */
- }
-
- MSC_BOT_State = BOT_DATA_IN;
- SCSI_blk_addr *= SCSI_blk_size;
- SCSI_blk_len *= SCSI_blk_size;
-
- /* cases 4,5 : Hi <> Dn */
- if (MSC_BOT_cbw.dDataLength != SCSI_blk_len)
- {
- SCSI_SenseCode(MSC_BOT_cbw.bLUN,
- ILLEGAL_REQUEST,
- INVALID_CDB);
- return -1;
- }
- }
- MSC_BOT_DataLen = MSC_MEDIA_PACKET;
-
- return SCSI_ProcessRead(lun);
-}
-
-/**
- * @brief SCSI_Write10
- * Process Write10 command
- * @param lun: Logical unit number
- * @param params: Command parameters
- * @retval status
- */
-
-static int8_t SCSI_Write10 (uint8_t lun , uint8_t *params)
-{
- if (MSC_BOT_State == BOT_IDLE) /* Idle */
- {
-
- /* case 8 : Hi <> Do */
-
- if ((MSC_BOT_cbw.bmFlags & 0x80) == 0x80)
- {
- SCSI_SenseCode(MSC_BOT_cbw.bLUN,
- ILLEGAL_REQUEST,
- INVALID_CDB);
- return -1;
- }
-
- /* Check whether Media is ready */
- if(USBD_STORAGE_fops->IsReady(lun) !=0 )
- {
- SCSI_SenseCode(lun,
- NOT_READY,
- MEDIUM_NOT_PRESENT);
- return -1;
- }
-
- /* Check If media is write-protected */
- if(USBD_STORAGE_fops->IsWriteProtected(lun) !=0 )
- {
- SCSI_SenseCode(lun,
- NOT_READY,
- WRITE_PROTECTED);
- return -1;
- }
-
-
- SCSI_blk_addr = (params[2] << 24) | \
- (params[3] << 16) | \
- (params[4] << 8) | \
- params[5];
- SCSI_blk_len = (params[7] << 8) | \
- params[8];
-
- /* check if LBA address is in the right range */
- if(SCSI_CheckAddressRange(lun, SCSI_blk_addr, SCSI_blk_len) < 0)
- {
- return -1; /* error */
- }
-
- SCSI_blk_addr *= SCSI_blk_size;
- SCSI_blk_len *= SCSI_blk_size;
-
- /* cases 3,11,13 : Hn,Ho <> D0 */
- if (MSC_BOT_cbw.dDataLength != SCSI_blk_len)
- {
- SCSI_SenseCode(MSC_BOT_cbw.bLUN,
- ILLEGAL_REQUEST,
- INVALID_CDB);
- return -1;
- }
-
- /* Prepare EP to receive first data packet */
- MSC_BOT_State = BOT_DATA_OUT;
- DCD_EP_PrepareRx (cdev,
- MSC_OUT_EP,
- MSC_BOT_Data,
- MIN (SCSI_blk_len, MSC_MEDIA_PACKET));
- }
- else /* Write Process ongoing */
- {
- return SCSI_ProcessWrite(lun);
- }
- return 0;
-}
-
-
-/**
- * @brief SCSI_Verify10
- * Process Verify10 command
- * @param lun: Logical unit number
- * @param params: Command parameters
- * @retval status
- */
-
-static int8_t SCSI_Verify10(uint8_t lun , uint8_t *params){
- if ((params[1]& 0x02) == 0x02)
- {
- SCSI_SenseCode (lun, ILLEGAL_REQUEST, INVALID_FIELED_IN_COMMAND);
- return -1; /* Error, Verify Mode Not supported*/
- }
-
- if(SCSI_CheckAddressRange(lun, SCSI_blk_addr, SCSI_blk_len) < 0)
- {
- return -1; /* error */
- }
- MSC_BOT_DataLen = 0;
- return 0;
-}
-
-/**
- * @brief SCSI_CheckAddressRange
- * Check address range
- * @param lun: Logical unit number
- * @param blk_offset: first block address
- * @param blk_nbr: number of block to be processed
- * @retval status
- */
-static int8_t SCSI_CheckAddressRange (uint8_t lun , uint32_t blk_offset , uint16_t blk_nbr)
-{
-
- if ((blk_offset + blk_nbr) > SCSI_blk_nbr )
- {
- SCSI_SenseCode(lun, ILLEGAL_REQUEST, ADDRESS_OUT_OF_RANGE);
- return -1;
- }
- return 0;
-}
-
-/**
- * @brief SCSI_ProcessRead
- * Handle Read Process
- * @param lun: Logical unit number
- * @retval status
- */
-static int8_t SCSI_ProcessRead (uint8_t lun)
-{
- uint32_t len;
-
- len = MIN(SCSI_blk_len , MSC_MEDIA_PACKET);
-
- if( USBD_STORAGE_fops->Read(lun ,
- MSC_BOT_Data,
- SCSI_blk_addr / SCSI_blk_size,
- len / SCSI_blk_size) < 0)
- {
-
- SCSI_SenseCode(lun, HARDWARE_ERROR, UNRECOVERED_READ_ERROR);
- return -1;
- }
-
-
- DCD_EP_Tx (cdev,
- MSC_IN_EP,
- MSC_BOT_Data,
- len);
-
-
- SCSI_blk_addr += len;
- SCSI_blk_len -= len;
-
- /* case 6 : Hi = Di */
- MSC_BOT_csw.dDataResidue -= len;
-
- if (SCSI_blk_len == 0)
- {
- MSC_BOT_State = BOT_LAST_DATA_IN;
- }
- return 0;
-}
-
-/**
- * @brief SCSI_ProcessWrite
- * Handle Write Process
- * @param lun: Logical unit number
- * @retval status
- */
-
-static int8_t SCSI_ProcessWrite (uint8_t lun)
-{
- uint32_t len;
-
- len = MIN(SCSI_blk_len , MSC_MEDIA_PACKET);
-
- if(USBD_STORAGE_fops->Write(lun ,
- MSC_BOT_Data,
- SCSI_blk_addr / SCSI_blk_size,
- len / SCSI_blk_size) < 0)
- {
- SCSI_SenseCode(lun, HARDWARE_ERROR, WRITE_FAULT);
- return -1;
- }
-
-
- SCSI_blk_addr += len;
- SCSI_blk_len -= len;
-
- /* case 12 : Ho = Do */
- MSC_BOT_csw.dDataResidue -= len;
-
- if (SCSI_blk_len == 0)
- {
- MSC_BOT_SendCSW (cdev, CSW_CMD_PASSED);
- }
- else
- {
- /* Prepare EP to Receive next packet */
- DCD_EP_PrepareRx (cdev,
- MSC_OUT_EP,
- MSC_BOT_Data,
- MIN (SCSI_blk_len, MSC_MEDIA_PACKET));
- }
-
- return 0;
-}
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/msc/src/usbd_storage_template.c b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/msc/src/usbd_storage_template.c
deleted file mode 100644
index 6b56841239f9aeb39111ec76460b9260f7f2b2ed..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Class/msc/src/usbd_storage_template.c
+++ /dev/null
@@ -1,175 +0,0 @@
-/**
- ******************************************************************************
- * @file usbd_storage_template.c
- * @author MCD Application Team
- * @version V1.0.1
- * @date 31-January-2014
- * @brief Memory management layer
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_msc_mem.h"
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-#define STORAGE_LUN_NBR 1
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* USB Mass storage Standard Inquiry Data */
-const int8_t STORAGE_Inquirydata[] = {//36
-
- /* LUN 0 */
- 0x00,
- 0x80,
- 0x02,
- 0x02,
- (USBD_STD_INQUIRY_LENGTH - 5),
- 0x00,
- 0x00,
- 0x00,
- 'S', 'T', 'M', ' ', ' ', ' ', ' ', ' ', /* Manufacturer : 8 bytes */
- 'P', 'r', 'o', 'd', 'u', 't', ' ', ' ', /* Product : 16 Bytes */
- ' ', ' ', ' ', ' ', ' ', ' ', ' ', ' ',
- '0', '.', '0' ,'1', /* Version : 4 Bytes */
-};
-
-USBD_STORAGE_cb_TypeDef USBD_MICRO_SDIO_fops =
-{
- STORAGE_Init,
- STORAGE_GetCapacity,
- STORAGE_IsReady,
- STORAGE_IsWriteProtected,
- STORAGE_Read,
- STORAGE_Write,
- STORAGE_GetMaxLun,
- STORAGE_Inquirydata,
-
-};
-
-USBD_STORAGE_cb_TypeDef *USBD_STORAGE_fops = &USBD_MICRO_SDIO_fops;
-
-/* Private function prototypes -----------------------------------------------*/
-int8_t STORAGE_Init (uint8_t lun);
-
-int8_t STORAGE_GetCapacity (uint8_t lun,
- uint32_t *block_num,
- uint16_t *block_size);
-
-int8_t STORAGE_IsReady (uint8_t lun);
-
-int8_t STORAGE_IsWriteProtected (uint8_t lun);
-
-int8_t STORAGE_Read (uint8_t lun,
- uint8_t *buf,
- uint32_t blk_addr,
- uint16_t blk_len);
-
-int8_t STORAGE_Write (uint8_t lun,
- uint8_t *buf,
- uint32_t blk_addr,
- uint16_t blk_len);
-
-int8_t STORAGE_GetMaxLun (void);
-
-/* Private functions ---------------------------------------------------------*/
-/**
- * @brief Initialize the storage medium
- * @param lun : logical unit number
- * @retval Status
- */
-int8_t STORAGE_Init (uint8_t lun)
-{
- return (0);
-}
-
-/**
- * @brief return medium capacity and block size
- * @param lun : logical unit number
- * @param block_num : number of physical block
- * @param block_size : size of a physical block
- * @retval Status
- */
-int8_t STORAGE_GetCapacity (uint8_t lun, uint32_t *block_num, uint16_t *block_size)
-{
- return (0);
-}
-
-/**
- * @brief check whether the medium is ready
- * @param lun : logical unit number
- * @retval Status
- */
-int8_t STORAGE_IsReady (uint8_t lun)
-{
- return (0);
-}
-
-/**
- * @brief check whether the medium is write-protected
- * @param lun : logical unit number
- * @retval Status
- */
-int8_t STORAGE_IsWriteProtected (uint8_t lun)
-{
- return 0;
-}
-
-/**
- * @brief Read data from the medium
- * @param lun : logical unit number
- * @param buf : Pointer to the buffer to save data
- * @param blk_addr : address of 1st block to be read
- * @param blk_len : nmber of blocks to be read
- * @retval Status
- */
-int8_t STORAGE_Read (uint8_t lun,
- uint8_t *buf,
- uint32_t blk_addr,
- uint16_t blk_len)
-{
- return 0;
-}
-/**
- * @brief Write data to the medium
- * @param lun : logical unit number
- * @param buf : Pointer to the buffer to write from
- * @param blk_addr : address of 1st block to be written
- * @param blk_len : nmber of blocks to be read
- * @retval Status
- */
-int8_t STORAGE_Write (uint8_t lun,
- uint8_t *buf,
- uint32_t blk_addr,
- uint16_t blk_len)
-{
- return (0);
-}
-/**
- * @brief Return number of supported logical unit
- * @param None
- * @retval number of logical unit
- */
-int8_t STORAGE_GetMaxLun (void)
-{
- return (STORAGE_LUN_NBR - 1);
-}
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Core/inc/usbd_conf_template.h b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Core/inc/usbd_conf_template.h
deleted file mode 100644
index e225398a76c6eeeceb0f078ac348e6aa68660ec6..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Core/inc/usbd_conf_template.h
+++ /dev/null
@@ -1,159 +0,0 @@
-/**
- ******************************************************************************
- * @file usbd_conf_template.h
- * @author MCD Application Team
- * @version V1.0.1
- * @date 31-January-2014
- * @brief usb device configuration template file
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __USBD_CONF__H__
-#define __USBD_CONF__H__
-
-/* Includes ------------------------------------------------------------------*/
-#include "usb_conf.h"
-#include "audio_app_conf.h" /* Audio example Include*/
-
-/* Exported defines ----------------------------------------------------------*/
-/*Common Defines*/
-#define USBD_SELF_POWERED
-#define USBD_CFG_MAX_NUM 1
-
-/*Audio Class user defines*/
-#define AUDIO_TOTAL_IF_NUM 0x02
-#define USBD_ITF_MAX_NUM 1
-#define USB_MAX_STR_DESC_SIZ 200
-#define AUDIO_OUT_EP 0x01
-
-/*CCID Class user defines*/
-#define USBD_ITF_MAX_NUM 1
-#define USB_MAX_STR_DESC_SIZ 64
-#define USB_SUPPORT_USER_STRING_DESC
-#define CCID_BULK_IN_EP 0x81
-#define CCID_BULK_OUT_EP 0x01
-#define CCID_INTR_IN_EP 0x82
-#define CCID_BULK_EP_MAX_PACKET 64
-#define CCID_INTR_EP_MAX_PACKET 8
-
-/*Composite HID + CDC Classes user defines*/
-#define USBD_ITF_MAX_NUM 1
-#define USB_MAX_STR_DESC_SIZ 64
-#define CUSTOMHID_SIZ_REPORT_DESC 163
-#define CUSTOMHID_SIZ_CONFIG_DESC 41
-#define HID_IN_EP 0x81
-#define HID_OUT_EP 0x01
-
-/*2 Bytes max*/
-#define HID_IN_PACKET 2
-#define HID_OUT_PACKET 2
-#define CDC_IN_EP 0x83 /* EP1 for data IN */
-#define CDC_OUT_EP 0x03 /* EP3 for data OUT */
-#define CDC_CMD_EP 0x82 /* EP2 for CDC commands */
-
-/* CDC Endpoints parameters: you can fine tune these values depending on the needed baudrate and performance. */
-#define CDC_DATA_MAX_PACKET_SIZE 64 /* Endpoint IN & OUT Packet size */
-#define CDC_CMD_PACKET_SZE 8 /* Control Endpoint Packet size */
-#define CDC_IN_FRAME_INTERVAL 5 /* Number of frames between IN transfers */
-#define APP_RX_DATA_SIZE 2048 /* Total size of IN buffer: APP_RX_DATA_SIZE*8/MAX_BAUDARATE*1000
- should be > CDC_IN_FRAME_INTERVAL */
-#define APP_FOPS VCP_fops
-
-/*Composite HID + MSC Class user defines*/
-#define USBD_ITF_MAX_NUM 1
-#define USB_MAX_STR_DESC_SIZ 64
-#define CUSTOMHID_SIZ_REPORT_DESC 163
-#define CUSTOMHID_SIZ_CONFIG_DESC 41
-#define HID_IN_EP 0x81
-#define HID_OUT_EP 0x01
-/*2 Bytes max*/
-#define HID_IN_PACKET 2
-#define HID_OUT_PACKET 2
-#define MSC_IN_EP 0x82
-#define MSC_OUT_EP 0x02
-#define MSC_MAX_PACKET 64
-#define MSC_MEDIA_PACKET 512
-
-/*Custom HID Class user defines*/
-#define USBD_ITF_MAX_NUM 1
-#define USB_MAX_STR_DESC_SIZ 64
-#define CUSTOMHID_SIZ_REPORT_DESC 163
-#define CUSTOMHID_SIZ_CONFIG_DESC 41
-#define HID_IN_EP 0x81
-#define HID_OUT_EP 0x01
-#define HID_IN_PACKET 2
-#define HID_OUT_PACKET 2
-
-/*DFU Class user defines*/
-#define USBD_ITF_MAX_NUM MAX_USED_MEDIA
-#define USB_MAX_STR_DESC_SIZ 200
-#define USB_SUPPORT_USER_STRING_DESC
-#define XFERSIZE 1024 /* Max DFU Packet Size = 1024 bytes */
-#define DFU_IN_EP 0x80
-#define DFU_OUT_EP 0x00
- /* Maximum number of supported media (Flash) */
-#define MAX_USED_MEDIA 1
-/* Flash memory address from where user application will be loaded
- This address represents the DFU code protected against write and erase operations.*/
-#define APP_DEFAULT_ADD 0x08003000
-#define DFU_MAL_IS_PROTECTED_AREA(add) (uint8_t)(((add >= 0x08000000) && (add < (APP_DEFAULT_ADD)))? 1:0)
-#define TRANSFER_SIZE_BYTES(sze) ((uint8_t)(sze)), /* XFERSIZEB0 */\
- ((uint8_t)(sze >> 8)) /* XFERSIZEB1 */
-
-/*HID Class user defines*/
-#define USBD_ITF_MAX_NUM 1
-#define USB_MAX_STR_DESC_SIZ 64
-#define USB_SUPPORT_USER_STRING_DESC
-#define HID_IN_EP 0x81
-#define HID_OUT_EP 0x01
-#define HID_IN_PACKET 4
-#define HID_OUT_PACKET 4
-
-/*MSC Class user defines*/
-#define USBD_ITF_MAX_NUM 1
-#define USB_MAX_STR_DESC_SIZ 64
-#define MSC_IN_EP 0x81
-#define MSC_OUT_EP 0x02
-#define MSC_MAX_PACKET 64
-#define MSC_MEDIA_PACKET 512
-
-/*VCP Class user defines*/
-#define USBD_ITF_MAX_NUM 1
-#define USB_MAX_STR_DESC_SIZ 255
-#define CDC_IN_EP 0x81 /* EP1 for data IN */
-#define CDC_OUT_EP 0x03 /* EP3 for data OUT */
-#define CDC_CMD_EP 0x82 /* EP2 for CDC commands */
-/* CDC Endpoints parameters: you can fine tune these values depending on the needed baudrate and performance. */
-#define CDC_DATA_MAX_PACKET_SIZE 64 /* Endpoint IN & OUT Packet size */
-#define CDC_CMD_PACKET_SZE 8 /* Control Endpoint Packet size */
-#define CDC_IN_FRAME_INTERVAL 5 /* Number of frames between IN transfers */
-#define APP_RX_DATA_SIZE 2048 /* Total size of IN buffer:
- APP_RX_DATA_SIZE*8/MAX_BAUDARATE*1000 should be > CDC_IN_FRAME_INTERVAL */
-#define APP_FOPS VCP_fops
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported macros -----------------------------------------------------------*/
-/* Exported variables --------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-#endif /* __USBD_CONF__H__ */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Core/inc/usbd_core.h b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Core/inc/usbd_core.h
deleted file mode 100644
index 094c0506797a93b3dbda57daac35f64f787ae779..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Core/inc/usbd_core.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/**
- ******************************************************************************
- * @file usbd_core.h
- * @author MCD Application Team
- * @version V1.0.1
- * @date 31-January-2014
- * @brief Header file for usbd_core.c
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __USBD_CORE_H
-#define __USBD_CORE_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "usb_dcd.h"
-#include "usb_dcd_int.h"
-
-/* Exported defines ----------------------------------------------------------*/
-/* Exported types ------------------------------------------------------------*/
-typedef enum {
- USBD_OK = 0,
- USBD_BUSY,
- USBD_FAIL,
-}USBD_Status;
-/* Exported macros -----------------------------------------------------------*/
-/* Exported variables --------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-void USBD_Init(USB_CORE_HANDLE *pdev,
- USBD_DEVICE *pDevice,
- USBD_Class_cb_TypeDef *class_cb,
- USBD_Usr_cb_TypeDef *usr_cb);
-
-USBD_Status USBD_DeInit(USB_CORE_HANDLE *pdev);
-
-USBD_Status USBD_ClrCfg(USB_CORE_HANDLE *pdev, uint8_t cfgidx);
-
-USBD_Status USBD_SetCfg(USB_CORE_HANDLE *pdev, uint8_t cfgidx);
-
-#endif /* __USBD_CORE_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Core/inc/usbd_def.h b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Core/inc/usbd_def.h
deleted file mode 100644
index e993039b2de33387522481498e5c28a0b381d786..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Core/inc/usbd_def.h
+++ /dev/null
@@ -1,100 +0,0 @@
-/**
- ******************************************************************************
- * @file usbd_def.h
- * @author MCD Application Team
- * @version V1.0.1
- * @date 31-January-2014
- * @brief general defines for the usb device library
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __USBD_DEF_H
-#define __USBD_DEF_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_conf.h"
-#include "stdbool.h"
-
-/* Exported defines ----------------------------------------------------------*/
-#ifndef NULL
- #define NULL 0
-#endif
-
-#define USB_LEN_DEV_QUALIFIER_DESC 0x0A
-#define USB_LEN_CFG_DESC 0x09
-
-#define USBD_IDX_LANGID_STR 0x00
-#define USBD_IDX_MFC_STR 0x01
-#define USBD_IDX_PRODUCT_STR 0x02
-#define USBD_IDX_SERIAL_STR 0x03
-#define USBD_IDX_CONFIG_STR 0x04
-#define USBD_IDX_INTERFACE_STR 0x05
-
-#define USB_REQ_TYPE_STANDARD 0x00
-#define USB_REQ_TYPE_CLASS 0x20
-#define USB_REQ_TYPE_MASK 0x60
-
-#define USB_REQ_RECIPIENT_DEVICE 0x00
-#define USB_REQ_RECIPIENT_INTERFACE 0x01
-#define USB_REQ_RECIPIENT_ENDPOINT 0x02
-#define USB_REQ_RECIPIENT_MASK 0x03
-
-#define USB_REQ_GET_STATUS 0x00
-#define USB_REQ_CLEAR_FEATURE 0x01
-#define USB_REQ_SET_FEATURE 0x03
-#define USB_REQ_SET_ADDRESS 0x05
-#define USB_REQ_GET_DESCRIPTOR 0x06
-#define USB_REQ_GET_CONFIGURATION 0x08
-#define USB_REQ_SET_CONFIGURATION 0x09
-#define USB_REQ_GET_INTERFACE 0x0A
-#define USB_REQ_SET_INTERFACE 0x0B
-
-#define USB_DESC_TYPE_DEVICE 1
-#define USB_DESC_TYPE_CONFIGURATION 2
-#define USB_DESC_TYPE_STRING 3
-#define USB_DESC_TYPE_DEVICE_QUALIFIER 6
-#define USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION 7
-#define USB_DESC_TYPE_BOS 0xF
-
-
-#define USB_CONFIG_REMOTE_WAKEUP 2
-#define USB_CONFIG_SELF_POWERED 1
-
-#define USB_FEATURE_EP_HALT 0
-#define USB_FEATURE_REMOTE_WAKEUP 1
-#define USB_FEATURE_TEST_MODE 2
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported macros -----------------------------------------------------------*/
-#define SWAPBYTE(addr) (((uint16_t)(*((uint8_t *)(addr)))) + \
- (((uint16_t)(*(((uint8_t *)(addr)) + 1))) << 8))
-
-#define LOBYTE(x) ((uint8_t)(x & 0x00FF))
-#define HIBYTE(x) ((uint8_t)((x & 0xFF00) >>8))
-
-#define MIN(a, b) (((a) < (b)) ? (a) : (b))
-/* Exported variables --------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-
-#endif /* __USBD_DEF_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Core/inc/usbd_ioreq.h b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Core/inc/usbd_ioreq.h
deleted file mode 100644
index ed9c29b433a457c10b19d7d382afa5b8bd186af6..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Core/inc/usbd_ioreq.h
+++ /dev/null
@@ -1,68 +0,0 @@
-/**
- ******************************************************************************
- * @file usbd_ioreq.h
- * @author MCD Application Team
- * @version V1.0.1
- * @date 31-January-2014
- * @brief header file for the usbd_ioreq.c file
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __USBD_IOREQ_H_
-#define __USBD_IOREQ_H_
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_def.h"
-#include "usbd_core.h"
-
-/* Exported defines ----------------------------------------------------------*/
-/* Exported types ------------------------------------------------------------*/
-/* Exported macros -----------------------------------------------------------*/
-/* Exported variables --------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-USBD_Status USBD_CtlSendData (USB_CORE_HANDLE *pdev,
- uint8_t *buf,
- uint16_t len);
-
-USBD_Status USBD_CtlContinueSendData (USB_CORE_HANDLE *pdev,
- uint8_t *pbuf,
- uint16_t len);
-
-USBD_Status USBD_CtlPrepareRx (USB_CORE_HANDLE *pdev,
- uint8_t *pbuf,
- uint16_t len);
-
-USBD_Status USBD_CtlContinueRx (USB_CORE_HANDLE *pdev,
- uint8_t *pbuf,
- uint16_t len);
-
-USBD_Status USBD_CtlSendStatus (USB_CORE_HANDLE *pdev);
-
-USBD_Status USBD_CtlReceiveStatus (USB_CORE_HANDLE *pdev);
-
-uint16_t USBD_GetRxCount (USB_CORE_HANDLE *pdev ,
- uint8_t epnum);
-
-
-#endif /* __USBD_IOREQ_H_ */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Core/inc/usbd_pwr.h b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Core/inc/usbd_pwr.h
deleted file mode 100644
index fc966af1d7a685980133b28734c966595b350746..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Core/inc/usbd_pwr.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/**
- ******************************************************************************
- * @file usbd_pwr.h
- * @author MCD Application Team
- * @version V1.0.1
- * @date 31-January-2014
- * @brief Header file for usbd_pwr.c
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __USBD_PWR_H__
-#define __USBD_PWR_H__
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_core.h"
-#include "usb_bsp.h"
-
-/* Exported defines ----------------------------------------------------------*/
-/* Exported types ------------------------------------------------------------*/
-typedef enum _RESUME_STATE
-{
- RESUME_EXTERNAL,
- RESUME_INTERNAL,
-#ifdef LPM_ENABLED
- L1_RESUME_INTERNAL,
-#endif
- RESUME_LATER,
- RESUME_WAIT,
- RESUME_START,
- RESUME_ON,
- RESUME_OFF,
- RESUME_ESOF
-} RESUME_STATE;
-
-/* Exported macros -----------------------------------------------------------*/
-/* Exported variables --------------------------------------------------------*/
-extern USB_CORE_HANDLE USB_Device_dev;
-
-/* Exported functions ------------------------------------------------------- */
-void Suspend(void);
-void Resume_Init(void);
-void Resume(RESUME_STATE eResumeSetVal);
-void Leave_LowPowerMode(void);
-
-#endif /*__USBD_PWR_H__*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Core/inc/usbd_req.h b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Core/inc/usbd_req.h
deleted file mode 100644
index 7e53ea65c9dd90012113b1f8c7500b983eacda55..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Core/inc/usbd_req.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/**
- ******************************************************************************
- * @file usbd_req.h
- * @author MCD Application Team
- * @version V1.0.1
- * @date 31-January-2014
- * @brief header file for the usbd_req.c file
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-
-#ifndef __USB_REQUEST_H_
-#define __USB_REQUEST_H_
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_ioreq.h"
-#include "usbd_desc.h"
-
-/* Exported defines ----------------------------------------------------------*/
-/* Exported types ------------------------------------------------------------*/
-/* Exported macros -----------------------------------------------------------*/
-/* Exported variables --------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-USBD_Status USBD_StdDevReq (USB_CORE_HANDLE *pdev, USB_SETUP_REQ *req);
-USBD_Status USBD_StdItfReq (USB_CORE_HANDLE *pdev, USB_SETUP_REQ *req);
-USBD_Status USBD_StdEPReq (USB_CORE_HANDLE *pdev, USB_SETUP_REQ *req);
-void USBD_ParseSetupRequest( USB_CORE_HANDLE *pdev,
- USB_SETUP_REQ *req);
-
-void USBD_CtlError( USB_CORE_HANDLE *pdev,
- USB_SETUP_REQ *req);
-
-void USBD_GetString(uint8_t *desc, uint8_t *unicode, uint16_t *len);
-
-#endif /* __USB_REQUEST_H_ */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Core/inc/usbd_usr.h b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Core/inc/usbd_usr.h
deleted file mode 100644
index 6f9ada201c668e18bce8f02447ec43859afe2b48..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Core/inc/usbd_usr.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/**
- ******************************************************************************
- * @file usbd_usr.h
- * @author MCD Application Team
- * @version V1.0.1
- * @date 31-January-2014
- * @brief Header file for usbd_usr.c
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __USBD_USR_H__
-#define __USBD_USR_H__
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_core.h"
-
-/* Exported defines ----------------------------------------------------------*/
-/* Exported types ------------------------------------------------------------*/
-/* Exported macros -----------------------------------------------------------*/
-/* Exported variables --------------------------------------------------------*/
-extern USBD_Usr_cb_TypeDef USR_cb;
-
-/* Exported functions ------------------------------------------------------- */
-void USBD_USR_Init(void);
-void USBD_USR_DeviceReset (uint8_t speed);
-void USBD_USR_DeviceConfigured (void);
-void USBD_USR_DeviceSuspended(void);
-void USBD_USR_DeviceResumed(void);
-
-#endif /*__USBD_USR_H__*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Core/src/usbd_core.c b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Core/src/usbd_core.c
deleted file mode 100644
index 5ae1d06632a819773f4674e4d5eced3758830045..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Core/src/usbd_core.c
+++ /dev/null
@@ -1,366 +0,0 @@
-/**
- ******************************************************************************
- * @file usbd_core.c
- * @author MCD Application Team
- * @version V1.0.1
- * @date 31-January-2014
- * @brief This file provides all the USBD core functions.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_core.h"
-#include "usbd_req.h"
-#include "usbd_ioreq.h"
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-extern uint32_t ADDRESS;
-
-/* Private function prototypes -----------------------------------------------*/
-static uint8_t USBD_SetupStage(USB_CORE_HANDLE *pdev);
-static uint8_t USBD_DataOutStage(USB_CORE_HANDLE *pdev , uint8_t epnum);
-static uint8_t USBD_DataInStage(USB_CORE_HANDLE *pdev , uint8_t epnum);
-static uint8_t USBD_SOF(USB_CORE_HANDLE *pdev);
-static uint8_t USBD_Reset(USB_CORE_HANDLE *pdev);
-static uint8_t USBD_Suspend(USB_CORE_HANDLE *pdev);
-static uint8_t USBD_Resume(USB_CORE_HANDLE *pdev);
-
-USBD_DCD_INT_cb_TypeDef USBD_DCD_INT_cb =
-{
- USBD_DataOutStage,
- USBD_DataInStage,
- USBD_SetupStage,
- USBD_SOF,
- USBD_Reset,
- USBD_Suspend,
- USBD_Resume,
-
-};
-
-USBD_DCD_INT_cb_TypeDef *USBD_DCD_INT_fops = &USBD_DCD_INT_cb;
-
-/* Private functions ---------------------------------------------------------*/
-/**
- * @brief USBD_Init
- * Initializes the device stack and load the class driver
- * @param pdev: device instance
- * @param class_cb: Class callback structure address
- * @param usr_cb: User callback structure address
- * @retval None
- */
-void USBD_Init(USB_CORE_HANDLE *pdev,
- USBD_DEVICE *pDevice,
- USBD_Class_cb_TypeDef *class_cb,
- USBD_Usr_cb_TypeDef *usr_cb)
-{
- /* Hardware Init */
- USB_BSP_Init(pdev);
-
- USBD_DeInit(pdev);
-
- /*Register class and user callbacks */
- pdev->dev.class_cb = class_cb;
- pdev->dev.usr_cb = usr_cb;
- pdev->dev.usr_device = pDevice;
-
- /* Update the serial number string descriptor with the data from the unique ID*/
- Get_SerialNum();
-
- /* set USB DEVICE core params */
- DCD_Init(pdev);
-
- /* Upon Init call usr callback */
- pdev->dev.usr_cb->Init();
-
- /* Enable Interrupts */
- USB_BSP_EnableInterrupt(pdev);
-
- /* Enable the pull-up */
-#ifdef INTERNAL_PULLUP
- DCD_DevConnect(pdev);
-#else
- USB_BSP_DevConnect(pdev);
-#endif
-}
-
-/**
- * @brief USBD_DeInit
- * Re-Initialize th device library
- * @param pdev: device instance
- * @retval status: status
- */
-USBD_Status USBD_DeInit(USB_CORE_HANDLE *pdev)
-{
- /* Software Init */
-
- return USBD_OK;
-}
-
-/**
- * @brief USBD_SetupStage
- * Handle the setup stage
- * @param pdev: device instance
- * @retval status
- */
-static uint8_t USBD_SetupStage(USB_CORE_HANDLE *pdev)
-{
- USB_SETUP_REQ req;
-
- USBD_ParseSetupRequest(pdev , &req);
-
- switch (req.bmRequest & 0x1F)
- {
- case USB_REQ_RECIPIENT_DEVICE:
- USBD_StdDevReq (pdev, &req);
- break;
-
- case USB_REQ_RECIPIENT_INTERFACE:
- USBD_StdItfReq(pdev, &req);
- break;
-
- case USB_REQ_RECIPIENT_ENDPOINT:
- USBD_StdEPReq(pdev, &req);
- break;
-
- default:
- DCD_EP_Stall(pdev , req.bmRequest & 0x80);
- break;
- }
- return USBD_OK;
-}
-
-/**
- * @brief USBD_DataOutStage
- * Handle data out stage
- * @param pdev: device instance
- * @param epnum: endpoint index
- * @retval status
- */
-static uint8_t USBD_DataOutStage(USB_CORE_HANDLE *pdev , uint8_t epnum)
-{
- USB_EP *ep;
-
- if(epnum == 0)
- {
- ep = &pdev->dev.out_ep[0];
- if ( pdev->dev.device_state == USB_EP0_DATA_OUT)
- {
- if(ep->rem_data_len > ep->maxpacket)
- {
- ep->rem_data_len -= ep->maxpacket;
-
- USBD_CtlContinueRx (pdev,
- ep->xfer_buff,
- MIN(ep->rem_data_len ,ep->maxpacket));
- }
- else
- {
- if((pdev->dev.class_cb->EP0_RxReady != NULL)&&
- (pdev->dev.device_status == USB_CONFIGURED))
- {
- pdev->dev.class_cb->EP0_RxReady(pdev);
- }
- USBD_CtlSendStatus(pdev);
- }
- }
- }
- else if((pdev->dev.class_cb->DataOut != NULL)&&
- (pdev->dev.device_status == USB_CONFIGURED))
- {
- pdev->dev.class_cb->DataOut(pdev, epnum);
- }
- return USBD_OK;
-}
-
-/**
- * @brief USBD_DataInStage
- * Handle data in stage
- * @param pdev: device instance
- * @param epnum: endpoint index
- * @retval status
- */
-static uint8_t USBD_DataInStage(USB_CORE_HANDLE *pdev , uint8_t epnum)
-{
- USB_EP *ep;
-
- if(epnum == 0)
- {
- ep = &pdev->dev.in_ep[0];
- if ( pdev->dev.device_state == USB_EP0_DATA_IN)
- {
- if(ep->rem_data_len > ep->maxpacket)
- {
- ep->rem_data_len -= ep->maxpacket;
- USBD_CtlContinueSendData (pdev,
- ep->xfer_buff,
- ep->rem_data_len);
- }
- else
- { /* last packet is MPS multiple, so send ZLP packet */
- if((ep->total_data_len % ep->maxpacket == 0) &&
- (ep->total_data_len >= ep->maxpacket) &&
- (ep->total_data_len < ep->ctl_data_len ))
- {
-
- USBD_CtlContinueSendData(pdev , NULL, 0);
- ep->ctl_data_len = 0;
- }
- else
- {
- if((pdev->dev.class_cb->EP0_TxSent != NULL)&&
- (pdev->dev.device_status == USB_CONFIGURED))
- {
- pdev->dev.class_cb->EP0_TxSent(pdev);
- }
- USBD_CtlReceiveStatus(pdev);
- }
- }
- }
- else if ((pdev->dev.device_state == USB_EP0_STATUS_IN)&& (ADDRESS!=0))
- {
-
- DCD_EP_SetAddress(pdev, ADDRESS);
- ADDRESS = 0;
- }
- }
- else if((pdev->dev.class_cb->DataIn != NULL)&&
- (pdev->dev.device_status == USB_CONFIGURED))
- {
- pdev->dev.class_cb->DataIn(pdev, epnum);
- }
- return USBD_OK;
-}
-
-/**
- * @brief USBD_Reset
- * Handle Reset event
- * @param pdev: device instance
- * @retval status
- */
-
-static uint8_t USBD_Reset(USB_CORE_HANDLE *pdev)
-{
-
- DCD_PMA_Config(pdev , 0x00 ,USB_SNG_BUF, ENDP0_RX_ADDRESS);
- DCD_PMA_Config(pdev , 0x80 ,USB_SNG_BUF, ENDP0_TX_ADDRESS);
-
- /* Open EP0 OUT */
- DCD_EP_Open(pdev,
- 0x00,
- USB_MAX_EP0_SIZE,
- EP_TYPE_CTRL);
-
- /* Open EP0 IN */
- DCD_EP_Open(pdev,
- 0x80,
- USB_MAX_EP0_SIZE,
- EP_TYPE_CTRL);
-
- /* Upon Reset call user call back */
- pdev->dev.device_status = USB_DEFAULT;
- pdev->dev.usr_cb->DeviceReset(pdev->dev.speed);
-
- return USBD_OK;
-}
-
-/**
- * @brief USBD_Resume
- * Handle Resume event
- * @param pdev: device instance
- * @retval status
- */
-
-static uint8_t USBD_Resume(USB_CORE_HANDLE *pdev)
-{
- /* Upon Resume call user call back */
- pdev->dev.usr_cb->DeviceResumed();
- pdev->dev.device_status = pdev->dev.device_old_status;
- return USBD_OK;
-}
-
-
-/**
- * @brief USBD_Suspend
- * Handle Suspend event
- * @param pdev: device instance
- * @retval status
- */
-
-static uint8_t USBD_Suspend(USB_CORE_HANDLE *pdev)
-{
- pdev->dev.device_old_status = pdev->dev.device_status;
- /*Device is in Suspended State*/
- pdev->dev.device_status = USB_SUSPENDED;
- /* Upon Resume call user call back */
- pdev->dev.usr_cb->DeviceSuspended();
- return USBD_OK;
-}
-
-
-/**
- * @brief USBD_SOF
- * Handle SOF event
- * @param pdev: device instance
- * @retval status
- */
-
-static uint8_t USBD_SOF(USB_CORE_HANDLE *pdev)
-{
- if(pdev->dev.class_cb->SOF)
- {
- pdev->dev.class_cb->SOF(pdev);
- }
- return USBD_OK;
-}
-/**
- * @brief USBD_SetCfg
- * Configure device and start the interface
- * @param pdev: device instance
- * @param cfgidx: configuration index
- * @retval status
- */
-
-USBD_Status USBD_SetCfg(USB_CORE_HANDLE *pdev, uint8_t cfgidx)
-{
- pdev->dev.class_cb->Init(pdev, cfgidx);
-
- /* Upon set config call user call back */
- pdev->dev.usr_cb->DeviceConfigured();
- return USBD_OK;
-}
-
-/**
- * @brief USBD_ClrCfg
- * Clear current configuration
- * @param pdev: device instance
- * @param cfgidx: configuration index
- * @retval status: USBD_Status
- */
-USBD_Status USBD_ClrCfg(USB_CORE_HANDLE *pdev, uint8_t cfgidx)
-{
- pdev->dev.class_cb->DeInit(pdev, cfgidx);
- return USBD_OK;
-}
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Core/src/usbd_ioreq.c b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Core/src/usbd_ioreq.c
deleted file mode 100644
index 181c9dd9d9e007aac88dfc027541c5f6deb38c59..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Core/src/usbd_ioreq.c
+++ /dev/null
@@ -1,175 +0,0 @@
-/**
- ******************************************************************************
- * @file usbd_ioreq.c
- * @author MCD Application Team
- * @version V1.0.1
- * @date 31-January-2014
- * @brief This file provides the IO requests APIs for control endpoints.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_ioreq.h"
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-/**
- * @brief USBD_CtlSendData
- * send data on the ctl pipe
- * @param pdev: device instance
- * @param buff: pointer to data buffer
- * @param len: length of data to be sent
- * @retval status
- */
-USBD_Status USBD_CtlSendData (USB_CORE_HANDLE *pdev,
- uint8_t *pbuf,
- uint16_t len)
-{
- USBD_Status ret = USBD_OK;
-
- pdev->dev.in_ep[0].total_data_len = len;
- pdev->dev.in_ep[0].rem_data_len = len;
- pdev->dev.device_state = USB_EP0_DATA_IN;
-
- DCD_EP_Tx (pdev, 0, pbuf, len);
-
- return ret;
-}
-
-/**
- * @brief USBD_CtlContinueSendData
- * continue sending data on the ctl pipe
- * @param pdev: device instance
- * @param buff: pointer to data buffer
- * @param len: length of data to be sent
- * @retval status
- */
-USBD_Status USBD_CtlContinueSendData (USB_CORE_HANDLE *pdev,
- uint8_t *pbuf,
- uint16_t len)
-{
- USBD_Status ret = USBD_OK;
-
- DCD_EP_Tx (pdev, 0, pbuf, len);
-
-
- return ret;
-}
-
-/**
- * @brief USBD_CtlPrepareRx
- * receive data on the ctl pipe
- * @param pdev: USB device instance
- * @param buff: pointer to data buffer
- * @param len: length of data to be received
- * @retval status
- */
-USBD_Status USBD_CtlPrepareRx (USB_CORE_HANDLE *pdev,
- uint8_t *pbuf,
- uint16_t len)
-{
- USBD_Status ret = USBD_OK;
-
- pdev->dev.out_ep[0].total_data_len = len;
- pdev->dev.out_ep[0].rem_data_len = len;
- pdev->dev.device_state = USB_EP0_DATA_OUT;
-
- DCD_EP_PrepareRx (pdev,
- 0,
- pbuf,
- len);
-
-
- return ret;
-}
-
-/**
- * @brief USBD_CtlContinueRx
- * continue receive data on the ctl pipe
- * @param pdev: USB device instance
- * @param buff: pointer to data buffer
- * @param len: length of data to be received
- * @retval status
- */
-USBD_Status USBD_CtlContinueRx (USB_CORE_HANDLE *pdev,
- uint8_t *pbuf,
- uint16_t len)
-{
- USBD_Status ret = USBD_OK;
-
- DCD_EP_PrepareRx (pdev,
- 0,
- pbuf,
- len);
- return ret;
-}
-/**
- * @brief USBD_CtlSendStatus
- * send zero length packet on the ctl pipe
- * @param pdev: USB device instance
- * @retval status
- */
-USBD_Status USBD_CtlSendStatus (USB_CORE_HANDLE *pdev)
-{
- USBD_Status ret = USBD_OK;
- pdev->dev.device_state = USB_EP0_STATUS_IN;
- DCD_EP_Tx (pdev,
- 0,
- NULL,
- 0);
- return ret;
-}
-
-/**
- * @brief USBD_CtlReceiveStatus
- * receive zero length packet on the ctl pipe
- * @param pdev: USB device instance
- * @retval status
- */
-USBD_Status USBD_CtlReceiveStatus (USB_CORE_HANDLE *pdev)
-{
- USBD_Status ret = USBD_OK;
- pdev->dev.device_state = USB_EP0_STATUS_OUT;
- DCD_EP_PrepareRx ( pdev,
- 0,
- NULL,
- 0);
-
- return ret;
-}
-
-
-/**
- * @brief USBD_GetRxCount
- * returns the received data length
- * @param pdev: USB device instance
- * epnum: endpoint index
- * @retval Rx Data blength
- */
-uint16_t USBD_GetRxCount (USB_CORE_HANDLE *pdev , uint8_t epnum)
-{
- return pdev->dev.out_ep[epnum].xfer_count;
-}
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Core/src/usbd_req.c b/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Core/src/usbd_req.c
deleted file mode 100644
index e75340b1d3ef25af8cf0b3ed6eae4a801d6c03bd..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/STM32F0x2_USB-FS-Device_Lib V1.0.0/Libraries/STM32_USB_Device_Library/Core/src/usbd_req.c
+++ /dev/null
@@ -1,693 +0,0 @@
-/**
- ******************************************************************************
- * @file usbd_req.c
- * @author MCD Application Team
- * @version V1.0.1
- * @date 31-January-2014
- * @brief This file provides the standard USB requests following chapter 9.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_req.h"
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-uint32_t ADDRESS=0;
-uint8_t USBD_StrDesc[USB_MAX_STR_DESC_SIZ] ;
-
-/* Private function prototypes -----------------------------------------------*/
-static void USBD_GetDescriptor(USB_CORE_HANDLE *pdev,
- USB_SETUP_REQ *req);
-
-static void USBD_SetAddress(USB_CORE_HANDLE *pdev,
- USB_SETUP_REQ *req);
-
-static void USBD_SetConfig(USB_CORE_HANDLE *pdev,
- USB_SETUP_REQ *req);
-
-static void USBD_GetConfig(USB_CORE_HANDLE *pdev,
- USB_SETUP_REQ *req);
-
-static void USBD_GetStatus(USB_CORE_HANDLE *pdev,
- USB_SETUP_REQ *req);
-
-static void USBD_SetFeature(USB_CORE_HANDLE *pdev,
- USB_SETUP_REQ *req);
-
-static void USBD_ClrFeature(USB_CORE_HANDLE *pdev,
- USB_SETUP_REQ *req);
-
-static uint8_t USBD_GetLen(uint8_t *buf);
-
-/* Private functions ---------------------------------------------------------*/
-/**
- * @brief USBD_StdDevReq
- * Handle standard usb device requests
- * @param pdev: device instance
- * @param req: usb request
- * @retval status
- */
-USBD_Status USBD_StdDevReq (USB_CORE_HANDLE *pdev, USB_SETUP_REQ *req)
-{
- USBD_Status ret = USBD_OK;
-
- switch (req->bRequest)
- {
- case USB_REQ_GET_DESCRIPTOR:
-
- USBD_GetDescriptor (pdev, req) ;
- break;
-
- case USB_REQ_SET_ADDRESS:
- USBD_SetAddress(pdev, req);
- break;
-
- case USB_REQ_SET_CONFIGURATION:
- USBD_SetConfig (pdev , req);
- break;
-
- case USB_REQ_GET_CONFIGURATION:
- USBD_GetConfig (pdev , req);
- break;
-
- case USB_REQ_GET_STATUS:
- USBD_GetStatus (pdev , req);
- break;
-
-
- case USB_REQ_SET_FEATURE:
- USBD_SetFeature (pdev , req);
- break;
-
- case USB_REQ_CLEAR_FEATURE:
- USBD_ClrFeature (pdev , req);
- break;
-
- default:
- USBD_CtlError(pdev , req);
- break;
- }
-
- return ret;
-}
-
-/**
- * @brief USBD_StdItfReq
- * Handle standard usb interface requests
- * @param pdev: USB device instance
- * @param req: usb request
- * @retval status
- */
-USBD_Status USBD_StdItfReq (USB_CORE_HANDLE *pdev, USB_SETUP_REQ *req)
-{
- USBD_Status ret = USBD_OK;
-
- switch (pdev->dev.device_status)
- {
- case USB_CONFIGURED:
-
- if (LOBYTE(req->wIndex) <= USBD_ITF_MAX_NUM)
- {
- ret = (USBD_Status) (pdev->dev.class_cb->Setup (pdev, req));
-
- if((req->wLength == 0)&& (ret == USBD_OK))
- {
- USBD_CtlSendStatus(pdev);
- }
- }
- else
- {
- USBD_CtlError(pdev , req);
- }
- break;
-
- default:
- USBD_CtlError(pdev , req);
- break;
- }
- return ret;
-}
-
-/**
- * @brief USBD_StdEPReq
- * Handle standard usb endpoint requests
- * @param pdev: USB device instance
- * @param req: usb request
- * @retval status
- */
-USBD_Status USBD_StdEPReq (USB_CORE_HANDLE *pdev, USB_SETUP_REQ *req)
-{
-
- uint8_t ep_addr;
- uint32_t USBD_ep_status = 0;
- USBD_Status ret = USBD_OK;
-
- ep_addr = LOBYTE(req->wIndex);
-
- switch (req->bRequest)
- {
- case USB_REQ_SET_FEATURE :
-
- switch (pdev->dev.device_status)
- {
- case USB_ADDRESSED:
- if ((ep_addr != 0x00) && (ep_addr != 0x80))
- {
- DCD_EP_Stall(pdev , ep_addr);
- }
- break;
-
- case USB_CONFIGURED:
- if (req->wValue == USB_FEATURE_EP_HALT)
- {
- if ((ep_addr != 0x00) && (ep_addr != 0x80))
- {
- DCD_EP_Stall(pdev , ep_addr);
-
- }
- }
- pdev->dev.class_cb->Setup (pdev, req);
- USBD_CtlSendStatus(pdev);
-
- break;
-
- default:
- USBD_CtlError(pdev , req);
- break;
- }
- break;
-
- case USB_REQ_CLEAR_FEATURE :
-
- switch (pdev->dev.device_status)
- {
- case USB_ADDRESSED:
- if ((ep_addr != 0x00) && (ep_addr != 0x80))
- {
- DCD_EP_Stall(pdev , ep_addr);
- }
- break;
-
- case USB_CONFIGURED:
- if (req->wValue == USB_FEATURE_EP_HALT)
- {
- if ((ep_addr != 0x00) && (ep_addr != 0x80))
- {
- DCD_EP_ClrStall(pdev , ep_addr);
- }
- }
- pdev->dev.class_cb->Setup (pdev, req);
- USBD_CtlSendStatus(pdev);
- break;
-
- default:
- USBD_CtlError(pdev , req);
- break;
- }
- break;
-
- case USB_REQ_GET_STATUS:
- switch (pdev->dev.device_status)
- {
- case USB_ADDRESSED:
- if ((ep_addr != 0x00) && (ep_addr != 0x80))
- {
- DCD_EP_Stall(pdev , ep_addr);
- }
- break;
-
- case USB_CONFIGURED:
-
- if ((ep_addr & 0x80)== 0x80)
- {
- if(pdev->dev.in_ep[ep_addr & 0x7F].is_stall)
- {
- USBD_ep_status = 0x0001;
- }
- else
- {
- USBD_ep_status = 0x0000;
- }
- }
- else if ((ep_addr & 0x80)== 0x00)
- {
- if(pdev->dev.out_ep[ep_addr].is_stall)
- {
- USBD_ep_status = 0x0001;
- }
-
- else
- {
- USBD_ep_status = 0x0000;
- }
- }
- USBD_CtlSendData (pdev,
- (uint8_t *)&USBD_ep_status,
- 2);
- break;
-
- default:
- USBD_CtlError(pdev , req);
- break;
- }
- break;
-
- default:
- break;
- }
- return ret;
-}
-/**
- * @brief USBD_GetDescriptor
- * Handle Get Descriptor requests
- * @param pdev: device instance
- * @param req: usb request
- * @retval status
- */
-static void USBD_GetDescriptor(USB_CORE_HANDLE *pdev,
- USB_SETUP_REQ *req)
-{
- uint16_t len;
- uint8_t *pbuf;
-
- switch (req->wValue >> 8)
- {
-#ifdef LPM_ENABLED
- case USB_DESC_TYPE_BOS:
- pbuf = pdev->dev.usr_device->GetBOSDescriptor(pdev->dev.speed, &len);
- break;
-#endif
- case USB_DESC_TYPE_DEVICE:
- pbuf = pdev->dev.usr_device->GetDeviceDescriptor(pdev->dev.speed, &len);
- if (req->wLength == 64)
- {
- len = 8;
- }
- break;
-
- case USB_DESC_TYPE_CONFIGURATION:
- pbuf = (uint8_t *)pdev->dev.class_cb->GetConfigDescriptor(pdev->dev.speed, &len);
- pdev->dev.pConfig_descriptor = pbuf;
- break;
-
- case USB_DESC_TYPE_STRING:
- switch ((uint8_t)(req->wValue))
- {
- case USBD_IDX_LANGID_STR:
- pbuf = pdev->dev.usr_device->GetLangIDStrDescriptor(pdev->dev.speed, &len);
- break;
-
- case USBD_IDX_MFC_STR:
- pbuf = pdev->dev.usr_device->GetManufacturerStrDescriptor(pdev->dev.speed, &len);
- break;
-
- case USBD_IDX_PRODUCT_STR:
- pbuf = pdev->dev.usr_device->GetProductStrDescriptor(pdev->dev.speed, &len);
- break;
-
- case USBD_IDX_SERIAL_STR:
- pbuf = pdev->dev.usr_device->GetSerialStrDescriptor(pdev->dev.speed, &len);
- break;
-
- case USBD_IDX_CONFIG_STR:
- pbuf = pdev->dev.usr_device->GetConfigurationStrDescriptor(pdev->dev.speed, &len);
- break;
-
- case USBD_IDX_INTERFACE_STR:
- pbuf = pdev->dev.usr_device->GetInterfaceStrDescriptor(pdev->dev.speed, &len);
- break;
-
- default:
-#ifdef USB_SUPPORT_USER_STRING_DESC
- pbuf = pdev->dev.class_cb->GetUsrStrDescriptor(pdev->dev.speed, (req->wValue) , &len);
- break;
-#else
- USBD_CtlError(pdev , req);
- return;
-#endif /* USBD_CtlError(pdev , req); */
- }
- break;
- case USB_DESC_TYPE_DEVICE_QUALIFIER:
- USBD_CtlError(pdev , req);
- return;
-
- case USB_DESC_TYPE_OTHER_SPEED_CONFIGURATION:
- USBD_CtlError(pdev , req);
- return;
- default:
- USBD_CtlError(pdev , req);
- return;
- }
-
- if((len != 0)&& (req->wLength != 0))
- {
-
- len = MIN(len , req->wLength);
-
- USBD_CtlSendData (pdev,
- pbuf,
- len);
- }
-
-}
-
-/**
- * @brief USBD_SetAddress
- * Set device address
- * @param pdev: device instance
- * @param req: usb request
- * @retval status
- */
-static void USBD_SetAddress(USB_CORE_HANDLE *pdev,
- USB_SETUP_REQ *req)
-{
- uint8_t dev_addr;
-
- if ((req->wIndex == 0) && (req->wLength == 0))
- {
- dev_addr = (uint8_t)(req->wValue) & 0x7F;
-
- if (pdev->dev.device_status == USB_CONFIGURED)
- {
- USBD_CtlError(pdev , req);
- }
- else
- {
- pdev->dev.device_address = dev_addr;
- ADDRESS = dev_addr;
- USBD_CtlSendStatus(pdev);
-
- if (dev_addr != 0)
- {
- pdev->dev.device_status = USB_ADDRESSED;
- }
- else
- {
- pdev->dev.device_status = USB_DEFAULT;
- }
- }
- }
- else
- {
- USBD_CtlError(pdev , req);
- }
-}
-
-/**
- * @brief USBD_SetConfig
- * Handle Set device configuration request
- * @param pdev: device instance
- * @param req: usb request
- * @retval status
- */
-static void USBD_SetConfig(USB_CORE_HANDLE *pdev,
- USB_SETUP_REQ *req)
-{
-
- static uint8_t cfgidx;
-
- cfgidx = (uint8_t)(req->wValue);
-
- if (cfgidx > USBD_CFG_MAX_NUM )
- {
- USBD_CtlError(pdev , req);
- }
- else
- {
- switch (pdev->dev.device_status)
- {
- case USB_ADDRESSED:
- if (cfgidx)
- {
- pdev->dev.device_config = cfgidx;
- pdev->dev.device_status = USB_CONFIGURED;
- USBD_SetCfg(pdev , cfgidx);
- USBD_CtlSendStatus(pdev);
- }
- else
- {
- USBD_CtlSendStatus(pdev);
- }
- break;
-
- case USB_CONFIGURED:
- if (cfgidx == 0)
- {
- pdev->dev.device_status = USB_ADDRESSED;
- pdev->dev.device_config = cfgidx;
- USBD_ClrCfg(pdev , cfgidx);
- USBD_CtlSendStatus(pdev);
- }
- else if (cfgidx != pdev->dev.device_config)
- {
- /* Clear old configuration */
- USBD_ClrCfg(pdev , pdev->dev.device_config);
-
- /* set new configuration */
- pdev->dev.device_config = cfgidx;
- USBD_SetCfg(pdev , cfgidx);
- USBD_CtlSendStatus(pdev);
- }
- else
- {
- USBD_CtlSendStatus(pdev);
- }
- break;
-
- default:
- USBD_CtlError(pdev , req);
- break;
- }
- }
-}
-
-/**
- * @brief USBD_GetConfig
- * Handle Get device configuration request
- * @param pdev: device instance
- * @param req: usb request
- * @retval status
- */
-static void USBD_GetConfig(USB_CORE_HANDLE *pdev,
- USB_SETUP_REQ *req)
-{
- uint32_t USBD_default_cfg = 0;
-
- if (req->wLength != 1)
- {
- USBD_CtlError(pdev , req);
- }
- else
- {
- switch (pdev->dev.device_status )
- {
- case USB_ADDRESSED:
-
- USBD_CtlSendData (pdev,
- (uint8_t *)&USBD_default_cfg,
- 1);
- break;
-
- case USB_CONFIGURED:
-
- USBD_CtlSendData (pdev,
- &pdev->dev.device_config,
- 1);
- break;
-
- default:
- USBD_CtlError(pdev , req);
- break;
- }
- }
-}
-
-/**
- * @brief USBD_GetStatus
- * Handle Get Status request
- * @param pdev: device instance
- * @param req: usb request
- * @retval status
- */
-static void USBD_GetStatus(USB_CORE_HANDLE *pdev,
- USB_SETUP_REQ *req)
-{
- uint32_t USBD_cfg_status = 0;
- switch (pdev->dev.device_status)
- {
- case USB_ADDRESSED:
- case USB_CONFIGURED:
-
-#ifdef USBD_SELF_POWERED
- USBD_cfg_status = USB_CONFIG_SELF_POWERED;
-#else
- USBD_cfg_status = 0x00;
-#endif
-
- if (pdev->dev.DevRemoteWakeup)
- {
- USBD_cfg_status |= USB_CONFIG_REMOTE_WAKEUP;
- }
-
- USBD_CtlSendData (pdev,
- (uint8_t *)&USBD_cfg_status,
- 2);
- break;
-
- default :
- USBD_CtlError(pdev , req);
- break;
- }
-}
-
-
-/**
- * @brief USBD_SetFeature
- * Handle Set device feature request
- * @param pdev: device instance
- * @param req: usb request
- * @retval status
- */
-static void USBD_SetFeature(USB_CORE_HANDLE *pdev,
- USB_SETUP_REQ *req)
-{
-
- if (req->wValue == USB_FEATURE_REMOTE_WAKEUP)
- {
- pdev->dev.DevRemoteWakeup = 1;
- pdev->dev.class_cb->Setup (pdev, req);
- USBD_CtlSendStatus(pdev);
- }
-}
-
-
-/**
- * @brief USBD_ClrFeature
- * Handle clear device feature request
- * @param pdev: device instance
- * @param req: usb request
- * @retval status
- */
-static void USBD_ClrFeature(USB_CORE_HANDLE *pdev,
- USB_SETUP_REQ *req)
-{
- switch (pdev->dev.device_status)
- {
- case USB_ADDRESSED:
- case USB_CONFIGURED:
- if (req->wValue == USB_FEATURE_REMOTE_WAKEUP)
- {
- pdev->dev.DevRemoteWakeup = 0;
- pdev->dev.class_cb->Setup (pdev, req);
- USBD_CtlSendStatus(pdev);
- }
- break;
-
- default :
- USBD_CtlError(pdev , req);
- break;
- }
-}
-
-/**
- * @brief USBD_ParseSetupRequest
- * Copy buffer into setup structure
- * @param pdev: device instance
- * @param req: usb request
- * @retval None
- */
-
-void USBD_ParseSetupRequest( USB_CORE_HANDLE *pdev,
- USB_SETUP_REQ *req)
-{
- req->bmRequest = *(uint8_t *) (pdev->dev.setup_packet);
- req->bRequest = *(uint8_t *) (pdev->dev.setup_packet + 1);
- req->wValue = SWAPBYTE (pdev->dev.setup_packet + 2);
- req->wIndex = SWAPBYTE (pdev->dev.setup_packet + 4);
- req->wLength = SWAPBYTE (pdev->dev.setup_packet + 6);
-
- pdev->dev.in_ep[0].ctl_data_len = req->wLength ;
- pdev->dev.device_state = USB_EP0_SETUP;
-}
-
-/**
- * @brief USBD_CtlError
- * Handle USB low level Error
- * @param pdev: device instance
- * @param req: usb request
- * @retval None
- */
-
-void USBD_CtlError( USB_CORE_HANDLE *pdev,
- USB_SETUP_REQ *req)
-{
- DCD_EP_Stall(pdev , 0);
-}
-
-
-/**
- * @brief USBD_GetString
- * Convert Ascii string into unicode one
- * @param desc : descriptor buffer
- * @param unicode : Formatted string buffer (unicode)
- * @param len : descriptor length
- * @retval None
- */
-void USBD_GetString(uint8_t *desc, uint8_t *unicode, uint16_t *len)
-{
- uint8_t idx = 0;
-
- if (desc != NULL)
- {
- *len = USBD_GetLen(desc) * 2 + 2;
- unicode[idx++] = *len;
- unicode[idx++] = USB_DESC_TYPE_STRING;
-
- while (*desc != NULL)
- {
- unicode[idx++] = *desc++;
- unicode[idx++] = 0x00;
- }
- }
-}
-
-/**
- * @brief USBD_GetLen
- * return the string length
- * @param buf : pointer to the ascii string buffer
- * @retval string length
- */
-static uint8_t USBD_GetLen(uint8_t *buf)
-{
- uint8_t len = 0;
-
- while (*buf != NULL)
- {
- len++;
- buf++;
- }
-
- return len;
-}
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/User/NHC_WCH_SDI.c b/attic/NHC-Link042/User/NHC_WCH_SDI.c
deleted file mode 100644
index 8a94e805c4023e93204b96dc7c3c9e6aef2d2a18..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/User/NHC_WCH_SDI.c
+++ /dev/null
@@ -1,430 +0,0 @@
-#include "NHC_WCH_SDI.h"
-
-/*
- 1-Wire WCH (CH32V003) debug protocol
- Ngo Hung Cuong
- http://vidieukhien.org
- ngohungcuong@gmail.com
-
- Based on STM32F042
-*/
-
-static uint16_t u16Capture[100];
-static uint8_t u8Data[100];
-
-#define SDI_1 GPIOA->BSRR = 0x00002000
-#define SDI_0 GPIOA->BRR = 0x00002000
-#define SDI_IN (GPIOA->IDR & 0x00002000)
-
-#define H_VAL 1
-#define L_VAL 32
-#define IN_VAL 4
-
-void NHC_Delay_Us(uint16_t u16Delay);
-void NHC_Delay_Ms(uint32_t u32Delay);
-
-void NHC_Delay_Us(uint16_t u16Delay)
-{
- uint16_t u16Tmp;
-
- u16Tmp = u16Delay * 48;
- TIM16->CNT = 0;
- while (TIM16->CNT < u16Tmp)
- {
- }
-}
-
-void NHC_Delay_Ms(uint32_t u32Delay)
-{
-
- while (u32Delay)
- {
- NHC_Delay_Us(500);
- NHC_Delay_Us(500);
- --u32Delay;
- }
-}
-
-void NHC_WchSdi_Init(void)
-{
- GPIO_InitTypeDef gpioInit;
- TIM_TimeBaseInitTypeDef timInit;
-
- //RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO, ENABLE);
- RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA, ENABLE);
- RCC_APB2PeriphClockCmd(RCC_APB2Periph_TIM16, ENABLE);
-
- timInit.TIM_ClockDivision = TIM_CKD_DIV1;
- timInit.TIM_CounterMode = TIM_CounterMode_Up;
- timInit.TIM_Period = 0xffff;
- timInit.TIM_Prescaler = 1 - 1;
- timInit.TIM_RepetitionCounter = 0;
-
- TIM_TimeBaseInit(TIM16, &timInit);
- TIM_Cmd(TIM16, ENABLE);
-
- GPIO_SetBits(GPIOA, GPIO_Pin_13);
- gpioInit.GPIO_Mode = GPIO_Mode_OUT;
- gpioInit.GPIO_OType = GPIO_OType_OD;
- gpioInit.GPIO_PuPd = GPIO_PuPd_NOPULL;
- gpioInit.GPIO_Pin = GPIO_Pin_13;
- gpioInit.GPIO_Speed = GPIO_Speed_Level_3;
- GPIO_Init(GPIOA, &gpioInit);
-
- SDI_1;
- NHC_Delay_Ms(1);
- SDI_0;
- NHC_Delay_Us(36);
- SDI_1;
-}
-
-void NHC_WchSdi_Exit(void)
-{
- GPIO_InitTypeDef gpioInit;
-
- GPIO_SetBits(GPIOA, GPIO_Pin_13);
- gpioInit.GPIO_Mode = GPIO_Mode_IN;
- gpioInit.GPIO_OType = GPIO_OType_OD;
- gpioInit.GPIO_PuPd = GPIO_PuPd_NOPULL;
- gpioInit.GPIO_Pin = GPIO_Pin_13;
- gpioInit.GPIO_Speed = GPIO_Speed_Level_3;
- GPIO_Init(GPIOA, &gpioInit);
-
- TIM_DeInit(TIM16);
- TIM_Cmd(TIM16, DISABLE);
-}
-
-void NHC_WchSdi_Write(uint8_t u8Address, uint32_t u32Data)
-{
- uint32_t i;
- uint8_t *p;
-
- u8Data[0] = 1;
-
- for (i = 0; i < 7; ++i)
- {
- if (u8Address & 0x40)
- {
- u8Data[i + 1] = 1;
- }
- else
- {
- u8Data[i + 1] = 0;
- }
- u8Address <<= 1;
- }
-
- u8Data[8] = 1;
-
- for (i = 0; i < 32; ++i)
- {
- if (u32Data & 0x80000000)
- {
- u8Data[i + 9] = 1;
- }
- else
- {
- u8Data[i + 9] = 0;
- }
- u32Data <<= 1;
- }
-
- p = u8Data;
-
- for (i = 0; i < 41; ++i)
- {
- if (*p++)
- {
- SDI_0;
- TIM16->CNT = 0;
- while (TIM16->CNT < H_VAL)
- {
- }
- SDI_1;
- TIM16->CNT = 0;
- while (TIM16->CNT < H_VAL)
- {
- }
- }
- else
- {
- SDI_0;
- TIM16->CNT = 0;
- while (TIM16->CNT < L_VAL)
- {
- }
- SDI_1;
- TIM16->CNT = 0;
- while (TIM16->CNT < H_VAL)
- {
- }
- }
- }
-
- NHC_Delay_Us(2);
-}
-
-uint32_t NHC_WchSdi_Read(uint8_t u8Address, uint32_t *pu32Data)
-{
- uint32_t i;
- uint32_t u32Tmp;
- uint8_t *p;
- uint16_t *pu16;
-
- u8Data[0] = 1;
- for (i = 0; i < 7; ++i)
- {
- if (u8Address & 0x40)
- {
- u8Data[i + 1] = 1;
- }
- else
- {
- u8Data[i + 1] = 0;
- }
- u8Address <<= 1;
- }
- u8Data[8] = 0;
-
- p = u8Data;
-
- for (i = 0; i < 9; ++i)
- {
- if (*p++)
- {
- SDI_0;
- TIM16->CNT = 0;
- while (TIM16->CNT < H_VAL)
- {
- }
- SDI_1;
- TIM16->CNT = 0;
- while (TIM16->CNT < H_VAL)
- {
- }
- }
- else
- {
- SDI_0;
- TIM16->CNT = 0;
- while (TIM16->CNT < L_VAL)
- {
- }
- SDI_1;
- TIM16->CNT = 0;
- while (TIM16->CNT < H_VAL)
- {
- }
- }
- }
-
- pu16 = u16Capture;
-
- for (i = 0; i < 32; ++i)
- {
- SDI_0;
- TIM16->CNT = 0;
- while (TIM16->CNT < H_VAL)
- {
- }
- SDI_1;
- TIM16->CNT = 0;
- while (1)
- {
- if (SDI_IN)
- {
- *pu16++ = TIM16->CNT;
- break;
- }
- if (TIM16->CNT > 144)
- {
- return 0;
- }
- }
- }
-
- u32Tmp = 0;
-
- for (i = 0; i < 32; ++i)
- {
- u32Tmp <<= 1;
- if (u16Capture[i] < IN_VAL)
- {
- u32Tmp |= 0x01;
- }
- }
-
- *pu32Data = u32Tmp;
-
- NHC_Delay_Us(2);
- return 1;
-}
-
-uint32_t NHC_WchSdi_WriteMem(uint32_t u32Address, uint32_t u32Data, uint8_t u8Width)
-{
- uint32_t u32Tmp;
- uint32_t i;
-
- u32Tmp = 2;
-
- if(u8Width == 8)
- {
- u32Tmp = 0;
- }
- else if (u8Width == 16)
- {
- u32Tmp = 1;
- }
- else if (u8Width == 32)
- {
- u32Tmp = 2;
- }
- else if (u8Width == 64)
- {
- u32Tmp = 3;
- }
- else if (u8Width == 128)
- {
- u32Tmp = 4;
- }
-
- u32Tmp <<= 12;
-
- NHC_WchSdi_Write(0x20, 0x00728023 | u32Tmp); //cho nay can thay doi
- NHC_WchSdi_Write(0x21, 0x00100073);
- NHC_WchSdi_Write(0x04, u32Address);
- NHC_WchSdi_Write(0x17, 0x00231005);
- for (i = 0; i < 1000; ++i)
- {
- if (NHC_WchSdi_Read(0x16, &u32Tmp))
- {
- if (!(u32Tmp & (1 << 12)))
- {
- break;
- }
- }
- }
- if (i == 1000)
- {
- return 0;
- }
- if (u32Tmp & (7 << 8))
- {
- return 0;
- }
- NHC_WchSdi_Write(0x04, u32Data);
- NHC_WchSdi_Write(0x17, 0x00271007);
- for (i = 0; i < 1000; ++i)
- {
- if (NHC_WchSdi_Read(0x16, &u32Tmp))
- {
- if (!(u32Tmp & (1 << 12)))
- {
- break;
- }
- }
- }
- if (i == 1000)
- {
- return 0;
- }
- if (u32Tmp & (7 << 8))
- {
- return 0;
- }
-
- return 1;
-}
-
-uint32_t NHC_WchSdi_ReadMem(uint32_t u32Address, uint32_t *pu32Data, uint8_t u8Width)
-{
- uint32_t u32Tmp;
- uint32_t i;
-
- u32Tmp = 2;
-
- if(u8Width == 8)
- {
- u32Tmp = 0;
- }
- else if (u8Width == 16)
- {
- u32Tmp = 1;
- }
- else if (u8Width == 32)
- {
- u32Tmp = 2;
- }
- else if (u8Width == 64)
- {
- u32Tmp = 3;
- }
- else if (u8Width == 128)
- {
- u32Tmp = 4;
- }
-
- u32Tmp <<= 12;
-
- //NHC_WchSdi_Write(0x10, 0x80000001);
- //NHC_WchSdi_Write(0x10, 0x80000001);
- //NHC_WchSdi_Write(0x10, 0x00000001);
- NHC_WchSdi_Write(0x20, 0x00028303 | u32Tmp); //cho nay can thay doi
- NHC_WchSdi_Write(0x21, 0x00100073);
- NHC_WchSdi_Write(0x04, u32Address);
- NHC_WchSdi_Write(0x17, 0x00271005);
- for (i = 0; i < 1000; ++i)
- {
- if (NHC_WchSdi_Read(0x16, &u32Tmp))
- {
- if (!(u32Tmp & (1 << 12)))
- {
- break;
- }
- }
- }
- if (i == 1000)
- {
- //day loi len
- *pu32Data = 0xffffffff;
- return 0;
- }
- if (u32Tmp & (7 << 8))
- {
- //day loi len
- *pu32Data = u32Tmp;
- return 0;
- }
-
- NHC_WchSdi_Write(0x17, 0x00221006);
- for (i = 0; i < 1000; ++i)
- {
- if (NHC_WchSdi_Read(0x16, &u32Tmp))
- {
- if (!(u32Tmp & (1 << 12)))
- {
- break;
- }
- }
- }
- if (i == 1000)
- {
- *pu32Data = 0xffffffff;
- return 0;
- }
- if (u32Tmp & (7 << 8))
- {
- *pu32Data = u32Tmp;
- return 0;
- }
-
- if (!NHC_WchSdi_Read(0x04, &u32Tmp))
- {
- *pu32Data = 0x00000000;
- return 0;
- }
-
- *pu32Data = u32Tmp;
-
- return 1;
-}
diff --git a/attic/NHC-Link042/User/NHC_WCH_SDI.h b/attic/NHC-Link042/User/NHC_WCH_SDI.h
deleted file mode 100644
index dd6797c7eb8f930b7655cf1d94e0aad3ebb99205..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/User/NHC_WCH_SDI.h
+++ /dev/null
@@ -1,57 +0,0 @@
-#ifndef NHC_WCH_SDI_H_
-#define NHC_WCH_SDI_H_
-
-#include "stm32f0xx.h"
-
-/*
- 1-Wire WCH (CH32V003) debug protocol
- Ngo Hung Cuong
- http://vidieukhien.org
- ngohungcuong@gmail.com
-
- Based on STM32F042
-*/
-
-#define WCH_SDI_DATA0 0x04
-#define WCH_SDI_DATA1 0x05
-#define WCH_SDI_DMCONTROL 0x10
-#define WCH_SDI_DMSTATUS 0x11
-#define WCH_SDI_HARTINFO 0x12
-#define WCH_SDI_ABSTRACTCS 0x16
-#define WCH_SDI_COMMAND 0x17
-#define WCH_SDI_ABSTRACTAUTO 0x18
-#define WCH_SDI_PROGBUFF0 0x20
-#define WCH_SDI_PROGBUFF1 0x21
-#define WCH_SDI_PROGBUFF2 0x22
-#define WCH_SDI_PROGBUFF3 0x23
-#define WCH_SDI_PROGBUFF4 0x24
-#define WCH_SDI_PROGBUFF5 0x25
-#define WCH_SDI_PROGBUFF6 0x26
-#define WCH_SDI_PROGBUFF7 0x27
-#define WCH_SDI_HALTSUM0 0x40
-
-#define WCH_SDI_CPBR 0x7C
-#define WCH_SDI_CFGR 0x7D
-#define WCH_SDI_SHDWCFGR 0x7E
-
-#define R32_FLASH_BASE 0x40022000
-#define R32_FLASH_ACTLR 0x40022000
-#define R32_FLASH_KEYR 0x40022004
-#define R32_FLASH_OBKEYR 0x40022008
-#define R32_FLASH_STATR 0x4002200C
-#define R32_FLASH_CTLR 0x40022010
-#define R32_FLASH_ADDR 0x40022014
-#define R32_FLASH_OBR 0x4002201C
-#define R32_FLASH_WPR 0x40022020
-#define R32_FLASH_MODEKEYR 0x40022024
-#define R32_FLASH_BOOT_MODEKEYR 0x40022028
-
-void NHC_WchSdi_Init(void);
-void NHC_WchSdi_Exit(void);
-void NHC_WchSdi_Write(uint8_t u8Address, uint32_t u32Data);
-uint32_t NHC_WchSdi_Read(uint8_t u8Address, uint32_t *pu32Data);
-
-uint32_t NHC_WchSdi_WriteMem(uint32_t u32Address, uint32_t u32Data, uint8_t u8Width);
-uint32_t NHC_WchSdi_ReadMem(uint32_t u32Address, uint32_t *pu32Data, uint8_t u8Width);
-
-#endif
diff --git a/attic/NHC-Link042/User/config.h b/attic/NHC-Link042/User/config.h
deleted file mode 100644
index 2485c6553bf8ce0afaa41bed7a62efdbaba2f429..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/User/config.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#define TAMPER_BUTTON_PIN GPIO_Pin_13
-#define TAMPER_BUTTON_GPIO_PORT GPIOC
-#define TAMPER_BUTTON_GPIO_CLK RCC_APB2Periph_GPIOC
-#define TAMPER_BUTTON_EXTI_LINE EXTI_Line13
-#define TAMPER_BUTTON_EXTI_PORT_SOURCE GPIO_PortSourceGPIOC
-#define TAMPER_BUTTON_EXTI_PIN_SOURCE GPIO_PinSource13
-#define TAMPER_BUTTON_EXTI_IRQn EXTI4_15_IRQn
diff --git a/attic/NHC-Link042/User/it.c b/attic/NHC-Link042/User/it.c
deleted file mode 100644
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..0000000000000000000000000000000000000000
diff --git a/attic/NHC-Link042/User/main.c b/attic/NHC-Link042/User/main.c
deleted file mode 100644
index da605db117a8991a443e034defdf47e033046399..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/User/main.c
+++ /dev/null
@@ -1,36 +0,0 @@
-#include "stm32f0xx.h"
-#include "usbd_usr.h"
-#include "usbd_desc.h"
-
-extern USBD_Class_cb_TypeDef USBD_HID_cb;
-USB_CORE_HANDLE USB_Device_dev ;
-
-GPIO_InitTypeDef gpioInit;
-
-int main(void) {
-
- RCC->APB2ENR |= RCC_APB2ENR_SYSCFGCOMPEN;
- // remap pins to enable USB
- SYSCFG->CFGR1 |= SYSCFG_CFGR1_PA11_PA12_RMP;
-
- RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA, ENABLE);
-
- USBD_Init(&USB_Device_dev,
- &USR_desc,
- &USBD_HID_cb,
- &USR_cb);
-
- RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA, ENABLE);
- gpioInit.GPIO_Mode = GPIO_Mode_OUT;
- gpioInit.GPIO_OType = GPIO_OType_PP;
- gpioInit.GPIO_Pin = GPIO_Pin_1;
- gpioInit.GPIO_PuPd = GPIO_PuPd_NOPULL;
- gpioInit.GPIO_Speed = GPIO_Speed_Level_3;
-
- GPIO_Init(GPIOA, &gpioInit);
- GPIO_ResetBits(GPIOA, GPIO_Pin_1);
-
- while(1) {
-
- }
-}
diff --git a/attic/NHC-Link042/User/stm32_it.c b/attic/NHC-Link042/User/stm32_it.c
deleted file mode 100644
index b1b432a9774e33363fd445c63da0138973c66b6b..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/User/stm32_it.c
+++ /dev/null
@@ -1,182 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32_it.c
- * @author MCD Application Team
- * @version V1.0.0
- * @date 31-January-2014
- * @brief Main Interrupt Service Routines.
- * This file provides template for all exceptions handler and peripherals
- * interrupt service routine.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32_it.h"
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/******************************************************************************/
-/* Cortex-M0 Processor Exceptions Handlers */
-/******************************************************************************/
-
-/**
- * @brief This function handles NMI exception.
- * @param None
- * @retval None
- */
-void NMI_Handler(void)
-{
-}
-
-/**
- * @brief This function handles Hard Fault exception.
- * @param None
- * @retval None
- */
-void HardFault_Handler(void)
-{
- /* Go to infinite loop when Hard Fault exception occurs */
- while (1)
- {
- }
-}
-
-/**
- * @brief This function handles SVCall exception.
- * @param None
- * @retval None
- */
-void SVC_Handler(void)
-{
-}
-
-/**
- * @brief This function handles PendSVC exception.
- * @param None
- * @retval None
- */
-void PendSV_Handler(void)
-{
-}
-
-/**
- * @brief This function handles SysTick Handler.
- * @param None
- * @retval None
- */
-void SysTick_Handler(void)
-{
-}
-
-/**
- * @brief This function handles USB FS Handler.
- * @param None
- * @retval None
- */
-void USB_IRQHandler(void)
-{
- USB_Istr();
-}
-
-/**
- * @brief This function handles EXTI14_15_IRQ Handler.
- * @param None
- * @retval None
- */
-void EXTI4_15_IRQHandler(void)
-{
-
- if (EXTI_GetITStatus(TAMPER_BUTTON_EXTI_LINE) != RESET)
- {
- /*
- if((PrevXferDone) && (USB_Device_dev.dev.device_status==USB_CONFIGURED))
- {
- Send_Buffer[0] = 0x06;
-
- if (STM_EVAL_PBGetState(BUTTON_TAMPER) == Bit_RESET)
- {
- Send_Buffer[1] = 0x01;
- }
- else
- {
- Send_Buffer[1] = 0x00;
- }
-
- USBD_HID_SendReport (&USB_Device_dev, Send_Buffer, 2);
- PrevXferDone = 0;
- }
- */
- /* Clear the EXTI line pending bit */
- EXTI_ClearITPendingBit(TAMPER_BUTTON_EXTI_LINE);
- }
-}
-
-/**
- * @brief This function handles DMA1_Channel1 Handler.
- * @param None
- * @retval None
- */
-void DMA1_Channel1_IRQHandler(void)
-{
- /*
- Send_Buffer[0] = 0x07;
-
- if((ADC_ConvertedValueX >>4) - (ADC_ConvertedValueX_1 >>4) > 4)
- {
- if ((PrevXferDone) && (USB_Device_dev.dev.device_status == USB_CONFIGURED))
- {
- Send_Buffer[1] = (uint8_t)(ADC_ConvertedValueX >>4);
-
- //USBD_HID_SendReport (&USB_Device_dev, Send_Buffer, 2);
-
- ADC_ConvertedValueX_1 = ADC_ConvertedValueX;
- PrevXferDone = 0;
- }
- }
- */
- /* Test DMA1 TC flag */
- //while((DMA_GetFlagStatus(DMA1_FLAG_TC1)) == RESET );
-
- //DMA_ClearFlag(DMA1_FLAG_TC1);
-}
-
-/******************************************************************************/
-/* STM32F0xx Peripherals Interrupt Handlers */
-/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */
-/* available peripheral interrupt handler's name please refer to the startup */
-/* file (startup_stm32f072.s). */
-/******************************************************************************/
-
-/**
- * @brief This function handles PPP interrupt request.
- * @param None
- * @retval None
- */
-/*void PPP_IRQHandler(void)
-{
-}*/
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/User/stm32_it.h b/attic/NHC-Link042/User/stm32_it.h
deleted file mode 100644
index 6f6922c84d598cfa4a9c383b426bdb330ba7f305..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/User/stm32_it.h
+++ /dev/null
@@ -1,64 +0,0 @@
-/**
- ******************************************************************************
- * @file stm32_it.h
- * @author MCD Application Team
- * @version V1.0.0
- * @date 31-January-2014
- * @brief This file contains the headers of the interrupt handlers.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32_IT_H
-#define __STM32_IT_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-//#include "usbd_custom_hid_core.h"
-
-#include "stm32f0xx.h"
-#include "config.h"
-#include "usbd_usr.h"
-#include "usbd_desc.h"
-//#include "vdclass.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-void NMI_Handler(void);
-void HardFault_Handler(void);
-void SVC_Handler(void);
-void PendSV_Handler(void);
-void SysTick_Handler(void);
-void USB_IRQHandler(void);
-void EXTI4_15_IRQHandler(void);
-void DMA1_Channel1_IRQHandler(void);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32_IT_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/User/stm32f0xx_conf.h b/attic/NHC-Link042/User/stm32f0xx_conf.h
deleted file mode 100644
index 4754231ab70326e1a6a2fffbe2ddf39434a3fee1..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/User/stm32f0xx_conf.h
+++ /dev/null
@@ -1,83 +0,0 @@
-/**
- ******************************************************************************
- * @file Project/STM32F0xx_StdPeriph_Templates/stm32f0xx_conf.h
- * @author MCD Application Team
- * @version V1.4.0
- * @date 24-July-2014
- * @brief Library configuration file.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F0XX_CONF_H
-#define __STM32F0XX_CONF_H
-
-/* Includes ------------------------------------------------------------------*/
-/* Comment the line below to disable peripheral header file inclusion */
-#include "stm32f0xx_adc.h"
-#include "stm32f0xx_can.h"
-#include "stm32f0xx_cec.h"
-#include "stm32f0xx_crc.h"
-#include "stm32f0xx_crs.h"
-#include "stm32f0xx_comp.h"
-#include "stm32f0xx_dac.h"
-#include "stm32f0xx_dbgmcu.h"
-#include "stm32f0xx_dma.h"
-#include "stm32f0xx_exti.h"
-#include "stm32f0xx_flash.h"
-#include "stm32f0xx_gpio.h"
-#include "stm32f0xx_syscfg.h"
-#include "stm32f0xx_i2c.h"
-#include "stm32f0xx_iwdg.h"
-#include "stm32f0xx_pwr.h"
-#include "stm32f0xx_rcc.h"
-#include "stm32f0xx_rtc.h"
-#include "stm32f0xx_spi.h"
-#include "stm32f0xx_tim.h"
-#include "stm32f0xx_usart.h"
-#include "stm32f0xx_wwdg.h"
-#include "stm32f0xx_misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Uncomment the line below to expanse the "assert_param" macro in the
- Standard Peripheral Library drivers code */
-/* #define USE_FULL_ASSERT 1 */
-
-/* Exported macro ------------------------------------------------------------*/
-#ifdef USE_FULL_ASSERT
-
-/**
- * @brief The assert_param macro is used for function's parameters check.
- * @param expr: If expr is false, it calls assert_failed function which reports
- * the name of the source file and the source line number of the call
- * that failed. If expr is true, it returns no value.
- * @retval None
- */
- #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
- void assert_failed(uint8_t* file, uint32_t line);
-#else
- #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */
-
-#endif /* __STM32F0XX_CONF_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/User/system_stm32f0xx.c b/attic/NHC-Link042/User/system_stm32f0xx.c
deleted file mode 100644
index 4816ad906582230620452ab9a3cd52e3629ff863..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/User/system_stm32f0xx.c
+++ /dev/null
@@ -1,331 +0,0 @@
-/**
- ******************************************************************************
- * @file system_stm32f0xx.c
- * @author MCD Application Team
- * @version V1.0.1
- * @date 15-March-2015
- * @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File.
- * This file contains the system clock configuration for STM32F0xx devices,
- * and is generated by the clock configuration tool
- * STM32f0xx_Clock_Configuration_V1.0.1.xls
- *
- * 1. This file provides two functions and one global variable to be called from
- * user application:
- * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
- * and Divider factors, AHB/APBx prescalers and Flash settings),
- * depending on the configuration made in the clock xls tool.
- * This function is called at startup just after reset and
- * before branch to main program. This call is made inside
- * the "startup_stm32f0xx.s" file.
- *
- * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
- * by the user application to setup the SysTick
- * timer or configure other parameters.
- *
- * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
- * be called whenever the core clock is changed
- * during program execution.
- *
- * 2. After each device reset the HSI (8 MHz Range) is used as system clock source.
- * Then SystemInit() function is called, in "startup_stm32f0xx.s" file, to
- * configure the system clock before to branch to main program.
- *
- * 3. If the system clock source selected by user fails to startup, the SystemInit()
- * function will do nothing and HSI still used as system clock source. User can
- * add some code to deal with this issue inside the SetSysClock() function.
- *
- * 4. The default value of HSE crystal is set to 8MHz, refer to "HSE_VALUE" define
- * in "stm32f0xx.h" file. When HSE is used as system clock source, directly or
- * through PLL, and you are using different crystal you have to adapt the HSE
- * value to your own configuration.
- *
- * 5. This file configures the system clock as follows:
- *=============================================================================
- *=============================================================================
- * System Clock source | PLL(HSI)
- *-----------------------------------------------------------------------------
- * SYSCLK(Hz) | 48000000
- *-----------------------------------------------------------------------------
- * HCLK(Hz) | 48000000
- *-----------------------------------------------------------------------------
- * AHB Prescaler | 1
- *-----------------------------------------------------------------------------
- * APB Prescaler | 1
- *-----------------------------------------------------------------------------
- * HSE Frequency(Hz) | NA
- *----------------------------------------------------------------------------
- * PLLMUL | 12
- *-----------------------------------------------------------------------------
- * PREDIV | 2
- *-----------------------------------------------------------------------------
- * Flash Latency(WS) | 1
- *-----------------------------------------------------------------------------
- * Prefetch Buffer | ON
- *-----------------------------------------------------------------------------
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2012 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/** @addtogroup CMSIS
- * @{
- */
-
-/** @addtogroup stm32f0xx_system
- * @{
- */
-
-/** @addtogroup STM32F0xx_System_Private_Includes
- * @{
- */
-
-#include "stm32f0xx.h"
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F0xx_System_Private_TypesDefinitions
- * @{
- */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F0xx_System_Private_Defines
- * @{
- */
-/**
- * @}
- */
-
-/** @addtogroup STM32F0xx_System_Private_Macros
- * @{
- */
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F0xx_System_Private_Variables
- * @{
- */
-uint32_t SystemCoreClock = 48000000;
-__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F0xx_System_Private_FunctionPrototypes
- * @{
- */
-
-static void SetSysClock(void);
-
-/**
- * @}
- */
-
-/** @addtogroup STM32F0xx_System_Private_Functions
- * @{
- */
-
-/**
- * @brief Setup the microcontroller system.
- * Initialize the Embedded Flash Interface, the PLL and update the
- * SystemCoreClock variable.
- * @param None
- * @retval None
- */
-void SystemInit (void)
-{
- /* Set HSION bit */
- RCC->CR |= (uint32_t)0x00000001;
-
- /* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */
- RCC->CFGR &= (uint32_t)0xF8FFB80C;
-
- /* Reset HSEON, CSSON and PLLON bits */
- RCC->CR &= (uint32_t)0xFEF6FFFF;
-
- /* Reset HSEBYP bit */
- RCC->CR &= (uint32_t)0xFFFBFFFF;
-
- /* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
- RCC->CFGR &= (uint32_t)0xFFC0FFFF;
-
- /* Reset PREDIV1[3:0] bits */
- RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
-
- /* Reset USARTSW[1:0], I2CSW, CECSW and ADCSW bits */
- RCC->CFGR3 &= (uint32_t)0xFFFFFEAC;
-
- /* Reset HSI14 bit */
- RCC->CR2 &= (uint32_t)0xFFFFFFFE;
-
- /* Disable all interrupts */
- RCC->CIR = 0x00000000;
-
- /* Configure the System clock frequency, AHB/APBx prescalers and Flash settings */
- SetSysClock();
-}
-
-/**
- * @brief Update SystemCoreClock according to Clock Register Values
- * The SystemCoreClock variable contains the core clock (HCLK), it can
- * be used by the user application to setup the SysTick timer or configure
- * other parameters.
- *
- * @note Each time the core clock (HCLK) changes, this function must be called
- * to update SystemCoreClock variable value. Otherwise, any configuration
- * based on this variable will be incorrect.
- *
- * @note - The system frequency computed by this function is not the real
- * frequency in the chip. It is calculated based on the predefined
- * constant and the selected clock source:
- *
- * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
- *
- * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
- *
- * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
- * or HSI_VALUE(*) multiplied/divided by the PLL factors.
- *
- * (*) HSI_VALUE is a constant defined in stm32f0xx.h file (default value
- * 8 MHz) but the real value may vary depending on the variations
- * in voltage and temperature.
- *
- * (**) HSE_VALUE is a constant defined in stm32f0xx.h file (default value
- * 8 MHz), user has to ensure that HSE_VALUE is same as the real
- * frequency of the crystal used. Otherwise, this function may
- * have wrong result.
- *
- * - The result of this function could be not correct when using fractional
- * value for HSE crystal.
- * @param None
- * @retval None
- */
-void SystemCoreClockUpdate (void)
-{
- uint32_t tmp = 0, pllmull = 0, pllsource = 0, prediv1factor = 0;
-
- /* Get SYSCLK source -------------------------------------------------------*/
- tmp = RCC->CFGR & RCC_CFGR_SWS;
-
- switch (tmp)
- {
- case 0x00: /* HSI used as system clock */
- SystemCoreClock = HSI_VALUE;
- break;
- case 0x04: /* HSE used as system clock */
- SystemCoreClock = HSE_VALUE;
- break;
- case 0x08: /* PLL used as system clock */
- /* Get PLL clock source and multiplication factor ----------------------*/
- pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
- pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
- pllmull = ( pllmull >> 18) + 2;
-
- if (pllsource == 0x00)
- {
- /* HSI oscillator clock divided by 2 selected as PLL clock entry */
- SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
- }
- else
- {
- prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
- /* HSE oscillator clock selected as PREDIV1 clock entry */
- SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
- }
- break;
- default: /* HSI used as system clock */
- SystemCoreClock = HSI_VALUE;
- break;
- }
- /* Compute HCLK clock frequency ----------------*/
- /* Get HCLK prescaler */
- tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
- /* HCLK clock frequency */
- SystemCoreClock >>= tmp;
-}
-
-/**
- * @brief Configures the System clock frequency, AHB/APBx prescalers and Flash
- * settings.
- * @note This function should be called only once the RCC clock configuration
- * is reset to the default reset state (done in SystemInit() function).
- * @param None
- * @retval None
- */
-static void SetSysClock(void)
-{
-/******************************************************************************/
-/* PLL (clocked by HSI) used as System clock source */
-/******************************************************************************/
-
- /* At this stage the HSI is already enabled and used as System clock source */
-
- /* SYSCLK, HCLK, PCLK configuration ----------------------------------------*/
-
- /* Enable Prefetch Buffer and set Flash Latency */
- FLASH->ACR = FLASH_ACR_PRFTBE | FLASH_ACR_LATENCY;
-
- /* HCLK = SYSCLK / 1 */
- RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
-
- /* PCLK = HCLK / 1 */
- RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE_DIV1;
-
- /* PLL configuration */
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
- RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSI_Div2 | RCC_CFGR_PLLXTPRE_PREDIV1 | RCC_CFGR_PLLMULL12);
-
- /* Enable PLL */
- RCC->CR |= RCC_CR_PLLON;
-
- /* Wait till PLL is ready */
- while((RCC->CR & RCC_CR_PLLRDY) == 0)
- {
- }
-
- /* Select PLL as system clock source */
- RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
- RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
-
- /* Wait till PLL is used as system clock source */
- while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)
- {
- }
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
diff --git a/attic/NHC-Link042/User/usb_bsp.c b/attic/NHC-Link042/User/usb_bsp.c
deleted file mode 100644
index 287fec87d8a8e69cc75cfdcbf3d52b38350104f5..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/User/usb_bsp.c
+++ /dev/null
@@ -1,183 +0,0 @@
-/**
- ******************************************************************************
- * @file usb_bsp.c
- * @author MCD Application Team
- * @version V1.0.0
- * @date 31-January-2014
- * @brief This file Provides Device Core configuration Functions
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "usb_bsp.h"
-#include "config.h"
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-#if defined USB_CLOCK_SOURCE_CRS
- static void CRS_Config(void);
-#endif /* USB_CLOCK_SOURCE_CRS */
-
-/* Private functions ---------------------------------------------------------*/
-
-/**
- * @brief Initialize BSP configurations
- * @param None
- * @retval None
- */
-
-void USB_BSP_Init(USB_CORE_HANDLE *pdev)
-{
- //EXTI_InitTypeDef EXTI_InitStructure;
-
- /* Enable USB clock */
- RCC_APB1PeriphClockCmd(RCC_APB1Periph_USB, ENABLE);
-
-#if defined USB_CLOCK_SOURCE_CRS
-
- /*For using CRS, you need to do the following:
- - Enable HSI48 (managed by the SystemInit() function at the application startup)
- - Select HSI48 as USB clock
- - Enable CRS clock
- - Set AUTOTRIMEN
- - Set CEN
- */
-
- /* Select HSI48 as USB clock */
- RCC_USBCLKConfig(RCC_USBCLK_HSI48);
-
- /* Configure the Clock Recovery System */
- CRS_Config();
-#else
- /* Configure PLL to be used as USB clock:
- - Enable HSE external clock (for this example the system is clocked by HSI48
- managed by the SystemInit() function at the application startup)
- - Enable PLL
- - Select PLL as USB clock */
- /* Enable HSE */
- RCC_HSEConfig(RCC_HSE_ON);
-
- /* Wait till HSE is ready */
- while (RCC_GetFlagStatus(RCC_FLAG_HSERDY) == RESET)
- {}
-
- /* Enable PLL */
- RCC_PLLCmd(ENABLE);
-
- /* Wait till PLL is ready */
- while (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET)
- {}
-
- /* Configure USBCLK from PLL clock */
- RCC_USBCLKConfig(RCC_USBCLK_PLLCLK);
-#endif /*USB_CLOCK_SOURCE_CRS */
-
- /* Configure the Tamper button in EXTI mode */
- //STM_EVAL_PBInit(BUTTON_TAMPER, Mode_EXTI);
- //----------------------------------------------------------------------------
- //ngo hung cuong
- /* Configure Tamper EXTI line to generate an interrupt on rising & falling edges */
- /*
- EXTI_InitStructure.EXTI_Line = TAMPER_BUTTON_EXTI_LINE;
- EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
- EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising_Falling;
- EXTI_InitStructure.EXTI_LineCmd = ENABLE;
- EXTI_Init(&EXTI_InitStructure);
- */
- /* Clear the Tamper EXTI line pending bit */
- EXTI_ClearITPendingBit(TAMPER_BUTTON_EXTI_LINE);
-
-#ifdef USB_DEVICE_LOW_PWR_MGMT_SUPPORT
-
- /* Enable the PWR clock */
- RCC_APB1PeriphClockCmd(RCC_APB1Periph_PWR, ENABLE);
-
- /* EXTI line 18 is connected to the USB Wakeup from suspend event */
- EXTI_ClearITPendingBit(EXTI_Line18);
- EXTI_InitStructure.EXTI_Line = EXTI_Line18;
- /*Must Configure the EXTI Line 18 to be sensitive to rising edge*/
- EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Rising;
- EXTI_InitStructure.EXTI_Mode = EXTI_Mode_Interrupt;
- EXTI_InitStructure.EXTI_LineCmd = ENABLE;
- EXTI_Init(&EXTI_InitStructure);
-#endif /*USB_DEVICE_LOW_PWR_MGMT_SUPPORT */
-
-}
-
-void USB_BSP_DevConnect(USB_CORE_HANDLE *pdev) {
- //khoi tao chan keo USB
-}
-
-
-/**
- * @brief Enable USB Global interrupt
- * @param None
- * @retval None
- */
-void USB_BSP_EnableInterrupt(USB_CORE_HANDLE *pdev)
-{
- NVIC_InitTypeDef NVIC_InitStructure;
-
- /* Enable the USB interrupt */
- NVIC_InitStructure.NVIC_IRQChannel = USB_IRQn;
- NVIC_InitStructure.NVIC_IRQChannelPriority = 1;
- NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
- NVIC_Init(&NVIC_InitStructure);
-
- /* Enable the Tamper EXTI line Interrupt */
- NVIC_InitStructure.NVIC_IRQChannel = TAMPER_BUTTON_EXTI_IRQn;
- NVIC_InitStructure.NVIC_IRQChannelPriority = 0;
- NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
- NVIC_Init(&NVIC_InitStructure);
-
- /* Enable the DMA1 Channel1 Interrupt */
- NVIC_InitStructure.NVIC_IRQChannel = DMA1_Channel1_IRQn;
- NVIC_InitStructure.NVIC_IRQChannelPriority = 2;
- NVIC_Init(&NVIC_InitStructure);
-}
-
-#if defined USB_CLOCK_SOURCE_CRS
-
-/**
- * @brief Configure CRS peripheral to automatically trim the HSI
- * oscillator according to USB SOF
- * @param None
- * @retval None
- */
-static void CRS_Config(void)
-{
- /*Enable CRS Clock*/
- RCC_APB1PeriphClockCmd(RCC_APB1Periph_CRS, ENABLE);
-
- /* Select USB SOF as synchronization source */
- CRS_SynchronizationSourceConfig(CRS_SYNCSource_USB);
-
- /*Enables the automatic hardware adjustment of TRIM bits: AUTOTRIMEN:*/
- CRS_AutomaticCalibrationCmd(ENABLE);
-
- /*Enables the oscillator clock for frequency error counter CEN*/
- CRS_FrequencyErrorCounterCmd(ENABLE);
-}
-#endif
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/User/usb_conf.h b/attic/NHC-Link042/User/usb_conf.h
deleted file mode 100644
index da72e7b01bec8a2f0e926623b6483c1428bb0a1c..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/User/usb_conf.h
+++ /dev/null
@@ -1,86 +0,0 @@
-/**
- ******************************************************************************
- * @file usb_conf.h
- * @author MCD Application Team
- * @version V1.0.0
- * @date 31-January-2014
- * @brief General low level driver configuration
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __USB_CONF__H__
-#define __USB_CONF__H__
-
-/* Includes ------------------------------------------------------------------*/
-
-#include "stm32f0xx.h"
-//#include "stm32072b_eval.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Select D+ pullup: internal or external */
-#ifdef USE_STM32072B_EVAL
- /* When using STM32072B_EVAL board the internal pullup must be enabled */
- //#define INTERNAL_PULLUP
- //chu y da thay doi cho nay
- //vi dung tro treo ngoai nen khong can cho nay
- //=================================================
-#endif
-
-/* Define if Low power mode is enabled; it allows entering the device into STOP mode
- following USB Suspend event, and wakes up after the USB wakeup event is received. */
-/* #define USB_DEVICE_LOW_PWR_MGMT_SUPPORT */
-
-/* Configure the USB clock source as HSI48 with Clock Recovery System(CRS)*/
-//#define USB_CLOCK_SOURCE_CRS
-//=======================================================================================
-//ngo hung cuong
-//=======================================================================================
-
-/* Endpoints used by the device */
-#define EP_NUM (2) /* EP0 + EP1 (IN/OUT) For HID */
-
-/* buffer table base address */
-#define BTABLE_ADDRESS (0x000)
-
-/* EP0, RX/TX buffers base address */
-#define ENDP0_RX_ADDRESS (0x40)
-#define ENDP0_TX_ADDRESS (0x80)
-
-/* EP1 Tx buffer base address */
-#define HID_IN_TX_ADDRESS (0x150)
-
-/* EP1 Rx buffer base address */
-#define HID_OUT_RX_ADDRESS (0x160)
-
-#define VD_IN_EP 0x81
-#define VD_OUT_EP 0x01
-
-#define VD_IN_PACKET 64
-#define VD_OUT_PACKET 64
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-#endif /* __USB_CONF__H__ */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/User/usbd_conf.h b/attic/NHC-Link042/User/usbd_conf.h
deleted file mode 100644
index 16e175300fe4f750941d8e5d69447778564a9db4..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/User/usbd_conf.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/**
- ******************************************************************************
- * @file usbd_conf.h
- * @author MCD Application Team
- * @version V1.0.0
- * @date 31-January-2014
- * @brief USB Device configuration file
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __USBD_CONF__H__
-#define __USBD_CONF__H__
-
-/* Includes ------------------------------------------------------------------*/
-#include "usb_conf.h"
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-#define USBD_CFG_MAX_NUM 1
-#define USBD_ITF_MAX_NUM 1
-#define USB_MAX_STR_DESC_SIZ 64
-#define USBD_SELF_POWERED
-
-#define CUSTOMHID_SIZ_REPORT_DESC 163
-#define CUSTOMHID_SIZ_CONFIG_DESC 41
-
-#define HID_IN_EP 0x81
-#define HID_OUT_EP 0x01
-
-#define HID_IN_PACKET 2
-#define HID_OUT_PACKET 2
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions ------------------------------------------------------- */
-
-#endif /* __USBD_CONF__H__ */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-
-
-/**
-* @}
-*/
-
diff --git a/attic/NHC-Link042/User/usbd_desc.c b/attic/NHC-Link042/User/usbd_desc.c
deleted file mode 100644
index f46dabff56013fbd59b89f09ee00f42ee3039f60..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/User/usbd_desc.c
+++ /dev/null
@@ -1,257 +0,0 @@
-/**
- ******************************************************************************
- * @file usbd_desc.c
- * @author MCD Application Team
- * @version V1.0.0
- * @date 31-January-2014
- * @brief This file provides the USBD descriptors and string formating method.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_desc.h"
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-#define USBD_VID 0x1986
-#define USBD_PID 0x0034
-
-#define USBD_LANGID_STRING 0x409
-#define USBD_MANUFACTURER_STRING "Hung Cuong Electronics"
-
-#define USBD_PRODUCT_FS_STRING "NHC-Link042"
-
-#define USBD_CONFIGURATION_FS_STRING "NHC-Link042"
-#define USBD_INTERFACE_FS_STRING "NHC-Link042"
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-char USBD_SERIALNUMBER_FS_STRING[26];
-
-USBD_DEVICE USR_desc =
-{
- USBD_USR_DeviceDescriptor,
- USBD_USR_LangIDStrDescriptor,
- USBD_USR_ManufacturerStrDescriptor,
- USBD_USR_ProductStrDescriptor,
- USBD_USR_SerialStrDescriptor,
- USBD_USR_ConfigStrDescriptor,
- USBD_USR_InterfaceStrDescriptor,
-};
-
-/* USB Standard Device Descriptor */
-const uint8_t USBD_DeviceDesc[USB_SIZ_DEVICE_DESC] =
-{
- 0x12, /*bLength */
- USB_DEVICE_DESCRIPTOR_TYPE, /*bDescriptorType*/
- 0x00, /*bcdUSB */
- 0x02,
- 0x00, /*bDeviceClass*/
- 0x00, /*bDeviceSubClass*/
- 0x00, /*bDeviceProtocol*/
- USB_MAX_EP0_SIZE, /*bMaxPacketSize*/
- LOBYTE(USBD_VID), /*idVendor*/
- HIBYTE(USBD_VID), /*idVendor*/
- LOBYTE(USBD_PID), /*idVendor*/
- HIBYTE(USBD_PID), /*idVendor*/
- 0x00, /*bcdDevice rel. 2.00*/
- 0x02,
- USBD_IDX_MFC_STR, /*Index of manufacturer string*/
- USBD_IDX_PRODUCT_STR, /*Index of product string*/
- USBD_IDX_SERIAL_STR, /*Index of serial number string*/
- USBD_CFG_MAX_NUM /*bNumConfigurations*/
-} ; /* USB_DeviceDescriptor */
-
-/* USB Standard Device Descriptor */
-const uint8_t USBD_DeviceQualifierDesc[USB_LEN_DEV_QUALIFIER_DESC] =
-{
- USB_LEN_DEV_QUALIFIER_DESC,
- USB_DESC_TYPE_DEVICE_QUALIFIER,
- 0x00,
- 0x02,
- 0x00,
- 0x00,
- 0x00,
- 0x40,
- 0x01,
- 0x00,
-};
-
-/* USB Standard Device Descriptor */
-const uint8_t USBD_LangIDDesc[USB_SIZ_STRING_LANGID] =
-{
- USB_SIZ_STRING_LANGID,
- USB_DESC_TYPE_STRING,
- LOBYTE(USBD_LANGID_STRING),
- HIBYTE(USBD_LANGID_STRING),
-};
-
-uint8_t USBD_StringSerial[USB_SIZ_STRING_SERIAL] =
-{
- USB_SIZ_STRING_SERIAL, /* bLength */
- USB_STRING_DESCRIPTOR_TYPE, /* bDescriptorType */
- '0', 0, '9', 0, '8', 0, '9', 0, '6', 0, '9', 0, '6', 0, '9', 0, '7', 0, '1', 0
-};
-
-/* Private function prototypes -----------------------------------------------*/
-//static void IntToUnicode (uint32_t value , uint8_t *pbuf , uint8_t len);
-
-/* Private functions ---------------------------------------------------------*/
-
-/**
- * @brief return the device descriptor
- * @param speed : current device speed
- * @param length : pointer to data length variable
- * @retval pointer to descriptor buffer
- */
-uint8_t * USBD_USR_DeviceDescriptor( uint8_t speed , uint16_t *length)
-{
- *length = sizeof(USBD_DeviceDesc);
- return (uint8_t*)USBD_DeviceDesc;
-}
-
-/**
- * @brief return the LangID string descriptor
- * @param speed : current device speed
- * @param length : pointer to data length variable
- * @retval pointer to descriptor buffer
- */
-uint8_t * USBD_USR_LangIDStrDescriptor( uint8_t speed , uint16_t *length)
-{
- *length = sizeof(USBD_LangIDDesc);
- return (uint8_t*)USBD_LangIDDesc;
-}
-
-/**
- * @brief return the product string descriptor
- * @param speed : current device speed
- * @param length : pointer to data length variable
- * @retval pointer to descriptor buffer
- */
-uint8_t * USBD_USR_ProductStrDescriptor( uint8_t speed , uint16_t *length)
-{
- USBD_GetString ( (uint8_t*)USBD_PRODUCT_FS_STRING, USBD_StrDesc, length);
- return USBD_StrDesc;
-}
-
-/**
- * @brief return the manufacturer string descriptor
- * @param speed : current device speed
- * @param length : pointer to data length variable
- * @retval pointer to descriptor buffer
- */
-uint8_t * USBD_USR_ManufacturerStrDescriptor( uint8_t speed , uint16_t *length)
-{
- USBD_GetString ( (uint8_t*)USBD_MANUFACTURER_STRING, USBD_StrDesc, length);
- return USBD_StrDesc;
-}
-
-/**
- * @brief return the serial number string descriptor
- * @param speed : current device speed
- * @param length : pointer to data length variable
- * @retval pointer to descriptor buffer
- */
-uint8_t * USBD_USR_SerialStrDescriptor( uint8_t speed , uint16_t *length)
-{
- *length = USB_SIZ_STRING_SERIAL;
- return USBD_StringSerial;
-}
-
-/**
- * @brief return the configuration string descriptor
- * @param speed : current device speed
- * @param length : pointer to data length variable
- * @retval pointer to descriptor buffer
- */
-uint8_t * USBD_USR_ConfigStrDescriptor( uint8_t speed , uint16_t *length)
-{
- USBD_GetString ( (uint8_t*)USBD_CONFIGURATION_FS_STRING, USBD_StrDesc, length);
- return USBD_StrDesc;
-}
-
-
-/**
- * @brief return the interface string descriptor
- * @param speed : current device speed
- * @param length : pointer to data length variable
- * @retval pointer to descriptor buffer
- */
-uint8_t * USBD_USR_InterfaceStrDescriptor( uint8_t speed , uint16_t *length)
-{
- USBD_GetString ( (uint8_t*)USBD_INTERFACE_FS_STRING, USBD_StrDesc, length);
- return USBD_StrDesc;
-}
-
-/**
- * @brief Create the serial number string descriptor
- * @param None
- * @retval None
- */
-void Get_SerialNum(void)
-{
-#if 0
- uint32_t Device_Serial0, Device_Serial1, Device_Serial2;
-
- Device_Serial0 = *(uint32_t*)Device1_Identifier;
- Device_Serial1 = *(uint32_t*)Device2_Identifier;
- Device_Serial2 = *(uint32_t*)Device3_Identifier;
-
- Device_Serial0 += Device_Serial2;
-
- if (Device_Serial0 != 0)
- {
- IntToUnicode (Device_Serial0, &USBD_StringSerial[2] ,8);
- IntToUnicode (Device_Serial1, &USBD_StringSerial[18] ,4);
- }
-#endif
-}
-
-/**
- * @brief Convert Hex 32Bits value into char
- * @param value: value to convert
- * @param pbuf: pointer to the buffer
- * @param len: buffer length
- * @retval None
- */
-#if 0
-static void IntToUnicode (uint32_t value , uint8_t *pbuf , uint8_t len)
-{
- uint8_t idx = 0;
-
- for( idx = 0 ; idx < len ; idx ++)
- {
- if( ((value >> 28)) < 0xA )
- {
- pbuf[ 2* idx] = (value >> 28) + '0';
- }
- else
- {
- pbuf[2* idx] = (value >> 28) + 'A' - 10;
- }
-
- value = value << 4;
-
- pbuf[ 2* idx + 1] = 0;
- }
-}
-#endif
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/User/usbd_desc.h b/attic/NHC-Link042/User/usbd_desc.h
deleted file mode 100644
index 7948aad30f756e4f99b6f93abf6d513d9434b93f..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/User/usbd_desc.h
+++ /dev/null
@@ -1,75 +0,0 @@
-/**
- ******************************************************************************
- * @file usbd_desc.h
- * @author MCD Application Team
- * @version V1.0.0
- * @date 31-January-2014
- * @brief header file for the usbd_desc.c file
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-
-#ifndef __USB_DESC_H
-#define __USB_DESC_H
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_req.h"
-
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-#define USB_DEVICE_DESCRIPTOR_TYPE 0x01
-#define USB_CONFIGURATION_DESCRIPTOR_TYPE 0x02
-#define USB_STRING_DESCRIPTOR_TYPE 0x03
-#define USB_INTERFACE_DESCRIPTOR_TYPE 0x04
-#define USB_ENDPOINT_DESCRIPTOR_TYPE 0x05
-#define USB_SIZ_DEVICE_DESC 18
-#define USB_SIZ_STRING_LANGID 4
-#define USB_SIZ_STRING_SERIAL 22
-
-#define Device1_Identifier (0x1FFFF7AC)
-#define Device2_Identifier (0x1FFFF7B0)
-#define Device3_Identifier (0x1FFFF7B4)
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported variables --------------------------------------------------------*/
-extern uint8_t USBD_StrDesc[USB_MAX_STR_DESC_SIZ];
-extern uint8_t USBD_OtherSpeedCfgDesc[USB_LEN_CFG_DESC];
-extern USBD_DEVICE USR_desc;
-extern uint8_t USBD_StringSerial[USB_SIZ_STRING_SERIAL];
-
-/* Exported functions ------------------------------------------------------- */
-void Get_SerialNum(void);
-uint8_t * USBD_USR_DeviceDescriptor( uint8_t speed , uint16_t *length);
-uint8_t * USBD_USR_LangIDStrDescriptor( uint8_t speed , uint16_t *length);
-uint8_t * USBD_USR_ManufacturerStrDescriptor ( uint8_t speed , uint16_t *length);
-uint8_t * USBD_USR_ProductStrDescriptor ( uint8_t speed , uint16_t *length);
-uint8_t * USBD_USR_SerialStrDescriptor( uint8_t speed , uint16_t *length);
-uint8_t * USBD_USR_ConfigStrDescriptor( uint8_t speed , uint16_t *length);
-uint8_t * USBD_USR_InterfaceStrDescriptor( uint8_t speed , uint16_t *length);
-
-#ifdef USB_SUPPORT_USER_STRING_DESC
-uint8_t * USBD_USR_USRStringDesc (uint8_t speed, uint8_t idx , uint16_t *length);
-#endif /* USB_SUPPORT_USER_STRING_DESC */
-
-#endif /* __USBD_DESC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/User/usbd_pwr.c b/attic/NHC-Link042/User/usbd_pwr.c
deleted file mode 100644
index 89eecfac9e3bbe56feafae86c7c57c51572e209a..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/User/usbd_pwr.c
+++ /dev/null
@@ -1,233 +0,0 @@
-/**
- ******************************************************************************
- * @file usbd_pwr.c
- * @author MCD Application Team
- * @version V1.0.0
- * @date 31-January-2014
- * @brief This file provides functions for power management
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_pwr.h"
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-struct
-{
- __IO RESUME_STATE eState;
- __IO uint8_t bESOFcnt;
-}
-ResumeS;
-
- __IO uint32_t remotewakeupon=0;
-
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/**
- * @brief Sets suspend mode operating conditions
- * @param None
- * @retval USB_SUCCESS
- */
-void Suspend(void)
-{
- uint16_t wCNTR;
-
- /*Store CNTR value */
- wCNTR = _GetCNTR();
- /* Set FSUSP bit in USB_CNTR register*/
- wCNTR |= CNTR_FSUSP;
- _SetCNTR(wCNTR);
-
- /* force low-power mode in the macrocell */
- wCNTR = _GetCNTR();
- wCNTR |= CNTR_LPMODE;
- _SetCNTR(wCNTR);
-
-#ifdef USB_DEVICE_LOW_PWR_MGMT_SUPPORT
-
- /* enter system in STOP mode, only when wakeup flag in not set */
- if((_GetISTR()&ISTR_WKUP)==0)
- {
- /*Enter STOP mode with SLEEPONEXIT*/
- PWR_EnterSTOPMode(PWR_Regulator_LowPower, PWR_STOPEntry_SLEEPONEXIT);
- }
- else
- {
- /* Clear Wakeup flag */
- _SetISTR(CLR_WKUP);
- /* clear FSUSP to abort entry in suspend mode */
- wCNTR = _GetCNTR();
- wCNTR&=~CNTR_FSUSP;
- _SetCNTR(wCNTR);
- }
-#endif
-}
-
-/**
- * @brief Handles wake-up restoring normal operations
- * @param None
- * @retval USB_SUCCESS
- */
-void Resume_Init(void)
-{
- uint16_t wCNTR;
-
- /* ------------------ ONLY WITH BUS-POWERED DEVICES ---------------------- */
- /* restart the clocks */
- /* ... */
-
- /* CNTR_LPMODE = 0 */
- wCNTR = _GetCNTR();
- wCNTR &= (~CNTR_LPMODE);
- _SetCNTR(wCNTR);
-#ifdef USB_DEVICE_LOW_PWR_MGMT_SUPPORT
- /* restore full power */
- /* ... on connected devices */
- Leave_LowPowerMode();
-#endif
- /* reset FSUSP bit */
- _SetCNTR(IMR_MSK);
-
-}
-
-
-/**
- * @brief Provides the state machine handling resume operations and
- * timing sequence. The control is based on the Resume structure
- * variables and on the ESOF interrupt calling this subroutine
- * without changing machine state.
- * @param a state machine value (RESUME_STATE)
- * RESUME_ESOF doesn't change ResumeS.eState allowing
- * decrementing of the ESOF counter in different states.
- * @retval Status
- */
-void Resume(RESUME_STATE eResumeSetVal)
-{
- uint16_t wCNTR;
-
- if (eResumeSetVal != RESUME_ESOF)
- ResumeS.eState = eResumeSetVal;
- switch (ResumeS.eState)
- {
- case RESUME_EXTERNAL:
-
-if (remotewakeupon ==0)
- {
- Resume_Init();
- ResumeS.eState = RESUME_OFF;
- }
- else /* RESUME detected during the RemoteWAkeup signalling => keep RemoteWakeup handling*/
- {
- ResumeS.eState = RESUME_ON;
- }
- break;
- case RESUME_INTERNAL:
- Resume_Init();
- ResumeS.eState = RESUME_START;
- remotewakeupon = 1;
- break;
- case RESUME_LATER:
- ResumeS.bESOFcnt = 2;
- ResumeS.eState = RESUME_WAIT;
- break;
- case RESUME_WAIT:
- ResumeS.bESOFcnt--;
- if (ResumeS.bESOFcnt == 0)
- ResumeS.eState = RESUME_START;
- break;
- case RESUME_START:
- wCNTR = _GetCNTR();
- wCNTR |= CNTR_RESUME;
- _SetCNTR(wCNTR);
- ResumeS.eState = RESUME_ON;
- ResumeS.bESOFcnt = 10;
- break;
- case RESUME_ON:
- ResumeS.bESOFcnt--;
- if (ResumeS.bESOFcnt == 0)
- {
- wCNTR = _GetCNTR();
- wCNTR &= (~CNTR_RESUME);
- _SetCNTR(wCNTR);
- ResumeS.eState = RESUME_OFF;
- remotewakeupon = 0;
- }
- break;
- case RESUME_OFF:
- case RESUME_ESOF:
- default:
- ResumeS.eState = RESUME_OFF;
- break;
- }
-}
-
-/**
- * @brief Restores system clocks and power while exiting suspend mode
- * @param None
- * @retval None
- */
-void Leave_LowPowerMode(void)
-{
-#if defined USB_CLOCK_SOURCE_CRS
- /* Enable HSI48 oscillator */
- RCC_HSI48Cmd(ENABLE);
-
- /* Wait till HSI48RDYF is set */
- while(RCC_GetFlagStatus(RCC_FLAG_HSI48RDY) == RESET)
- {
- }
- /* Select HSI48 as system clock source */
- RCC_SYSCLKConfig(RCC_SYSCLKSource_HSI48);
-
-#else
-
- /* After wake-up from STOP mode restore system clock (system clock = PLL clock
- from HSE source )*/
- /* Enable HSE */
- RCC_HSEConfig(RCC_HSE_ON);
-
- /* Wait till HSE is ready */
- while (RCC_GetFlagStatus(RCC_FLAG_HSERDY) == RESET)
- {}
-
- /* Enable PLL */
- RCC_PLLCmd(ENABLE);
-
- /* Wait till PLL is ready */
- while (RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET)
- {}
-
- /* Select PLL as system clock source */
- RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
-
- /* Wait till PLL is used as system clock source */
- while (RCC_GetSYSCLKSource() != 0x08)
- {}
-#endif /* USB_CLOCK_SOURCE_CRS */
-
- /*Low Power Sleep on Exit Disabled*/
- NVIC_SystemLPConfig(NVIC_LP_SLEEPONEXIT, DISABLE);
-}
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/NHC-Link042/User/usbd_usr.c b/attic/NHC-Link042/User/usbd_usr.c
deleted file mode 100644
index 1aa74a5e2b79af6d9dfbdd9f69d929e27805c558..0000000000000000000000000000000000000000
--- a/attic/NHC-Link042/User/usbd_usr.c
+++ /dev/null
@@ -1,118 +0,0 @@
-/**
- ******************************************************************************
- * @file usbd_usr.c
- * @author MCD Application Team
- * @version V1.0.0
- * @date 31-January-2014
- * @brief This file contains user callback structure for USB events Management
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "usbd_usr.h"
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-//#define ADC1_DR_Address 0x40012440
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-
-USBD_Usr_cb_TypeDef USR_cb =
-{
- USBD_USR_Init,
- USBD_USR_DeviceReset,
- USBD_USR_DeviceConfigured,
- USBD_USR_DeviceSuspended,
- USBD_USR_DeviceResumed,
-};
-
-//uint32_t ADC_ConvertedValueX = 0;
-//uint32_t ADC_ConvertedValueX_1 = 0;
-
-/* Private function prototypes -----------------------------------------------*/
-//static void ADC_Configuration(void);
-
-/* Private functions ---------------------------------------------------------*/
-
-/**
- * @brief Device lib initialization
- * @param None
- * @retval None
- */
-void USBD_USR_Init(void)
-{
- /* Initialize LEDs */
- //STM_EVAL_LEDInit(LED1);
- //STM_EVAL_LEDInit(LED2);
- //STM_EVAL_LEDInit(LED3);
- //STM_EVAL_LEDInit(LED4);
-
- /* Configure the ADC*/
- //ADC_Configuration();
-
-}
-
-/**
- * @brief Reset Event
- * @param speed : device speed
- * @retval None
- */
-void USBD_USR_DeviceReset(uint8_t speed )
-{
-}
-
-/**
- * @brief Configuration Event
- * @param None
- * @retval None
- */
-void USBD_USR_DeviceConfigured (void)
-{
-}
-
-/**
- * @brief Device suspend Event
- * @param None
- * @retval None
- */
-void USBD_USR_DeviceSuspended(void)
-{
-}
-
-
-/**
- * @brief Device resume Event
- * @param None
- * @retval None
- */
-void USBD_USR_DeviceResumed(void)
-{
-}
-
-/**
- * @brief ADC_Configuration
-* Configure the ADC
- * @param None
- * @retval None
- */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/attic/ch32v003evt/LICENSE b/attic/ch32v003evt/LICENSE
deleted file mode 100644
index e637ef03ccc23467d29464a6a086720c4e4eb67d..0000000000000000000000000000000000000000
--- a/attic/ch32v003evt/LICENSE
+++ /dev/null
@@ -1,12 +0,0 @@
-All documents from WCH are under the following license. This works for any of
-their code. I've done the best I can to extract only the definitions to put into
-this folder, but depending on jurisdiction, the code in this folder may actually
-taint MIT or BSD licsned code.
-
-/********************************** (C) COPYRIGHT *******************************
- * Author : WCH
- *********************************************************************************
- * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
- * Attention: This software (modified or not) and binary are used for
- * microcontroller manufactured by Nanjing Qinheng Microelectronics.
- *******************************************************************************/
diff --git a/attic/ch32v003evt/ch32v003.ld b/attic/ch32v003evt/ch32v003.ld
deleted file mode 100644
index d3d27288f1530e420dafd11ea17d1c93401890c9..0000000000000000000000000000000000000000
--- a/attic/ch32v003evt/ch32v003.ld
+++ /dev/null
@@ -1,159 +0,0 @@
-ENTRY( InterruptVector )
-
-__stack_size = 256;
-
-PROVIDE( _stack_size = __stack_size );
-
-MEMORY
-{
- FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 16K
- RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 2K
-}
-
-SECTIONS
-{
- .init :
- {
- _sinit = .;
- . = ALIGN(4);
- KEEP(*(SORT_NONE(.init)))
- . = ALIGN(4);
- _einit = .;
- } >FLASH AT>FLASH
-
- .text :
- {
- . = ALIGN(4);
- *(.text)
- *(.text.*)
- *(.rodata)
- *(.rodata*)
- *(.gnu.linkonce.t.*)
- . = ALIGN(4);
- } >FLASH AT>FLASH
-
- .fini :
- {
- KEEP(*(SORT_NONE(.fini)))
- . = ALIGN(4);
- } >FLASH AT>FLASH
-
- PROVIDE( _etext = . );
- PROVIDE( _eitcm = . );
-
- .preinit_array :
- {
- PROVIDE_HIDDEN (__preinit_array_start = .);
- KEEP (*(.preinit_array))
- PROVIDE_HIDDEN (__preinit_array_end = .);
- } >FLASH AT>FLASH
-
- .init_array :
- {
- PROVIDE_HIDDEN (__init_array_start = .);
- KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
- KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
- PROVIDE_HIDDEN (__init_array_end = .);
- } >FLASH AT>FLASH
-
- .fini_array :
- {
- PROVIDE_HIDDEN (__fini_array_start = .);
- KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
- KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
- PROVIDE_HIDDEN (__fini_array_end = .);
- } >FLASH AT>FLASH
-
- .ctors :
- {
- /* gcc uses crtbegin.o to find the start of
- the constructors, so we make sure it is
- first. Because this is a wildcard, it
- doesn't matter if the user does not
- actually link against crtbegin.o; the
- linker won't look for a file to match a
- wildcard. The wildcard also means that it
- doesn't matter which directory crtbegin.o
- is in. */
- KEEP (*crtbegin.o(.ctors))
- KEEP (*crtbegin?.o(.ctors))
- /* We don't want to include the .ctor section from
- the crtend.o file until after the sorted ctors.
- The .ctor section from the crtend file contains the
- end of ctors marker and it must be last */
- KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
- KEEP (*(SORT(.ctors.*)))
- KEEP (*(.ctors))
- } >FLASH AT>FLASH
-
- .dtors :
- {
- KEEP (*crtbegin.o(.dtors))
- KEEP (*crtbegin?.o(.dtors))
- KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
- KEEP (*(SORT(.dtors.*)))
- KEEP (*(.dtors))
- } >FLASH AT>FLASH
-
- .dalign :
- {
- . = ALIGN(4);
- PROVIDE(_data_vma = .);
- } >RAM AT>FLASH
-
- .dlalign :
- {
- . = ALIGN(4);
- PROVIDE(_data_lma = .);
- } >FLASH AT>FLASH
-
- .data :
- {
- . = ALIGN(4);
- *(.gnu.linkonce.r.*)
- *(.data .data.*)
- *(.gnu.linkonce.d.*)
- . = ALIGN(8);
- PROVIDE( __global_pointer$ = . + 0x800 );
- *(.sdata .sdata.*)
- *(.sdata2*)
- *(.gnu.linkonce.s.*)
- . = ALIGN(8);
- *(.srodata.cst16)
- *(.srodata.cst8)
- *(.srodata.cst4)
- *(.srodata.cst2)
- *(.srodata .srodata.*)
- . = ALIGN(4);
- PROVIDE( _edata = .);
- } >RAM AT>FLASH
-
- .bss :
- {
- . = ALIGN(4);
- PROVIDE( _sbss = .);
- *(.sbss*)
- *(.gnu.linkonce.sb.*)
- *(.bss*)
- *(.gnu.linkonce.b.*)
- *(COMMON*)
- . = ALIGN(4);
- PROVIDE( _ebss = .);
- } >RAM AT>FLASH
-
- PROVIDE( _end = _ebss);
- PROVIDE( end = . );
-
- .stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size :
- {
- PROVIDE( _heap_end = . );
- . = ALIGN(4);
- PROVIDE(_susrstack = . );
- . = . + __stack_size;
- PROVIDE( _eusrstack = .);
- } >RAM
-
-}
-
-
-
diff --git a/attic/ch32v003evt/ch32v00x.h b/attic/ch32v003evt/ch32v00x.h
deleted file mode 100644
index 915968b30edb11407ce53f70de15dd16bb22a71e..0000000000000000000000000000000000000000
--- a/attic/ch32v003evt/ch32v00x.h
+++ /dev/null
@@ -1,2402 +0,0 @@
-/********************************** (C) COPYRIGHT *******************************
- * File Name : ch32v00x.h
- * Author : WCH
- * Version : V1.0.0
- * Date : 2022/08/08
- * Description : CH32V00x Device Peripheral Access Layer Header File.
- *********************************************************************************
- * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
- * Attention: This software (modified or not) and binary are used for
- * microcontroller manufactured by Nanjing Qinheng Microelectronics.
- *******************************************************************************/
-#ifndef __CH32V00x_H
-#define __CH32V00x_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define __MPU_PRESENT 0 /* Other CH32 devices does not provide an MPU */
-#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */
-
-#define HSE_VALUE ((uint32_t)24000000) /* Value of the External oscillator in Hz */
-
-/* In the following line adjust the External High Speed oscillator (HSE) Startup Timeout value */
-#define HSE_STARTUP_TIMEOUT ((uint16_t)0x2000) /* Time out for HSE start up */
-
-#define HSI_VALUE ((uint32_t)24000000) /* Value of the Internal oscillator in Hz */
-
-
-/* Interrupt Number Definition, according to the selected device */
-typedef enum IRQn
-{
- /****** RISC-V Processor Exceptions Numbers *******************************************************/
- NonMaskableInt_IRQn = 2, /* 2 Non Maskable Interrupt */
- EXC_IRQn = 3, /* 3 Exception Interrupt */
- SysTicK_IRQn = 12, /* 12 System timer Interrupt */
- Software_IRQn = 14, /* 14 software Interrupt */
-
- /****** RISC-V specific Interrupt Numbers *********************************************************/
- WWDG_IRQn = 16, /* Window WatchDog Interrupt */
- PVD_IRQn = 17, /* PVD through EXTI Line detection Interrupt */
- FLASH_IRQn = 18, /* FLASH global Interrupt */
- RCC_IRQn = 19, /* RCC global Interrupt */
- EXTI7_0_IRQn = 20, /* External Line[7:0] Interrupts */
- AWU_IRQn = 21, /* AWU global Interrupt */
- DMA1_Channel1_IRQn = 22, /* DMA1 Channel 1 global Interrupt */
- DMA1_Channel2_IRQn = 23, /* DMA1 Channel 2 global Interrupt */
- DMA1_Channel3_IRQn = 24, /* DMA1 Channel 3 global Interrupt */
- DMA1_Channel4_IRQn = 25, /* DMA1 Channel 4 global Interrupt */
- DMA1_Channel5_IRQn = 26, /* DMA1 Channel 5 global Interrupt */
- DMA1_Channel6_IRQn = 27, /* DMA1 Channel 6 global Interrupt */
- DMA1_Channel7_IRQn = 28, /* DMA1 Channel 7 global Interrupt */
- ADC_IRQn = 29, /* ADC global Interrupt */
- I2C1_EV_IRQn = 30, /* I2C1 Event Interrupt */
- I2C1_ER_IRQn = 31, /* I2C1 Error Interrupt */
- USART1_IRQn = 32, /* USART1 global Interrupt */
- SPI1_IRQn = 33, /* SPI1 global Interrupt */
- TIM1_BRK_IRQn = 34, /* TIM1 Break Interrupt */
- TIM1_UP_IRQn = 35, /* TIM1 Update Interrupt */
- TIM1_TRG_COM_IRQn = 36, /* TIM1 Trigger and Commutation Interrupt */
- TIM1_CC_IRQn = 37, /* TIM1 Capture Compare Interrupt */
- TIM2_IRQn = 38, /* TIM2 global Interrupt */
-
-} IRQn_Type;
-
-#define HardFault_IRQn EXC_IRQn
-
-#include <stdint.h>
-#include <core_riscv.h>
-#include <system_ch32v00x.h>
-
-/* Standard Peripheral Library old definitions (maintained for legacy purpose) */
-#define HSI_Value HSI_VALUE
-#define HSE_Value HSE_VALUE
-#define HSEStartUp_TimeOut HSE_STARTUP_TIMEOUT
-
-/* Analog to Digital Converter */
-typedef struct
-{
- __IO uint32_t STATR;
- __IO uint32_t CTLR1;
- __IO uint32_t CTLR2;
- __IO uint32_t SAMPTR1;
- __IO uint32_t SAMPTR2;
- __IO uint32_t IOFR1;
- __IO uint32_t IOFR2;
- __IO uint32_t IOFR3;
- __IO uint32_t IOFR4;
- __IO uint32_t WDHTR;
- __IO uint32_t WDLTR;
- __IO uint32_t RSQR1;
- __IO uint32_t RSQR2;
- __IO uint32_t RSQR3;
- __IO uint32_t ISQR;
- __IO uint32_t IDATAR1;
- __IO uint32_t IDATAR2;
- __IO uint32_t IDATAR3;
- __IO uint32_t IDATAR4;
- __IO uint32_t RDATAR;
- __IO uint32_t DLYR;
-} ADC_TypeDef;
-
-/* Debug MCU */
-typedef struct
-{
- __IO uint32_t CFGR0;
- __IO uint32_t CFGR1;
-} DBGMCU_TypeDef;
-
-/* DMA Controller */
-typedef struct
-{
- __IO uint32_t CFGR;
- __IO uint32_t CNTR;
- __IO uint32_t PADDR;
- __IO uint32_t MADDR;
-} DMA_Channel_TypeDef;
-
-typedef struct
-{
- __IO uint32_t INTFR;
- __IO uint32_t INTFCR;
-} DMA_TypeDef;
-
-/* External Interrupt/Event Controller */
-typedef struct
-{
- __IO uint32_t INTENR;
- __IO uint32_t EVENR;
- __IO uint32_t RTENR;
- __IO uint32_t FTENR;
- __IO uint32_t SWIEVR;
- __IO uint32_t INTFR;
-} EXTI_TypeDef;
-
-/* FLASH Registers */
-typedef struct
-{
- __IO uint32_t ACTLR;
- __IO uint32_t KEYR;
- __IO uint32_t OBKEYR;
- __IO uint32_t STATR;
- __IO uint32_t CTLR;
- __IO uint32_t ADDR;
- __IO uint32_t RESERVED;
- __IO uint32_t OBR;
- __IO uint32_t WPR;
- __IO uint32_t MODEKEYR;
- __IO uint32_t BOOT_MODEKEYR;
-} FLASH_TypeDef;
-
-/* Option Bytes Registers */
-typedef struct
-{
- __IO uint16_t RDPR;
- __IO uint16_t USER;
- __IO uint16_t Data0;
- __IO uint16_t Data1;
- __IO uint16_t WRPR0;
- __IO uint16_t WRPR1;
-} OB_TypeDef;
-
-/* General Purpose I/O */
-typedef struct
-{
- __IO uint32_t CFGLR;
- __IO uint32_t CFGHR;
- __IO uint32_t INDR;
- __IO uint32_t OUTDR;
- __IO uint32_t BSHR;
- __IO uint32_t BCR;
- __IO uint32_t LCKR;
-} GPIO_TypeDef;
-
-/* Alternate Function I/O */
-typedef struct
-{
- uint32_t RESERVED0;
- __IO uint32_t PCFR1;
- __IO uint32_t EXTICR;
-} AFIO_TypeDef;
-
-/* Inter Integrated Circuit Interface */
-typedef struct
-{
- __IO uint16_t CTLR1;
- uint16_t RESERVED0;
- __IO uint16_t CTLR2;
- uint16_t RESERVED1;
- __IO uint16_t OADDR1;
- uint16_t RESERVED2;
- __IO uint16_t OADDR2;
- uint16_t RESERVED3;
- __IO uint16_t DATAR;
- uint16_t RESERVED4;
- __IO uint16_t STAR1;
- uint16_t RESERVED5;
- __IO uint16_t STAR2;
- uint16_t RESERVED6;
- __IO uint16_t CKCFGR;
- uint16_t RESERVED7;
-} I2C_TypeDef;
-
-/* Independent WatchDog */
-typedef struct
-{
- __IO uint32_t CTLR;
- __IO uint32_t PSCR;
- __IO uint32_t RLDR;
- __IO uint32_t STATR;
-} IWDG_TypeDef;
-
-/* Power Control */
-typedef struct
-{
- __IO uint32_t CTLR;
- __IO uint32_t CSR;
- __IO uint32_t AWUCSR;
- __IO uint32_t AWUWR;
- __IO uint32_t AWUPSC;
-} PWR_TypeDef;
-
-/* Reset and Clock Control */
-typedef struct
-{
- __IO uint32_t CTLR;
- __IO uint32_t CFGR0;
- __IO uint32_t INTR;
- __IO uint32_t APB2PRSTR;
- __IO uint32_t APB1PRSTR;
- __IO uint32_t AHBPCENR;
- __IO uint32_t APB2PCENR;
- __IO uint32_t APB1PCENR;
- __IO uint32_t RESERVED0;
- __IO uint32_t RSTSCKR;
-} RCC_TypeDef;
-
-/* Serial Peripheral Interface */
-typedef struct
-{
- __IO uint16_t CTLR1;
- uint16_t RESERVED0;
- __IO uint16_t CTLR2;
- uint16_t RESERVED1;
- __IO uint16_t STATR;
- uint16_t RESERVED2;
- __IO uint16_t DATAR;
- uint16_t RESERVED3;
- __IO uint16_t CRCR;
- uint16_t RESERVED4;
- __IO uint16_t RCRCR;
- uint16_t RESERVED5;
- __IO uint16_t TCRCR;
- uint16_t RESERVED6;
- uint32_t RESERVED7;
- uint32_t RESERVED8;
- __IO uint16_t HSCR;
- uint16_t RESERVED9;
-} SPI_TypeDef;
-
-/* TIM */
-typedef struct
-{
- __IO uint16_t CTLR1;
- uint16_t RESERVED0;
- __IO uint16_t CTLR2;
- uint16_t RESERVED1;
- __IO uint16_t SMCFGR;
- uint16_t RESERVED2;
- __IO uint16_t DMAINTENR;
- uint16_t RESERVED3;
- __IO uint16_t INTFR;
- uint16_t RESERVED4;
- __IO uint16_t SWEVGR;
- uint16_t RESERVED5;
- __IO uint16_t CHCTLR1;
- uint16_t RESERVED6;
- __IO uint16_t CHCTLR2;
- uint16_t RESERVED7;
- __IO uint16_t CCER;
- uint16_t RESERVED8;
- __IO uint16_t CNT;
- uint16_t RESERVED9;
- __IO uint16_t PSC;
- uint16_t RESERVED10;
- __IO uint16_t ATRLR;
- uint16_t RESERVED11;
- __IO uint16_t RPTCR;
- uint16_t RESERVED12;
- __IO uint32_t CH1CVR;
- __IO uint32_t CH2CVR;
- __IO uint32_t CH3CVR;
- __IO uint32_t CH4CVR;
- __IO uint16_t BDTR;
- uint16_t RESERVED13;
- __IO uint16_t DMACFGR;
- uint16_t RESERVED14;
- __IO uint16_t DMAADR;
- uint16_t RESERVED15;
-} TIM_TypeDef;
-
-/* Universal Synchronous Asynchronous Receiver Transmitter */
-typedef struct
-{
- __IO uint16_t STATR;
- uint16_t RESERVED0;
- __IO uint16_t DATAR;
- uint16_t RESERVED1;
- __IO uint16_t BRR;
- uint16_t RESERVED2;
- __IO uint16_t CTLR1;
- uint16_t RESERVED3;
- __IO uint16_t CTLR2;
- uint16_t RESERVED4;
- __IO uint16_t CTLR3;
- uint16_t RESERVED5;
- __IO uint16_t GPR;
- uint16_t RESERVED6;
-} USART_TypeDef;
-
-/* Window WatchDog */
-typedef struct
-{
- __IO uint32_t CTLR;
- __IO uint32_t CFGR;
- __IO uint32_t STATR;
-} WWDG_TypeDef;
-
-/* Enhanced Registers */
-typedef struct
-{
- __IO uint32_t EXTEN_CTR;
-} EXTEN_TypeDef;
-
-/* Peripheral memory map */
-#define FLASH_BASE ((uint32_t)0x08000000) /* FLASH base address in the alias region */
-#define SRAM_BASE ((uint32_t)0x20000000) /* SRAM base address in the alias region */
-#define PERIPH_BASE ((uint32_t)0x40000000) /* Peripheral base address in the alias region */
-
-#define APB1PERIPH_BASE (PERIPH_BASE)
-#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
-#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
-
-#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
-#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
-#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
-#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
-#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
-
-#define AFIO_BASE (APB2PERIPH_BASE + 0x0000)
-#define EXTI_BASE (APB2PERIPH_BASE + 0x0400)
-#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800)
-#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000)
-#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400)
-#define ADC1_BASE (APB2PERIPH_BASE + 0x2400)
-#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00)
-#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
-#define USART1_BASE (APB2PERIPH_BASE + 0x3800)
-
-#define DMA1_BASE (AHBPERIPH_BASE + 0x0000)
-#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008)
-#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C)
-#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030)
-#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044)
-#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058)
-#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C)
-#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080)
-#define RCC_BASE (AHBPERIPH_BASE + 0x1000)
-
-#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /* Flash registers base address */
-#define OB_BASE ((uint32_t)0x1FFFF800) /* Flash Option Bytes base address */
-#define EXTEN_BASE ((uint32_t)0x40023800)
-
-/* Peripheral declaration */
-#define TIM2 ((TIM_TypeDef *)TIM2_BASE)
-#define WWDG ((WWDG_TypeDef *)WWDG_BASE)
-#define IWDG ((IWDG_TypeDef *)IWDG_BASE)
-#define I2C1 ((I2C_TypeDef *)I2C1_BASE)
-#define PWR ((PWR_TypeDef *)PWR_BASE)
-#define AFIO ((AFIO_TypeDef *)AFIO_BASE)
-#define EXTI ((EXTI_TypeDef *)EXTI_BASE)
-#define GPIOA ((GPIO_TypeDef *)GPIOA_BASE)
-#define GPIOC ((GPIO_TypeDef *)GPIOC_BASE)
-#define GPIOD ((GPIO_TypeDef *)GPIOD_BASE)
-#define ADC1 ((ADC_TypeDef *)ADC1_BASE)
-#define TIM1 ((TIM_TypeDef *)TIM1_BASE)
-#define SPI1 ((SPI_TypeDef *)SPI1_BASE)
-#define USART1 ((USART_TypeDef *)USART1_BASE)
-#define DMA1 ((DMA_TypeDef *)DMA1_BASE)
-#define DMA1_Channel1 ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE)
-#define DMA1_Channel2 ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE)
-#define DMA1_Channel3 ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE)
-#define DMA1_Channel4 ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE)
-#define DMA1_Channel5 ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE)
-#define DMA1_Channel6 ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE)
-#define DMA1_Channel7 ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE)
-#define RCC ((RCC_TypeDef *)RCC_BASE)
-#define FLASH ((FLASH_TypeDef *)FLASH_R_BASE)
-#define OB ((OB_TypeDef *)OB_BASE)
-#define EXTEN ((EXTEN_TypeDef *)EXTEN_BASE)
-
-/******************************************************************************/
-/* Peripheral Registers Bits Definition */
-/******************************************************************************/
-
-/******************************************************************************/
-/* Analog to Digital Converter */
-/******************************************************************************/
-
-/******************** Bit definition for ADC_STATR register ********************/
-#define ADC_AWD ((uint8_t)0x01) /* Analog watchdog flag */
-#define ADC_EOC ((uint8_t)0x02) /* End of conversion */
-#define ADC_JEOC ((uint8_t)0x04) /* Injected channel end of conversion */
-#define ADC_JSTRT ((uint8_t)0x08) /* Injected channel Start flag */
-#define ADC_STRT ((uint8_t)0x10) /* Regular channel Start flag */
-
-/******************* Bit definition for ADC_CTLR1 register ********************/
-#define ADC_AWDCH ((uint32_t)0x0000001F) /* AWDCH[4:0] bits (Analog watchdog channel select bits) */
-#define ADC_AWDCH_0 ((uint32_t)0x00000001) /* Bit 0 */
-#define ADC_AWDCH_1 ((uint32_t)0x00000002) /* Bit 1 */
-#define ADC_AWDCH_2 ((uint32_t)0x00000004) /* Bit 2 */
-#define ADC_AWDCH_3 ((uint32_t)0x00000008) /* Bit 3 */
-#define ADC_AWDCH_4 ((uint32_t)0x00000010) /* Bit 4 */
-
-#define ADC_EOCIE ((uint32_t)0x00000020) /* Interrupt enable for EOC */
-#define ADC_AWDIE ((uint32_t)0x00000040) /* Analog Watchdog interrupt enable */
-#define ADC_JEOCIE ((uint32_t)0x00000080) /* Interrupt enable for injected channels */
-#define ADC_SCAN ((uint32_t)0x00000100) /* Scan mode */
-#define ADC_AWDSGL ((uint32_t)0x00000200) /* Enable the watchdog on a single channel in scan mode */
-#define ADC_JAUTO ((uint32_t)0x00000400) /* Automatic injected group conversion */
-#define ADC_DISCEN ((uint32_t)0x00000800) /* Discontinuous mode on regular channels */
-#define ADC_JDISCEN ((uint32_t)0x00001000) /* Discontinuous mode on injected channels */
-
-#define ADC_DISCNUM ((uint32_t)0x0000E000) /* DISCNUM[2:0] bits (Discontinuous mode channel count) */
-#define ADC_DISCNUM_0 ((uint32_t)0x00002000) /* Bit 0 */
-#define ADC_DISCNUM_1 ((uint32_t)0x00004000) /* Bit 1 */
-#define ADC_DISCNUM_2 ((uint32_t)0x00008000) /* Bit 2 */
-
-#define ADC_DUALMOD ((uint32_t)0x000F0000) /* DUALMOD[3:0] bits (Dual mode selection) */
-#define ADC_DUALMOD_0 ((uint32_t)0x00010000) /* Bit 0 */
-#define ADC_DUALMOD_1 ((uint32_t)0x00020000) /* Bit 1 */
-#define ADC_DUALMOD_2 ((uint32_t)0x00040000) /* Bit 2 */
-#define ADC_DUALMOD_3 ((uint32_t)0x00080000) /* Bit 3 */
-
-#define ADC_JAWDEN ((uint32_t)0x00400000) /* Analog watchdog enable on injected channels */
-#define ADC_AWDEN ((uint32_t)0x00800000) /* Analog watchdog enable on regular channels */
-
-/******************* Bit definition for ADC_CTLR2 register ********************/
-#define ADC_ADON ((uint32_t)0x00000001) /* A/D Converter ON / OFF */
-#define ADC_CONT ((uint32_t)0x00000002) /* Continuous Conversion */
-#define ADC_CAL ((uint32_t)0x00000004) /* A/D Calibration */
-#define ADC_RSTCAL ((uint32_t)0x00000008) /* Reset Calibration */
-#define ADC_DMA ((uint32_t)0x00000100) /* Direct Memory access mode */
-#define ADC_ALIGN ((uint32_t)0x00000800) /* Data Alignment */
-
-#define ADC_JEXTSEL ((uint32_t)0x00007000) /* JEXTSEL[2:0] bits (External event select for injected group) */
-#define ADC_JEXTSEL_0 ((uint32_t)0x00001000) /* Bit 0 */
-#define ADC_JEXTSEL_1 ((uint32_t)0x00002000) /* Bit 1 */
-#define ADC_JEXTSEL_2 ((uint32_t)0x00004000) /* Bit 2 */
-
-#define ADC_JEXTTRIG ((uint32_t)0x00008000) /* External Trigger Conversion mode for injected channels */
-
-#define ADC_EXTSEL ((uint32_t)0x000E0000) /* EXTSEL[2:0] bits (External Event Select for regular group) */
-#define ADC_EXTSEL_0 ((uint32_t)0x00020000) /* Bit 0 */
-#define ADC_EXTSEL_1 ((uint32_t)0x00040000) /* Bit 1 */
-#define ADC_EXTSEL_2 ((uint32_t)0x00080000) /* Bit 2 */
-
-#define ADC_EXTTRIG ((uint32_t)0x00100000) /* External Trigger Conversion mode for regular channels */
-#define ADC_JSWSTART ((uint32_t)0x00200000) /* Start Conversion of injected channels */
-#define ADC_SWSTART ((uint32_t)0x00400000) /* Start Conversion of regular channels */
-#define ADC_TSVREFE ((uint32_t)0x00800000) /* Temperature Sensor and VREFINT Enable */
-
-/****************** Bit definition for ADC_SAMPTR1 register *******************/
-#define ADC_SMP10 ((uint32_t)0x00000007) /* SMP10[2:0] bits (Channel 10 Sample time selection) */
-#define ADC_SMP10_0 ((uint32_t)0x00000001) /* Bit 0 */
-#define ADC_SMP10_1 ((uint32_t)0x00000002) /* Bit 1 */
-#define ADC_SMP10_2 ((uint32_t)0x00000004) /* Bit 2 */
-
-#define ADC_SMP11 ((uint32_t)0x00000038) /* SMP11[2:0] bits (Channel 11 Sample time selection) */
-#define ADC_SMP11_0 ((uint32_t)0x00000008) /* Bit 0 */
-#define ADC_SMP11_1 ((uint32_t)0x00000010) /* Bit 1 */
-#define ADC_SMP11_2 ((uint32_t)0x00000020) /* Bit 2 */
-
-#define ADC_SMP12 ((uint32_t)0x000001C0) /* SMP12[2:0] bits (Channel 12 Sample time selection) */
-#define ADC_SMP12_0 ((uint32_t)0x00000040) /* Bit 0 */
-#define ADC_SMP12_1 ((uint32_t)0x00000080) /* Bit 1 */
-#define ADC_SMP12_2 ((uint32_t)0x00000100) /* Bit 2 */
-
-#define ADC_SMP13 ((uint32_t)0x00000E00) /* SMP13[2:0] bits (Channel 13 Sample time selection) */
-#define ADC_SMP13_0 ((uint32_t)0x00000200) /* Bit 0 */
-#define ADC_SMP13_1 ((uint32_t)0x00000400) /* Bit 1 */
-#define ADC_SMP13_2 ((uint32_t)0x00000800) /* Bit 2 */
-
-#define ADC_SMP14 ((uint32_t)0x00007000) /* SMP14[2:0] bits (Channel 14 Sample time selection) */
-#define ADC_SMP14_0 ((uint32_t)0x00001000) /* Bit 0 */
-#define ADC_SMP14_1 ((uint32_t)0x00002000) /* Bit 1 */
-#define ADC_SMP14_2 ((uint32_t)0x00004000) /* Bit 2 */
-
-#define ADC_SMP15 ((uint32_t)0x00038000) /* SMP15[2:0] bits (Channel 15 Sample time selection) */
-#define ADC_SMP15_0 ((uint32_t)0x00008000) /* Bit 0 */
-#define ADC_SMP15_1 ((uint32_t)0x00010000) /* Bit 1 */
-#define ADC_SMP15_2 ((uint32_t)0x00020000) /* Bit 2 */
-
-#define ADC_SMP16 ((uint32_t)0x001C0000) /* SMP16[2:0] bits (Channel 16 Sample time selection) */
-#define ADC_SMP16_0 ((uint32_t)0x00040000) /* Bit 0 */
-#define ADC_SMP16_1 ((uint32_t)0x00080000) /* Bit 1 */
-#define ADC_SMP16_2 ((uint32_t)0x00100000) /* Bit 2 */
-
-#define ADC_SMP17 ((uint32_t)0x00E00000) /* SMP17[2:0] bits (Channel 17 Sample time selection) */
-#define ADC_SMP17_0 ((uint32_t)0x00200000) /* Bit 0 */
-#define ADC_SMP17_1 ((uint32_t)0x00400000) /* Bit 1 */
-#define ADC_SMP17_2 ((uint32_t)0x00800000) /* Bit 2 */
-
-/****************** Bit definition for ADC_SAMPTR2 register *******************/
-#define ADC_SMP0 ((uint32_t)0x00000007) /* SMP0[2:0] bits (Channel 0 Sample time selection) */
-#define ADC_SMP0_0 ((uint32_t)0x00000001) /* Bit 0 */
-#define ADC_SMP0_1 ((uint32_t)0x00000002) /* Bit 1 */
-#define ADC_SMP0_2 ((uint32_t)0x00000004) /* Bit 2 */
-
-#define ADC_SMP1 ((uint32_t)0x00000038) /* SMP1[2:0] bits (Channel 1 Sample time selection) */
-#define ADC_SMP1_0 ((uint32_t)0x00000008) /* Bit 0 */
-#define ADC_SMP1_1 ((uint32_t)0x00000010) /* Bit 1 */
-#define ADC_SMP1_2 ((uint32_t)0x00000020) /* Bit 2 */
-
-#define ADC_SMP2 ((uint32_t)0x000001C0) /* SMP2[2:0] bits (Channel 2 Sample time selection) */
-#define ADC_SMP2_0 ((uint32_t)0x00000040) /* Bit 0 */
-#define ADC_SMP2_1 ((uint32_t)0x00000080) /* Bit 1 */
-#define ADC_SMP2_2 ((uint32_t)0x00000100) /* Bit 2 */
-
-#define ADC_SMP3 ((uint32_t)0x00000E00) /* SMP3[2:0] bits (Channel 3 Sample time selection) */
-#define ADC_SMP3_0 ((uint32_t)0x00000200) /* Bit 0 */
-#define ADC_SMP3_1 ((uint32_t)0x00000400) /* Bit 1 */
-#define ADC_SMP3_2 ((uint32_t)0x00000800) /* Bit 2 */
-
-#define ADC_SMP4 ((uint32_t)0x00007000) /* SMP4[2:0] bits (Channel 4 Sample time selection) */
-#define ADC_SMP4_0 ((uint32_t)0x00001000) /* Bit 0 */
-#define ADC_SMP4_1 ((uint32_t)0x00002000) /* Bit 1 */
-#define ADC_SMP4_2 ((uint32_t)0x00004000) /* Bit 2 */
-
-#define ADC_SMP5 ((uint32_t)0x00038000) /* SMP5[2:0] bits (Channel 5 Sample time selection) */
-#define ADC_SMP5_0 ((uint32_t)0x00008000) /* Bit 0 */
-#define ADC_SMP5_1 ((uint32_t)0x00010000) /* Bit 1 */
-#define ADC_SMP5_2 ((uint32_t)0x00020000) /* Bit 2 */
-
-#define ADC_SMP6 ((uint32_t)0x001C0000) /* SMP6[2:0] bits (Channel 6 Sample time selection) */
-#define ADC_SMP6_0 ((uint32_t)0x00040000) /* Bit 0 */
-#define ADC_SMP6_1 ((uint32_t)0x00080000) /* Bit 1 */
-#define ADC_SMP6_2 ((uint32_t)0x00100000) /* Bit 2 */
-
-#define ADC_SMP7 ((uint32_t)0x00E00000) /* SMP7[2:0] bits (Channel 7 Sample time selection) */
-#define ADC_SMP7_0 ((uint32_t)0x00200000) /* Bit 0 */
-#define ADC_SMP7_1 ((uint32_t)0x00400000) /* Bit 1 */
-#define ADC_SMP7_2 ((uint32_t)0x00800000) /* Bit 2 */
-
-#define ADC_SMP8 ((uint32_t)0x07000000) /* SMP8[2:0] bits (Channel 8 Sample time selection) */
-#define ADC_SMP8_0 ((uint32_t)0x01000000) /* Bit 0 */
-#define ADC_SMP8_1 ((uint32_t)0x02000000) /* Bit 1 */
-#define ADC_SMP8_2 ((uint32_t)0x04000000) /* Bit 2 */
-
-#define ADC_SMP9 ((uint32_t)0x38000000) /* SMP9[2:0] bits (Channel 9 Sample time selection) */
-#define ADC_SMP9_0 ((uint32_t)0x08000000) /* Bit 0 */
-#define ADC_SMP9_1 ((uint32_t)0x10000000) /* Bit 1 */
-#define ADC_SMP9_2 ((uint32_t)0x20000000) /* Bit 2 */
-
-/****************** Bit definition for ADC_IOFR1 register *******************/
-#define ADC_JOFFSET1 ((uint16_t)0x0FFF) /* Data offset for injected channel 1 */
-
-/****************** Bit definition for ADC_IOFR2 register *******************/
-#define ADC_JOFFSET2 ((uint16_t)0x0FFF) /* Data offset for injected channel 2 */
-
-/****************** Bit definition for ADC_IOFR3 register *******************/
-#define ADC_JOFFSET3 ((uint16_t)0x0FFF) /* Data offset for injected channel 3 */
-
-/****************** Bit definition for ADC_IOFR4 register *******************/
-#define ADC_JOFFSET4 ((uint16_t)0x0FFF) /* Data offset for injected channel 4 */
-
-/******************* Bit definition for ADC_WDHTR register ********************/
-#define ADC_HT ((uint16_t)0x0FFF) /* Analog watchdog high threshold */
-
-/******************* Bit definition for ADC_WDLTR register ********************/
-#define ADC_LT ((uint16_t)0x0FFF) /* Analog watchdog low threshold */
-
-/******************* Bit definition for ADC_RSQR1 register *******************/
-#define ADC_SQ13 ((uint32_t)0x0000001F) /* SQ13[4:0] bits (13th conversion in regular sequence) */
-#define ADC_SQ13_0 ((uint32_t)0x00000001) /* Bit 0 */
-#define ADC_SQ13_1 ((uint32_t)0x00000002) /* Bit 1 */
-#define ADC_SQ13_2 ((uint32_t)0x00000004) /* Bit 2 */
-#define ADC_SQ13_3 ((uint32_t)0x00000008) /* Bit 3 */
-#define ADC_SQ13_4 ((uint32_t)0x00000010) /* Bit 4 */
-
-#define ADC_SQ14 ((uint32_t)0x000003E0) /* SQ14[4:0] bits (14th conversion in regular sequence) */
-#define ADC_SQ14_0 ((uint32_t)0x00000020) /* Bit 0 */
-#define ADC_SQ14_1 ((uint32_t)0x00000040) /* Bit 1 */
-#define ADC_SQ14_2 ((uint32_t)0x00000080) /* Bit 2 */
-#define ADC_SQ14_3 ((uint32_t)0x00000100) /* Bit 3 */
-#define ADC_SQ14_4 ((uint32_t)0x00000200) /* Bit 4 */
-
-#define ADC_SQ15 ((uint32_t)0x00007C00) /* SQ15[4:0] bits (15th conversion in regular sequence) */
-#define ADC_SQ15_0 ((uint32_t)0x00000400) /* Bit 0 */
-#define ADC_SQ15_1 ((uint32_t)0x00000800) /* Bit 1 */
-#define ADC_SQ15_2 ((uint32_t)0x00001000) /* Bit 2 */
-#define ADC_SQ15_3 ((uint32_t)0x00002000) /* Bit 3 */
-#define ADC_SQ15_4 ((uint32_t)0x00004000) /* Bit 4 */
-
-#define ADC_SQ16 ((uint32_t)0x000F8000) /* SQ16[4:0] bits (16th conversion in regular sequence) */
-#define ADC_SQ16_0 ((uint32_t)0x00008000) /* Bit 0 */
-#define ADC_SQ16_1 ((uint32_t)0x00010000) /* Bit 1 */
-#define ADC_SQ16_2 ((uint32_t)0x00020000) /* Bit 2 */
-#define ADC_SQ16_3 ((uint32_t)0x00040000) /* Bit 3 */
-#define ADC_SQ16_4 ((uint32_t)0x00080000) /* Bit 4 */
-
-#define ADC_L ((uint32_t)0x00F00000) /* L[3:0] bits (Regular channel sequence length) */
-#define ADC_L_0 ((uint32_t)0x00100000) /* Bit 0 */
-#define ADC_L_1 ((uint32_t)0x00200000) /* Bit 1 */
-#define ADC_L_2 ((uint32_t)0x00400000) /* Bit 2 */
-#define ADC_L_3 ((uint32_t)0x00800000) /* Bit 3 */
-
-/******************* Bit definition for ADC_RSQR2 register *******************/
-#define ADC_SQ7 ((uint32_t)0x0000001F) /* SQ7[4:0] bits (7th conversion in regular sequence) */
-#define ADC_SQ7_0 ((uint32_t)0x00000001) /* Bit 0 */
-#define ADC_SQ7_1 ((uint32_t)0x00000002) /* Bit 1 */
-#define ADC_SQ7_2 ((uint32_t)0x00000004) /* Bit 2 */
-#define ADC_SQ7_3 ((uint32_t)0x00000008) /* Bit 3 */
-#define ADC_SQ7_4 ((uint32_t)0x00000010) /* Bit 4 */
-
-#define ADC_SQ8 ((uint32_t)0x000003E0) /* SQ8[4:0] bits (8th conversion in regular sequence) */
-#define ADC_SQ8_0 ((uint32_t)0x00000020) /* Bit 0 */
-#define ADC_SQ8_1 ((uint32_t)0x00000040) /* Bit 1 */
-#define ADC_SQ8_2 ((uint32_t)0x00000080) /* Bit 2 */
-#define ADC_SQ8_3 ((uint32_t)0x00000100) /* Bit 3 */
-#define ADC_SQ8_4 ((uint32_t)0x00000200) /* Bit 4 */
-
-#define ADC_SQ9 ((uint32_t)0x00007C00) /* SQ9[4:0] bits (9th conversion in regular sequence) */
-#define ADC_SQ9_0 ((uint32_t)0x00000400) /* Bit 0 */
-#define ADC_SQ9_1 ((uint32_t)0x00000800) /* Bit 1 */
-#define ADC_SQ9_2 ((uint32_t)0x00001000) /* Bit 2 */
-#define ADC_SQ9_3 ((uint32_t)0x00002000) /* Bit 3 */
-#define ADC_SQ9_4 ((uint32_t)0x00004000) /* Bit 4 */
-
-#define ADC_SQ10 ((uint32_t)0x000F8000) /* SQ10[4:0] bits (10th conversion in regular sequence) */
-#define ADC_SQ10_0 ((uint32_t)0x00008000) /* Bit 0 */
-#define ADC_SQ10_1 ((uint32_t)0x00010000) /* Bit 1 */
-#define ADC_SQ10_2 ((uint32_t)0x00020000) /* Bit 2 */
-#define ADC_SQ10_3 ((uint32_t)0x00040000) /* Bit 3 */
-#define ADC_SQ10_4 ((uint32_t)0x00080000) /* Bit 4 */
-
-#define ADC_SQ11 ((uint32_t)0x01F00000) /* SQ11[4:0] bits (11th conversion in regular sequence) */
-#define ADC_SQ11_0 ((uint32_t)0x00100000) /* Bit 0 */
-#define ADC_SQ11_1 ((uint32_t)0x00200000) /* Bit 1 */
-#define ADC_SQ11_2 ((uint32_t)0x00400000) /* Bit 2 */
-#define ADC_SQ11_3 ((uint32_t)0x00800000) /* Bit 3 */
-#define ADC_SQ11_4 ((uint32_t)0x01000000) /* Bit 4 */
-
-#define ADC_SQ12 ((uint32_t)0x3E000000) /* SQ12[4:0] bits (12th conversion in regular sequence) */
-#define ADC_SQ12_0 ((uint32_t)0x02000000) /* Bit 0 */
-#define ADC_SQ12_1 ((uint32_t)0x04000000) /* Bit 1 */
-#define ADC_SQ12_2 ((uint32_t)0x08000000) /* Bit 2 */
-#define ADC_SQ12_3 ((uint32_t)0x10000000) /* Bit 3 */
-#define ADC_SQ12_4 ((uint32_t)0x20000000) /* Bit 4 */
-
-/******************* Bit definition for ADC_RSQR3 register *******************/
-#define ADC_SQ1 ((uint32_t)0x0000001F) /* SQ1[4:0] bits (1st conversion in regular sequence) */
-#define ADC_SQ1_0 ((uint32_t)0x00000001) /* Bit 0 */
-#define ADC_SQ1_1 ((uint32_t)0x00000002) /* Bit 1 */
-#define ADC_SQ1_2 ((uint32_t)0x00000004) /* Bit 2 */
-#define ADC_SQ1_3 ((uint32_t)0x00000008) /* Bit 3 */
-#define ADC_SQ1_4 ((uint32_t)0x00000010) /* Bit 4 */
-
-#define ADC_SQ2 ((uint32_t)0x000003E0) /* SQ2[4:0] bits (2nd conversion in regular sequence) */
-#define ADC_SQ2_0 ((uint32_t)0x00000020) /* Bit 0 */
-#define ADC_SQ2_1 ((uint32_t)0x00000040) /* Bit 1 */
-#define ADC_SQ2_2 ((uint32_t)0x00000080) /* Bit 2 */
-#define ADC_SQ2_3 ((uint32_t)0x00000100) /* Bit 3 */
-#define ADC_SQ2_4 ((uint32_t)0x00000200) /* Bit 4 */
-
-#define ADC_SQ3 ((uint32_t)0x00007C00) /* SQ3[4:0] bits (3rd conversion in regular sequence) */
-#define ADC_SQ3_0 ((uint32_t)0x00000400) /* Bit 0 */
-#define ADC_SQ3_1 ((uint32_t)0x00000800) /* Bit 1 */
-#define ADC_SQ3_2 ((uint32_t)0x00001000) /* Bit 2 */
-#define ADC_SQ3_3 ((uint32_t)0x00002000) /* Bit 3 */
-#define ADC_SQ3_4 ((uint32_t)0x00004000) /* Bit 4 */
-
-#define ADC_SQ4 ((uint32_t)0x000F8000) /* SQ4[4:0] bits (4th conversion in regular sequence) */
-#define ADC_SQ4_0 ((uint32_t)0x00008000) /* Bit 0 */
-#define ADC_SQ4_1 ((uint32_t)0x00010000) /* Bit 1 */
-#define ADC_SQ4_2 ((uint32_t)0x00020000) /* Bit 2 */
-#define ADC_SQ4_3 ((uint32_t)0x00040000) /* Bit 3 */
-#define ADC_SQ4_4 ((uint32_t)0x00080000) /* Bit 4 */
-
-#define ADC_SQ5 ((uint32_t)0x01F00000) /* SQ5[4:0] bits (5th conversion in regular sequence) */
-#define ADC_SQ5_0 ((uint32_t)0x00100000) /* Bit 0 */
-#define ADC_SQ5_1 ((uint32_t)0x00200000) /* Bit 1 */
-#define ADC_SQ5_2 ((uint32_t)0x00400000) /* Bit 2 */
-#define ADC_SQ5_3 ((uint32_t)0x00800000) /* Bit 3 */
-#define ADC_SQ5_4 ((uint32_t)0x01000000) /* Bit 4 */
-
-#define ADC_SQ6 ((uint32_t)0x3E000000) /* SQ6[4:0] bits (6th conversion in regular sequence) */
-#define ADC_SQ6_0 ((uint32_t)0x02000000) /* Bit 0 */
-#define ADC_SQ6_1 ((uint32_t)0x04000000) /* Bit 1 */
-#define ADC_SQ6_2 ((uint32_t)0x08000000) /* Bit 2 */
-#define ADC_SQ6_3 ((uint32_t)0x10000000) /* Bit 3 */
-#define ADC_SQ6_4 ((uint32_t)0x20000000) /* Bit 4 */
-
-/******************* Bit definition for ADC_ISQR register *******************/
-#define ADC_JSQ1 ((uint32_t)0x0000001F) /* JSQ1[4:0] bits (1st conversion in injected sequence) */
-#define ADC_JSQ1_0 ((uint32_t)0x00000001) /* Bit 0 */
-#define ADC_JSQ1_1 ((uint32_t)0x00000002) /* Bit 1 */
-#define ADC_JSQ1_2 ((uint32_t)0x00000004) /* Bit 2 */
-#define ADC_JSQ1_3 ((uint32_t)0x00000008) /* Bit 3 */
-#define ADC_JSQ1_4 ((uint32_t)0x00000010) /* Bit 4 */
-
-#define ADC_JSQ2 ((uint32_t)0x000003E0) /* JSQ2[4:0] bits (2nd conversion in injected sequence) */
-#define ADC_JSQ2_0 ((uint32_t)0x00000020) /* Bit 0 */
-#define ADC_JSQ2_1 ((uint32_t)0x00000040) /* Bit 1 */
-#define ADC_JSQ2_2 ((uint32_t)0x00000080) /* Bit 2 */
-#define ADC_JSQ2_3 ((uint32_t)0x00000100) /* Bit 3 */
-#define ADC_JSQ2_4 ((uint32_t)0x00000200) /* Bit 4 */
-
-#define ADC_JSQ3 ((uint32_t)0x00007C00) /* JSQ3[4:0] bits (3rd conversion in injected sequence) */
-#define ADC_JSQ3_0 ((uint32_t)0x00000400) /* Bit 0 */
-#define ADC_JSQ3_1 ((uint32_t)0x00000800) /* Bit 1 */
-#define ADC_JSQ3_2 ((uint32_t)0x00001000) /* Bit 2 */
-#define ADC_JSQ3_3 ((uint32_t)0x00002000) /* Bit 3 */
-#define ADC_JSQ3_4 ((uint32_t)0x00004000) /* Bit 4 */
-
-#define ADC_JSQ4 ((uint32_t)0x000F8000) /* JSQ4[4:0] bits (4th conversion in injected sequence) */
-#define ADC_JSQ4_0 ((uint32_t)0x00008000) /* Bit 0 */
-#define ADC_JSQ4_1 ((uint32_t)0x00010000) /* Bit 1 */
-#define ADC_JSQ4_2 ((uint32_t)0x00020000) /* Bit 2 */
-#define ADC_JSQ4_3 ((uint32_t)0x00040000) /* Bit 3 */
-#define ADC_JSQ4_4 ((uint32_t)0x00080000) /* Bit 4 */
-
-#define ADC_JL ((uint32_t)0x00300000) /* JL[1:0] bits (Injected Sequence length) */
-#define ADC_JL_0 ((uint32_t)0x00100000) /* Bit 0 */
-#define ADC_JL_1 ((uint32_t)0x00200000) /* Bit 1 */
-
-/******************* Bit definition for ADC_IDATAR1 register *******************/
-#define ADC_IDATAR1_JDATA ((uint16_t)0xFFFF) /* Injected data */
-
-/******************* Bit definition for ADC_IDATAR2 register *******************/
-#define ADC_IDATAR2_JDATA ((uint16_t)0xFFFF) /* Injected data */
-
-/******************* Bit definition for ADC_IDATAR3 register *******************/
-#define ADC_IDATAR3_JDATA ((uint16_t)0xFFFF) /* Injected data */
-
-/******************* Bit definition for ADC_IDATAR4 register *******************/
-#define ADC_IDATAR4_JDATA ((uint16_t)0xFFFF) /* Injected data */
-
-/******************** Bit definition for ADC_RDATAR register ********************/
-#define ADC_RDATAR_DATA ((uint32_t)0x0000FFFF) /* Regular data */
-#define ADC_RDATAR_ADC2DATA ((uint32_t)0xFFFF0000) /* ADC2 data */
-
-/******************************************************************************/
-/* DMA Controller */
-/******************************************************************************/
-
-/******************* Bit definition for DMA_INTFR register ********************/
-#define DMA_GIF1 ((uint32_t)0x00000001) /* Channel 1 Global interrupt flag */
-#define DMA_TCIF1 ((uint32_t)0x00000002) /* Channel 1 Transfer Complete flag */
-#define DMA_HTIF1 ((uint32_t)0x00000004) /* Channel 1 Half Transfer flag */
-#define DMA_TEIF1 ((uint32_t)0x00000008) /* Channel 1 Transfer Error flag */
-#define DMA_GIF2 ((uint32_t)0x00000010) /* Channel 2 Global interrupt flag */
-#define DMA_TCIF2 ((uint32_t)0x00000020) /* Channel 2 Transfer Complete flag */
-#define DMA_HTIF2 ((uint32_t)0x00000040) /* Channel 2 Half Transfer flag */
-#define DMA_TEIF2 ((uint32_t)0x00000080) /* Channel 2 Transfer Error flag */
-#define DMA_GIF3 ((uint32_t)0x00000100) /* Channel 3 Global interrupt flag */
-#define DMA_TCIF3 ((uint32_t)0x00000200) /* Channel 3 Transfer Complete flag */
-#define DMA_HTIF3 ((uint32_t)0x00000400) /* Channel 3 Half Transfer flag */
-#define DMA_TEIF3 ((uint32_t)0x00000800) /* Channel 3 Transfer Error flag */
-#define DMA_GIF4 ((uint32_t)0x00001000) /* Channel 4 Global interrupt flag */
-#define DMA_TCIF4 ((uint32_t)0x00002000) /* Channel 4 Transfer Complete flag */
-#define DMA_HTIF4 ((uint32_t)0x00004000) /* Channel 4 Half Transfer flag */
-#define DMA_TEIF4 ((uint32_t)0x00008000) /* Channel 4 Transfer Error flag */
-#define DMA_GIF5 ((uint32_t)0x00010000) /* Channel 5 Global interrupt flag */
-#define DMA_TCIF5 ((uint32_t)0x00020000) /* Channel 5 Transfer Complete flag */
-#define DMA_HTIF5 ((uint32_t)0x00040000) /* Channel 5 Half Transfer flag */
-#define DMA_TEIF5 ((uint32_t)0x00080000) /* Channel 5 Transfer Error flag */
-#define DMA_GIF6 ((uint32_t)0x00100000) /* Channel 6 Global interrupt flag */
-#define DMA_TCIF6 ((uint32_t)0x00200000) /* Channel 6 Transfer Complete flag */
-#define DMA_HTIF6 ((uint32_t)0x00400000) /* Channel 6 Half Transfer flag */
-#define DMA_TEIF6 ((uint32_t)0x00800000) /* Channel 6 Transfer Error flag */
-#define DMA_GIF7 ((uint32_t)0x01000000) /* Channel 7 Global interrupt flag */
-#define DMA_TCIF7 ((uint32_t)0x02000000) /* Channel 7 Transfer Complete flag */
-#define DMA_HTIF7 ((uint32_t)0x04000000) /* Channel 7 Half Transfer flag */
-#define DMA_TEIF7 ((uint32_t)0x08000000) /* Channel 7 Transfer Error flag */
-
-/******************* Bit definition for DMA_INTFCR register *******************/
-#define DMA_CGIF1 ((uint32_t)0x00000001) /* Channel 1 Global interrupt clear */
-#define DMA_CTCIF1 ((uint32_t)0x00000002) /* Channel 1 Transfer Complete clear */
-#define DMA_CHTIF1 ((uint32_t)0x00000004) /* Channel 1 Half Transfer clear */
-#define DMA_CTEIF1 ((uint32_t)0x00000008) /* Channel 1 Transfer Error clear */
-#define DMA_CGIF2 ((uint32_t)0x00000010) /* Channel 2 Global interrupt clear */
-#define DMA_CTCIF2 ((uint32_t)0x00000020) /* Channel 2 Transfer Complete clear */
-#define DMA_CHTIF2 ((uint32_t)0x00000040) /* Channel 2 Half Transfer clear */
-#define DMA_CTEIF2 ((uint32_t)0x00000080) /* Channel 2 Transfer Error clear */
-#define DMA_CGIF3 ((uint32_t)0x00000100) /* Channel 3 Global interrupt clear */
-#define DMA_CTCIF3 ((uint32_t)0x00000200) /* Channel 3 Transfer Complete clear */
-#define DMA_CHTIF3 ((uint32_t)0x00000400) /* Channel 3 Half Transfer clear */
-#define DMA_CTEIF3 ((uint32_t)0x00000800) /* Channel 3 Transfer Error clear */
-#define DMA_CGIF4 ((uint32_t)0x00001000) /* Channel 4 Global interrupt clear */
-#define DMA_CTCIF4 ((uint32_t)0x00002000) /* Channel 4 Transfer Complete clear */
-#define DMA_CHTIF4 ((uint32_t)0x00004000) /* Channel 4 Half Transfer clear */
-#define DMA_CTEIF4 ((uint32_t)0x00008000) /* Channel 4 Transfer Error clear */
-#define DMA_CGIF5 ((uint32_t)0x00010000) /* Channel 5 Global interrupt clear */
-#define DMA_CTCIF5 ((uint32_t)0x00020000) /* Channel 5 Transfer Complete clear */
-#define DMA_CHTIF5 ((uint32_t)0x00040000) /* Channel 5 Half Transfer clear */
-#define DMA_CTEIF5 ((uint32_t)0x00080000) /* Channel 5 Transfer Error clear */
-#define DMA_CGIF6 ((uint32_t)0x00100000) /* Channel 6 Global interrupt clear */
-#define DMA_CTCIF6 ((uint32_t)0x00200000) /* Channel 6 Transfer Complete clear */
-#define DMA_CHTIF6 ((uint32_t)0x00400000) /* Channel 6 Half Transfer clear */
-#define DMA_CTEIF6 ((uint32_t)0x00800000) /* Channel 6 Transfer Error clear */
-#define DMA_CGIF7 ((uint32_t)0x01000000) /* Channel 7 Global interrupt clear */
-#define DMA_CTCIF7 ((uint32_t)0x02000000) /* Channel 7 Transfer Complete clear */
-#define DMA_CHTIF7 ((uint32_t)0x04000000) /* Channel 7 Half Transfer clear */
-#define DMA_CTEIF7 ((uint32_t)0x08000000) /* Channel 7 Transfer Error clear */
-
-/******************* Bit definition for DMA_CFGR1 register *******************/
-#define DMA_CFGR1_EN ((uint16_t)0x0001) /* Channel enable*/
-#define DMA_CFGR1_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */
-#define DMA_CFGR1_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */
-#define DMA_CFGR1_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */
-#define DMA_CFGR1_DIR ((uint16_t)0x0010) /* Data transfer direction */
-#define DMA_CFGR1_CIRC ((uint16_t)0x0020) /* Circular mode */
-#define DMA_CFGR1_PINC ((uint16_t)0x0040) /* Peripheral increment mode */
-#define DMA_CFGR1_MINC ((uint16_t)0x0080) /* Memory increment mode */
-
-#define DMA_CFGR1_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */
-#define DMA_CFGR1_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */
-#define DMA_CFGR1_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */
-
-#define DMA_CFGR1_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */
-#define DMA_CFGR1_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */
-#define DMA_CFGR1_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */
-
-#define DMA_CFGR1_PL ((uint16_t)0x3000) /* PL[1:0] bits(Channel Priority level) */
-#define DMA_CFGR1_PL_0 ((uint16_t)0x1000) /* Bit 0 */
-#define DMA_CFGR1_PL_1 ((uint16_t)0x2000) /* Bit 1 */
-
-#define DMA_CFGR1_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */
-
-/******************* Bit definition for DMA_CFGR2 register *******************/
-#define DMA_CFGR2_EN ((uint16_t)0x0001) /* Channel enable */
-#define DMA_CFGR2_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */
-#define DMA_CFGR2_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */
-#define DMA_CFGR2_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */
-#define DMA_CFGR2_DIR ((uint16_t)0x0010) /* Data transfer direction */
-#define DMA_CFGR2_CIRC ((uint16_t)0x0020) /* Circular mode */
-#define DMA_CFGR2_PINC ((uint16_t)0x0040) /* Peripheral increment mode */
-#define DMA_CFGR2_MINC ((uint16_t)0x0080) /* Memory increment mode */
-
-#define DMA_CFGR2_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */
-#define DMA_CFGR2_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */
-#define DMA_CFGR2_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */
-
-#define DMA_CFGR2_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */
-#define DMA_CFGR2_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */
-#define DMA_CFGR2_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */
-
-#define DMA_CFGR2_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */
-#define DMA_CFGR2_PL_0 ((uint16_t)0x1000) /* Bit 0 */
-#define DMA_CFGR2_PL_1 ((uint16_t)0x2000) /* Bit 1 */
-
-#define DMA_CFGR2_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */
-
-/******************* Bit definition for DMA_CFGR3 register *******************/
-#define DMA_CFGR3_EN ((uint16_t)0x0001) /* Channel enable */
-#define DMA_CFGR3_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */
-#define DMA_CFGR3_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */
-#define DMA_CFGR3_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */
-#define DMA_CFGR3_DIR ((uint16_t)0x0010) /* Data transfer direction */
-#define DMA_CFGR3_CIRC ((uint16_t)0x0020) /* Circular mode */
-#define DMA_CFGR3_PINC ((uint16_t)0x0040) /* Peripheral increment mode */
-#define DMA_CFGR3_MINC ((uint16_t)0x0080) /* Memory increment mode */
-
-#define DMA_CFGR3_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */
-#define DMA_CFGR3_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */
-#define DMA_CFGR3_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */
-
-#define DMA_CFGR3_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */
-#define DMA_CFGR3_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */
-#define DMA_CFGR3_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */
-
-#define DMA_CFGR3_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */
-#define DMA_CFGR3_PL_0 ((uint16_t)0x1000) /* Bit 0 */
-#define DMA_CFGR3_PL_1 ((uint16_t)0x2000) /* Bit 1 */
-
-#define DMA_CFGR3_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */
-
-/******************* Bit definition for DMA_CFG4 register *******************/
-#define DMA_CFG4_EN ((uint16_t)0x0001) /* Channel enable */
-#define DMA_CFG4_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */
-#define DMA_CFG4_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */
-#define DMA_CFG4_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */
-#define DMA_CFG4_DIR ((uint16_t)0x0010) /* Data transfer direction */
-#define DMA_CFG4_CIRC ((uint16_t)0x0020) /* Circular mode */
-#define DMA_CFG4_PINC ((uint16_t)0x0040) /* Peripheral increment mode */
-#define DMA_CFG4_MINC ((uint16_t)0x0080) /* Memory increment mode */
-
-#define DMA_CFG4_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */
-#define DMA_CFG4_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */
-#define DMA_CFG4_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */
-
-#define DMA_CFG4_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */
-#define DMA_CFG4_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */
-#define DMA_CFG4_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */
-
-#define DMA_CFG4_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */
-#define DMA_CFG4_PL_0 ((uint16_t)0x1000) /* Bit 0 */
-#define DMA_CFG4_PL_1 ((uint16_t)0x2000) /* Bit 1 */
-
-#define DMA_CFG4_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */
-
-/****************** Bit definition for DMA_CFG5 register *******************/
-#define DMA_CFG5_EN ((uint16_t)0x0001) /* Channel enable */
-#define DMA_CFG5_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */
-#define DMA_CFG5_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */
-#define DMA_CFG5_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */
-#define DMA_CFG5_DIR ((uint16_t)0x0010) /* Data transfer direction */
-#define DMA_CFG5_CIRC ((uint16_t)0x0020) /* Circular mode */
-#define DMA_CFG5_PINC ((uint16_t)0x0040) /* Peripheral increment mode */
-#define DMA_CFG5_MINC ((uint16_t)0x0080) /* Memory increment mode */
-
-#define DMA_CFG5_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */
-#define DMA_CFG5_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */
-#define DMA_CFG5_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */
-
-#define DMA_CFG5_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */
-#define DMA_CFG5_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */
-#define DMA_CFG5_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */
-
-#define DMA_CFG5_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */
-#define DMA_CFG5_PL_0 ((uint16_t)0x1000) /* Bit 0 */
-#define DMA_CFG5_PL_1 ((uint16_t)0x2000) /* Bit 1 */
-
-#define DMA_CFG5_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode enable */
-
-/******************* Bit definition for DMA_CFG6 register *******************/
-#define DMA_CFG6_EN ((uint16_t)0x0001) /* Channel enable */
-#define DMA_CFG6_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */
-#define DMA_CFG6_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */
-#define DMA_CFG6_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */
-#define DMA_CFG6_DIR ((uint16_t)0x0010) /* Data transfer direction */
-#define DMA_CFG6_CIRC ((uint16_t)0x0020) /* Circular mode */
-#define DMA_CFG6_PINC ((uint16_t)0x0040) /* Peripheral increment mode */
-#define DMA_CFG6_MINC ((uint16_t)0x0080) /* Memory increment mode */
-
-#define DMA_CFG6_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */
-#define DMA_CFG6_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */
-#define DMA_CFG6_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */
-
-#define DMA_CFG6_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */
-#define DMA_CFG6_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */
-#define DMA_CFG6_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */
-
-#define DMA_CFG6_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */
-#define DMA_CFG6_PL_0 ((uint16_t)0x1000) /* Bit 0 */
-#define DMA_CFG6_PL_1 ((uint16_t)0x2000) /* Bit 1 */
-
-#define DMA_CFG6_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */
-
-/******************* Bit definition for DMA_CFG7 register *******************/
-#define DMA_CFG7_EN ((uint16_t)0x0001) /* Channel enable */
-#define DMA_CFG7_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */
-#define DMA_CFG7_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */
-#define DMA_CFG7_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */
-#define DMA_CFG7_DIR ((uint16_t)0x0010) /* Data transfer direction */
-#define DMA_CFG7_CIRC ((uint16_t)0x0020) /* Circular mode */
-#define DMA_CFG7_PINC ((uint16_t)0x0040) /* Peripheral increment mode */
-#define DMA_CFG7_MINC ((uint16_t)0x0080) /* Memory increment mode */
-
-#define DMA_CFG7_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */
-#define DMA_CFG7_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */
-#define DMA_CFG7_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */
-
-#define DMA_CFG7_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */
-#define DMA_CFG7_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */
-#define DMA_CFG7_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */
-
-#define DMA_CFG7_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */
-#define DMA_CFG7_PL_0 ((uint16_t)0x1000) /* Bit 0 */
-#define DMA_CFG7_PL_1 ((uint16_t)0x2000) /* Bit 1 */
-
-#define DMA_CFG7_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode enable */
-
-/****************** Bit definition for DMA_CNTR1 register ******************/
-#define DMA_CNTR1_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */
-
-/****************** Bit definition for DMA_CNTR2 register ******************/
-#define DMA_CNTR2_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */
-
-/****************** Bit definition for DMA_CNTR3 register ******************/
-#define DMA_CNTR3_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */
-
-/****************** Bit definition for DMA_CNTR4 register ******************/
-#define DMA_CNTR4_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */
-
-/****************** Bit definition for DMA_CNTR5 register ******************/
-#define DMA_CNTR5_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */
-
-/****************** Bit definition for DMA_CNTR6 register ******************/
-#define DMA_CNTR6_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */
-
-/****************** Bit definition for DMA_CNTR7 register ******************/
-#define DMA_CNTR7_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */
-
-/****************** Bit definition for DMA_PADDR1 register *******************/
-#define DMA_PADDR1_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */
-
-/****************** Bit definition for DMA_PADDR2 register *******************/
-#define DMA_PADDR2_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */
-
-/****************** Bit definition for DMA_PADDR3 register *******************/
-#define DMA_PADDR3_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */
-
-/****************** Bit definition for DMA_PADDR4 register *******************/
-#define DMA_PADDR4_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */
-
-/****************** Bit definition for DMA_PADDR5 register *******************/
-#define DMA_PADDR5_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */
-
-/****************** Bit definition for DMA_PADDR6 register *******************/
-#define DMA_PADDR6_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */
-
-/****************** Bit definition for DMA_PADDR7 register *******************/
-#define DMA_PADDR7_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */
-
-/****************** Bit definition for DMA_MADDR1 register *******************/
-#define DMA_MADDR1_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */
-
-/****************** Bit definition for DMA_MADDR2 register *******************/
-#define DMA_MADDR2_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */
-
-/****************** Bit definition for DMA_MADDR3 register *******************/
-#define DMA_MADDR3_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */
-
-/****************** Bit definition for DMA_MADDR4 register *******************/
-#define DMA_MADDR4_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */
-
-/****************** Bit definition for DMA_MADDR5 register *******************/
-#define DMA_MADDR5_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */
-
-/****************** Bit definition for DMA_MADDR6 register *******************/
-#define DMA_MADDR6_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */
-
-/****************** Bit definition for DMA_MADDR7 register *******************/
-#define DMA_MADDR7_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */
-
-/******************************************************************************/
-/* External Interrupt/Event Controller */
-/******************************************************************************/
-
-/******************* Bit definition for EXTI_INTENR register *******************/
-#define EXTI_INTENR_MR0 ((uint32_t)0x00000001) /* Interrupt Mask on line 0 */
-#define EXTI_INTENR_MR1 ((uint32_t)0x00000002) /* Interrupt Mask on line 1 */
-#define EXTI_INTENR_MR2 ((uint32_t)0x00000004) /* Interrupt Mask on line 2 */
-#define EXTI_INTENR_MR3 ((uint32_t)0x00000008) /* Interrupt Mask on line 3 */
-#define EXTI_INTENR_MR4 ((uint32_t)0x00000010) /* Interrupt Mask on line 4 */
-#define EXTI_INTENR_MR5 ((uint32_t)0x00000020) /* Interrupt Mask on line 5 */
-#define EXTI_INTENR_MR6 ((uint32_t)0x00000040) /* Interrupt Mask on line 6 */
-#define EXTI_INTENR_MR7 ((uint32_t)0x00000080) /* Interrupt Mask on line 7 */
-#define EXTI_INTENR_MR8 ((uint32_t)0x00000100) /* Interrupt Mask on line 8 */
-#define EXTI_INTENR_MR9 ((uint32_t)0x00000200) /* Interrupt Mask on line 9 */
-
-/******************* Bit definition for EXTI_EVENR register *******************/
-#define EXTI_EVENR_MR0 ((uint32_t)0x00000001) /* Event Mask on line 0 */
-#define EXTI_EVENR_MR1 ((uint32_t)0x00000002) /* Event Mask on line 1 */
-#define EXTI_EVENR_MR2 ((uint32_t)0x00000004) /* Event Mask on line 2 */
-#define EXTI_EVENR_MR3 ((uint32_t)0x00000008) /* Event Mask on line 3 */
-#define EXTI_EVENR_MR4 ((uint32_t)0x00000010) /* Event Mask on line 4 */
-#define EXTI_EVENR_MR5 ((uint32_t)0x00000020) /* Event Mask on line 5 */
-#define EXTI_EVENR_MR6 ((uint32_t)0x00000040) /* Event Mask on line 6 */
-#define EXTI_EVENR_MR7 ((uint32_t)0x00000080) /* Event Mask on line 7 */
-#define EXTI_EVENR_MR8 ((uint32_t)0x00000100) /* Event Mask on line 8 */
-#define EXTI_EVENR_MR9 ((uint32_t)0x00000200) /* Event Mask on line 9 */
-
-/****************** Bit definition for EXTI_RTENR register *******************/
-#define EXTI_RTENR_TR0 ((uint32_t)0x00000001) /* Rising trigger event configuration bit of line 0 */
-#define EXTI_RTENR_TR1 ((uint32_t)0x00000002) /* Rising trigger event configuration bit of line 1 */
-#define EXTI_RTENR_TR2 ((uint32_t)0x00000004) /* Rising trigger event configuration bit of line 2 */
-#define EXTI_RTENR_TR3 ((uint32_t)0x00000008) /* Rising trigger event configuration bit of line 3 */
-#define EXTI_RTENR_TR4 ((uint32_t)0x00000010) /* Rising trigger event configuration bit of line 4 */
-#define EXTI_RTENR_TR5 ((uint32_t)0x00000020) /* Rising trigger event configuration bit of line 5 */
-#define EXTI_RTENR_TR6 ((uint32_t)0x00000040) /* Rising trigger event configuration bit of line 6 */
-#define EXTI_RTENR_TR7 ((uint32_t)0x00000080) /* Rising trigger event configuration bit of line 7 */
-#define EXTI_RTENR_TR8 ((uint32_t)0x00000100) /* Rising trigger event configuration bit of line 8 */
-#define EXTI_RTENR_TR9 ((uint32_t)0x00000200) /* Rising trigger event configuration bit of line 9 */
-
-/****************** Bit definition for EXTI_FTENR register *******************/
-#define EXTI_FTENR_TR0 ((uint32_t)0x00000001) /* Falling trigger event configuration bit of line 0 */
-#define EXTI_FTENR_TR1 ((uint32_t)0x00000002) /* Falling trigger event configuration bit of line 1 */
-#define EXTI_FTENR_TR2 ((uint32_t)0x00000004) /* Falling trigger event configuration bit of line 2 */
-#define EXTI_FTENR_TR3 ((uint32_t)0x00000008) /* Falling trigger event configuration bit of line 3 */
-#define EXTI_FTENR_TR4 ((uint32_t)0x00000010) /* Falling trigger event configuration bit of line 4 */
-#define EXTI_FTENR_TR5 ((uint32_t)0x00000020) /* Falling trigger event configuration bit of line 5 */
-#define EXTI_FTENR_TR6 ((uint32_t)0x00000040) /* Falling trigger event configuration bit of line 6 */
-#define EXTI_FTENR_TR7 ((uint32_t)0x00000080) /* Falling trigger event configuration bit of line 7 */
-#define EXTI_FTENR_TR8 ((uint32_t)0x00000100) /* Falling trigger event configuration bit of line 8 */
-#define EXTI_FTENR_TR9 ((uint32_t)0x00000200) /* Falling trigger event configuration bit of line 9 */
-
-/****************** Bit definition for EXTI_SWIEVR register ******************/
-#define EXTI_SWIEVR_SWIEVR0 ((uint32_t)0x00000001) /* Software Interrupt on line 0 */
-#define EXTI_SWIEVR_SWIEVR1 ((uint32_t)0x00000002) /* Software Interrupt on line 1 */
-#define EXTI_SWIEVR_SWIEVR2 ((uint32_t)0x00000004) /* Software Interrupt on line 2 */
-#define EXTI_SWIEVR_SWIEVR3 ((uint32_t)0x00000008) /* Software Interrupt on line 3 */
-#define EXTI_SWIEVR_SWIEVR4 ((uint32_t)0x00000010) /* Software Interrupt on line 4 */
-#define EXTI_SWIEVR_SWIEVR5 ((uint32_t)0x00000020) /* Software Interrupt on line 5 */
-#define EXTI_SWIEVR_SWIEVR6 ((uint32_t)0x00000040) /* Software Interrupt on line 6 */
-#define EXTI_SWIEVR_SWIEVR7 ((uint32_t)0x00000080) /* Software Interrupt on line 7 */
-#define EXTI_SWIEVR_SWIEVR8 ((uint32_t)0x00000100) /* Software Interrupt on line 8 */
-#define EXTI_SWIEVR_SWIEVR9 ((uint32_t)0x00000200) /* Software Interrupt on line 9 */
-
-/******************* Bit definition for EXTI_INTFR register ********************/
-#define EXTI_INTF_INTF0 ((uint32_t)0x00000001) /* Pending bit for line 0 */
-#define EXTI_INTF_INTF1 ((uint32_t)0x00000002) /* Pending bit for line 1 */
-#define EXTI_INTF_INTF2 ((uint32_t)0x00000004) /* Pending bit for line 2 */
-#define EXTI_INTF_INTF3 ((uint32_t)0x00000008) /* Pending bit for line 3 */
-#define EXTI_INTF_INTF4 ((uint32_t)0x00000010) /* Pending bit for line 4 */
-#define EXTI_INTF_INTF5 ((uint32_t)0x00000020) /* Pending bit for line 5 */
-#define EXTI_INTF_INTF6 ((uint32_t)0x00000040) /* Pending bit for line 6 */
-#define EXTI_INTF_INTF7 ((uint32_t)0x00000080) /* Pending bit for line 7 */
-#define EXTI_INTF_INTF8 ((uint32_t)0x00000100) /* Pending bit for line 8 */
-#define EXTI_INTF_INTF9 ((uint32_t)0x00000200) /* Pending bit for line 9 */
-
-/******************************************************************************/
-/* FLASH and Option Bytes Registers */
-/******************************************************************************/
-
-/******************* Bit definition for FLASH_ACTLR register ******************/
-#define FLASH_ACTLR_LATENCY ((uint8_t)0x03) /* LATENCY[2:0] bits (Latency) */
-#define FLASH_ACTLR_LATENCY_0 ((uint8_t)0x00) /* Bit 0 */
-#define FLASH_ACTLR_LATENCY_1 ((uint8_t)0x01) /* Bit 0 */
-#define FLASH_ACTLR_LATENCY_2 ((uint8_t)0x02) /* Bit 1 */
-
-/****************** Bit definition for FLASH_KEYR register ******************/
-#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /* FPEC Key */
-
-/***************** Bit definition for FLASH_OBKEYR register ****************/
-#define FLASH_OBKEYR_OBKEYR ((uint32_t)0xFFFFFFFF) /* Option Byte Key */
-
-/****************** Bit definition for FLASH_STATR register *******************/
-#define FLASH_STATR_BSY ((uint8_t)0x01) /* Busy */
-#define FLASH_STATR_WRPRTERR ((uint8_t)0x10) /* Write Protection Error */
-#define FLASH_STATR_EOP ((uint8_t)0x20) /* End of operation */
-
-/******************* Bit definition for FLASH_CTLR register *******************/
-#define FLASH_CTLR_PG ((uint16_t)0x0001) /* Programming */
-#define FLASH_CTLR_PER ((uint16_t)0x0002) /* Page Erase 1KByte*/
-#define FLASH_CTLR_MER ((uint16_t)0x0004) /* Mass Erase */
-#define FLASH_CTLR_OPTPG ((uint16_t)0x0010) /* Option Byte Programming */
-#define FLASH_CTLR_OPTER ((uint16_t)0x0020) /* Option Byte Erase */
-#define FLASH_CTLR_STRT ((uint16_t)0x0040) /* Start */
-#define FLASH_CTLR_LOCK ((uint16_t)0x0080) /* Lock */
-#define FLASH_CTLR_OPTWRE ((uint16_t)0x0200) /* Option Bytes Write Enable */
-#define FLASH_CTLR_ERRIE ((uint16_t)0x0400) /* Error Interrupt Enable */
-#define FLASH_CTLR_EOPIE ((uint16_t)0x1000) /* End of operation interrupt enable */
-#define FLASH_CTLR_PAGE_PG ((uint16_t)0x00010000) /* Page Programming 64Byte */
-#define FLASH_CTLR_PAGE_ER ((uint16_t)0x00020000) /* Page Erase 64Byte */
-#define FLASH_CTLR_BUF_LOAD ((uint16_t)0x00040000) /* Buffer Load */
-#define FLASH_CTLR_BUF_RST ((uint16_t)0x00080000) /* Buffer Reset */
-
-/******************* Bit definition for FLASH_ADDR register *******************/
-#define FLASH_ADDR_FAR ((uint32_t)0xFFFFFFFF) /* Flash Address */
-
-/****************** Bit definition for FLASH_OBR register *******************/
-#define FLASH_OBR_OPTERR ((uint16_t)0x0001) /* Option Byte Error */
-#define FLASH_OBR_RDPRT ((uint16_t)0x0002) /* Read protection */
-
-#define FLASH_OBR_USER ((uint16_t)0x03FC) /* User Option Bytes */
-#define FLASH_OBR_WDG_SW ((uint16_t)0x0004) /* WDG_SW */
-#define FLASH_OBR_nRST_STOP ((uint16_t)0x0008) /* nRST_STOP */
-#define FLASH_OBR_nRST_STDBY ((uint16_t)0x0010) /* nRST_STDBY */
-#define FLASH_OBR_RST_MODE ((uint16_t)0x0060) /* RST_MODE */
-
-/****************** Bit definition for FLASH_WPR register ******************/
-#define FLASH_WPR_WRP ((uint32_t)0xFFFFFFFF) /* Write Protect */
-
-/****************** Bit definition for FLASH_RDPR register *******************/
-#define FLASH_RDPR_RDPR ((uint32_t)0x000000FF) /* Read protection option byte */
-#define FLASH_RDPR_nRDPR ((uint32_t)0x0000FF00) /* Read protection complemented option byte */
-
-/****************** Bit definition for FLASH_USER register ******************/
-#define FLASH_USER_USER ((uint32_t)0x00FF0000) /* User option byte */
-#define FLASH_USER_nUSER ((uint32_t)0xFF000000) /* User complemented option byte */
-
-/****************** Bit definition for FLASH_Data0 register *****************/
-#define FLASH_Data0_Data0 ((uint32_t)0x000000FF) /* User data storage option byte */
-#define FLASH_Data0_nData0 ((uint32_t)0x0000FF00) /* User data storage complemented option byte */
-
-/****************** Bit definition for FLASH_Data1 register *****************/
-#define FLASH_Data1_Data1 ((uint32_t)0x00FF0000) /* User data storage option byte */
-#define FLASH_Data1_nData1 ((uint32_t)0xFF000000) /* User data storage complemented option byte */
-
-/****************** Bit definition for FLASH_WRPR0 register ******************/
-#define FLASH_WRPR0_WRPR0 ((uint32_t)0x000000FF) /* Flash memory write protection option bytes */
-#define FLASH_WRPR0_nWRPR0 ((uint32_t)0x0000FF00) /* Flash memory write protection complemented option bytes */
-
-/****************** Bit definition for FLASH_WRPR1 register ******************/
-#define FLASH_WRPR1_WRPR1 ((uint32_t)0x00FF0000) /* Flash memory write protection option bytes */
-#define FLASH_WRPR1_nWRPR1 ((uint32_t)0xFF000000) /* Flash memory write protection complemented option bytes */
-
-
-/******************************************************************************/
-/* General Purpose and Alternate Function I/O */
-/******************************************************************************/
-
-/******************* Bit definition for GPIO_CFGLR register *******************/
-#define GPIO_CFGLR_MODE ((uint32_t)0x33333333) /* Port x mode bits */
-
-#define GPIO_CFGLR_MODE0 ((uint32_t)0x00000003) /* MODE0[1:0] bits (Port x mode bits, pin 0) */
-#define GPIO_CFGLR_MODE0_0 ((uint32_t)0x00000001) /* Bit 0 */
-#define GPIO_CFGLR_MODE0_1 ((uint32_t)0x00000002) /* Bit 1 */
-
-#define GPIO_CFGLR_MODE1 ((uint32_t)0x00000030) /* MODE1[1:0] bits (Port x mode bits, pin 1) */
-#define GPIO_CFGLR_MODE1_0 ((uint32_t)0x00000010) /* Bit 0 */
-#define GPIO_CFGLR_MODE1_1 ((uint32_t)0x00000020) /* Bit 1 */
-
-#define GPIO_CFGLR_MODE2 ((uint32_t)0x00000300) /* MODE2[1:0] bits (Port x mode bits, pin 2) */
-#define GPIO_CFGLR_MODE2_0 ((uint32_t)0x00000100) /* Bit 0 */
-#define GPIO_CFGLR_MODE2_1 ((uint32_t)0x00000200) /* Bit 1 */
-
-#define GPIO_CFGLR_MODE3 ((uint32_t)0x00003000) /* MODE3[1:0] bits (Port x mode bits, pin 3) */
-#define GPIO_CFGLR_MODE3_0 ((uint32_t)0x00001000) /* Bit 0 */
-#define GPIO_CFGLR_MODE3_1 ((uint32_t)0x00002000) /* Bit 1 */
-
-#define GPIO_CFGLR_MODE4 ((uint32_t)0x00030000) /* MODE4[1:0] bits (Port x mode bits, pin 4) */
-#define GPIO_CFGLR_MODE4_0 ((uint32_t)0x00010000) /* Bit 0 */
-#define GPIO_CFGLR_MODE4_1 ((uint32_t)0x00020000) /* Bit 1 */
-
-#define GPIO_CFGLR_MODE5 ((uint32_t)0x00300000) /* MODE5[1:0] bits (Port x mode bits, pin 5) */
-#define GPIO_CFGLR_MODE5_0 ((uint32_t)0x00100000) /* Bit 0 */
-#define GPIO_CFGLR_MODE5_1 ((uint32_t)0x00200000) /* Bit 1 */
-
-#define GPIO_CFGLR_MODE6 ((uint32_t)0x03000000) /* MODE6[1:0] bits (Port x mode bits, pin 6) */
-#define GPIO_CFGLR_MODE6_0 ((uint32_t)0x01000000) /* Bit 0 */
-#define GPIO_CFGLR_MODE6_1 ((uint32_t)0x02000000) /* Bit 1 */
-
-#define GPIO_CFGLR_MODE7 ((uint32_t)0x30000000) /* MODE7[1:0] bits (Port x mode bits, pin 7) */
-#define GPIO_CFGLR_MODE7_0 ((uint32_t)0x10000000) /* Bit 0 */
-#define GPIO_CFGLR_MODE7_1 ((uint32_t)0x20000000) /* Bit 1 */
-
-#define GPIO_CFGLR_CNF ((uint32_t)0xCCCCCCCC) /* Port x configuration bits */
-
-#define GPIO_CFGLR_CNF0 ((uint32_t)0x0000000C) /* CNF0[1:0] bits (Port x configuration bits, pin 0) */
-#define GPIO_CFGLR_CNF0_0 ((uint32_t)0x00000004) /* Bit 0 */
-#define GPIO_CFGLR_CNF0_1 ((uint32_t)0x00000008) /* Bit 1 */
-
-#define GPIO_CFGLR_CNF1 ((uint32_t)0x000000C0) /* CNF1[1:0] bits (Port x configuration bits, pin 1) */
-#define GPIO_CFGLR_CNF1_0 ((uint32_t)0x00000040) /* Bit 0 */
-#define GPIO_CFGLR_CNF1_1 ((uint32_t)0x00000080) /* Bit 1 */
-
-#define GPIO_CFGLR_CNF2 ((uint32_t)0x00000C00) /* CNF2[1:0] bits (Port x configuration bits, pin 2) */
-#define GPIO_CFGLR_CNF2_0 ((uint32_t)0x00000400) /* Bit 0 */
-#define GPIO_CFGLR_CNF2_1 ((uint32_t)0x00000800) /* Bit 1 */
-
-#define GPIO_CFGLR_CNF3 ((uint32_t)0x0000C000) /* CNF3[1:0] bits (Port x configuration bits, pin 3) */
-#define GPIO_CFGLR_CNF3_0 ((uint32_t)0x00004000) /* Bit 0 */
-#define GPIO_CFGLR_CNF3_1 ((uint32_t)0x00008000) /* Bit 1 */
-
-#define GPIO_CFGLR_CNF4 ((uint32_t)0x000C0000) /* CNF4[1:0] bits (Port x configuration bits, pin 4) */
-#define GPIO_CFGLR_CNF4_0 ((uint32_t)0x00040000) /* Bit 0 */
-#define GPIO_CFGLR_CNF4_1 ((uint32_t)0x00080000) /* Bit 1 */
-
-#define GPIO_CFGLR_CNF5 ((uint32_t)0x00C00000) /* CNF5[1:0] bits (Port x configuration bits, pin 5) */
-#define GPIO_CFGLR_CNF5_0 ((uint32_t)0x00400000) /* Bit 0 */
-#define GPIO_CFGLR_CNF5_1 ((uint32_t)0x00800000) /* Bit 1 */
-
-#define GPIO_CFGLR_CNF6 ((uint32_t)0x0C000000) /* CNF6[1:0] bits (Port x configuration bits, pin 6) */
-#define GPIO_CFGLR_CNF6_0 ((uint32_t)0x04000000) /* Bit 0 */
-#define GPIO_CFGLR_CNF6_1 ((uint32_t)0x08000000) /* Bit 1 */
-
-#define GPIO_CFGLR_CNF7 ((uint32_t)0xC0000000) /* CNF7[1:0] bits (Port x configuration bits, pin 7) */
-#define GPIO_CFGLR_CNF7_0 ((uint32_t)0x40000000) /* Bit 0 */
-#define GPIO_CFGLR_CNF7_1 ((uint32_t)0x80000000) /* Bit 1 */
-
-/******************* Bit definition for GPIO_CFGHR register *******************/
-#define GPIO_CFGHR_MODE ((uint32_t)0x33333333) /* Port x mode bits */
-
-#define GPIO_CFGHR_MODE8 ((uint32_t)0x00000003) /* MODE8[1:0] bits (Port x mode bits, pin 8) */
-#define GPIO_CFGHR_MODE8_0 ((uint32_t)0x00000001) /* Bit 0 */
-#define GPIO_CFGHR_MODE8_1 ((uint32_t)0x00000002) /* Bit 1 */
-
-#define GPIO_CFGHR_MODE9 ((uint32_t)0x00000030) /* MODE9[1:0] bits (Port x mode bits, pin 9) */
-#define GPIO_CFGHR_MODE9_0 ((uint32_t)0x00000010) /* Bit 0 */
-#define GPIO_CFGHR_MODE9_1 ((uint32_t)0x00000020) /* Bit 1 */
-
-#define GPIO_CFGHR_MODE10 ((uint32_t)0x00000300) /* MODE10[1:0] bits (Port x mode bits, pin 10) */
-#define GPIO_CFGHR_MODE10_0 ((uint32_t)0x00000100) /* Bit 0 */
-#define GPIO_CFGHR_MODE10_1 ((uint32_t)0x00000200) /* Bit 1 */
-
-#define GPIO_CFGHR_MODE11 ((uint32_t)0x00003000) /* MODE11[1:0] bits (Port x mode bits, pin 11) */
-#define GPIO_CFGHR_MODE11_0 ((uint32_t)0x00001000) /* Bit 0 */
-#define GPIO_CFGHR_MODE11_1 ((uint32_t)0x00002000) /* Bit 1 */
-
-#define GPIO_CFGHR_MODE12 ((uint32_t)0x00030000) /* MODE12[1:0] bits (Port x mode bits, pin 12) */
-#define GPIO_CFGHR_MODE12_0 ((uint32_t)0x00010000) /* Bit 0 */
-#define GPIO_CFGHR_MODE12_1 ((uint32_t)0x00020000) /* Bit 1 */
-
-#define GPIO_CFGHR_MODE13 ((uint32_t)0x00300000) /* MODE13[1:0] bits (Port x mode bits, pin 13) */
-#define GPIO_CFGHR_MODE13_0 ((uint32_t)0x00100000) /* Bit 0 */
-#define GPIO_CFGHR_MODE13_1 ((uint32_t)0x00200000) /* Bit 1 */
-
-#define GPIO_CFGHR_MODE14 ((uint32_t)0x03000000) /* MODE14[1:0] bits (Port x mode bits, pin 14) */
-#define GPIO_CFGHR_MODE14_0 ((uint32_t)0x01000000) /* Bit 0 */
-#define GPIO_CFGHR_MODE14_1 ((uint32_t)0x02000000) /* Bit 1 */
-
-#define GPIO_CFGHR_MODE15 ((uint32_t)0x30000000) /* MODE15[1:0] bits (Port x mode bits, pin 15) */
-#define GPIO_CFGHR_MODE15_0 ((uint32_t)0x10000000) /* Bit 0 */
-#define GPIO_CFGHR_MODE15_1 ((uint32_t)0x20000000) /* Bit 1 */
-
-#define GPIO_CFGHR_CNF ((uint32_t)0xCCCCCCCC) /* Port x configuration bits */
-
-#define GPIO_CFGHR_CNF8 ((uint32_t)0x0000000C) /* CNF8[1:0] bits (Port x configuration bits, pin 8) */
-#define GPIO_CFGHR_CNF8_0 ((uint32_t)0x00000004) /* Bit 0 */
-#define GPIO_CFGHR_CNF8_1 ((uint32_t)0x00000008) /* Bit 1 */
-
-#define GPIO_CFGHR_CNF9 ((uint32_t)0x000000C0) /* CNF9[1:0] bits (Port x configuration bits, pin 9) */
-#define GPIO_CFGHR_CNF9_0 ((uint32_t)0x00000040) /* Bit 0 */
-#define GPIO_CFGHR_CNF9_1 ((uint32_t)0x00000080) /* Bit 1 */
-
-#define GPIO_CFGHR_CNF10 ((uint32_t)0x00000C00) /* CNF10[1:0] bits (Port x configuration bits, pin 10) */
-#define GPIO_CFGHR_CNF10_0 ((uint32_t)0x00000400) /* Bit 0 */
-#define GPIO_CFGHR_CNF10_1 ((uint32_t)0x00000800) /* Bit 1 */
-
-#define GPIO_CFGHR_CNF11 ((uint32_t)0x0000C000) /* CNF11[1:0] bits (Port x configuration bits, pin 11) */
-#define GPIO_CFGHR_CNF11_0 ((uint32_t)0x00004000) /* Bit 0 */
-#define GPIO_CFGHR_CNF11_1 ((uint32_t)0x00008000) /* Bit 1 */
-
-#define GPIO_CFGHR_CNF12 ((uint32_t)0x000C0000) /* CNF12[1:0] bits (Port x configuration bits, pin 12) */
-#define GPIO_CFGHR_CNF12_0 ((uint32_t)0x00040000) /* Bit 0 */
-#define GPIO_CFGHR_CNF12_1 ((uint32_t)0x00080000) /* Bit 1 */
-
-#define GPIO_CFGHR_CNF13 ((uint32_t)0x00C00000) /* CNF13[1:0] bits (Port x configuration bits, pin 13) */
-#define GPIO_CFGHR_CNF13_0 ((uint32_t)0x00400000) /* Bit 0 */
-#define GPIO_CFGHR_CNF13_1 ((uint32_t)0x00800000) /* Bit 1 */
-
-#define GPIO_CFGHR_CNF14 ((uint32_t)0x0C000000) /* CNF14[1:0] bits (Port x configuration bits, pin 14) */
-#define GPIO_CFGHR_CNF14_0 ((uint32_t)0x04000000) /* Bit 0 */
-#define GPIO_CFGHR_CNF14_1 ((uint32_t)0x08000000) /* Bit 1 */
-
-#define GPIO_CFGHR_CNF15 ((uint32_t)0xC0000000) /* CNF15[1:0] bits (Port x configuration bits, pin 15) */
-#define GPIO_CFGHR_CNF15_0 ((uint32_t)0x40000000) /* Bit 0 */
-#define GPIO_CFGHR_CNF15_1 ((uint32_t)0x80000000) /* Bit 1 */
-
-/******************* Bit definition for GPIO_INDR register *******************/
-#define GPIO_INDR_IDR0 ((uint16_t)0x0001) /* Port input data, bit 0 */
-#define GPIO_INDR_IDR1 ((uint16_t)0x0002) /* Port input data, bit 1 */
-#define GPIO_INDR_IDR2 ((uint16_t)0x0004) /* Port input data, bit 2 */
-#define GPIO_INDR_IDR3 ((uint16_t)0x0008) /* Port input data, bit 3 */
-#define GPIO_INDR_IDR4 ((uint16_t)0x0010) /* Port input data, bit 4 */
-#define GPIO_INDR_IDR5 ((uint16_t)0x0020) /* Port input data, bit 5 */
-#define GPIO_INDR_IDR6 ((uint16_t)0x0040) /* Port input data, bit 6 */
-#define GPIO_INDR_IDR7 ((uint16_t)0x0080) /* Port input data, bit 7 */
-#define GPIO_INDR_IDR8 ((uint16_t)0x0100) /* Port input data, bit 8 */
-#define GPIO_INDR_IDR9 ((uint16_t)0x0200) /* Port input data, bit 9 */
-#define GPIO_INDR_IDR10 ((uint16_t)0x0400) /* Port input data, bit 10 */
-#define GPIO_INDR_IDR11 ((uint16_t)0x0800) /* Port input data, bit 11 */
-#define GPIO_INDR_IDR12 ((uint16_t)0x1000) /* Port input data, bit 12 */
-#define GPIO_INDR_IDR13 ((uint16_t)0x2000) /* Port input data, bit 13 */
-#define GPIO_INDR_IDR14 ((uint16_t)0x4000) /* Port input data, bit 14 */
-#define GPIO_INDR_IDR15 ((uint16_t)0x8000) /* Port input data, bit 15 */
-
-/******************* Bit definition for GPIO_OUTDR register *******************/
-#define GPIO_OUTDR_ODR0 ((uint16_t)0x0001) /* Port output data, bit 0 */
-#define GPIO_OUTDR_ODR1 ((uint16_t)0x0002) /* Port output data, bit 1 */
-#define GPIO_OUTDR_ODR2 ((uint16_t)0x0004) /* Port output data, bit 2 */
-#define GPIO_OUTDR_ODR3 ((uint16_t)0x0008) /* Port output data, bit 3 */
-#define GPIO_OUTDR_ODR4 ((uint16_t)0x0010) /* Port output data, bit 4 */
-#define GPIO_OUTDR_ODR5 ((uint16_t)0x0020) /* Port output data, bit 5 */
-#define GPIO_OUTDR_ODR6 ((uint16_t)0x0040) /* Port output data, bit 6 */
-#define GPIO_OUTDR_ODR7 ((uint16_t)0x0080) /* Port output data, bit 7 */
-#define GPIO_OUTDR_ODR8 ((uint16_t)0x0100) /* Port output data, bit 8 */
-#define GPIO_OUTDR_ODR9 ((uint16_t)0x0200) /* Port output data, bit 9 */
-#define GPIO_OUTDR_ODR10 ((uint16_t)0x0400) /* Port output data, bit 10 */
-#define GPIO_OUTDR_ODR11 ((uint16_t)0x0800) /* Port output data, bit 11 */
-#define GPIO_OUTDR_ODR12 ((uint16_t)0x1000) /* Port output data, bit 12 */
-#define GPIO_OUTDR_ODR13 ((uint16_t)0x2000) /* Port output data, bit 13 */
-#define GPIO_OUTDR_ODR14 ((uint16_t)0x4000) /* Port output data, bit 14 */
-#define GPIO_OUTDR_ODR15 ((uint16_t)0x8000) /* Port output data, bit 15 */
-
-/****************** Bit definition for GPIO_BSHR register *******************/
-#define GPIO_BSHR_BS0 ((uint32_t)0x00000001) /* Port x Set bit 0 */
-#define GPIO_BSHR_BS1 ((uint32_t)0x00000002) /* Port x Set bit 1 */
-#define GPIO_BSHR_BS2 ((uint32_t)0x00000004) /* Port x Set bit 2 */
-#define GPIO_BSHR_BS3 ((uint32_t)0x00000008) /* Port x Set bit 3 */
-#define GPIO_BSHR_BS4 ((uint32_t)0x00000010) /* Port x Set bit 4 */
-#define GPIO_BSHR_BS5 ((uint32_t)0x00000020) /* Port x Set bit 5 */
-#define GPIO_BSHR_BS6 ((uint32_t)0x00000040) /* Port x Set bit 6 */
-#define GPIO_BSHR_BS7 ((uint32_t)0x00000080) /* Port x Set bit 7 */
-#define GPIO_BSHR_BS8 ((uint32_t)0x00000100) /* Port x Set bit 8 */
-#define GPIO_BSHR_BS9 ((uint32_t)0x00000200) /* Port x Set bit 9 */
-#define GPIO_BSHR_BS10 ((uint32_t)0x00000400) /* Port x Set bit 10 */
-#define GPIO_BSHR_BS11 ((uint32_t)0x00000800) /* Port x Set bit 11 */
-#define GPIO_BSHR_BS12 ((uint32_t)0x00001000) /* Port x Set bit 12 */
-#define GPIO_BSHR_BS13 ((uint32_t)0x00002000) /* Port x Set bit 13 */
-#define GPIO_BSHR_BS14 ((uint32_t)0x00004000) /* Port x Set bit 14 */
-#define GPIO_BSHR_BS15 ((uint32_t)0x00008000) /* Port x Set bit 15 */
-
-#define GPIO_BSHR_BR0 ((uint32_t)0x00010000) /* Port x Reset bit 0 */
-#define GPIO_BSHR_BR1 ((uint32_t)0x00020000) /* Port x Reset bit 1 */
-#define GPIO_BSHR_BR2 ((uint32_t)0x00040000) /* Port x Reset bit 2 */
-#define GPIO_BSHR_BR3 ((uint32_t)0x00080000) /* Port x Reset bit 3 */
-#define GPIO_BSHR_BR4 ((uint32_t)0x00100000) /* Port x Reset bit 4 */
-#define GPIO_BSHR_BR5 ((uint32_t)0x00200000) /* Port x Reset bit 5 */
-#define GPIO_BSHR_BR6 ((uint32_t)0x00400000) /* Port x Reset bit 6 */
-#define GPIO_BSHR_BR7 ((uint32_t)0x00800000) /* Port x Reset bit 7 */
-#define GPIO_BSHR_BR8 ((uint32_t)0x01000000) /* Port x Reset bit 8 */
-#define GPIO_BSHR_BR9 ((uint32_t)0x02000000) /* Port x Reset bit 9 */
-#define GPIO_BSHR_BR10 ((uint32_t)0x04000000) /* Port x Reset bit 10 */
-#define GPIO_BSHR_BR11 ((uint32_t)0x08000000) /* Port x Reset bit 11 */
-#define GPIO_BSHR_BR12 ((uint32_t)0x10000000) /* Port x Reset bit 12 */
-#define GPIO_BSHR_BR13 ((uint32_t)0x20000000) /* Port x Reset bit 13 */
-#define GPIO_BSHR_BR14 ((uint32_t)0x40000000) /* Port x Reset bit 14 */
-#define GPIO_BSHR_BR15 ((uint32_t)0x80000000) /* Port x Reset bit 15 */
-
-/******************* Bit definition for GPIO_BCR register *******************/
-#define GPIO_BCR_BR0 ((uint16_t)0x0001) /* Port x Reset bit 0 */
-#define GPIO_BCR_BR1 ((uint16_t)0x0002) /* Port x Reset bit 1 */
-#define GPIO_BCR_BR2 ((uint16_t)0x0004) /* Port x Reset bit 2 */
-#define GPIO_BCR_BR3 ((uint16_t)0x0008) /* Port x Reset bit 3 */
-#define GPIO_BCR_BR4 ((uint16_t)0x0010) /* Port x Reset bit 4 */
-#define GPIO_BCR_BR5 ((uint16_t)0x0020) /* Port x Reset bit 5 */
-#define GPIO_BCR_BR6 ((uint16_t)0x0040) /* Port x Reset bit 6 */
-#define GPIO_BCR_BR7 ((uint16_t)0x0080) /* Port x Reset bit 7 */
-#define GPIO_BCR_BR8 ((uint16_t)0x0100) /* Port x Reset bit 8 */
-#define GPIO_BCR_BR9 ((uint16_t)0x0200) /* Port x Reset bit 9 */
-#define GPIO_BCR_BR10 ((uint16_t)0x0400) /* Port x Reset bit 10 */
-#define GPIO_BCR_BR11 ((uint16_t)0x0800) /* Port x Reset bit 11 */
-#define GPIO_BCR_BR12 ((uint16_t)0x1000) /* Port x Reset bit 12 */
-#define GPIO_BCR_BR13 ((uint16_t)0x2000) /* Port x Reset bit 13 */
-#define GPIO_BCR_BR14 ((uint16_t)0x4000) /* Port x Reset bit 14 */
-#define GPIO_BCR_BR15 ((uint16_t)0x8000) /* Port x Reset bit 15 */
-
-/****************** Bit definition for GPIO_LCKR register *******************/
-#define GPIO_LCK0 ((uint32_t)0x00000001) /* Port x Lock bit 0 */
-#define GPIO_LCK1 ((uint32_t)0x00000002) /* Port x Lock bit 1 */
-#define GPIO_LCK2 ((uint32_t)0x00000004) /* Port x Lock bit 2 */
-#define GPIO_LCK3 ((uint32_t)0x00000008) /* Port x Lock bit 3 */
-#define GPIO_LCK4 ((uint32_t)0x00000010) /* Port x Lock bit 4 */
-#define GPIO_LCK5 ((uint32_t)0x00000020) /* Port x Lock bit 5 */
-#define GPIO_LCK6 ((uint32_t)0x00000040) /* Port x Lock bit 6 */
-#define GPIO_LCK7 ((uint32_t)0x00000080) /* Port x Lock bit 7 */
-#define GPIO_LCK8 ((uint32_t)0x00000100) /* Port x Lock bit 8 */
-#define GPIO_LCK9 ((uint32_t)0x00000200) /* Port x Lock bit 9 */
-#define GPIO_LCK10 ((uint32_t)0x00000400) /* Port x Lock bit 10 */
-#define GPIO_LCK11 ((uint32_t)0x00000800) /* Port x Lock bit 11 */
-#define GPIO_LCK12 ((uint32_t)0x00001000) /* Port x Lock bit 12 */
-#define GPIO_LCK13 ((uint32_t)0x00002000) /* Port x Lock bit 13 */
-#define GPIO_LCK14 ((uint32_t)0x00004000) /* Port x Lock bit 14 */
-#define GPIO_LCK15 ((uint32_t)0x00008000) /* Port x Lock bit 15 */
-#define GPIO_LCKK ((uint32_t)0x00010000) /* Lock key */
-
-/****************** Bit definition for AFIO_PCFR1register *******************/
-#define AFIO_PCFR1_SPI1_REMAP ((uint32_t)0x00000001) /* SPI1 remapping */
-#define AFIO_PCFR1_I2C1_REMAP ((uint32_t)0x00000002) /* I2C1 remapping */
-#define AFIO_PCFR1_USART1_REMAP ((uint32_t)0x00000004) /* USART1 remapping */
-#define AFIO_PCFR1_USART2_REMAP ((uint32_t)0x00000008) /* USART2 remapping */
-
-#define AFIO_PCFR1_USART3_REMAP ((uint32_t)0x00000030) /* USART3_REMAP[1:0] bits (USART3 remapping) */
-#define AFIO_PCFR1_USART3_REMAP_0 ((uint32_t)0x00000010) /* Bit 0 */
-#define AFIO_PCFR1_USART3_REMAP_1 ((uint32_t)0x00000020) /* Bit 1 */
-
-#define AFIO_PCFR1_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /* No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */
-#define AFIO_PCFR1_USART3_REMAP_PARTIALREMAP ((uint32_t)0x00000010) /* Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */
-#define AFIO_PCFR1_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030) /* Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */
-
-#define AFIO_PCFR1_TIM1_REMAP ((uint32_t)0x000000C0) /* TIM1_REMAP[1:0] bits (TIM1 remapping) */
-#define AFIO_PCFR1_TIM1_REMAP_0 ((uint32_t)0x00000040) /* Bit 0 */
-#define AFIO_PCFR1_TIM1_REMAP_1 ((uint32_t)0x00000080) /* Bit 1 */
-
-#define AFIO_PCFR1_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /* No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */
-#define AFIO_PCFR1_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) /* Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */
-#define AFIO_PCFR1_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) /* Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */
-
-#define AFIO_PCFR1_TIM2_REMAP ((uint32_t)0x00000300) /* TIM2_REMAP[1:0] bits (TIM2 remapping) */
-#define AFIO_PCFR1_TIM2_REMAP_0 ((uint32_t)0x00000100) /* Bit 0 */
-#define AFIO_PCFR1_TIM2_REMAP_1 ((uint32_t)0x00000200) /* Bit 1 */
-
-#define AFIO_PCFR1_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /* No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */
-#define AFIO_PCFR1_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) /* Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */
-#define AFIO_PCFR1_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) /* Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */
-#define AFIO_PCFR1_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) /* Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */
-
-#define AFIO_PCFR1_TIM3_REMAP ((uint32_t)0x00000C00) /* TIM3_REMAP[1:0] bits (TIM3 remapping) */
-#define AFIO_PCFR1_TIM3_REMAP_0 ((uint32_t)0x00000400) /* Bit 0 */
-#define AFIO_PCFR1_TIM3_REMAP_1 ((uint32_t)0x00000800) /* Bit 1 */
-
-#define AFIO_PCFR1_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /* No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */
-#define AFIO_PCFR1_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) /* Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */
-#define AFIO_PCFR1_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) /* Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */
-
-#define AFIO_PCFR1_TIM4_REMAP ((uint32_t)0x00001000) /* TIM4_REMAP bit (TIM4 remapping) */
-
-#define AFIO_PCFR1_CAN_REMAP ((uint32_t)0x00006000) /* CAN_REMAP[1:0] bits (CAN Alternate function remapping) */
-#define AFIO_PCFR1_CAN_REMAP_0 ((uint32_t)0x00002000) /* Bit 0 */
-#define AFIO_PCFR1_CAN_REMAP_1 ((uint32_t)0x00004000) /* Bit 1 */
-
-#define AFIO_PCFR1_CAN_REMAP_REMAP1 ((uint32_t)0x00000000) /* CANRX mapped to PA11, CANTX mapped to PA12 */
-#define AFIO_PCFR1_CAN_REMAP_REMAP2 ((uint32_t)0x00004000) /* CANRX mapped to PB8, CANTX mapped to PB9 */
-#define AFIO_PCFR1_CAN_REMAP_REMAP3 ((uint32_t)0x00006000) /* CANRX mapped to PD0, CANTX mapped to PD1 */
-
-#define AFIO_PCFR1_PA12_REMAP ((uint32_t)0x00008000) /* Port D0/Port D1 mapping on OSC_IN/OSC_OUT */
-#define AFIO_PCFR1_TIM5CH4_IREMAP ((uint32_t)0x00010000) /* TIM5 Channel4 Internal Remap */
-#define AFIO_PCFR1_ADC1_ETRGINJ_REMAP ((uint32_t)0x00020000) /* ADC 1 External Trigger Injected Conversion remapping */
-#define AFIO_PCFR1_ADC1_ETRGREG_REMAP ((uint32_t)0x00040000) /* ADC 1 External Trigger Regular Conversion remapping */
-#define AFIO_PCFR1_ADC2_ETRGINJ_REMAP ((uint32_t)0x00080000) /* ADC 2 External Trigger Injected Conversion remapping */
-#define AFIO_PCFR1_ADC2_ETRGREG_REMAP ((uint32_t)0x00100000) /* ADC 2 External Trigger Regular Conversion remapping */
-
-#define AFIO_PCFR1_SWJ_CFG ((uint32_t)0x07000000) /* SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */
-#define AFIO_PCFR1_SWJ_CFG_0 ((uint32_t)0x01000000) /* Bit 0 */
-#define AFIO_PCFR1_SWJ_CFG_1 ((uint32_t)0x02000000) /* Bit 1 */
-#define AFIO_PCFR1_SWJ_CFG_2 ((uint32_t)0x04000000) /* Bit 2 */
-
-#define AFIO_PCFR1_SWJ_CFG_RESET ((uint32_t)0x00000000) /* Full SWJ (JTAG-DP + SW-DP) : Reset State */
-#define AFIO_PCFR1_SWJ_CFG_NOJNTRST ((uint32_t)0x01000000) /* Full SWJ (JTAG-DP + SW-DP) but without JNTRST */
-#define AFIO_PCFR1_SWJ_CFG_JTAGDISABLE ((uint32_t)0x02000000) /* JTAG-DP Disabled and SW-DP Enabled */
-#define AFIO_PCFR1_SWJ_CFG_DISABLE ((uint32_t)0x04000000) /* JTAG-DP Disabled and SW-DP Disabled */
-
-/***************** Bit definition for AFIO_EXTICR1 register *****************/
-#define AFIO_EXTICR1_EXTI0 ((uint16_t)0x000F) /* EXTI 0 configuration */
-#define AFIO_EXTICR1_EXTI1 ((uint16_t)0x00F0) /* EXTI 1 configuration */
-#define AFIO_EXTICR1_EXTI2 ((uint16_t)0x0F00) /* EXTI 2 configuration */
-#define AFIO_EXTICR1_EXTI3 ((uint16_t)0xF000) /* EXTI 3 configuration */
-
-#define AFIO_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /* PA[0] pin */
-#define AFIO_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /* PB[0] pin */
-#define AFIO_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /* PC[0] pin */
-#define AFIO_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /* PD[0] pin */
-#define AFIO_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /* PE[0] pin */
-#define AFIO_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /* PF[0] pin */
-#define AFIO_EXTICR1_EXTI0_PG ((uint16_t)0x0006) /* PG[0] pin */
-
-#define AFIO_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /* PA[1] pin */
-#define AFIO_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /* PB[1] pin */
-#define AFIO_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /* PC[1] pin */
-#define AFIO_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /* PD[1] pin */
-#define AFIO_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /* PE[1] pin */
-#define AFIO_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /* PF[1] pin */
-#define AFIO_EXTICR1_EXTI1_PG ((uint16_t)0x0060) /* PG[1] pin */
-
-#define AFIO_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /* PA[2] pin */
-#define AFIO_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /* PB[2] pin */
-#define AFIO_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /* PC[2] pin */
-#define AFIO_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /* PD[2] pin */
-#define AFIO_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /* PE[2] pin */
-#define AFIO_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /* PF[2] pin */
-#define AFIO_EXTICR1_EXTI2_PG ((uint16_t)0x0600) /* PG[2] pin */
-
-#define AFIO_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /* PA[3] pin */
-#define AFIO_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /* PB[3] pin */
-#define AFIO_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /* PC[3] pin */
-#define AFIO_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /* PD[3] pin */
-#define AFIO_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /* PE[3] pin */
-#define AFIO_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /* PF[3] pin */
-#define AFIO_EXTICR1_EXTI3_PG ((uint16_t)0x6000) /* PG[3] pin */
-
-/******************************************************************************/
-/* Independent WATCHDOG */
-/******************************************************************************/
-
-/******************* Bit definition for IWDG_CTLR register ********************/
-#define IWDG_KEY ((uint16_t)0xFFFF) /* Key value (write only, read 0000h) */
-
-/******************* Bit definition for IWDG_PSCR register ********************/
-#define IWDG_PR ((uint8_t)0x07) /* PR[2:0] (Prescaler divider) */
-#define IWDG_PR_0 ((uint8_t)0x01) /* Bit 0 */
-#define IWDG_PR_1 ((uint8_t)0x02) /* Bit 1 */
-#define IWDG_PR_2 ((uint8_t)0x04) /* Bit 2 */
-
-/******************* Bit definition for IWDG_RLDR register *******************/
-#define IWDG_RL ((uint16_t)0x0FFF) /* Watchdog counter reload value */
-
-/******************* Bit definition for IWDG_STATR register ********************/
-#define IWDG_PVU ((uint8_t)0x01) /* Watchdog prescaler value update */
-#define IWDG_RVU ((uint8_t)0x02) /* Watchdog counter reload value update */
-
-/******************************************************************************/
-/* Inter-integrated Circuit Interface */
-/******************************************************************************/
-
-/******************* Bit definition for I2C_CTLR1 register ********************/
-#define I2C_CTLR1_PE ((uint16_t)0x0001) /* Peripheral Enable */
-#define I2C_CTLR1_SMBUS ((uint16_t)0x0002) /* SMBus Mode */
-#define I2C_CTLR1_SMBTYPE ((uint16_t)0x0008) /* SMBus Type */
-#define I2C_CTLR1_ENARP ((uint16_t)0x0010) /* ARP Enable */
-#define I2C_CTLR1_ENPEC ((uint16_t)0x0020) /* PEC Enable */
-#define I2C_CTLR1_ENGC ((uint16_t)0x0040) /* General Call Enable */
-#define I2C_CTLR1_NOSTRETCH ((uint16_t)0x0080) /* Clock Stretching Disable (Slave mode) */
-#define I2C_CTLR1_START ((uint16_t)0x0100) /* Start Generation */
-#define I2C_CTLR1_STOP ((uint16_t)0x0200) /* Stop Generation */
-#define I2C_CTLR1_ACK ((uint16_t)0x0400) /* Acknowledge Enable */
-#define I2C_CTLR1_POS ((uint16_t)0x0800) /* Acknowledge/PEC Position (for data reception) */
-#define I2C_CTLR1_PEC ((uint16_t)0x1000) /* Packet Error Checking */
-#define I2C_CTLR1_ALERT ((uint16_t)0x2000) /* SMBus Alert */
-#define I2C_CTLR1_SWRST ((uint16_t)0x8000) /* Software Reset */
-
-/******************* Bit definition for I2C_CTLR2 register ********************/
-#define I2C_CTLR2_FREQ ((uint16_t)0x003F) /* FREQ[5:0] bits (Peripheral Clock Frequency) */
-#define I2C_CTLR2_FREQ_0 ((uint16_t)0x0001) /* Bit 0 */
-#define I2C_CTLR2_FREQ_1 ((uint16_t)0x0002) /* Bit 1 */
-#define I2C_CTLR2_FREQ_2 ((uint16_t)0x0004) /* Bit 2 */
-#define I2C_CTLR2_FREQ_3 ((uint16_t)0x0008) /* Bit 3 */
-#define I2C_CTLR2_FREQ_4 ((uint16_t)0x0010) /* Bit 4 */
-#define I2C_CTLR2_FREQ_5 ((uint16_t)0x0020) /* Bit 5 */
-
-#define I2C_CTLR2_ITERREN ((uint16_t)0x0100) /* Error Interrupt Enable */
-#define I2C_CTLR2_ITEVTEN ((uint16_t)0x0200) /* Event Interrupt Enable */
-#define I2C_CTLR2_ITBUFEN ((uint16_t)0x0400) /* Buffer Interrupt Enable */
-#define I2C_CTLR2_DMAEN ((uint16_t)0x0800) /* DMA Requests Enable */
-#define I2C_CTLR2_LAST ((uint16_t)0x1000) /* DMA Last Transfer */
-
-/******************* Bit definition for I2C_OADDR1 register *******************/
-#define I2C_OADDR1_ADD1_7 ((uint16_t)0x00FE) /* Interface Address */
-#define I2C_OADDR1_ADD8_9 ((uint16_t)0x0300) /* Interface Address */
-
-#define I2C_OADDR1_ADD0 ((uint16_t)0x0001) /* Bit 0 */
-#define I2C_OADDR1_ADD1 ((uint16_t)0x0002) /* Bit 1 */
-#define I2C_OADDR1_ADD2 ((uint16_t)0x0004) /* Bit 2 */
-#define I2C_OADDR1_ADD3 ((uint16_t)0x0008) /* Bit 3 */
-#define I2C_OADDR1_ADD4 ((uint16_t)0x0010) /* Bit 4 */
-#define I2C_OADDR1_ADD5 ((uint16_t)0x0020) /* Bit 5 */
-#define I2C_OADDR1_ADD6 ((uint16_t)0x0040) /* Bit 6 */
-#define I2C_OADDR1_ADD7 ((uint16_t)0x0080) /* Bit 7 */
-#define I2C_OADDR1_ADD8 ((uint16_t)0x0100) /* Bit 8 */
-#define I2C_OADDR1_ADD9 ((uint16_t)0x0200) /* Bit 9 */
-
-#define I2C_OADDR1_ADDMODE ((uint16_t)0x8000) /* Addressing Mode (Slave mode) */
-
-/******************* Bit definition for I2C_OADDR2 register *******************/
-#define I2C_OADDR2_ENDUAL ((uint8_t)0x01) /* Dual addressing mode enable */
-#define I2C_OADDR2_ADD2 ((uint8_t)0xFE) /* Interface address */
-
-/******************** Bit definition for I2C_DATAR register ********************/
-#define I2C_DR_DATAR ((uint8_t)0xFF) /* 8-bit Data Register */
-
-/******************* Bit definition for I2C_STAR1 register ********************/
-#define I2C_STAR1_SB ((uint16_t)0x0001) /* Start Bit (Master mode) */
-#define I2C_STAR1_ADDR ((uint16_t)0x0002) /* Address sent (master mode)/matched (slave mode) */
-#define I2C_STAR1_BTF ((uint16_t)0x0004) /* Byte Transfer Finished */
-#define I2C_STAR1_ADD10 ((uint16_t)0x0008) /* 10-bit header sent (Master mode) */
-#define I2C_STAR1_STOPF ((uint16_t)0x0010) /* Stop detection (Slave mode) */
-#define I2C_STAR1_RXNE ((uint16_t)0x0040) /* Data Register not Empty (receivers) */
-#define I2C_STAR1_TXE ((uint16_t)0x0080) /* Data Register Empty (transmitters) */
-#define I2C_STAR1_BERR ((uint16_t)0x0100) /* Bus Error */
-#define I2C_STAR1_ARLO ((uint16_t)0x0200) /* Arbitration Lost (master mode) */
-#define I2C_STAR1_AF ((uint16_t)0x0400) /* Acknowledge Failure */
-#define I2C_STAR1_OVR ((uint16_t)0x0800) /* Overrun/Underrun */
-#define I2C_STAR1_PECERR ((uint16_t)0x1000) /* PEC Error in reception */
-#define I2C_STAR1_TIMEOUT ((uint16_t)0x4000) /* Timeout or Tlow Error */
-#define I2C_STAR1_SMBALERT ((uint16_t)0x8000) /* SMBus Alert */
-
-/******************* Bit definition for I2C_STAR2 register ********************/
-#define I2C_STAR2_MSL ((uint16_t)0x0001) /* Master/Slave */
-#define I2C_STAR2_BUSY ((uint16_t)0x0002) /* Bus Busy */
-#define I2C_STAR2_TRA ((uint16_t)0x0004) /* Transmitter/Receiver */
-#define I2C_STAR2_GENCALL ((uint16_t)0x0010) /* General Call Address (Slave mode) */
-#define I2C_STAR2_SMBDEFAULT ((uint16_t)0x0020) /* SMBus Device Default Address (Slave mode) */
-#define I2C_STAR2_SMBHOST ((uint16_t)0x0040) /* SMBus Host Header (Slave mode) */
-#define I2C_STAR2_DUALF ((uint16_t)0x0080) /* Dual Flag (Slave mode) */
-#define I2C_STAR2_PEC ((uint16_t)0xFF00) /* Packet Error Checking Register */
-
-/******************* Bit definition for I2C_CKCFGR register ********************/
-#define I2C_CKCFGR_CCR ((uint16_t)0x0FFF) /* Clock Control Register in Fast/Standard mode (Master mode) */
-#define I2C_CKCFGR_DUTY ((uint16_t)0x4000) /* Fast Mode Duty Cycle */
-#define I2C_CKCFGR_FS ((uint16_t)0x8000) /* I2C Master Mode Selection */
-
-/******************************************************************************/
-/* Power Control */
-/******************************************************************************/
-
-/******************** Bit definition for PWR_CTLR register ********************/
-#define PWR_CTLR_LPDS ((uint16_t)0x0001) /* Low-Power Deepsleep */
-#define PWR_CTLR_PDDS ((uint16_t)0x0002) /* Power Down Deepsleep */
-#define PWR_CTLR_CWUF ((uint16_t)0x0004) /* Clear Wakeup Flag */
-#define PWR_CTLR_CSBF ((uint16_t)0x0008) /* Clear Standby Flag */
-#define PWR_CTLR_PVDE ((uint16_t)0x0010) /* Power Voltage Detector Enable */
-
-#define PWR_CTLR_PLS ((uint16_t)0x00E0) /* PLS[2:0] bits (PVD Level Selection) */
-#define PWR_CTLR_PLS_0 ((uint16_t)0x0020) /* Bit 0 */
-#define PWR_CTLR_PLS_1 ((uint16_t)0x0040) /* Bit 1 */
-#define PWR_CTLR_PLS_2 ((uint16_t)0x0080) /* Bit 2 */
-
-#define PWR_CTLR_PLS_2V2 ((uint16_t)0x0000) /* PVD level 2.2V */
-#define PWR_CTLR_PLS_2V3 ((uint16_t)0x0020) /* PVD level 2.3V */
-#define PWR_CTLR_PLS_2V4 ((uint16_t)0x0040) /* PVD level 2.4V */
-#define PWR_CTLR_PLS_2V5 ((uint16_t)0x0060) /* PVD level 2.5V */
-#define PWR_CTLR_PLS_2V6 ((uint16_t)0x0080) /* PVD level 2.6V */
-#define PWR_CTLR_PLS_2V7 ((uint16_t)0x00A0) /* PVD level 2.7V */
-#define PWR_CTLR_PLS_2V8 ((uint16_t)0x00C0) /* PVD level 2.8V */
-#define PWR_CTLR_PLS_2V9 ((uint16_t)0x00E0) /* PVD level 2.9V */
-
-#define PWR_CTLR_DBP ((uint16_t)0x0100) /* Disable Backup Domain write protection */
-
-/******************* Bit definition for PWR_CSR register ********************/
-#define PWR_CSR_WUF ((uint16_t)0x0001) /* Wakeup Flag */
-#define PWR_CSR_SBF ((uint16_t)0x0002) /* Standby Flag */
-#define PWR_CSR_PVDO ((uint16_t)0x0004) /* PVD Output */
-#define PWR_CSR_EWUP ((uint16_t)0x0100) /* Enable WKUP pin */
-
-/******************************************************************************/
-/* Reset and Clock Control */
-/******************************************************************************/
-
-/******************** Bit definition for RCC_CTLR register ********************/
-#define RCC_HSION ((uint32_t)0x00000001) /* Internal High Speed clock enable */
-#define RCC_HSIRDY ((uint32_t)0x00000002) /* Internal High Speed clock ready flag */
-#define RCC_HSITRIM ((uint32_t)0x000000F8) /* Internal High Speed clock trimming */
-#define RCC_HSICAL ((uint32_t)0x0000FF00) /* Internal High Speed clock Calibration */
-#define RCC_HSEON ((uint32_t)0x00010000) /* External High Speed clock enable */
-#define RCC_HSERDY ((uint32_t)0x00020000) /* External High Speed clock ready flag */
-#define RCC_HSEBYP ((uint32_t)0x00040000) /* External High Speed clock Bypass */
-#define RCC_CSSON ((uint32_t)0x00080000) /* Clock Security System enable */
-#define RCC_PLLON ((uint32_t)0x01000000) /* PLL enable */
-#define RCC_PLLRDY ((uint32_t)0x02000000) /* PLL clock ready flag */
-
-/******************* Bit definition for RCC_CFGR0 register *******************/
-#define RCC_SW ((uint32_t)0x00000003) /* SW[1:0] bits (System clock Switch) */
-#define RCC_SW_0 ((uint32_t)0x00000001) /* Bit 0 */
-#define RCC_SW_1 ((uint32_t)0x00000002) /* Bit 1 */
-
-#define RCC_SW_HSI ((uint32_t)0x00000000) /* HSI selected as system clock */
-#define RCC_SW_HSE ((uint32_t)0x00000001) /* HSE selected as system clock */
-#define RCC_SW_PLL ((uint32_t)0x00000002) /* PLL selected as system clock */
-
-#define RCC_SWS ((uint32_t)0x0000000C) /* SWS[1:0] bits (System Clock Switch Status) */
-#define RCC_SWS_0 ((uint32_t)0x00000004) /* Bit 0 */
-#define RCC_SWS_1 ((uint32_t)0x00000008) /* Bit 1 */
-
-#define RCC_SWS_HSI ((uint32_t)0x00000000) /* HSI oscillator used as system clock */
-#define RCC_SWS_HSE ((uint32_t)0x00000004) /* HSE oscillator used as system clock */
-#define RCC_SWS_PLL ((uint32_t)0x00000008) /* PLL used as system clock */
-
-#define RCC_HPRE ((uint32_t)0x000000F0) /* HPRE[3:0] bits (AHB prescaler) */
-#define RCC_HPRE_0 ((uint32_t)0x00000010) /* Bit 0 */
-#define RCC_HPRE_1 ((uint32_t)0x00000020) /* Bit 1 */
-#define RCC_HPRE_2 ((uint32_t)0x00000040) /* Bit 2 */
-#define RCC_HPRE_3 ((uint32_t)0x00000080) /* Bit 3 */
-
-#define RCC_HPRE_DIV1 ((uint32_t)0x00000000) /* SYSCLK not divided */
-#define RCC_HPRE_DIV2 ((uint32_t)0x00000010) /* SYSCLK divided by 2 */
-#define RCC_HPRE_DIV3 ((uint32_t)0x00000020) /* SYSCLK divided by 3 */
-#define RCC_HPRE_DIV4 ((uint32_t)0x00000030) /* SYSCLK divided by 4 */
-#define RCC_HPRE_DIV5 ((uint32_t)0x00000040) /* SYSCLK divided by 5 */
-#define RCC_HPRE_DIV6 ((uint32_t)0x00000050) /* SYSCLK divided by 6 */
-#define RCC_HPRE_DIV7 ((uint32_t)0x00000060) /* SYSCLK divided by 7 */
-#define RCC_HPRE_DIV8 ((uint32_t)0x00000070) /* SYSCLK divided by 8 */
-#define RCC_HPRE_DIV16 ((uint32_t)0x000000B0) /* SYSCLK divided by 16 */
-#define RCC_HPRE_DIV32 ((uint32_t)0x000000C0) /* SYSCLK divided by 32 */
-#define RCC_HPRE_DIV64 ((uint32_t)0x000000D0) /* SYSCLK divided by 64 */
-#define RCC_HPRE_DIV128 ((uint32_t)0x000000E0) /* SYSCLK divided by 128 */
-#define RCC_HPRE_DIV256 ((uint32_t)0x000000F0) /* SYSCLK divided by 256 */
-
-#define RCC_PPRE1 ((uint32_t)0x00000700) /* PRE1[2:0] bits (APB1 prescaler) */
-#define RCC_PPRE1_0 ((uint32_t)0x00000100) /* Bit 0 */
-#define RCC_PPRE1_1 ((uint32_t)0x00000200) /* Bit 1 */
-#define RCC_PPRE1_2 ((uint32_t)0x00000400) /* Bit 2 */
-
-#define RCC_PPRE1_DIV1 ((uint32_t)0x00000000) /* HCLK not divided */
-#define RCC_PPRE1_DIV2 ((uint32_t)0x00000400) /* HCLK divided by 2 */
-#define RCC_PPRE1_DIV4 ((uint32_t)0x00000500) /* HCLK divided by 4 */
-#define RCC_PPRE1_DIV8 ((uint32_t)0x00000600) /* HCLK divided by 8 */
-#define RCC_PPRE1_DIV16 ((uint32_t)0x00000700) /* HCLK divided by 16 */
-
-#define RCC_PPRE2 ((uint32_t)0x00003800) /* PRE2[2:0] bits (APB2 prescaler) */
-#define RCC_PPRE2_0 ((uint32_t)0x00000800) /* Bit 0 */
-#define RCC_PPRE2_1 ((uint32_t)0x00001000) /* Bit 1 */
-#define RCC_PPRE2_2 ((uint32_t)0x00002000) /* Bit 2 */
-
-#define RCC_PPRE2_DIV1 ((uint32_t)0x00000000) /* HCLK not divided */
-#define RCC_PPRE2_DIV2 ((uint32_t)0x00002000) /* HCLK divided by 2 */
-#define RCC_PPRE2_DIV4 ((uint32_t)0x00002800) /* HCLK divided by 4 */
-#define RCC_PPRE2_DIV8 ((uint32_t)0x00003000) /* HCLK divided by 8 */
-#define RCC_PPRE2_DIV16 ((uint32_t)0x00003800) /* HCLK divided by 16 */
-
-#define RCC_ADCPRE ((uint32_t)0x0000C000) /* ADCPRE[1:0] bits (ADC prescaler) */
-#define RCC_ADCPRE_0 ((uint32_t)0x00004000) /* Bit 0 */
-#define RCC_ADCPRE_1 ((uint32_t)0x00008000) /* Bit 1 */
-
-#define RCC_ADCPRE_DIV2 ((uint32_t)0x00000000) /* PCLK2 divided by 2 */
-#define RCC_ADCPRE_DIV4 ((uint32_t)0x00004000) /* PCLK2 divided by 4 */
-#define RCC_ADCPRE_DIV6 ((uint32_t)0x00008000) /* PCLK2 divided by 6 */
-#define RCC_ADCPRE_DIV8 ((uint32_t)0x0000C000) /* PCLK2 divided by 8 */
-
-#define RCC_PLLSRC ((uint32_t)0x00010000) /* PLL entry clock source */
-
-#define RCC_PLLXTPRE ((uint32_t)0x00020000) /* HSE divider for PLL entry */
-
-#define RCC_PLLMULL ((uint32_t)0x003C0000) /* PLLMUL[3:0] bits (PLL multiplication factor) */
-#define RCC_PLLMULL_0 ((uint32_t)0x00040000) /* Bit 0 */
-#define RCC_PLLMULL_1 ((uint32_t)0x00080000) /* Bit 1 */
-#define RCC_PLLMULL_2 ((uint32_t)0x00100000) /* Bit 2 */
-#define RCC_PLLMULL_3 ((uint32_t)0x00200000) /* Bit 3 */
-
-#define RCC_PLLSRC_HSI_Mul2 ((uint32_t)0x00000000) /* HSI clock*2 selected as PLL entry clock source */
-#define RCC_PLLSRC_HSE_Mul2 ((uint32_t)0x00010000) /* HSE clock*2 selected as PLL entry clock source */
-
-#define RCC_PLLXTPRE_HSE ((uint32_t)0x00000000) /* HSE clock not divided for PLL entry */
-#define RCC_PLLXTPRE_HSE_Div2 ((uint32_t)0x00020000) /* HSE clock divided by 2 for PLL entry */
-
-#define RCC_PLLMULL2 ((uint32_t)0x00000000) /* PLL input clock*2 */
-#define RCC_PLLMULL3 ((uint32_t)0x00040000) /* PLL input clock*3 */
-#define RCC_PLLMULL4 ((uint32_t)0x00080000) /* PLL input clock*4 */
-#define RCC_PLLMULL5 ((uint32_t)0x000C0000) /* PLL input clock*5 */
-#define RCC_PLLMULL6 ((uint32_t)0x00100000) /* PLL input clock*6 */
-#define RCC_PLLMULL7 ((uint32_t)0x00140000) /* PLL input clock*7 */
-#define RCC_PLLMULL8 ((uint32_t)0x00180000) /* PLL input clock*8 */
-#define RCC_PLLMULL9 ((uint32_t)0x001C0000) /* PLL input clock*9 */
-#define RCC_PLLMULL10 ((uint32_t)0x00200000) /* PLL input clock10 */
-#define RCC_PLLMULL11 ((uint32_t)0x00240000) /* PLL input clock*11 */
-#define RCC_PLLMULL12 ((uint32_t)0x00280000) /* PLL input clock*12 */
-#define RCC_PLLMULL13 ((uint32_t)0x002C0000) /* PLL input clock*13 */
-#define RCC_PLLMULL14 ((uint32_t)0x00300000) /* PLL input clock*14 */
-#define RCC_PLLMULL15 ((uint32_t)0x00340000) /* PLL input clock*15 */
-#define RCC_PLLMULL16 ((uint32_t)0x00380000) /* PLL input clock*16 */
-#define RCC_USBPRE ((uint32_t)0x00400000) /* USB Device prescaler */
-
-#define RCC_CFGR0_MCO ((uint32_t)0x07000000) /* MCO[2:0] bits (Microcontroller Clock Output) */
-#define RCC_MCO_0 ((uint32_t)0x01000000) /* Bit 0 */
-#define RCC_MCO_1 ((uint32_t)0x02000000) /* Bit 1 */
-#define RCC_MCO_2 ((uint32_t)0x04000000) /* Bit 2 */
-
-#define RCC_MCO_NOCLOCK ((uint32_t)0x00000000) /* No clock */
-#define RCC_CFGR0_MCO_SYSCLK ((uint32_t)0x04000000) /* System clock selected as MCO source */
-#define RCC_CFGR0_MCO_HSI ((uint32_t)0x05000000) /* HSI clock selected as MCO source */
-#define RCC_CFGR0_MCO_HSE ((uint32_t)0x06000000) /* HSE clock selected as MCO source */
-#define RCC_CFGR0_MCO_PLL ((uint32_t)0x07000000) /* PLL clock divided by 2 selected as MCO source */
-
-/******************* Bit definition for RCC_INTR register ********************/
-#define RCC_LSIRDYF ((uint32_t)0x00000001) /* LSI Ready Interrupt flag */
-#define RCC_LSERDYF ((uint32_t)0x00000002) /* LSE Ready Interrupt flag */
-#define RCC_HSIRDYF ((uint32_t)0x00000004) /* HSI Ready Interrupt flag */
-#define RCC_HSERDYF ((uint32_t)0x00000008) /* HSE Ready Interrupt flag */
-#define RCC_PLLRDYF ((uint32_t)0x00000010) /* PLL Ready Interrupt flag */
-#define RCC_CSSF ((uint32_t)0x00000080) /* Clock Security System Interrupt flag */
-#define RCC_LSIRDYIE ((uint32_t)0x00000100) /* LSI Ready Interrupt Enable */
-#define RCC_LSERDYIE ((uint32_t)0x00000200) /* LSE Ready Interrupt Enable */
-#define RCC_HSIRDYIE ((uint32_t)0x00000400) /* HSI Ready Interrupt Enable */
-#define RCC_HSERDYIE ((uint32_t)0x00000800) /* HSE Ready Interrupt Enable */
-#define RCC_PLLRDYIE ((uint32_t)0x00001000) /* PLL Ready Interrupt Enable */
-#define RCC_LSIRDYC ((uint32_t)0x00010000) /* LSI Ready Interrupt Clear */
-#define RCC_LSERDYC ((uint32_t)0x00020000) /* LSE Ready Interrupt Clear */
-#define RCC_HSIRDYC ((uint32_t)0x00040000) /* HSI Ready Interrupt Clear */
-#define RCC_HSERDYC ((uint32_t)0x00080000) /* HSE Ready Interrupt Clear */
-#define RCC_PLLRDYC ((uint32_t)0x00100000) /* PLL Ready Interrupt Clear */
-#define RCC_CSSC ((uint32_t)0x00800000) /* Clock Security System Interrupt Clear */
-
-/***************** Bit definition for RCC_APB2PRSTR register *****************/
-#define RCC_AFIORST ((uint32_t)0x00000001) /* Alternate Function I/O reset */
-#define RCC_IOPARST ((uint32_t)0x00000004) /* I/O port A reset */
-#define RCC_IOPBRST ((uint32_t)0x00000008) /* I/O port B reset */
-#define RCC_IOPCRST ((uint32_t)0x00000010) /* I/O port C reset */
-#define RCC_IOPDRST ((uint32_t)0x00000020) /* I/O port D reset */
-#define RCC_ADC1RST ((uint32_t)0x00000200) /* ADC 1 interface reset */
-
-#define RCC_ADC2RST ((uint32_t)0x00000400) /* ADC 2 interface reset */
-
-#define RCC_TIM1RST ((uint32_t)0x00000800) /* TIM1 Timer reset */
-#define RCC_SPI1RST ((uint32_t)0x00001000) /* SPI 1 reset */
-#define RCC_USART1RST ((uint32_t)0x00004000) /* USART1 reset */
-
-#define RCC_IOPERST ((uint32_t)0x00000040) /* I/O port E reset */
-
-/***************** Bit definition for RCC_APB1PRSTR register *****************/
-#define RCC_TIM2RST ((uint32_t)0x00000001) /* Timer 2 reset */
-#define RCC_TIM3RST ((uint32_t)0x00000002) /* Timer 3 reset */
-#define RCC_WWDGRST ((uint32_t)0x00000800) /* Window Watchdog reset */
-#define RCC_USART2RST ((uint32_t)0x00020000) /* USART 2 reset */
-#define RCC_I2C1RST ((uint32_t)0x00200000) /* I2C 1 reset */
-
-#define RCC_CAN1RST ((uint32_t)0x02000000) /* CAN1 reset */
-
-#define RCC_BKPRST ((uint32_t)0x08000000) /* Backup interface reset */
-#define RCC_PWRRST ((uint32_t)0x10000000) /* Power interface reset */
-
-#define RCC_TIM4RST ((uint32_t)0x00000004) /* Timer 4 reset */
-#define RCC_SPI2RST ((uint32_t)0x00004000) /* SPI 2 reset */
-#define RCC_USART3RST ((uint32_t)0x00040000) /* USART 3 reset */
-#define RCC_I2C2RST ((uint32_t)0x00400000) /* I2C 2 reset */
-
-#define RCC_USBRST ((uint32_t)0x00800000) /* USB Device reset */
-
-/****************** Bit definition for RCC_AHBPCENR register ******************/
-#define RCC_DMA1EN ((uint16_t)0x0001) /* DMA1 clock enable */
-#define RCC_SRAMEN ((uint16_t)0x0004) /* SRAM interface clock enable */
-#define RCC_FLITFEN ((uint16_t)0x0010) /* FLITF clock enable */
-#define RCC_CRCEN ((uint16_t)0x0040) /* CRC clock enable */
-#define RCC_USBHD ((uint16_t)0x1000)
-
-/****************** Bit definition for RCC_APB2PCENR register *****************/
-#define RCC_AFIOEN ((uint32_t)0x00000001) /* Alternate Function I/O clock enable */
-#define RCC_IOPAEN ((uint32_t)0x00000004) /* I/O port A clock enable */
-#define RCC_IOPBEN ((uint32_t)0x00000008) /* I/O port B clock enable */
-#define RCC_IOPCEN ((uint32_t)0x00000010) /* I/O port C clock enable */
-#define RCC_IOPDEN ((uint32_t)0x00000020) /* I/O port D clock enable */
-#define RCC_ADC1EN ((uint32_t)0x00000200) /* ADC 1 interface clock enable */
-
-#define RCC_ADC2EN ((uint32_t)0x00000400) /* ADC 2 interface clock enable */
-
-#define RCC_TIM1EN ((uint32_t)0x00000800) /* TIM1 Timer clock enable */
-#define RCC_SPI1EN ((uint32_t)0x00001000) /* SPI 1 clock enable */
-#define RCC_USART1EN ((uint32_t)0x00004000) /* USART1 clock enable */
-
-/***************** Bit definition for RCC_APB1PCENR register ******************/
-#define RCC_TIM2EN ((uint32_t)0x00000001) /* Timer 2 clock enabled*/
-#define RCC_TIM3EN ((uint32_t)0x00000002) /* Timer 3 clock enable */
-#define RCC_WWDGEN ((uint32_t)0x00000800) /* Window Watchdog clock enable */
-#define RCC_USART2EN ((uint32_t)0x00020000) /* USART 2 clock enable */
-#define RCC_I2C1EN ((uint32_t)0x00200000) /* I2C 1 clock enable */
-
-#define RCC_BKPEN ((uint32_t)0x08000000) /* Backup interface clock enable */
-#define RCC_PWREN ((uint32_t)0x10000000) /* Power interface clock enable */
-
-#define RCC_USBEN ((uint32_t)0x00800000) /* USB Device clock enable */
-
-/******************* Bit definition for RCC_RSTSCKR register ********************/
-#define RCC_LSION ((uint32_t)0x00000001) /* Internal Low Speed oscillator enable */
-#define RCC_LSIRDY ((uint32_t)0x00000002) /* Internal Low Speed oscillator Ready */
-#define RCC_RMVF ((uint32_t)0x01000000) /* Remove reset flag */
-#define RCC_PINRSTF ((uint32_t)0x04000000) /* PIN reset flag */
-#define RCC_PORRSTF ((uint32_t)0x08000000) /* POR/PDR reset flag */
-#define RCC_SFTRSTF ((uint32_t)0x10000000) /* Software Reset flag */
-#define RCC_IWDGRSTF ((uint32_t)0x20000000) /* Independent Watchdog reset flag */
-#define RCC_WWDGRSTF ((uint32_t)0x40000000) /* Window watchdog reset flag */
-#define RCC_LPWRRSTF ((uint32_t)0x80000000) /* Low-Power reset flag */
-
-/******************************************************************************/
-/* Serial Peripheral Interface */
-/******************************************************************************/
-
-/******************* Bit definition for SPI_CTLR1 register ********************/
-#define SPI_CTLR1_CPHA ((uint16_t)0x0001) /* Clock Phase */
-#define SPI_CTLR1_CPOL ((uint16_t)0x0002) /* Clock Polarity */
-#define SPI_CTLR1_MSTR ((uint16_t)0x0004) /* Master Selection */
-
-#define SPI_CTLR1_BR ((uint16_t)0x0038) /* BR[2:0] bits (Baud Rate Control) */
-#define SPI_CTLR1_BR_0 ((uint16_t)0x0008) /* Bit 0 */
-#define SPI_CTLR1_BR_1 ((uint16_t)0x0010) /* Bit 1 */
-#define SPI_CTLR1_BR_2 ((uint16_t)0x0020) /* Bit 2 */
-
-#define SPI_CTLR1_SPE ((uint16_t)0x0040) /* SPI Enable */
-#define SPI_CTLR1_SSI ((uint16_t)0x0100) /* Internal slave select */
-#define SPI_CTLR1_SSM ((uint16_t)0x0200) /* Software slave management */
-#define SPI_CTLR1_RXONLY ((uint16_t)0x0400) /* Receive only */
-#define SPI_CTLR1_DFF ((uint16_t)0x0800) /* Data Frame Format */
-#define SPI_CTLR1_CRCNEXT ((uint16_t)0x1000) /* Transmit CRC next */
-#define SPI_CTLR1_CRCEN ((uint16_t)0x2000) /* Hardware CRC calculation enable */
-#define SPI_CTLR1_BIDIOE ((uint16_t)0x4000) /* Output enable in bidirectional mode */
-#define SPI_CTLR1_BIDIMODE ((uint16_t)0x8000) /* Bidirectional data mode enable */
-
-/******************* Bit definition for SPI_CTLR2 register ********************/
-#define SPI_CTLR2_RXDMAEN ((uint8_t)0x01) /* Rx Buffer DMA Enable */
-#define SPI_CTLR2_TXDMAEN ((uint8_t)0x02) /* Tx Buffer DMA Enable */
-#define SPI_CTLR2_SSOE ((uint8_t)0x04) /* SS Output Enable */
-#define SPI_CTLR2_ERRIE ((uint8_t)0x20) /* Error Interrupt Enable */
-#define SPI_CTLR2_RXNEIE ((uint8_t)0x40) /* RX buffer Not Empty Interrupt Enable */
-#define SPI_CTLR2_TXEIE ((uint8_t)0x80) /* Tx buffer Empty Interrupt Enable */
-
-/******************** Bit definition for SPI_STATR register ********************/
-#define SPI_STATR_RXNE ((uint8_t)0x01) /* Receive buffer Not Empty */
-#define SPI_STATR_TXE ((uint8_t)0x02) /* Transmit buffer Empty */
-#define SPI_STATR_CHSIDE ((uint8_t)0x04) /* Channel side */
-#define SPI_STATR_UDR ((uint8_t)0x08) /* Underrun flag */
-#define SPI_STATR_CRCERR ((uint8_t)0x10) /* CRC Error flag */
-#define SPI_STATR_MODF ((uint8_t)0x20) /* Mode fault */
-#define SPI_STATR_OVR ((uint8_t)0x40) /* Overrun flag */
-#define SPI_STATR_BSY ((uint8_t)0x80) /* Busy flag */
-
-/******************** Bit definition for SPI_DATAR register ********************/
-#define SPI_DATAR_DR ((uint16_t)0xFFFF) /* Data Register */
-
-/******************* Bit definition for SPI_CRCR register ******************/
-#define SPI_CRCR_CRCPOLY ((uint16_t)0xFFFF) /* CRC polynomial register */
-
-/****************** Bit definition for SPI_RCRCR register ******************/
-#define SPI_RCRCR_RXCRC ((uint16_t)0xFFFF) /* Rx CRC Register */
-
-/****************** Bit definition for SPI_TCRCR register ******************/
-#define SPI_TCRCR_TXCRC ((uint16_t)0xFFFF) /* Tx CRC Register */
-
-/******************************************************************************/
-/* TIM */
-/******************************************************************************/
-
-/******************* Bit definition for TIM_CTLR1 register ********************/
-#define TIM_CEN ((uint16_t)0x0001) /* Counter enable */
-#define TIM_UDIS ((uint16_t)0x0002) /* Update disable */
-#define TIM_URS ((uint16_t)0x0004) /* Update request source */
-#define TIM_OPM ((uint16_t)0x0008) /* One pulse mode */
-#define TIM_DIR ((uint16_t)0x0010) /* Direction */
-
-#define TIM_CMS ((uint16_t)0x0060) /* CMS[1:0] bits (Center-aligned mode selection) */
-#define TIM_CMS_0 ((uint16_t)0x0020) /* Bit 0 */
-#define TIM_CMS_1 ((uint16_t)0x0040) /* Bit 1 */
-
-#define TIM_ARPE ((uint16_t)0x0080) /* Auto-reload preload enable */
-
-#define TIM_CTLR1_CKD ((uint16_t)0x0300) /* CKD[1:0] bits (clock division) */
-#define TIM_CKD_0 ((uint16_t)0x0100) /* Bit 0 */
-#define TIM_CKD_1 ((uint16_t)0x0200) /* Bit 1 */
-
-/******************* Bit definition for TIM_CTLR2 register ********************/
-#define TIM_CCPC ((uint16_t)0x0001) /* Capture/Compare Preloaded Control */
-#define TIM_CCUS ((uint16_t)0x0004) /* Capture/Compare Control Update Selection */
-#define TIM_CCDS ((uint16_t)0x0008) /* Capture/Compare DMA Selection */
-
-#define TIM_MMS ((uint16_t)0x0070) /* MMS[2:0] bits (Master Mode Selection) */
-#define TIM_MMS_0 ((uint16_t)0x0010) /* Bit 0 */
-#define TIM_MMS_1 ((uint16_t)0x0020) /* Bit 1 */
-#define TIM_MMS_2 ((uint16_t)0x0040) /* Bit 2 */
-
-#define TIM_TI1S ((uint16_t)0x0080) /* TI1 Selection */
-#define TIM_OIS1 ((uint16_t)0x0100) /* Output Idle state 1 (OC1 output) */
-#define TIM_OIS1N ((uint16_t)0x0200) /* Output Idle state 1 (OC1N output) */
-#define TIM_OIS2 ((uint16_t)0x0400) /* Output Idle state 2 (OC2 output) */
-#define TIM_OIS2N ((uint16_t)0x0800) /* Output Idle state 2 (OC2N output) */
-#define TIM_OIS3 ((uint16_t)0x1000) /* Output Idle state 3 (OC3 output) */
-#define TIM_OIS3N ((uint16_t)0x2000) /* Output Idle state 3 (OC3N output) */
-#define TIM_OIS4 ((uint16_t)0x4000) /* Output Idle state 4 (OC4 output) */
-
-/******************* Bit definition for TIM_SMCFGR register *******************/
-#define TIM_SMS ((uint16_t)0x0007) /* SMS[2:0] bits (Slave mode selection) */
-#define TIM_SMS_0 ((uint16_t)0x0001) /* Bit 0 */
-#define TIM_SMS_1 ((uint16_t)0x0002) /* Bit 1 */
-#define TIM_SMS_2 ((uint16_t)0x0004) /* Bit 2 */
-
-#define TIM_TS ((uint16_t)0x0070) /* TS[2:0] bits (Trigger selection) */
-#define TIM_TS_0 ((uint16_t)0x0010) /* Bit 0 */
-#define TIM_TS_1 ((uint16_t)0x0020) /* Bit 1 */
-#define TIM_TS_2 ((uint16_t)0x0040) /* Bit 2 */
-
-#define TIM_MSM ((uint16_t)0x0080) /* Master/slave mode */
-
-#define TIM_ETF ((uint16_t)0x0F00) /* ETF[3:0] bits (External trigger filter) */
-#define TIM_ETF_0 ((uint16_t)0x0100) /* Bit 0 */
-#define TIM_ETF_1 ((uint16_t)0x0200) /* Bit 1 */
-#define TIM_ETF_2 ((uint16_t)0x0400) /* Bit 2 */
-#define TIM_ETF_3 ((uint16_t)0x0800) /* Bit 3 */
-
-#define TIM_ETPS ((uint16_t)0x3000) /* ETPS[1:0] bits (External trigger prescaler) */
-#define TIM_ETPS_0 ((uint16_t)0x1000) /* Bit 0 */
-#define TIM_ETPS_1 ((uint16_t)0x2000) /* Bit 1 */
-
-#define TIM_ECE ((uint16_t)0x4000) /* External clock enable */
-#define TIM_ETP ((uint16_t)0x8000) /* External trigger polarity */
-
-/******************* Bit definition for TIM_DMAINTENR register *******************/
-#define TIM_UIE ((uint16_t)0x0001) /* Update interrupt enable */
-#define TIM_CC1IE ((uint16_t)0x0002) /* Capture/Compare 1 interrupt enable */
-#define TIM_CC2IE ((uint16_t)0x0004) /* Capture/Compare 2 interrupt enable */
-#define TIM_CC3IE ((uint16_t)0x0008) /* Capture/Compare 3 interrupt enable */
-#define TIM_CC4IE ((uint16_t)0x0010) /* Capture/Compare 4 interrupt enable */
-#define TIM_COMIE ((uint16_t)0x0020) /* COM interrupt enable */
-#define TIM_TIE ((uint16_t)0x0040) /* Trigger interrupt enable */
-#define TIM_BIE ((uint16_t)0x0080) /* Break interrupt enable */
-#define TIM_UDE ((uint16_t)0x0100) /* Update DMA request enable */
-#define TIM_CC1DE ((uint16_t)0x0200) /* Capture/Compare 1 DMA request enable */
-#define TIM_CC2DE ((uint16_t)0x0400) /* Capture/Compare 2 DMA request enable */
-#define TIM_CC3DE ((uint16_t)0x0800) /* Capture/Compare 3 DMA request enable */
-#define TIM_CC4DE ((uint16_t)0x1000) /* Capture/Compare 4 DMA request enable */
-#define TIM_COMDE ((uint16_t)0x2000) /* COM DMA request enable */
-#define TIM_TDE ((uint16_t)0x4000) /* Trigger DMA request enable */
-
-/******************** Bit definition for TIM_INTFR register ********************/
-#define TIM_UIF ((uint16_t)0x0001) /* Update interrupt Flag */
-#define TIM_CC1IF ((uint16_t)0x0002) /* Capture/Compare 1 interrupt Flag */
-#define TIM_CC2IF ((uint16_t)0x0004) /* Capture/Compare 2 interrupt Flag */
-#define TIM_CC3IF ((uint16_t)0x0008) /* Capture/Compare 3 interrupt Flag */
-#define TIM_CC4IF ((uint16_t)0x0010) /* Capture/Compare 4 interrupt Flag */
-#define TIM_COMIF ((uint16_t)0x0020) /* COM interrupt Flag */
-#define TIM_TIF ((uint16_t)0x0040) /* Trigger interrupt Flag */
-#define TIM_BIF ((uint16_t)0x0080) /* Break interrupt Flag */
-#define TIM_CC1OF ((uint16_t)0x0200) /* Capture/Compare 1 Overcapture Flag */
-#define TIM_CC2OF ((uint16_t)0x0400) /* Capture/Compare 2 Overcapture Flag */
-#define TIM_CC3OF ((uint16_t)0x0800) /* Capture/Compare 3 Overcapture Flag */
-#define TIM_CC4OF ((uint16_t)0x1000) /* Capture/Compare 4 Overcapture Flag */
-
-/******************* Bit definition for TIM_SWEVGR register ********************/
-#define TIM_UG ((uint8_t)0x01) /* Update Generation */
-#define TIM_CC1G ((uint8_t)0x02) /* Capture/Compare 1 Generation */
-#define TIM_CC2G ((uint8_t)0x04) /* Capture/Compare 2 Generation */
-#define TIM_CC3G ((uint8_t)0x08) /* Capture/Compare 3 Generation */
-#define TIM_CC4G ((uint8_t)0x10) /* Capture/Compare 4 Generation */
-#define TIM_COMG ((uint8_t)0x20) /* Capture/Compare Control Update Generation */
-#define TIM_TG ((uint8_t)0x40) /* Trigger Generation */
-#define TIM_BG ((uint8_t)0x80) /* Break Generation */
-
-/****************** Bit definition for TIM_CHCTLR1 register *******************/
-#define TIM_CC1S ((uint16_t)0x0003) /* CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define TIM_CC1S_0 ((uint16_t)0x0001) /* Bit 0 */
-#define TIM_CC1S_1 ((uint16_t)0x0002) /* Bit 1 */
-
-#define TIM_OC1FE ((uint16_t)0x0004) /* Output Compare 1 Fast enable */
-#define TIM_OC1PE ((uint16_t)0x0008) /* Output Compare 1 Preload enable */
-
-#define TIM_OC1M ((uint16_t)0x0070) /* OC1M[2:0] bits (Output Compare 1 Mode) */
-#define TIM_OC1M_0 ((uint16_t)0x0010) /* Bit 0 */
-#define TIM_OC1M_1 ((uint16_t)0x0020) /* Bit 1 */
-#define TIM_OC1M_2 ((uint16_t)0x0040) /* Bit 2 */
-
-#define TIM_OC1CE ((uint16_t)0x0080) /* Output Compare 1Clear Enable */
-
-#define TIM_CC2S ((uint16_t)0x0300) /* CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define TIM_CC2S_0 ((uint16_t)0x0100) /* Bit 0 */
-#define TIM_CC2S_1 ((uint16_t)0x0200) /* Bit 1 */
-
-#define TIM_OC2FE ((uint16_t)0x0400) /* Output Compare 2 Fast enable */
-#define TIM_OC2PE ((uint16_t)0x0800) /* Output Compare 2 Preload enable */
-
-#define TIM_OC2M ((uint16_t)0x7000) /* OC2M[2:0] bits (Output Compare 2 Mode) */
-#define TIM_OC2M_0 ((uint16_t)0x1000) /* Bit 0 */
-#define TIM_OC2M_1 ((uint16_t)0x2000) /* Bit 1 */
-#define TIM_OC2M_2 ((uint16_t)0x4000) /* Bit 2 */
-
-#define TIM_OC2CE ((uint16_t)0x8000) /* Output Compare 2 Clear Enable */
-
-#define TIM_IC1PSC ((uint16_t)0x000C) /* IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define TIM_IC1PSC_0 ((uint16_t)0x0004) /* Bit 0 */
-#define TIM_IC1PSC_1 ((uint16_t)0x0008) /* Bit 1 */
-
-#define TIM_IC1F ((uint16_t)0x00F0) /* IC1F[3:0] bits (Input Capture 1 Filter) */
-#define TIM_IC1F_0 ((uint16_t)0x0010) /* Bit 0 */
-#define TIM_IC1F_1 ((uint16_t)0x0020) /* Bit 1 */
-#define TIM_IC1F_2 ((uint16_t)0x0040) /* Bit 2 */
-#define TIM_IC1F_3 ((uint16_t)0x0080) /* Bit 3 */
-
-#define TIM_IC2PSC ((uint16_t)0x0C00) /* IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
-#define TIM_IC2PSC_0 ((uint16_t)0x0400) /* Bit 0 */
-#define TIM_IC2PSC_1 ((uint16_t)0x0800) /* Bit 1 */
-
-#define TIM_IC2F ((uint16_t)0xF000) /* IC2F[3:0] bits (Input Capture 2 Filter) */
-#define TIM_IC2F_0 ((uint16_t)0x1000) /* Bit 0 */
-#define TIM_IC2F_1 ((uint16_t)0x2000) /* Bit 1 */
-#define TIM_IC2F_2 ((uint16_t)0x4000) /* Bit 2 */
-#define TIM_IC2F_3 ((uint16_t)0x8000) /* Bit 3 */
-
-/****************** Bit definition for TIM_CHCTLR2 register *******************/
-#define TIM_CC3S ((uint16_t)0x0003) /* CC3S[1:0] bits (Capture/Compare 3 Selection) */
-#define TIM_CC3S_0 ((uint16_t)0x0001) /* Bit 0 */
-#define TIM_CC3S_1 ((uint16_t)0x0002) /* Bit 1 */
-
-#define TIM_OC3FE ((uint16_t)0x0004) /* Output Compare 3 Fast enable */
-#define TIM_OC3PE ((uint16_t)0x0008) /* Output Compare 3 Preload enable */
-
-#define TIM_OC3M ((uint16_t)0x0070) /* OC3M[2:0] bits (Output Compare 3 Mode) */
-#define TIM_OC3M_0 ((uint16_t)0x0010) /* Bit 0 */
-#define TIM_OC3M_1 ((uint16_t)0x0020) /* Bit 1 */
-#define TIM_OC3M_2 ((uint16_t)0x0040) /* Bit 2 */
-
-#define TIM_OC3CE ((uint16_t)0x0080) /* Output Compare 3 Clear Enable */
-
-#define TIM_CC4S ((uint16_t)0x0300) /* CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define TIM_CC4S_0 ((uint16_t)0x0100) /* Bit 0 */
-#define TIM_CC4S_1 ((uint16_t)0x0200) /* Bit 1 */
-
-#define TIM_OC4FE ((uint16_t)0x0400) /* Output Compare 4 Fast enable */
-#define TIM_OC4PE ((uint16_t)0x0800) /* Output Compare 4 Preload enable */
-
-#define TIM_OC4M ((uint16_t)0x7000) /* OC4M[2:0] bits (Output Compare 4 Mode) */
-#define TIM_OC4M_0 ((uint16_t)0x1000) /* Bit 0 */
-#define TIM_OC4M_1 ((uint16_t)0x2000) /* Bit 1 */
-#define TIM_OC4M_2 ((uint16_t)0x4000) /* Bit 2 */
-
-#define TIM_OC4CE ((uint16_t)0x8000) /* Output Compare 4 Clear Enable */
-
-#define TIM_IC3PSC ((uint16_t)0x000C) /* IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define TIM_IC3PSC_0 ((uint16_t)0x0004) /* Bit 0 */
-#define TIM_IC3PSC_1 ((uint16_t)0x0008) /* Bit 1 */
-
-#define TIM_IC3F ((uint16_t)0x00F0) /* IC3F[3:0] bits (Input Capture 3 Filter) */
-#define TIM_IC3F_0 ((uint16_t)0x0010) /* Bit 0 */
-#define TIM_IC3F_1 ((uint16_t)0x0020) /* Bit 1 */
-#define TIM_IC3F_2 ((uint16_t)0x0040) /* Bit 2 */
-#define TIM_IC3F_3 ((uint16_t)0x0080) /* Bit 3 */
-
-#define TIM_IC4PSC ((uint16_t)0x0C00) /* IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define TIM_IC4PSC_0 ((uint16_t)0x0400) /* Bit 0 */
-#define TIM_IC4PSC_1 ((uint16_t)0x0800) /* Bit 1 */
-
-#define TIM_IC4F ((uint16_t)0xF000) /* IC4F[3:0] bits (Input Capture 4 Filter) */
-#define TIM_IC4F_0 ((uint16_t)0x1000) /* Bit 0 */
-#define TIM_IC4F_1 ((uint16_t)0x2000) /* Bit 1 */
-#define TIM_IC4F_2 ((uint16_t)0x4000) /* Bit 2 */
-#define TIM_IC4F_3 ((uint16_t)0x8000) /* Bit 3 */
-
-/******************* Bit definition for TIM_CCER register *******************/
-#define TIM_CC1E ((uint16_t)0x0001) /* Capture/Compare 1 output enable */
-#define TIM_CC1P ((uint16_t)0x0002) /* Capture/Compare 1 output Polarity */
-#define TIM_CC1NE ((uint16_t)0x0004) /* Capture/Compare 1 Complementary output enable */
-#define TIM_CC1NP ((uint16_t)0x0008) /* Capture/Compare 1 Complementary output Polarity */
-#define TIM_CC2E ((uint16_t)0x0010) /* Capture/Compare 2 output enable */
-#define TIM_CC2P ((uint16_t)0x0020) /* Capture/Compare 2 output Polarity */
-#define TIM_CC2NE ((uint16_t)0x0040) /* Capture/Compare 2 Complementary output enable */
-#define TIM_CC2NP ((uint16_t)0x0080) /* Capture/Compare 2 Complementary output Polarity */
-#define TIM_CC3E ((uint16_t)0x0100) /* Capture/Compare 3 output enable */
-#define TIM_CC3P ((uint16_t)0x0200) /* Capture/Compare 3 output Polarity */
-#define TIM_CC3NE ((uint16_t)0x0400) /* Capture/Compare 3 Complementary output enable */
-#define TIM_CC3NP ((uint16_t)0x0800) /* Capture/Compare 3 Complementary output Polarity */
-#define TIM_CC4E ((uint16_t)0x1000) /* Capture/Compare 4 output enable */
-#define TIM_CC4P ((uint16_t)0x2000) /* Capture/Compare 4 output Polarity */
-#define TIM_CC4NP ((uint16_t)0x8000) /* Capture/Compare 4 Complementary output Polarity */
-
-/******************* Bit definition for TIM_CNT register ********************/
-#define TIM_CNT ((uint16_t)0xFFFF) /* Counter Value */
-
-/******************* Bit definition for TIM_PSC register ********************/
-#define TIM_PSC ((uint16_t)0xFFFF) /* Prescaler Value */
-
-/******************* Bit definition for TIM_ATRLR register ********************/
-#define TIM_ARR ((uint16_t)0xFFFF) /* actual auto-reload Value */
-
-/******************* Bit definition for TIM_RPTCR register ********************/
-#define TIM_REP ((uint8_t)0xFF) /* Repetition Counter Value */
-
-/******************* Bit definition for TIM_CH1CVR register *******************/
-#define TIM_CCR1 ((uint16_t)0xFFFF) /* Capture/Compare 1 Value */
-
-/******************* Bit definition for TIM_CH2CVR register *******************/
-#define TIM_CCR2 ((uint16_t)0xFFFF) /* Capture/Compare 2 Value */
-
-/******************* Bit definition for TIM_CH3CVR register *******************/
-#define TIM_CCR3 ((uint16_t)0xFFFF) /* Capture/Compare 3 Value */
-
-/******************* Bit definition for TIM_CH4CVR register *******************/
-#define TIM_CCR4 ((uint16_t)0xFFFF) /* Capture/Compare 4 Value */
-
-/******************* Bit definition for TIM_BDTR register *******************/
-#define TIM_DTG ((uint16_t)0x00FF) /* DTG[0:7] bits (Dead-Time Generator set-up) */
-#define TIM_DTG_0 ((uint16_t)0x0001) /* Bit 0 */
-#define TIM_DTG_1 ((uint16_t)0x0002) /* Bit 1 */
-#define TIM_DTG_2 ((uint16_t)0x0004) /* Bit 2 */
-#define TIM_DTG_3 ((uint16_t)0x0008) /* Bit 3 */
-#define TIM_DTG_4 ((uint16_t)0x0010) /* Bit 4 */
-#define TIM_DTG_5 ((uint16_t)0x0020) /* Bit 5 */
-#define TIM_DTG_6 ((uint16_t)0x0040) /* Bit 6 */
-#define TIM_DTG_7 ((uint16_t)0x0080) /* Bit 7 */
-
-#define TIM_LOCK ((uint16_t)0x0300) /* LOCK[1:0] bits (Lock Configuration) */
-#define TIM_LOCK_0 ((uint16_t)0x0100) /* Bit 0 */
-#define TIM_LOCK_1 ((uint16_t)0x0200) /* Bit 1 */
-
-#define TIM_OSSI ((uint16_t)0x0400) /* Off-State Selection for Idle mode */
-#define TIM_OSSR ((uint16_t)0x0800) /* Off-State Selection for Run mode */
-#define TIM_BKE ((uint16_t)0x1000) /* Break enable */
-#define TIM_BKP ((uint16_t)0x2000) /* Break Polarity */
-#define TIM_AOE ((uint16_t)0x4000) /* Automatic Output enable */
-#define TIM_MOE ((uint16_t)0x8000) /* Main Output enable */
-
-/******************* Bit definition for TIM_DMACFGR register ********************/
-#define TIM_DBA ((uint16_t)0x001F) /* DBA[4:0] bits (DMA Base Address) */
-#define TIM_DBA_0 ((uint16_t)0x0001) /* Bit 0 */
-#define TIM_DBA_1 ((uint16_t)0x0002) /* Bit 1 */
-#define TIM_DBA_2 ((uint16_t)0x0004) /* Bit 2 */
-#define TIM_DBA_3 ((uint16_t)0x0008) /* Bit 3 */
-#define TIM_DBA_4 ((uint16_t)0x0010) /* Bit 4 */
-
-#define TIM_DBL ((uint16_t)0x1F00) /* DBL[4:0] bits (DMA Burst Length) */
-#define TIM_DBL_0 ((uint16_t)0x0100) /* Bit 0 */
-#define TIM_DBL_1 ((uint16_t)0x0200) /* Bit 1 */
-#define TIM_DBL_2 ((uint16_t)0x0400) /* Bit 2 */
-#define TIM_DBL_3 ((uint16_t)0x0800) /* Bit 3 */
-#define TIM_DBL_4 ((uint16_t)0x1000) /* Bit 4 */
-
-/******************* Bit definition for TIM_DMAADR register *******************/
-#define TIM_DMAR_DMAB ((uint16_t)0xFFFF) /* DMA register for burst accesses */
-
-/******************************************************************************/
-/* Universal Synchronous Asynchronous Receiver Transmitter */
-/******************************************************************************/
-
-/******************* Bit definition for USART_STATR register *******************/
-#define USART_STATR_PE ((uint16_t)0x0001) /* Parity Error */
-#define USART_STATR_FE ((uint16_t)0x0002) /* Framing Error */
-#define USART_STATR_NE ((uint16_t)0x0004) /* Noise Error Flag */
-#define USART_STATR_ORE ((uint16_t)0x0008) /* OverRun Error */
-#define USART_STATR_IDLE ((uint16_t)0x0010) /* IDLE line detected */
-#define USART_STATR_RXNE ((uint16_t)0x0020) /* Read Data Register Not Empty */
-#define USART_STATR_TC ((uint16_t)0x0040) /* Transmission Complete */
-#define USART_STATR_TXE ((uint16_t)0x0080) /* Transmit Data Register Empty */
-#define USART_STATR_LBD ((uint16_t)0x0100) /* LIN Break Detection Flag */
-#define USART_STATR_CTS ((uint16_t)0x0200) /* CTS Flag */
-
-/******************* Bit definition for USART_DATAR register *******************/
-#define USART_DATAR_DR ((uint16_t)0x01FF) /* Data value */
-
-/****************** Bit definition for USART_BRR register *******************/
-#define USART_BRR_DIV_Fraction ((uint16_t)0x000F) /* Fraction of USARTDIV */
-#define USART_BRR_DIV_Mantissa ((uint16_t)0xFFF0) /* Mantissa of USARTDIV */
-
-/****************** Bit definition for USART_CTLR1 register *******************/
-#define USART_CTLR1_SBK ((uint16_t)0x0001) /* Send Break */
-#define USART_CTLR1_RWU ((uint16_t)0x0002) /* Receiver wakeup */
-#define USART_CTLR1_RE ((uint16_t)0x0004) /* Receiver Enable */
-#define USART_CTLR1_TE ((uint16_t)0x0008) /* Transmitter Enable */
-#define USART_CTLR1_IDLEIE ((uint16_t)0x0010) /* IDLE Interrupt Enable */
-#define USART_CTLR1_RXNEIE ((uint16_t)0x0020) /* RXNE Interrupt Enable */
-#define USART_CTLR1_TCIE ((uint16_t)0x0040) /* Transmission Complete Interrupt Enable */
-#define USART_CTLR1_TXEIE ((uint16_t)0x0080) /* PE Interrupt Enable */
-#define USART_CTLR1_PEIE ((uint16_t)0x0100) /* PE Interrupt Enable */
-#define USART_CTLR1_PS ((uint16_t)0x0200) /* Parity Selection */
-#define USART_CTLR1_PCE ((uint16_t)0x0400) /* Parity Control Enable */
-#define USART_CTLR1_WAKE ((uint16_t)0x0800) /* Wakeup method */
-#define USART_CTLR1_M ((uint16_t)0x1000) /* Word length */
-#define USART_CTLR1_UE ((uint16_t)0x2000) /* USART Enable */
-#define USART_CTLR1_OVER8 ((uint16_t)0x8000) /* USART Oversmapling 8-bits */
-
-/****************** Bit definition for USART_CTLR2 register *******************/
-#define USART_CTLR2_ADD ((uint16_t)0x000F) /* Address of the USART node */
-#define USART_CTLR2_LBDL ((uint16_t)0x0020) /* LIN Break Detection Length */
-#define USART_CTLR2_LBDIE ((uint16_t)0x0040) /* LIN Break Detection Interrupt Enable */
-#define USART_CTLR2_LBCL ((uint16_t)0x0100) /* Last Bit Clock pulse */
-#define USART_CTLR2_CPHA ((uint16_t)0x0200) /* Clock Phase */
-#define USART_CTLR2_CPOL ((uint16_t)0x0400) /* Clock Polarity */
-#define USART_CTLR2_CLKEN ((uint16_t)0x0800) /* Clock Enable */
-
-#define USART_CTLR2_STOP ((uint16_t)0x3000) /* STOP[1:0] bits (STOP bits) */
-#define USART_CTLR2_STOP_0 ((uint16_t)0x1000) /* Bit 0 */
-#define USART_CTLR2_STOP_1 ((uint16_t)0x2000) /* Bit 1 */
-
-#define USART_CTLR2_LINEN ((uint16_t)0x4000) /* LIN mode enable */
-
-/****************** Bit definition for USART_CTLR3 register *******************/
-#define USART_CTLR3_EIE ((uint16_t)0x0001) /* Error Interrupt Enable */
-#define USART_CTLR3_IREN ((uint16_t)0x0002) /* IrDA mode Enable */
-#define USART_CTLR3_IRLP ((uint16_t)0x0004) /* IrDA Low-Power */
-#define USART_CTLR3_HDSEL ((uint16_t)0x0008) /* Half-Duplex Selection */
-#define USART_CTLR3_NACK ((uint16_t)0x0010) /* Smartcard NACK enable */
-#define USART_CTLR3_SCEN ((uint16_t)0x0020) /* Smartcard mode enable */
-#define USART_CTLR3_DMAR ((uint16_t)0x0040) /* DMA Enable Receiver */
-#define USART_CTLR3_DMAT ((uint16_t)0x0080) /* DMA Enable Transmitter */
-#define USART_CTLR3_RTSE ((uint16_t)0x0100) /* RTS Enable */
-#define USART_CTLR3_CTSE ((uint16_t)0x0200) /* CTS Enable */
-#define USART_CTLR3_CTSIE ((uint16_t)0x0400) /* CTS Interrupt Enable */
-#define USART_CTLR3_ONEBIT ((uint16_t)0x0800) /* One Bit method */
-
-/****************** Bit definition for USART_GPR register ******************/
-#define USART_GPR_PSC ((uint16_t)0x00FF) /* PSC[7:0] bits (Prescaler value) */
-#define USART_GPR_PSC_0 ((uint16_t)0x0001) /* Bit 0 */
-#define USART_GPR_PSC_1 ((uint16_t)0x0002) /* Bit 1 */
-#define USART_GPR_PSC_2 ((uint16_t)0x0004) /* Bit 2 */
-#define USART_GPR_PSC_3 ((uint16_t)0x0008) /* Bit 3 */
-#define USART_GPR_PSC_4 ((uint16_t)0x0010) /* Bit 4 */
-#define USART_GPR_PSC_5 ((uint16_t)0x0020) /* Bit 5 */
-#define USART_GPR_PSC_6 ((uint16_t)0x0040) /* Bit 6 */
-#define USART_GPR_PSC_7 ((uint16_t)0x0080) /* Bit 7 */
-
-#define USART_GPR_GT ((uint16_t)0xFF00) /* Guard time value */
-
-/******************************************************************************/
-/* Window WATCHDOG */
-/******************************************************************************/
-
-/******************* Bit definition for WWDG_CTLR register ********************/
-#define WWDG_CTLR_T ((uint8_t)0x7F) /* T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define WWDG_CTLR_T0 ((uint8_t)0x01) /* Bit 0 */
-#define WWDG_CTLR_T1 ((uint8_t)0x02) /* Bit 1 */
-#define WWDG_CTLR_T2 ((uint8_t)0x04) /* Bit 2 */
-#define WWDG_CTLR_T3 ((uint8_t)0x08) /* Bit 3 */
-#define WWDG_CTLR_T4 ((uint8_t)0x10) /* Bit 4 */
-#define WWDG_CTLR_T5 ((uint8_t)0x20) /* Bit 5 */
-#define WWDG_CTLR_T6 ((uint8_t)0x40) /* Bit 6 */
-
-#define WWDG_CTLR_WDGA ((uint8_t)0x80) /* Activation bit */
-
-/******************* Bit definition for WWDG_CFGR register *******************/
-#define WWDG_CFGR_W ((uint16_t)0x007F) /* W[6:0] bits (7-bit window value) */
-#define WWDG_CFGR_W0 ((uint16_t)0x0001) /* Bit 0 */
-#define WWDG_CFGR_W1 ((uint16_t)0x0002) /* Bit 1 */
-#define WWDG_CFGR_W2 ((uint16_t)0x0004) /* Bit 2 */
-#define WWDG_CFGR_W3 ((uint16_t)0x0008) /* Bit 3 */
-#define WWDG_CFGR_W4 ((uint16_t)0x0010) /* Bit 4 */
-#define WWDG_CFGR_W5 ((uint16_t)0x0020) /* Bit 5 */
-#define WWDG_CFGR_W6 ((uint16_t)0x0040) /* Bit 6 */
-
-#define WWDG_CFGR_WDGTB ((uint16_t)0x0180) /* WDGTB[1:0] bits (Timer Base) */
-#define WWDG_CFGR_WDGTB0 ((uint16_t)0x0080) /* Bit 0 */
-#define WWDG_CFGR_WDGTB1 ((uint16_t)0x0100) /* Bit 1 */
-
-#define WWDG_CFGR_EWI ((uint16_t)0x0200) /* Early Wakeup Interrupt */
-
-/******************* Bit definition for WWDG_STATR register ********************/
-#define WWDG_STATR_EWIF ((uint8_t)0x01) /* Early Wakeup Interrupt Flag */
-
-/******************************************************************************/
-/* ENHANCED FUNNCTION */
-/******************************************************************************/
-
-/**************************** Enhanced register *****************************/
-#define EXTEN_LOCKUP_EN ((uint32_t)0x00000040) /* Bit 6 */
-#define EXTEN_LOCKUP_RSTF ((uint32_t)0x00000080) /* Bit 7 */
-
-#define EXTEN_LDO_TRIM ((uint32_t)0x00000400) /* Bit 10 */
-
-#define EXTEN_OPA_EN ((uint32_t)0x00010000)
-#define EXTEN_OPA_NSEL ((uint32_t)0x00020000)
-#define EXTEN_OPA_PSEL ((uint32_t)0x00040000)
-
-#include <ch32v00x_conf.h>
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __CH32V00x_H */
diff --git a/attic/ch32v003evt/ch32v00x_conf.h b/attic/ch32v003evt/ch32v00x_conf.h
deleted file mode 100644
index 217af40d57d30349d14b4ba0be8e2d7fcd6b10c2..0000000000000000000000000000000000000000
--- a/attic/ch32v003evt/ch32v00x_conf.h
+++ /dev/null
@@ -1,1813 +0,0 @@
-/*
- * This file contains the contents of various parts of the evt.
- *
- * The collection of this file was generated by cnlohr, 2023-02-18
- *
- * Contents subject to below copyright where applicable by law.
- *
- * (IANAL, BUT Because it is an interface, it is unlikely protected by copyright)
- *
- *********************************** (C) COPYRIGHT *******************************
- * File Name : ------------------
- * Author : WCH
- * Version : V1.0.0
- * Date : 2020/08/08
- * Description : Library configuration file.
-*********************************************************************************
-* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
-* Attention: This software (modified or not) and binary are used for
-* microcontroller manufactured by Nanjing Qinheng Microelectronics.
-*******************************************************************************/
-#ifndef __CH32V00x_CONF_H
-#define __CH32V00x_CONF_H
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-// Tricky: We need to make sure main and SystemInit() are preserved.
-int main() __attribute__((used));
-void SystemInit(void) __attribute__((used));
-
-// Useful functions
-void SystemInit48HSI( void );
-
-#define UART_BAUD_RATE 115200
-#define OVER8DIV 4
-#define INTEGER_DIVIDER (((25 * (APB_CLOCK)) / ((OVER8DIV) * (UART_BAUD_RATE))))
-#define FRACTIONAL_DIVIDER ((INTEGER_DIVIDER)%100)
-#define UART_BRR ((((INTEGER_DIVIDER) / 100) << 4) | (((((FRACTIONAL_DIVIDER) * ((OVER8DIV)*2)) + 50)/100)&7))
-// Put an output debug UART on Pin D5.
-// You can write to this with printf(...) or puts(...)
-// Call with SetupUART( UART_BRR )
-void SetupUART( int uartBRR );
-
-
-/* ch32v00x_gpio.c -----------------------------------------------------------*/
-/* MASK */
-#define LSB_MASK ((uint16_t)0xFFFF)
-#define DBGAFR_POSITION_MASK ((uint32_t)0x000F0000)
-#define DBGAFR_SDI_MASK ((uint32_t)0xF8FFFFFF)
-#define DBGAFR_LOCATION_MASK ((uint32_t)0x00200000)
-#define DBGAFR_NUMBITS_MASK ((uint32_t)0x00100000)
-
-
-/* ch32v00x_adc.c ------------------------------------------------------------*/
-/*
-/* ADC DISCNUM mask */
-#define CTLR1_DISCNUM_Reset ((uint32_t)0xFFFF1FFF)
-
-/* ADC DISCEN mask */
-#define CTLR1_DISCEN_Set ((uint32_t)0x00000800)
-#define CTLR1_DISCEN_Reset ((uint32_t)0xFFFFF7FF)
-
-/* ADC JAUTO mask */
-#define CTLR1_JAUTO_Set ((uint32_t)0x00000400)
-#define CTLR1_JAUTO_Reset ((uint32_t)0xFFFFFBFF)
-
-/* ADC JDISCEN mask */
-#define CTLR1_JDISCEN_Set ((uint32_t)0x00001000)
-#define CTLR1_JDISCEN_Reset ((uint32_t)0xFFFFEFFF)
-
-/* ADC AWDCH mask */
-#define CTLR1_AWDCH_Reset ((uint32_t)0xFFFFFFE0)
-
-/* ADC Analog watchdog enable mode mask */
-#define CTLR1_AWDMode_Reset ((uint32_t)0xFF3FFDFF)
-
-///* CTLR1 register Mask */
-//Editor's Note: Overloaded Definition
-#define ADC_CTLR1_CLEAR_Mask ((uint32_t)0xFFF0FEFF)
-
-/* ADC ADON mask */
-#define CTLR2_ADON_Set ((uint32_t)0x00000001)
-#define CTLR2_ADON_Reset ((uint32_t)0xFFFFFFFE)
-
-/* ADC DMA mask */
-#define CTLR2_DMA_Set ((uint32_t)0x00000100)
-#define CTLR2_DMA_Reset ((uint32_t)0xFFFFFEFF)
-
-/* ADC RSTCAL mask */
-#define CTLR2_RSTCAL_Set ((uint32_t)0x00000008)
-
-/* ADC CAL mask */
-#define CTLR2_CAL_Set ((uint32_t)0x00000004)
-
-/* ADC SWSTART mask */
-#define CTLR2_SWSTART_Set ((uint32_t)0x00400000)
-
-/* ADC EXTTRIG mask */
-#define CTLR2_EXTTRIG_Set ((uint32_t)0x00100000)
-#define CTLR2_EXTTRIG_Reset ((uint32_t)0xFFEFFFFF)
-
-/* ADC Software start mask */
-#define CTLR2_EXTTRIG_SWSTART_Set ((uint32_t)0x00500000)
-#define CTLR2_EXTTRIG_SWSTART_Reset ((uint32_t)0xFFAFFFFF)
-
-/* ADC JEXTSEL mask */
-#define CTLR2_JEXTSEL_Reset ((uint32_t)0xFFFF8FFF)
-
-/* ADC JEXTTRIG mask */
-#define CTLR2_JEXTTRIG_Set ((uint32_t)0x00008000)
-#define CTLR2_JEXTTRIG_Reset ((uint32_t)0xFFFF7FFF)
-
-/* ADC JSWSTART mask */
-#define CTLR2_JSWSTART_Set ((uint32_t)0x00200000)
-
-/* ADC injected software start mask */
-#define CTLR2_JEXTTRIG_JSWSTART_Set ((uint32_t)0x00208000)
-#define CTLR2_JEXTTRIG_JSWSTART_Reset ((uint32_t)0xFFDF7FFF)
-
-/* ADC TSPD mask */
-#define CTLR2_TSVREFE_Set ((uint32_t)0x00800000)
-#define CTLR2_TSVREFE_Reset ((uint32_t)0xFF7FFFFF)
-
-/* CTLR2 register Mask */
-#define CTLR2_CLEAR_Mask ((uint32_t)0xFFF1F7FD)
-
-/* ADC SQx mask */
-#define RSQR3_SQ_Set ((uint32_t)0x0000001F)
-#define RSQR2_SQ_Set ((uint32_t)0x0000001F)
-#define RSQR1_SQ_Set ((uint32_t)0x0000001F)
-
-/* RSQR1 register Mask */
-#define RSQR1_CLEAR_Mask ((uint32_t)0xFF0FFFFF)
-
-/* ADC JSQx mask */
-#define ISQR_JSQ_Set ((uint32_t)0x0000001F)
-
-/* ADC JL mask */
-#define ISQR_JL_Set ((uint32_t)0x00300000)
-#define ISQR_JL_Reset ((uint32_t)0xFFCFFFFF)
-
-/* ADC SMPx mask */
-#define SAMPTR1_SMP_Set ((uint32_t)0x00000007)
-#define SAMPTR2_SMP_Set ((uint32_t)0x00000007)
-
-/* ADC IDATARx registers offset */
-#define IDATAR_Offset ((uint8_t)0x28)
-
-
-/* ch32v00x_dbgmcu.c ---------------------------------------------------------*/
-#define IDCODE_DEVID_MASK ((uint32_t)0x0000FFFF)
-
-
-/* ch32v00x_dma.c ------------------------------------------------------------*/
-
-/* DMA1 Channelx interrupt pending bit masks */
-#define DMA1_Channel1_IT_Mask ((uint32_t)(DMA_GIF1 | DMA_TCIF1 | DMA_HTIF1 | DMA_TEIF1))
-#define DMA1_Channel2_IT_Mask ((uint32_t)(DMA_GIF2 | DMA_TCIF2 | DMA_HTIF2 | DMA_TEIF2))
-#define DMA1_Channel3_IT_Mask ((uint32_t)(DMA_GIF3 | DMA_TCIF3 | DMA_HTIF3 | DMA_TEIF3))
-#define DMA1_Channel4_IT_Mask ((uint32_t)(DMA_GIF4 | DMA_TCIF4 | DMA_HTIF4 | DMA_TEIF4))
-#define DMA1_Channel5_IT_Mask ((uint32_t)(DMA_GIF5 | DMA_TCIF5 | DMA_HTIF5 | DMA_TEIF5))
-#define DMA1_Channel6_IT_Mask ((uint32_t)(DMA_GIF6 | DMA_TCIF6 | DMA_HTIF6 | DMA_TEIF6))
-#define DMA1_Channel7_IT_Mask ((uint32_t)(DMA_GIF7 | DMA_TCIF7 | DMA_HTIF7 | DMA_TEIF7))
-
-/* DMA2 FLAG mask */
-// Editor's note: Overloaded Definition.
-#define DMA2_FLAG_Mask ((uint32_t)0x10000000)
-
-/* DMA registers Masks */
-#define CFGR_CLEAR_Mask ((uint32_t)0xFFFF800F)
-
-/* ch32v00x_exti.c -----------------------------------------------------------*/
-
-
-/* No interrupt selected */
-#define EXTI_LINENONE ((uint32_t)0x00000)
-
-/* ch32v00x_flash.c ----------------------------------------------------------*/
-
-/* Flash Access Control Register bits */
-#define ACR_LATENCY_Mask ((uint32_t)0x00000038)
-
-/* Flash Control Register bits */
-#define CR_PG_Set ((uint32_t)0x00000001)
-#define CR_PG_Reset ((uint32_t)0xFFFFFFFE)
-#define CR_PER_Set ((uint32_t)0x00000002)
-#define CR_PER_Reset ((uint32_t)0xFFFFFFFD)
-#define CR_MER_Set ((uint32_t)0x00000004)
-#define CR_MER_Reset ((uint32_t)0xFFFFFFFB)
-#define CR_OPTPG_Set ((uint32_t)0x00000010)
-#define CR_OPTPG_Reset ((uint32_t)0xFFFFFFEF)
-#define CR_OPTER_Set ((uint32_t)0x00000020)
-#define CR_OPTER_Reset ((uint32_t)0xFFFFFFDF)
-#define CR_STRT_Set ((uint32_t)0x00000040)
-#define CR_LOCK_Set ((uint32_t)0x00000080)
-#define CR_PAGE_PG ((uint32_t)0x00010000)
-#define CR_PAGE_ER ((uint32_t)0x00020000)
-#define CR_BUF_LOAD ((uint32_t)0x00040000)
-#define CR_BUF_RST ((uint32_t)0x00080000)
-
-/* FLASH Status Register bits */
-#define SR_BSY ((uint32_t)0x00000001)
-#define SR_WRPRTERR ((uint32_t)0x00000010)
-#define SR_EOP ((uint32_t)0x00000020)
-
-/* FLASH Mask */
-#define RDPRT_Mask ((uint32_t)0x00000002)
-#define WRP0_Mask ((uint32_t)0x000000FF)
-#define WRP1_Mask ((uint32_t)0x0000FF00)
-#define WRP2_Mask ((uint32_t)0x00FF0000)
-#define WRP3_Mask ((uint32_t)0xFF000000)
-
-/* FLASH Keys */
-#define RDP_Key ((uint16_t)0x00A5)
-#define FLASH_KEY1 ((uint32_t)0x45670123)
-#define FLASH_KEY2 ((uint32_t)0xCDEF89AB)
-
-/* FLASH BANK address */
-#define FLASH_BANK1_END_ADDRESS ((uint32_t)0x807FFFF)
-
-/* Delay definition */
-#define EraseTimeout ((uint32_t)0x000B0000)
-#define ProgramTimeout ((uint32_t)0x00002000)
-
-/* Flash Program Vaild Address */
-#define ValidAddrStart (FLASH_BASE)
-#define ValidAddrEnd (FLASH_BASE + 0x4000)
-
-/* ch32v00x_i2c.c ------------------------------------------------------------*/
-
-
-/* I2C SPE mask */
-#define CTLR1_PE_Set ((uint16_t)0x0001)
-#define CTLR1_PE_Reset ((uint16_t)0xFFFE)
-
-/* I2C START mask */
-#define CTLR1_START_Set ((uint16_t)0x0100)
-#define CTLR1_START_Reset ((uint16_t)0xFEFF)
-
-/* I2C STOP mask */
-#define CTLR1_STOP_Set ((uint16_t)0x0200)
-#define CTLR1_STOP_Reset ((uint16_t)0xFDFF)
-
-/* I2C ACK mask */
-#define CTLR1_ACK_Set ((uint16_t)0x0400)
-#define CTLR1_ACK_Reset ((uint16_t)0xFBFF)
-
-/* I2C ENGC mask */
-#define CTLR1_ENGC_Set ((uint16_t)0x0040)
-#define CTLR1_ENGC_Reset ((uint16_t)0xFFBF)
-
-/* I2C SWRST mask */
-#define CTLR1_SWRST_Set ((uint16_t)0x8000)
-#define CTLR1_SWRST_Reset ((uint16_t)0x7FFF)
-
-/* I2C PEC mask */
-#define CTLR1_PEC_Set ((uint16_t)0x1000)
-#define CTLR1_PEC_Reset ((uint16_t)0xEFFF)
-
-/* I2C ENPEC mask */
-#define CTLR1_ENPEC_Set ((uint16_t)0x0020)
-#define CTLR1_ENPEC_Reset ((uint16_t)0xFFDF)
-
-/* I2C ENARP mask */
-#define CTLR1_ENARP_Set ((uint16_t)0x0010)
-#define CTLR1_ENARP_Reset ((uint16_t)0xFFEF)
-
-/* I2C NOSTRETCH mask */
-#define CTLR1_NOSTRETCH_Set ((uint16_t)0x0080)
-#define CTLR1_NOSTRETCH_Reset ((uint16_t)0xFF7F)
-
-////* I2C registers Masks */
-// Editor's note: Overloaded Definition.
-#define I2C_CTLR1_CLEAR_Mask ((uint16_t)0xFBF5)
-
-/* I2C DMAEN mask */
-#define CTLR2_DMAEN_Set ((uint16_t)0x0800)
-#define CTLR2_DMAEN_Reset ((uint16_t)0xF7FF)
-
-/* I2C LAST mask */
-#define CTLR2_LAST_Set ((uint16_t)0x1000)
-#define CTLR2_LAST_Reset ((uint16_t)0xEFFF)
-
-/* I2C FREQ mask */
-#define CTLR2_FREQ_Reset ((uint16_t)0xFFC0)
-
-/* I2C ADD0 mask */
-#define OADDR1_ADD0_Set ((uint16_t)0x0001)
-#define OADDR1_ADD0_Reset ((uint16_t)0xFFFE)
-
-/* I2C ENDUAL mask */
-#define OADDR2_ENDUAL_Set ((uint16_t)0x0001)
-#define OADDR2_ENDUAL_Reset ((uint16_t)0xFFFE)
-
-/* I2C ADD2 mask */
-#define OADDR2_ADD2_Reset ((uint16_t)0xFF01)
-
-/* I2C F/S mask */
-#define CKCFGR_FS_Set ((uint16_t)0x8000)
-
-/* I2C CCR mask */
-#define CKCFGR_CCR_Set ((uint16_t)0x0FFF)
-
-/* I2C FLAG mask */
-//Editor's Note: Overloaded Definition
-#define I2c_FLAG_Mask ((uint32_t)0x00FFFFFF)
-
-/* I2C Interrupt Enable mask */
-#define ITEN_Mask ((uint32_t)0x07000000)
-
-/* ch32v00x_iwdg.c -----------------------------------------------------------*/
-
-/* CTLR register bit mask */
-#define CTLR_KEY_Reload ((uint16_t)0xAAAA)
-#define CTLR_KEY_Enable ((uint16_t)0xCCCC)
-
-/* ch32v00x_pwr.c ------------------------------------------------------------*/
-
-
-/* PWR registers bit mask */
-/* CTLR register bit mask */
-#define CTLR_DS_MASK ((uint32_t)0xFFFFFFFD)
-#define CTLR_PLS_MASK ((uint32_t)0xFFFFFF1F)
-#define AWUPSC_MASK ((uint32_t)0xFFFFFFF0)
-#define AWUWR_MASK ((uint32_t)0xFFFFFFC0)
-
-/* ch32v00x_rcc.c ------------------------------------------------------------*/
-
-/* RCC registers bit address in the alias region */
-#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
-
-/* BDCTLR Register */
-#define BDCTLR_OFFSET (RCC_OFFSET + 0x20)
-
-/* RCC registers bit mask */
-
-/* CTLR register bit mask */
-#define CTLR_HSEBYP_Reset ((uint32_t)0xFFFBFFFF)
-#define CTLR_HSEBYP_Set ((uint32_t)0x00040000)
-#define CTLR_HSEON_Reset ((uint32_t)0xFFFEFFFF)
-#define CTLR_HSEON_Set ((uint32_t)0x00010000)
-#define CTLR_HSITRIM_Mask ((uint32_t)0xFFFFFF07)
-
-#define CFGR0_PLL_Mask ((uint32_t)0xFFC0FFFF)
-#define CFGR0_PLLMull_Mask ((uint32_t)0x003C0000)
-#define CFGR0_PLLSRC_Mask ((uint32_t)0x00010000)
-#define CFGR0_PLLXTPRE_Mask ((uint32_t)0x00020000)
-#define CFGR0_SWS_Mask ((uint32_t)0x0000000C)
-#define CFGR0_SW_Mask ((uint32_t)0xFFFFFFFC)
-#define CFGR0_HPRE_Reset_Mask ((uint32_t)0xFFFFFF0F)
-#define CFGR0_HPRE_Set_Mask ((uint32_t)0x000000F0)
-#define CFGR0_PPRE1_Reset_Mask ((uint32_t)0xFFFFF8FF)
-#define CFGR0_PPRE1_Set_Mask ((uint32_t)0x00000700)
-#define CFGR0_PPRE2_Reset_Mask ((uint32_t)0xFFFFC7FF)
-#define CFGR0_PPRE2_Set_Mask ((uint32_t)0x00003800)
-#define CFGR0_ADCPRE_Reset_Mask ((uint32_t)0xFFFF07FF)
-#define CFGR0_ADCPRE_Set_Mask ((uint32_t)0x0000F800)
-
-/* RSTSCKR register bit mask */
-#define RSTSCKR_RMVF_Set ((uint32_t)0x01000000)
-
-/* RCC Flag Mask */
-//Editor's Note: Overloaded Definition
-#define RCC_FLAG_Mask ((uint8_t)0x1F)
-
-/* INTR register byte 2 (Bits[15:8]) base address */
-#define INTR_BYTE2_ADDRESS ((uint32_t)0x40021009)
-
-/* INTR register byte 3 (Bits[23:16]) base address */
-#define INTR_BYTE3_ADDRESS ((uint32_t)0x4002100A)
-
-/* CFGR0 register byte 4 (Bits[31:24]) base address */
-#define CFGR0_BYTE4_ADDRESS ((uint32_t)0x40021007)
-
-/* BDCTLR register base address */
-#define BDCTLR_ADDRESS (PERIPH_BASE + BDCTLR_OFFSET)
-
-static __I uint8_t APBAHBPrescTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8};
-static __I uint8_t ADCPrescTable[20] = {2, 4, 6, 8, 4, 8, 12, 16, 8, 16, 24, 32, 16, 32, 48, 64, 32, 64, 96, 128};
-
-
-/* ch32v00x_spi.c ------------------------------------------------------------*/
-
-
-/* SPI SPE mask */
-#define CTLR1_SPE_Set ((uint16_t)0x0040)
-#define CTLR1_SPE_Reset ((uint16_t)0xFFBF)
-
-/* SPI CRCNext mask */
-#define CTLR1_CRCNext_Set ((uint16_t)0x1000)
-
-/* SPI CRCEN mask */
-#define CTLR1_CRCEN_Set ((uint16_t)0x2000)
-#define CTLR1_CRCEN_Reset ((uint16_t)0xDFFF)
-
-/* SPI SSOE mask */
-#define CTLR2_SSOE_Set ((uint16_t)0x0004)
-#define CTLR2_SSOE_Reset ((uint16_t)0xFFFB)
-
-/* SPI registers Masks */
-//Editor's Note: Overloaded Definition
-#define SPI_CTLR1_CLEAR_Mask ((uint16_t)0x3040)
-#define I2SCFGR_CLEAR_Mask ((uint16_t)0xF040)
-
-
-/* ch32v00x_tim.c ------------------------------------------------------------*/
-
-/* TIM registers bit mask */
-#define SMCFGR_ETR_Mask ((uint16_t)0x00FF)
-#define CHCTLR_Offset ((uint16_t)0x0018)
-#define CCER_CCE_Set ((uint16_t)0x0001)
-#define CCER_CCNE_Set ((uint16_t)0x0004)
-
-/* ch32v00x_usart.c ----------------------------------------------------------*/
-
-/* USART_Private_Defines */
-#define CTLR1_UE_Set ((uint16_t)0x2000) /* USART Enable Mask */
-#define CTLR1_UE_Reset ((uint16_t)0xDFFF) /* USART Disable Mask */
-
-#define CTLR1_WAKE_Mask ((uint16_t)0xF7FF) /* USART WakeUp Method Mask */
-
-#define CTLR1_RWU_Set ((uint16_t)0x0002) /* USART mute mode Enable Mask */
-#define CTLR1_RWU_Reset ((uint16_t)0xFFFD) /* USART mute mode Enable Mask */
-#define CTLR1_SBK_Set ((uint16_t)0x0001) /* USART Break Character send Mask */
-//Editor's Note: Overloaded Definition
-#define USART_CTLR1_CLEAR_Mask ((uint16_t)0xE9F3) /* USART CR1 Mask */
-#define CTLR2_Address_Mask ((uint16_t)0xFFF0) /* USART address Mask */
-
-#define CTLR2_LINEN_Set ((uint16_t)0x4000) /* USART LIN Enable Mask */
-#define CTLR2_LINEN_Reset ((uint16_t)0xBFFF) /* USART LIN Disable Mask */
-
-#define CTLR2_LBDL_Mask ((uint16_t)0xFFDF) /* USART LIN Break detection Mask */
-#define CTLR2_STOP_CLEAR_Mask ((uint16_t)0xCFFF) /* USART CR2 STOP Bits Mask */
-#define CTLR2_CLOCK_CLEAR_Mask ((uint16_t)0xF0FF) /* USART CR2 Clock Mask */
-
-#define CTLR3_SCEN_Set ((uint16_t)0x0020) /* USART SC Enable Mask */
-#define CTLR3_SCEN_Reset ((uint16_t)0xFFDF) /* USART SC Disable Mask */
-
-#define CTLR3_NACK_Set ((uint16_t)0x0010) /* USART SC NACK Enable Mask */
-#define CTLR3_NACK_Reset ((uint16_t)0xFFEF) /* USART SC NACK Disable Mask */
-
-#define CTLR3_HDSEL_Set ((uint16_t)0x0008) /* USART Half-Duplex Enable Mask */
-#define CTLR3_HDSEL_Reset ((uint16_t)0xFFF7) /* USART Half-Duplex Disable Mask */
-
-#define CTLR3_IRLP_Mask ((uint16_t)0xFFFB) /* USART IrDA LowPower mode Mask */
-#define CTLR3_CLEAR_Mask ((uint16_t)0xFCFF) /* USART CR3 Mask */
-
-#define CTLR3_IREN_Set ((uint16_t)0x0002) /* USART IrDA Enable Mask */
-#define CTLR3_IREN_Reset ((uint16_t)0xFFFD) /* USART IrDA Disable Mask */
-#define GPR_LSB_Mask ((uint16_t)0x00FF) /* Guard Time Register LSB Mask */
-#define GPR_MSB_Mask ((uint16_t)0xFF00) /* Guard Time Register MSB Mask */
-#define IT_Mask ((uint16_t)0x001F) /* USART Interrupt Mask */
-
-/* USART OverSampling-8 Mask */
-#define CTLR1_OVER8_Set ((uint16_t)0x8000) /* USART OVER8 mode Enable Mask */
-#define CTLR1_OVER8_Reset ((uint16_t)0x7FFF) /* USART OVER8 mode Disable Mask */
-
-/* USART One Bit Sampling Mask */
-#define CTLR3_ONEBITE_Set ((uint16_t)0x0800) /* USART ONEBITE mode Enable Mask */
-#define CTLR3_ONEBITE_Reset ((uint16_t)0xF7FF) /* USART ONEBITE mode Disable Mask */
-
-/* ch32v00x_wwdg.c ------------------------------------------------------------*/
-
-
-/* CTLR register bit mask */
-#define CTLR_WDGA_Set ((uint32_t)0x00000080)
-
-/* CFGR register bit mask */
-#define CFGR_WDGTB_Mask ((uint32_t)0xFFFFFE7F)
-#define CFGR_W_Mask ((uint32_t)0xFFFFFF80)
-#define BIT_Mask ((uint8_t)0x7F)
-
-
-/* ch32v00x_adc.h ------------------------------------------------------------*/
-
-
-
-/* ADC_mode */
-#define ADC_Mode_Independent ((uint32_t)0x00000000)
-
-/* ADC_external_trigger_sources_for_regular_channels_conversion */
-#define ADC_ExternalTrigConv_T1_TRGO ((uint32_t)0x00000000)
-#define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00020000)
-#define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x00040000)
-#define ADC_ExternalTrigConv_T2_TRGO ((uint32_t)0x00060000)
-#define ADC_ExternalTrigConv_T2_CC1 ((uint32_t)0x00080000)
-#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x000A0000)
-#define ADC_ExternalTrigConv_Ext_PD3_PC2 ((uint32_t)0x000C0000)
-#define ADC_ExternalTrigConv_None ((uint32_t)0x000E0000)
-
-/* ADC_data_align */
-#define ADC_DataAlign_Right ((uint32_t)0x00000000)
-#define ADC_DataAlign_Left ((uint32_t)0x00000800)
-
-/* ADC_channels */
-#define ADC_Channel_0 ((uint8_t)0x00)
-#define ADC_Channel_1 ((uint8_t)0x01)
-#define ADC_Channel_2 ((uint8_t)0x02)
-#define ADC_Channel_3 ((uint8_t)0x03)
-#define ADC_Channel_4 ((uint8_t)0x04)
-#define ADC_Channel_5 ((uint8_t)0x05)
-#define ADC_Channel_6 ((uint8_t)0x06)
-#define ADC_Channel_7 ((uint8_t)0x07)
-#define ADC_Channel_8 ((uint8_t)0x08)
-#define ADC_Channel_9 ((uint8_t)0x09)
-
-#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_8)
-#define ADC_Channel_Vcalint ((uint8_t)ADC_Channel_9)
-
-/* ADC_sampling_time */
-#define ADC_SampleTime_3Cycles ((uint8_t)0x00)
-#define ADC_SampleTime_9Cycles ((uint8_t)0x01)
-#define ADC_SampleTime_15Cycles ((uint8_t)0x02)
-#define ADC_SampleTime_30Cycles ((uint8_t)0x03)
-#define ADC_SampleTime_43Cycles ((uint8_t)0x04)
-#define ADC_SampleTime_57Cycles ((uint8_t)0x05)
-#define ADC_SampleTime_73Cycles ((uint8_t)0x06)
-#define ADC_SampleTime_241Cycles ((uint8_t)0x07)
-
-/* ADC_external_trigger_sources_for_injected_channels_conversion */
-#define ADC_ExternalTrigInjecConv_T1_CC3 ((uint32_t)0x00000000)
-#define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00001000)
-#define ADC_ExternalTrigInjecConv_T2_CC3 ((uint32_t)0x00002000)
-#define ADC_ExternalTrigInjecConv_T2_CC4 ((uint32_t)0x00003000)
-#define ADC_ExternalTrigInjecConv_Ext_PD1_PA2 ((uint32_t)0x00006000)
-#define ADC_ExternalTrigInjecConv_None ((uint32_t)0x00007000)
-
-/* ADC_injected_channel_selection */
-#define ADC_InjectedChannel_1 ((uint8_t)0x14)
-#define ADC_InjectedChannel_2 ((uint8_t)0x18)
-#define ADC_InjectedChannel_3 ((uint8_t)0x1C)
-#define ADC_InjectedChannel_4 ((uint8_t)0x20)
-
-/* ADC_analog_watchdog_selection */
-#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200)
-#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200)
-#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200)
-#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000)
-#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000)
-#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000)
-#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000)
-
-/* ADC_interrupts_definition */
-#define ADC_IT_EOC ((uint16_t)0x0220)
-#define ADC_IT_AWD ((uint16_t)0x0140)
-#define ADC_IT_JEOC ((uint16_t)0x0480)
-
-/* ADC_flags_definition */
-#define ADC_FLAG_AWD ((uint8_t)0x01)
-#define ADC_FLAG_EOC ((uint8_t)0x02)
-#define ADC_FLAG_JEOC ((uint8_t)0x04)
-#define ADC_FLAG_JSTRT ((uint8_t)0x08)
-#define ADC_FLAG_STRT ((uint8_t)0x10)
-
-/* ADC_calibration_voltage_definition */
-#define ADC_CALVOL_50PERCENT ((uint32_t)0x02000000)
-#define ADC_CALVOL_75PERCENT ((uint32_t)0x04000000)
-
-/* ADC_external_trigger_sources_delay_channels_definition */
-#define ADC_ExternalTrigRegul_DLY ((uint32_t)0x00000000)
-#define ADC_ExternalTrigInjec_DLY ((uint32_t)0x00020000)
-
-
-
-/* ch32v00x_dbgmcu.h ---------------------------------------------------------*/
-
-/* CFGR0 Register */
-#define DBGMCU_IWDG_STOP ((uint32_t)0x00000001)
-#define DBGMCU_WWDG_STOP ((uint32_t)0x00000002)
-#define DBGMCU_TIM1_STOP ((uint32_t)0x00000010)
-#define DBGMCU_TIM2_STOP ((uint32_t)0x00000020)
-
-/* ch32v00x_dma.h ------------------------------------------------------------*/
-
-/* DMA_data_transfer_direction */
-#define DMA_DIR_PeripheralDST ((uint32_t)0x00000010)
-#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000)
-
-/* DMA_peripheral_incremented_mode */
-#define DMA_PeripheralInc_Enable ((uint32_t)0x00000040)
-#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000)
-
-/* DMA_memory_incremented_mode */
-#define DMA_MemoryInc_Enable ((uint32_t)0x00000080)
-#define DMA_MemoryInc_Disable ((uint32_t)0x00000000)
-
-/* DMA_peripheral_data_size */
-#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000)
-#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100)
-#define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200)
-
-/* DMA_memory_data_size */
-#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000)
-#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400)
-#define DMA_MemoryDataSize_Word ((uint32_t)0x00000800)
-
-/* DMA_circular_normal_mode */
-#define DMA_Mode_Circular ((uint32_t)0x00000020)
-#define DMA_Mode_Normal ((uint32_t)0x00000000)
-
-/* DMA_priority_level */
-#define DMA_Priority_VeryHigh ((uint32_t)0x00003000)
-#define DMA_Priority_High ((uint32_t)0x00002000)
-#define DMA_Priority_Medium ((uint32_t)0x00001000)
-#define DMA_Priority_Low ((uint32_t)0x00000000)
-
-/* DMA_memory_to_memory */
-#define DMA_M2M_Enable ((uint32_t)0x00004000)
-#define DMA_M2M_Disable ((uint32_t)0x00000000)
-
-/* DMA_interrupts_definition */
-#define DMA_IT_TC ((uint32_t)0x00000002)
-#define DMA_IT_HT ((uint32_t)0x00000004)
-#define DMA_IT_TE ((uint32_t)0x00000008)
-
-#define DMA1_IT_GL1 ((uint32_t)0x00000001)
-#define DMA1_IT_TC1 ((uint32_t)0x00000002)
-#define DMA1_IT_HT1 ((uint32_t)0x00000004)
-#define DMA1_IT_TE1 ((uint32_t)0x00000008)
-#define DMA1_IT_GL2 ((uint32_t)0x00000010)
-#define DMA1_IT_TC2 ((uint32_t)0x00000020)
-#define DMA1_IT_HT2 ((uint32_t)0x00000040)
-#define DMA1_IT_TE2 ((uint32_t)0x00000080)
-#define DMA1_IT_GL3 ((uint32_t)0x00000100)
-#define DMA1_IT_TC3 ((uint32_t)0x00000200)
-#define DMA1_IT_HT3 ((uint32_t)0x00000400)
-#define DMA1_IT_TE3 ((uint32_t)0x00000800)
-#define DMA1_IT_GL4 ((uint32_t)0x00001000)
-#define DMA1_IT_TC4 ((uint32_t)0x00002000)
-#define DMA1_IT_HT4 ((uint32_t)0x00004000)
-#define DMA1_IT_TE4 ((uint32_t)0x00008000)
-#define DMA1_IT_GL5 ((uint32_t)0x00010000)
-#define DMA1_IT_TC5 ((uint32_t)0x00020000)
-#define DMA1_IT_HT5 ((uint32_t)0x00040000)
-#define DMA1_IT_TE5 ((uint32_t)0x00080000)
-#define DMA1_IT_GL6 ((uint32_t)0x00100000)
-#define DMA1_IT_TC6 ((uint32_t)0x00200000)
-#define DMA1_IT_HT6 ((uint32_t)0x00400000)
-#define DMA1_IT_TE6 ((uint32_t)0x00800000)
-#define DMA1_IT_GL7 ((uint32_t)0x01000000)
-#define DMA1_IT_TC7 ((uint32_t)0x02000000)
-#define DMA1_IT_HT7 ((uint32_t)0x04000000)
-#define DMA1_IT_TE7 ((uint32_t)0x08000000)
-
-/* DMA_flags_definition */
-#define DMA1_FLAG_GL1 ((uint32_t)0x00000001)
-#define DMA1_FLAG_TC1 ((uint32_t)0x00000002)
-#define DMA1_FLAG_HT1 ((uint32_t)0x00000004)
-#define DMA1_FLAG_TE1 ((uint32_t)0x00000008)
-#define DMA1_FLAG_GL2 ((uint32_t)0x00000010)
-#define DMA1_FLAG_TC2 ((uint32_t)0x00000020)
-#define DMA1_FLAG_HT2 ((uint32_t)0x00000040)
-#define DMA1_FLAG_TE2 ((uint32_t)0x00000080)
-#define DMA1_FLAG_GL3 ((uint32_t)0x00000100)
-#define DMA1_FLAG_TC3 ((uint32_t)0x00000200)
-#define DMA1_FLAG_HT3 ((uint32_t)0x00000400)
-#define DMA1_FLAG_TE3 ((uint32_t)0x00000800)
-#define DMA1_FLAG_GL4 ((uint32_t)0x00001000)
-#define DMA1_FLAG_TC4 ((uint32_t)0x00002000)
-#define DMA1_FLAG_HT4 ((uint32_t)0x00004000)
-#define DMA1_FLAG_TE4 ((uint32_t)0x00008000)
-#define DMA1_FLAG_GL5 ((uint32_t)0x00010000)
-#define DMA1_FLAG_TC5 ((uint32_t)0x00020000)
-#define DMA1_FLAG_HT5 ((uint32_t)0x00040000)
-#define DMA1_FLAG_TE5 ((uint32_t)0x00080000)
-#define DMA1_FLAG_GL6 ((uint32_t)0x00100000)
-#define DMA1_FLAG_TC6 ((uint32_t)0x00200000)
-#define DMA1_FLAG_HT6 ((uint32_t)0x00400000)
-#define DMA1_FLAG_TE6 ((uint32_t)0x00800000)
-#define DMA1_FLAG_GL7 ((uint32_t)0x01000000)
-#define DMA1_FLAG_TC7 ((uint32_t)0x02000000)
-#define DMA1_FLAG_HT7 ((uint32_t)0x04000000)
-#define DMA1_FLAG_TE7 ((uint32_t)0x08000000)
-
-/* ch32v00x_exti.h -----------------------------------------------------------*/
-
-/* EXTI mode enumeration */
-typedef enum
-{
- EXTI_Mode_Interrupt = 0x00,
- EXTI_Mode_Event = 0x04
-} EXTIMode_TypeDef;
-
-/* EXTI Trigger enumeration */
-typedef enum
-{
- EXTI_Trigger_Rising = 0x08,
- EXTI_Trigger_Falling = 0x0C,
- EXTI_Trigger_Rising_Falling = 0x10
-} EXTITrigger_TypeDef;
-
-/* EXTI_Lines */
-#define EXTI_Line0 ((uint32_t)0x00001) /* External interrupt line 0 */
-#define EXTI_Line1 ((uint32_t)0x00002) /* External interrupt line 1 */
-#define EXTI_Line2 ((uint32_t)0x00004) /* External interrupt line 2 */
-#define EXTI_Line3 ((uint32_t)0x00008) /* External interrupt line 3 */
-#define EXTI_Line4 ((uint32_t)0x00010) /* External interrupt line 4 */
-#define EXTI_Line5 ((uint32_t)0x00020) /* External interrupt line 5 */
-#define EXTI_Line6 ((uint32_t)0x00040) /* External interrupt line 6 */
-#define EXTI_Line7 ((uint32_t)0x00080) /* External interrupt line 7 */
-#define EXTI_Line8 ((uint32_t)0x00100) /* External interrupt line 8 Connected to the PVD Output */
-#define EXTI_Line9 ((uint32_t)0x00200) /* External interrupt line 9 Connected to the PWR Auto Wake-up event*/
-
-
-/* ch32v00x_flash.h ----------------------------------------------------------*/
-
-
-/* FLASH Status */
-typedef enum
-{
- FLASH_BUSY = 1,
- FLASH_ERROR_PG,
- FLASH_ERROR_WRP,
- FLASH_COMPLETE,
- FLASH_TIMEOUT
-} FLASH_Status;
-
-
-/* Flash_Latency */
-#define FLASH_Latency_0 ((uint32_t)0x00000000) /* FLASH Zero Latency cycle */
-#define FLASH_Latency_1 ((uint32_t)0x00000001) /* FLASH One Latency cycle */
-#define FLASH_Latency_2 ((uint32_t)0x00000002) /* FLASH Two Latency cycles */
-
-/* Values to be used with CH32V00x devices (1page = 64Byte) */
-#define FLASH_WRProt_Pages0to15 ((uint32_t)0x00000001) /* CH32 Low and Medium density devices: Write protection of page 0 to 15 */
-#define FLASH_WRProt_Pages16to31 ((uint32_t)0x00000002) /* CH32 Low and Medium density devices: Write protection of page 16 to 31 */
-#define FLASH_WRProt_Pages32to47 ((uint32_t)0x00000004) /* CH32 Low and Medium density devices: Write protection of page 32 to 47 */
-#define FLASH_WRProt_Pages48to63 ((uint32_t)0x00000008) /* CH32 Low and Medium density devices: Write protection of page 48 to 63 */
-#define FLASH_WRProt_Pages64to79 ((uint32_t)0x00000010) /* CH32 Low and Medium density devices: Write protection of page 64 to 79 */
-#define FLASH_WRProt_Pages80to95 ((uint32_t)0x00000020) /* CH32 Low and Medium density devices: Write protection of page 80 to 95 */
-#define FLASH_WRProt_Pages96to111 ((uint32_t)0x00000040) /* CH32 Low and Medium density devices: Write protection of page 96 to 111 */
-#define FLASH_WRProt_Pages112to127 ((uint32_t)0x00000080) /* CH32 Low and Medium density devices: Write protection of page 112 to 127 */
-#define FLASH_WRProt_Pages128to143 ((uint32_t)0x00000100) /* CH32 Medium-density devices: Write protection of page 128 to 143 */
-#define FLASH_WRProt_Pages144to159 ((uint32_t)0x00000200) /* CH32 Medium-density devices: Write protection of page 144 to 159 */
-#define FLASH_WRProt_Pages160to175 ((uint32_t)0x00000400) /* CH32 Medium-density devices: Write protection of page 160 to 175 */
-#define FLASH_WRProt_Pages176to191 ((uint32_t)0x00000800) /* CH32 Medium-density devices: Write protection of page 176 to 191 */
-#define FLASH_WRProt_Pages192to207 ((uint32_t)0x00001000) /* CH32 Medium-density devices: Write protection of page 192 to 207 */
-#define FLASH_WRProt_Pages208to223 ((uint32_t)0x00002000) /* CH32 Medium-density devices: Write protection of page 208 to 223 */
-#define FLASH_WRProt_Pages224to239 ((uint32_t)0x00004000) /* CH32 Medium-density devices: Write protection of page 224 to 239 */
-#define FLASH_WRProt_Pages240to255 ((uint32_t)0x00008000) /* CH32 Medium-density devices: Write protection of page 240 to 255 */
-
-#define FLASH_WRProt_AllPages ((uint32_t)0x0000FFFF) /* Write protection of all Pages */
-
-/* Option_Bytes_IWatchdog */
-#define OB_IWDG_SW ((uint16_t)0x0001) /* Software IWDG selected */
-#define OB_IWDG_HW ((uint16_t)0x0000) /* Hardware IWDG selected */
-
-/* Option_Bytes_nRST_STOP */
-#define OB_STOP_NoRST ((uint16_t)0x0002) /* No reset generated when entering in STOP */
-#define OB_STOP_RST ((uint16_t)0x0000) /* Reset generated when entering in STOP */
-
-/* Option_Bytes_nRST_STDBY */
-#define OB_STDBY_NoRST ((uint16_t)0x0004) /* No reset generated when entering in STANDBY */
-#define OB_STDBY_RST ((uint16_t)0x0000) /* Reset generated when entering in STANDBY */
-
-/* Option_Bytes_RST_ENandDT */
-#define OB_RST_NoEN ((uint16_t)0x0018) /* Reset IO disable (PD7)*/
-#define OB_RST_EN_DT12ms ((uint16_t)0x0010) /* Reset IO enable (PD7) and Ignore delay time 12ms */
-#define OB_RST_EN_DT1ms ((uint16_t)0x0008) /* Reset IO enable (PD7) and Ignore delay time 1ms */
-#define OB_RST_EN_DT128ms ((uint16_t)0x0000) /* Reset IO enable (PD7) and Ignore delay time 128ms */
-
-/* FLASH_Interrupts */
-#define FLASH_IT_ERROR ((uint32_t)0x00000400) /* FPEC error interrupt source */
-#define FLASH_IT_EOP ((uint32_t)0x00001000) /* End of FLASH Operation Interrupt source */
-#define FLASH_IT_BANK1_ERROR FLASH_IT_ERROR /* FPEC BANK1 error interrupt source */
-#define FLASH_IT_BANK1_EOP FLASH_IT_EOP /* End of FLASH BANK1 Operation Interrupt source */
-
-/* FLASH_Flags */
-#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /* FLASH Busy flag */
-#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /* FLASH End of Operation flag */
-#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /* FLASH Write protected error flag */
-#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /* FLASH Option Byte error flag */
-
-#define FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY /* FLASH BANK1 Busy flag*/
-#define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP /* FLASH BANK1 End of Operation flag */
-#define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /* FLASH BANK1 Write protected error flag */
-
-/* System_Reset_Start_Mode */
-#define Start_Mode_USER ((uint32_t)0x00000000)
-#define Start_Mode_BOOT ((uint32_t)0x00004000)
-
-
-/* ch32v00x_gpio.h ------------------------------------------------------------*/
-
-/* Output Maximum frequency selection */
-typedef enum
-{
- GPIO_Speed_10MHz = 1,
- GPIO_Speed_2MHz,
- GPIO_Speed_50MHz
-} GPIOSpeed_TypeDef;
-
-#define GPIO_SPEED_IN 0
-
-#define GPIO_CNF_IN_ANALOG 0
-#define GPIO_CNF_IN_FLOATING 4
-#define GPIO_CNF_IN_PUPD 8
-#define GPIO_CNF_OUT_PP 0
-#define GPIO_CNF_OUT_OD 4
-#define GPIO_CNF_OUT_PP_AF 8
-#define GPIO_CNF_OUT_OD_AF 12
-
-/* Configuration Mode enumeration */
-/*
-typedef enum
-{
- GPIO_Mode_AIN = 0x0,
- GPIO_Mode_IN_FLOATING = 0x04,
- GPIO_Mode_IPD = 0x28,
- GPIO_Mode_IPU = 0x48,
- GPIO_Mode_Out_OD = 0x14,
- GPIO_Mode_Out_PP = 0x10,
- GPIO_Mode_AF_OD = 0x1C,
- GPIO_Mode_AF_PP = 0x18
-} GPIOMode_TypeDef;
-*/
-
-
-/* Bit_SET and Bit_RESET enumeration */
-typedef enum
-{
- Bit_RESET = 0,
- Bit_SET
-} BitAction;
-
-/* GPIO_pins_define */
-#define GPIO_Pin_0 ((uint16_t)0x0001) /* Pin 0 selected */
-#define GPIO_Pin_1 ((uint16_t)0x0002) /* Pin 1 selected */
-#define GPIO_Pin_2 ((uint16_t)0x0004) /* Pin 2 selected */
-#define GPIO_Pin_3 ((uint16_t)0x0008) /* Pin 3 selected */
-#define GPIO_Pin_4 ((uint16_t)0x0010) /* Pin 4 selected */
-#define GPIO_Pin_5 ((uint16_t)0x0020) /* Pin 5 selected */
-#define GPIO_Pin_6 ((uint16_t)0x0040) /* Pin 6 selected */
-#define GPIO_Pin_7 ((uint16_t)0x0080) /* Pin 7 selected */
-#define GPIO_Pin_All ((uint16_t)0xFFFF) /* All pins selected */
-
-/* GPIO_Remap_define */
-#define GPIO_Remap_SPI1 ((uint32_t)0x00000001) /* SPI1 Alternate Function mapping */
-#define GPIO_PartialRemap_I2C1 ((uint32_t)0x10000002) /* I2C1 Partial Alternate Function mapping */
-#define GPIO_FullRemap_I2C1 ((uint32_t)0x10400002) /* I2C1 Full Alternate Function mapping */
-#define GPIO_PartialRemap1_USART1 ((uint32_t)0x80000004) /* USART1 Partial1 Alternate Function mapping */
-#define GPIO_PartialRemap2_USART1 ((uint32_t)0x80200000) /* USART1 Partial2 Alternate Function mapping */
-#define GPIO_FullRemap_USART1 ((uint32_t)0x80200004) /* USART1 Full Alternate Function mapping */
-#define GPIO_PartialRemap1_TIM1 ((uint32_t)0x00160040) /* TIM1 Partial1 Alternate Function mapping */
-#define GPIO_PartialRemap2_TIM1 ((uint32_t)0x00160080) /* TIM1 Partial2 Alternate Function mapping */
-#define GPIO_FullRemap_TIM1 ((uint32_t)0x001600C0) /* TIM1 Full Alternate Function mapping */
-#define GPIO_PartialRemap1_TIM2 ((uint32_t)0x00180100) /* TIM2 Partial1 Alternate Function mapping */
-#define GPIO_PartialRemap2_TIM2 ((uint32_t)0x00180200) /* TIM2 Partial2 Alternate Function mapping */
-#define GPIO_FullRemap_TIM2 ((uint32_t)0x00180300) /* TIM2 Full Alternate Function mapping */
-#define GPIO_Remap_PA1_2 ((uint32_t)0x00008000) /* PA1 and PA2 Alternate Function mapping */
-#define GPIO_Remap_ADC1_ETRGINJ ((uint32_t)0x00200002) /* ADC1 External Trigger Injected Conversion remapping */
-#define GPIO_Remap_ADC1_ETRGREG ((uint32_t)0x00200004) /* ADC1 External Trigger Regular Conversion remapping */
-#define GPIO_Remap_LSI_CAL ((uint32_t)0x00200080) /* LSI calibration Alternate Function mapping */
-#define GPIO_Remap_SDI_Disable ((uint32_t)0x00300400) /* SDI Disabled */
-
-/* GPIO_Port_Sources */
-#define GPIO_PortSourceGPIOA ((uint8_t)0x00)
-#define GPIO_PortSourceGPIOC ((uint8_t)0x02)
-#define GPIO_PortSourceGPIOD ((uint8_t)0x03)
-
-/* GPIO_Pin_sources */
-#define GPIO_PinSource0 ((uint8_t)0x00)
-#define GPIO_PinSource1 ((uint8_t)0x01)
-#define GPIO_PinSource2 ((uint8_t)0x02)
-#define GPIO_PinSource3 ((uint8_t)0x03)
-#define GPIO_PinSource4 ((uint8_t)0x04)
-#define GPIO_PinSource5 ((uint8_t)0x05)
-#define GPIO_PinSource6 ((uint8_t)0x06)
-#define GPIO_PinSource7 ((uint8_t)0x07)
-
-/* ch32v00x_i2c.h ------------------------------------------------------------*/
-
-/* I2C_mode */
-#define I2C_Mode_I2C ((uint16_t)0x0000)
-
-/* I2C_duty_cycle_in_fast_mode */
-#define I2C_DutyCycle_16_9 ((uint16_t)0x4000) /* I2C fast mode Tlow/Thigh = 16/9 */
-#define I2C_DutyCycle_2 ((uint16_t)0xBFFF) /* I2C fast mode Tlow/Thigh = 2 */
-
-/* I2C_acknowledgement */
-#define I2C_Ack_Enable ((uint16_t)0x0400)
-#define I2C_Ack_Disable ((uint16_t)0x0000)
-
-/* I2C_transfer_direction */
-#define I2C_Direction_Transmitter ((uint8_t)0x00)
-#define I2C_Direction_Receiver ((uint8_t)0x01)
-
-/* I2C_acknowledged_address */
-#define I2C_AcknowledgedAddress_7bit ((uint16_t)0x4000)
-#define I2C_AcknowledgedAddress_10bit ((uint16_t)0xC000)
-
-/* I2C_registers */
-#define I2C_Register_CTLR1 ((uint8_t)0x00)
-#define I2C_Register_CTLR2 ((uint8_t)0x04)
-#define I2C_Register_OADDR1 ((uint8_t)0x08)
-#define I2C_Register_OADDR2 ((uint8_t)0x0C)
-#define I2C_Register_DATAR ((uint8_t)0x10)
-#define I2C_Register_STAR1 ((uint8_t)0x14)
-#define I2C_Register_STAR2 ((uint8_t)0x18)
-#define I2C_Register_CKCFGR ((uint8_t)0x1C)
-
-/* I2C_PEC_position */
-#define I2C_PECPosition_Next ((uint16_t)0x0800)
-#define I2C_PECPosition_Current ((uint16_t)0xF7FF)
-
-/* I2C_NACK_position */
-#define I2C_NACKPosition_Next ((uint16_t)0x0800)
-#define I2C_NACKPosition_Current ((uint16_t)0xF7FF)
-
-/* I2C_interrupts_definition */
-#define I2C_IT_BUF ((uint16_t)0x0400)
-#define I2C_IT_EVT ((uint16_t)0x0200)
-#define I2C_IT_ERR ((uint16_t)0x0100)
-
-/* I2C_interrupts_definition */
-#define I2C_IT_PECERR ((uint32_t)0x01001000)
-#define I2C_IT_OVR ((uint32_t)0x01000800)
-#define I2C_IT_AF ((uint32_t)0x01000400)
-#define I2C_IT_ARLO ((uint32_t)0x01000200)
-#define I2C_IT_BERR ((uint32_t)0x01000100)
-#define I2C_IT_TXE ((uint32_t)0x06000080)
-#define I2C_IT_RXNE ((uint32_t)0x06000040)
-#define I2C_IT_STOPF ((uint32_t)0x02000010)
-#define I2C_IT_ADD10 ((uint32_t)0x02000008)
-#define I2C_IT_BTF ((uint32_t)0x02000004)
-#define I2C_IT_ADDR ((uint32_t)0x02000002)
-#define I2C_IT_SB ((uint32_t)0x02000001)
-
-/* SR2 register flags */
-#define I2C_FLAG_DUALF ((uint32_t)0x00800000)
-#define I2C_FLAG_GENCALL ((uint32_t)0x00100000)
-#define I2C_FLAG_TRA ((uint32_t)0x00040000)
-#define I2C_FLAG_BUSY ((uint32_t)0x00020000)
-#define I2C_FLAG_MSL ((uint32_t)0x00010000)
-
-/* SR1 register flags */
-#define I2C_FLAG_PECERR ((uint32_t)0x10001000)
-#define I2C_FLAG_OVR ((uint32_t)0x10000800)
-#define I2C_FLAG_AF ((uint32_t)0x10000400)
-#define I2C_FLAG_ARLO ((uint32_t)0x10000200)
-#define I2C_FLAG_BERR ((uint32_t)0x10000100)
-#define I2C_FLAG_TXE ((uint32_t)0x10000080)
-#define I2C_FLAG_RXNE ((uint32_t)0x10000040)
-#define I2C_FLAG_STOPF ((uint32_t)0x10000010)
-#define I2C_FLAG_ADD10 ((uint32_t)0x10000008)
-#define I2C_FLAG_BTF ((uint32_t)0x10000004)
-#define I2C_FLAG_ADDR ((uint32_t)0x10000002)
-#define I2C_FLAG_SB ((uint32_t)0x10000001)
-
-/****************I2C Master Events (Events grouped in order of communication)********************/
-
-/********************************************************************************************************************
- * @brief Start communicate
- *
- * After master use I2C_GenerateSTART() function sending the START condition,the master
- * has to wait for event 5(the Start condition has been correctly
- * released on the I2C bus ).
- *
- */
-/* EVT5 */
-#define I2C_EVENT_MASTER_MODE_SELECT ((uint32_t)0x00030001) /* BUSY, MSL and SB flag */
-
-/********************************************************************************************************************
- * @brief Address Acknowledge
- *
- * When start condition correctly released on the bus(check EVT5), the
- * master use I2C_Send7bitAddress() function sends the address of the slave(s) with which it will communicate
- * it also determines master as transmitter or Receiver. Then the master has to wait that a slave acknowledges
- * his address. If an acknowledge is sent on the bus, one of the following events will be set:
- *
- *
- *
- * 1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED
- * event is set.
- *
- * 2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED
- * is set
- *
- * 3) In case of 10-Bit addressing mode, the master (after generating the START
- * and checking on EVT5) use I2C_SendData() function send the header of 10-bit addressing mode.
- * Then master wait EVT9. EVT9 means that the 10-bit addressing header has been correctly sent
- * on the bus. Then master should use the function I2C_Send7bitAddress() to send the second part
- * of the 10-bit address (LSB) . Then master should wait for event 6.
- *
- *
- */
-
-/* EVT6 */
-#define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED ((uint32_t)0x00070082) /* BUSY, MSL, ADDR, TXE and TRA flags */
-#define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED ((uint32_t)0x00030002) /* BUSY, MSL and ADDR flags */
-/*EVT9 */
-#define I2C_EVENT_MASTER_MODE_ADDRESS10 ((uint32_t)0x00030008) /* BUSY, MSL and ADD10 flags */
-
-/********************************************************************************************************************
- * @brief Communication events
- *
- * If START condition has generated and slave address
- * been acknowledged. then the master has to check one of the following events for
- * communication procedures:
- *
- * 1) Master Receiver mode: The master has to wait on the event EVT7 then use
- * I2C_ReceiveData() function to read the data received from the slave .
- *
- * 2) Master Transmitter mode: The master use I2C_SendData() function to send data
- * then to wait on event EVT8 or EVT8_2.
- * These two events are similar:
- * - EVT8 means that the data has been written in the data register and is
- * being shifted out.
- * - EVT8_2 means that the data has been physically shifted out and output
- * on the bus.
- * In most cases, using EVT8 is sufficient for the application.
- * Using EVT8_2 will leads to a slower communication speed but will more reliable .
- * EVT8_2 is also more suitable than EVT8 for testing on the last data transmission
- *
- *
- * Note:
- * In case the user software does not guarantee that this event EVT7 is managed before
- * the current byte end of transfer, then user may check on I2C_EVENT_MASTER_BYTE_RECEIVED
- * and I2C_FLAG_BTF flag at the same time .But in this case the communication may be slower.
- *
- *
- */
-
-/* Master Receive mode */
-/* EVT7 */
-#define I2C_EVENT_MASTER_BYTE_RECEIVED ((uint32_t)0x00030040) /* BUSY, MSL and RXNE flags */
-
-/* Master Transmitter mode*/
-/* EVT8 */
-#define I2C_EVENT_MASTER_BYTE_TRANSMITTING ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */
-/* EVT8_2 */
-#define I2C_EVENT_MASTER_BYTE_TRANSMITTED ((uint32_t)0x00070084) /* TRA, BUSY, MSL, TXE and BTF flags */
-
-/******************I2C Slave Events (Events grouped in order of communication)******************/
-
-/********************************************************************************************************************
- * @brief Start Communicate events
- *
- * Wait on one of these events at the start of the communication. It means that
- * the I2C peripheral detected a start condition of master device generate on the bus.
- * If the acknowledge feature is enabled through function I2C_AcknowledgeConfig()),The peripheral generates an ACK condition on the bus.
- *
- *
- *
- * a) In normal case (only one address managed by the slave), when the address
- * sent by the master matches the own address of the peripheral (configured by
- * I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set
- * (where XXX could be TRANSMITTER or RECEIVER).
- *
- * b) In case the address sent by the master matches the second address of the
- * peripheral (configured by the function I2C_OwnAddress2Config() and enabled
- * by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED
- * (where XXX could be TRANSMITTER or RECEIVER) are set.
- *
- * c) In case the address sent by the master is General Call (address 0x00) and
- * if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd())
- * the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED.
- *
- */
-
-/* EVT1 */
-/* a) Case of One Single Address managed by the slave */
-#define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED ((uint32_t)0x00020002) /* BUSY and ADDR flags */
-#define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */
-
-/* b) Case of Dual address managed by the slave */
-#define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED ((uint32_t)0x00820000) /* DUALF and BUSY flags */
-#define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080) /* DUALF, TRA, BUSY and TXE flags */
-
-/* c) Case of General Call enabled for the slave */
-#define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED ((uint32_t)0x00120000) /* GENCALL and BUSY flags */
-
-/********************************************************************************************************************
- * @brief Communication events
- *
- * Wait on one of these events when EVT1 has already been checked :
- *
- * - Slave Receiver mode:
- * - EVT2--The device is expecting to receive a data byte .
- * - EVT4--The device is expecting the end of the communication: master
- * sends a stop condition and data transmission is stopped.
- *
- * - Slave Transmitter mode:
- * - EVT3--When a byte has been transmitted by the slave and the Master is expecting
- * the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and
- * I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. If the user software doesn't guarantee
- * the EVT3 is managed before the current byte end of transfer The second one can optionally
- * be used.
- * - EVT3_2--When the master sends a NACK to tell slave device that data transmission
- * shall end . The slave device has to stop sending
- * data bytes and wait a Stop condition from bus.
- *
- * Note:
- * If the user software does not guarantee that the event 2 is
- * managed before the current byte end of transfer, User may check on I2C_EVENT_SLAVE_BYTE_RECEIVED
- * and I2C_FLAG_BTF flag at the same time .
- * In this case the communication will be slower.
- *
- */
-
-/* Slave Receiver mode*/
-/* EVT2 */
-#define I2C_EVENT_SLAVE_BYTE_RECEIVED ((uint32_t)0x00020040) /* BUSY and RXNE flags */
-/* EVT4 */
-#define I2C_EVENT_SLAVE_STOP_DETECTED ((uint32_t)0x00000010) /* STOPF flag */
-
-/* Slave Transmitter mode -----------------------*/
-/* EVT3 */
-#define I2C_EVENT_SLAVE_BYTE_TRANSMITTED ((uint32_t)0x00060084) /* TRA, BUSY, TXE and BTF flags */
-#define I2C_EVENT_SLAVE_BYTE_TRANSMITTING ((uint32_t)0x00060080) /* TRA, BUSY and TXE flags */
-/*EVT3_2 */
-#define I2C_EVENT_SLAVE_ACK_FAILURE ((uint32_t)0x00000400) /* AF flag */
-
-
-/* ch32v00x_iwdg.h -----------------------------------------------------------*/
-
-/* IWDG_WriteAccess */
-#define IWDG_WriteAccess_Enable ((uint16_t)0x5555)
-#define IWDG_WriteAccess_Disable ((uint16_t)0x0000)
-
-/* IWDG_prescaler */
-#define IWDG_Prescaler_4 ((uint8_t)0x00)
-#define IWDG_Prescaler_8 ((uint8_t)0x01)
-#define IWDG_Prescaler_16 ((uint8_t)0x02)
-#define IWDG_Prescaler_32 ((uint8_t)0x03)
-#define IWDG_Prescaler_64 ((uint8_t)0x04)
-#define IWDG_Prescaler_128 ((uint8_t)0x05)
-#define IWDG_Prescaler_256 ((uint8_t)0x06)
-
-/* IWDG_Flag */
-#define IWDG_FLAG_PVU ((uint16_t)0x0001)
-#define IWDG_FLAG_RVU ((uint16_t)0x0002)
-
-
-/* ch32v00x_misc.h -----------------------------------------------------------*/
-
-/* Preemption_Priority_Group */
-#define NVIC_PriorityGroup_0 ((uint32_t)0x00)
-#define NVIC_PriorityGroup_1 ((uint32_t)0x01)
-#define NVIC_PriorityGroup_2 ((uint32_t)0x02)
-#define NVIC_PriorityGroup_3 ((uint32_t)0x03)
-#define NVIC_PriorityGroup_4 ((uint32_t)0x04)
-
-
-/* ch32v00x_opa.h ------------------------------------------------------------*/
-
-/* Editor's note: I don't know if this is actually useful */
-
-/* OPA PSEL enumeration */
-typedef enum
-{
- CHP0 = 0,
- CHP1
-} OPA_PSEL_TypeDef;
-
-/* OPA NSEL enumeration */
-typedef enum
-{
- CHN0 = 0,
- CHN1
-} OPA_NSEL_TypeDef;
-
-
-/* OPA Init Structure definition */
-typedef struct
-{
- OPA_PSEL_TypeDef PSEL; /* Specifies the positive channel of OPA */
- OPA_NSEL_TypeDef NSEL; /* Specifies the negative channel of OPA */
-} OPA_InitTypeDef;
-
-
-/* ch32v00x_pwr.h ------------------------------------------------------------*/
-
-
-/* PVD_detection_level */
-#define PWR_PVDLevel_2V9 ((uint32_t)0x00000000)
-#define PWR_PVDLevel_3V1 ((uint32_t)0x00000020)
-#define PWR_PVDLevel_3V3 ((uint32_t)0x00000040)
-#define PWR_PVDLevel_3V5 ((uint32_t)0x00000060)
-#define PWR_PVDLevel_3V7 ((uint32_t)0x00000080)
-#define PWR_PVDLevel_3V9 ((uint32_t)0x000000A0)
-#define PWR_PVDLevel_4V1 ((uint32_t)0x000000C0)
-#define PWR_PVDLevel_4V4 ((uint32_t)0x000000E0)
-
-/* PWR_AWU_Prescaler */
-#define PWR_AWU_Prescaler_1 ((uint32_t)0x00000000)
-#define PWR_AWU_Prescaler_2 ((uint32_t)0x00000002)
-#define PWR_AWU_Prescaler_4 ((uint32_t)0x00000003)
-#define PWR_AWU_Prescaler_8 ((uint32_t)0x00000004)
-#define PWR_AWU_Prescaler_16 ((uint32_t)0x00000005)
-#define PWR_AWU_Prescaler_32 ((uint32_t)0x00000006)
-#define PWR_AWU_Prescaler_64 ((uint32_t)0x00000007)
-#define PWR_AWU_Prescaler_128 ((uint32_t)0x00000008)
-#define PWR_AWU_Prescaler_256 ((uint32_t)0x00000009)
-#define PWR_AWU_Prescaler_512 ((uint32_t)0x0000000A)
-#define PWR_AWU_Prescaler_1024 ((uint32_t)0x0000000B)
-#define PWR_AWU_Prescaler_2048 ((uint32_t)0x0000000C)
-#define PWR_AWU_Prescaler_4096 ((uint32_t)0x0000000D)
-#define PWR_AWU_Prescaler_10240 ((uint32_t)0x0000000E)
-#define PWR_AWU_Prescaler_61440 ((uint32_t)0x0000000F)
-
-/* STOP_mode_entry */
-#define PWR_STANDBYEntry_WFI ((uint8_t)0x01)
-#define PWR_STANDBYEntry_WFE ((uint8_t)0x02)
-
-/* PWR_Flag */
-#define PWR_FLAG_PVDO ((uint32_t)0x00000004)
-
-
-/* ch32v00x_rcc.h ------------------------------------------------------------*/
-
-
-/* HSE_configuration */
-#define RCC_HSE_OFF ((uint32_t)0x00000000)
-#define RCC_HSE_ON ((uint32_t)0x00010000)
-#define RCC_HSE_Bypass ((uint32_t)0x00040000)
-
-/* PLL_entry_clock_source */
-#define RCC_PLLSource_HSI_MUL2 ((uint32_t)0x00000000)
-#define RCC_PLLSource_HSE_MUL2 ((uint32_t)0x00030000)
-
-/* System_clock_source */
-#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000)
-#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001)
-#define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002)
-
-/* AHB_clock_source */
-#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000)
-#define RCC_SYSCLK_Div2 ((uint32_t)0x00000010)
-#define RCC_SYSCLK_Div3 ((uint32_t)0x00000020)
-#define RCC_SYSCLK_Div4 ((uint32_t)0x00000030)
-#define RCC_SYSCLK_Div5 ((uint32_t)0x00000040)
-#define RCC_SYSCLK_Div6 ((uint32_t)0x00000050)
-#define RCC_SYSCLK_Div7 ((uint32_t)0x00000060)
-#define RCC_SYSCLK_Div8 ((uint32_t)0x00000070)
-#define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0)
-#define RCC_SYSCLK_Div32 ((uint32_t)0x000000C0)
-#define RCC_SYSCLK_Div64 ((uint32_t)0x000000D0)
-#define RCC_SYSCLK_Div128 ((uint32_t)0x000000E0)
-#define RCC_SYSCLK_Div256 ((uint32_t)0x000000F0)
-
-/* RCC_Interrupt_source */
-#define RCC_IT_LSIRDY ((uint8_t)0x01)
-#define RCC_IT_HSIRDY ((uint8_t)0x04)
-#define RCC_IT_HSERDY ((uint8_t)0x08)
-#define RCC_IT_PLLRDY ((uint8_t)0x10)
-#define RCC_IT_CSS ((uint8_t)0x80)
-
-/* ADC_clock_source */
-#define RCC_PCLK2_Div2 ((uint32_t)0x00000000)
-#define RCC_PCLK2_Div4 ((uint32_t)0x00004000)
-#define RCC_PCLK2_Div6 ((uint32_t)0x00008000)
-#define RCC_PCLK2_Div8 ((uint32_t)0x0000C000)
-#define RCC_PCLK2_Div12 ((uint32_t)0x0000A000)
-#define RCC_PCLK2_Div16 ((uint32_t)0x0000E000)
-#define RCC_PCLK2_Div24 ((uint32_t)0x0000A800)
-#define RCC_PCLK2_Div32 ((uint32_t)0x0000E800)
-#define RCC_PCLK2_Div48 ((uint32_t)0x0000B000)
-#define RCC_PCLK2_Div64 ((uint32_t)0x0000F000)
-#define RCC_PCLK2_Div96 ((uint32_t)0x0000B800)
-#define RCC_PCLK2_Div128 ((uint32_t)0x0000F800)
-
-/* AHB_peripheral */
-#define RCC_AHBPeriph_DMA1 ((uint32_t)0x00000001)
-#define RCC_AHBPeriph_SRAM ((uint32_t)0x00000004)
-
-/* APB2_peripheral */
-#define RCC_APB2Periph_AFIO ((uint32_t)0x00000001)
-#define RCC_APB2Periph_GPIOA ((uint32_t)0x00000004)
-#define RCC_APB2Periph_GPIOC ((uint32_t)0x00000010)
-#define RCC_APB2Periph_GPIOD ((uint32_t)0x00000020)
-#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000200)
-#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000800)
-#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000)
-#define RCC_APB2Periph_USART1 ((uint32_t)0x00004000)
-
-/* APB1_peripheral */
-#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001)
-#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800)
-#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000)
-#define RCC_APB1Periph_PWR ((uint32_t)0x10000000)
-
-/* Clock_source_to_output_on_MCO_pin */
-#define RCC_MCO_NoClock ((uint8_t)0x00)
-#define RCC_MCO_SYSCLK ((uint8_t)0x04)
-#define RCC_MCO_HSI ((uint8_t)0x05)
-#define RCC_MCO_HSE ((uint8_t)0x06)
-#define RCC_MCO_PLLCLK ((uint8_t)0x07)
-
-/* RCC_Flag */
-#define RCC_FLAG_HSIRDY ((uint8_t)0x21)
-#define RCC_FLAG_HSERDY ((uint8_t)0x31)
-#define RCC_FLAG_PLLRDY ((uint8_t)0x39)
-#define RCC_FLAG_LSIRDY ((uint8_t)0x61)
-#define RCC_FLAG_PINRST ((uint8_t)0x7A)
-#define RCC_FLAG_PORRST ((uint8_t)0x7B)
-#define RCC_FLAG_SFTRST ((uint8_t)0x7C)
-#define RCC_FLAG_IWDGRST ((uint8_t)0x7D)
-#define RCC_FLAG_WWDGRST ((uint8_t)0x7E)
-#define RCC_FLAG_LPWRRST ((uint8_t)0x7F)
-
-/* SysTick_clock_source */
-#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB)
-#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004)
-
-
-/* ch32v00x_spi.h ------------------------------------------------------------*/
-
-
-/* SPI_data_direction */
-#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000)
-#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400)
-#define SPI_Direction_1Line_Rx ((uint16_t)0x8000)
-#define SPI_Direction_1Line_Tx ((uint16_t)0xC000)
-
-/* SPI_mode */
-#define SPI_Mode_Master ((uint16_t)0x0104)
-#define SPI_Mode_Slave ((uint16_t)0x0000)
-
-/* SPI_data_size */
-#define SPI_DataSize_16b ((uint16_t)0x0800)
-#define SPI_DataSize_8b ((uint16_t)0x0000)
-
-/* SPI_Clock_Polarity */
-#define SPI_CPOL_Low ((uint16_t)0x0000)
-#define SPI_CPOL_High ((uint16_t)0x0002)
-
-/* SPI_Clock_Phase */
-#define SPI_CPHA_1Edge ((uint16_t)0x0000)
-#define SPI_CPHA_2Edge ((uint16_t)0x0001)
-
-/* SPI_Slave_Select_management */
-#define SPI_NSS_Soft ((uint16_t)0x0200)
-#define SPI_NSS_Hard ((uint16_t)0x0000)
-
-/* SPI_BaudRate_Prescaler */
-#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000)
-#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008)
-#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010)
-#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018)
-#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020)
-#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028)
-#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030)
-#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038)
-
-/* SPI_MSB transmission */
-#define SPI_FirstBit_MSB ((uint16_t)0x0000)
-
-/* SPI_I2S_DMA_transfer_requests */
-#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002)
-#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001)
-
-/* SPI_NSS_internal_software_management */
-#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100)
-#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF)
-
-/* SPI_CRC_Transmit_Receive */
-#define SPI_CRC_Tx ((uint8_t)0x00)
-#define SPI_CRC_Rx ((uint8_t)0x01)
-
-/* SPI_direction_transmit_receive */
-#define SPI_Direction_Rx ((uint16_t)0xBFFF)
-#define SPI_Direction_Tx ((uint16_t)0x4000)
-
-/* SPI_I2S_interrupts_definition */
-#define SPI_I2S_IT_TXE ((uint8_t)0x71)
-#define SPI_I2S_IT_RXNE ((uint8_t)0x60)
-#define SPI_I2S_IT_ERR ((uint8_t)0x50)
-#define SPI_I2S_IT_OVR ((uint8_t)0x56)
-#define SPI_IT_MODF ((uint8_t)0x55)
-#define SPI_IT_CRCERR ((uint8_t)0x54)
-#define I2S_IT_UDR ((uint8_t)0x53)
-
-/* SPI_I2S_flags_definition */
-#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001)
-#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002)
-#define I2S_FLAG_CHSIDE ((uint16_t)0x0004)
-#define I2S_FLAG_UDR ((uint16_t)0x0008)
-#define SPI_FLAG_CRCERR ((uint16_t)0x0010)
-#define SPI_FLAG_MODF ((uint16_t)0x0020)
-#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040)
-#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080)
-
-
-/* ch32v00x_tim.h ------------------------------------------------------------*/
-
-/* TIM_Output_Compare_and_PWM_modes */
-#define TIM_OCMode_Timing ((uint16_t)0x0000)
-#define TIM_OCMode_Active ((uint16_t)0x0010)
-#define TIM_OCMode_Inactive ((uint16_t)0x0020)
-#define TIM_OCMode_Toggle ((uint16_t)0x0030)
-#define TIM_OCMode_PWM1 ((uint16_t)0x0060)
-#define TIM_OCMode_PWM2 ((uint16_t)0x0070)
-
-/* TIM_One_Pulse_Mode */
-#define TIM_OPMode_Single ((uint16_t)0x0008)
-#define TIM_OPMode_Repetitive ((uint16_t)0x0000)
-
-/* TIM_Channel */
-#define TIM_Channel_1 ((uint16_t)0x0000)
-#define TIM_Channel_2 ((uint16_t)0x0004)
-#define TIM_Channel_3 ((uint16_t)0x0008)
-#define TIM_Channel_4 ((uint16_t)0x000C)
-
-/* TIM_Clock_Division_CKD */
-#define TIM_CKD_DIV1 ((uint16_t)0x0000)
-#define TIM_CKD_DIV2 ((uint16_t)0x0100)
-#define TIM_CKD_DIV4 ((uint16_t)0x0200)
-
-/* TIM_Counter_Mode */
-#define TIM_CounterMode_Up ((uint16_t)0x0000)
-#define TIM_CounterMode_Down ((uint16_t)0x0010)
-#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020)
-#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040)
-#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060)
-
-/* TIM_Output_Compare_Polarity */
-#define TIM_OCPolarity_High ((uint16_t)0x0000)
-#define TIM_OCPolarity_Low ((uint16_t)0x0002)
-
-/* TIM_Output_Compare_N_Polarity */
-#define TIM_OCNPolarity_High ((uint16_t)0x0000)
-#define TIM_OCNPolarity_Low ((uint16_t)0x0008)
-
-/* TIM_Output_Compare_state */
-#define TIM_OutputState_Disable ((uint16_t)0x0000)
-#define TIM_OutputState_Enable ((uint16_t)0x0001)
-
-/* TIM_Output_Compare_N_state */
-#define TIM_OutputNState_Disable ((uint16_t)0x0000)
-#define TIM_OutputNState_Enable ((uint16_t)0x0004)
-
-/* TIM_Capture_Compare_state */
-#define TIM_CCx_Enable ((uint16_t)0x0001)
-#define TIM_CCx_Disable ((uint16_t)0x0000)
-
-/* TIM_Capture_Compare_N_state */
-#define TIM_CCxN_Enable ((uint16_t)0x0004)
-#define TIM_CCxN_Disable ((uint16_t)0x0000)
-
-/* Break_Input_enable_disable */
-#define TIM_Break_Enable ((uint16_t)0x1000)
-#define TIM_Break_Disable ((uint16_t)0x0000)
-
-/* Break_Polarity */
-#define TIM_BreakPolarity_Low ((uint16_t)0x0000)
-#define TIM_BreakPolarity_High ((uint16_t)0x2000)
-
-/* TIM_AOE_Bit_Set_Reset */
-#define TIM_AutomaticOutput_Enable ((uint16_t)0x4000)
-#define TIM_AutomaticOutput_Disable ((uint16_t)0x0000)
-
-/* Lock_level */
-#define TIM_LOCKLevel_OFF ((uint16_t)0x0000)
-#define TIM_LOCKLevel_1 ((uint16_t)0x0100)
-#define TIM_LOCKLevel_2 ((uint16_t)0x0200)
-#define TIM_LOCKLevel_3 ((uint16_t)0x0300)
-
-/* OSSI_Off_State_Selection_for_Idle_mode_state */
-#define TIM_OSSIState_Enable ((uint16_t)0x0400)
-#define TIM_OSSIState_Disable ((uint16_t)0x0000)
-
-/* OSSR_Off_State_Selection_for_Run_mode_state */
-#define TIM_OSSRState_Enable ((uint16_t)0x0800)
-#define TIM_OSSRState_Disable ((uint16_t)0x0000)
-
-/* TIM_Output_Compare_Idle_State */
-#define TIM_OCIdleState_Set ((uint16_t)0x0100)
-#define TIM_OCIdleState_Reset ((uint16_t)0x0000)
-
-/* TIM_Output_Compare_N_Idle_State */
-#define TIM_OCNIdleState_Set ((uint16_t)0x0200)
-#define TIM_OCNIdleState_Reset ((uint16_t)0x0000)
-
-/* TIM_Input_Capture_Polarity */
-#define TIM_ICPolarity_Rising ((uint16_t)0x0000)
-#define TIM_ICPolarity_Falling ((uint16_t)0x0002)
-#define TIM_ICPolarity_BothEdge ((uint16_t)0x000A)
-
-/* TIM_Input_Capture_Selection */
-#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /* TIM Input 1, 2, 3 or 4 is selected to be \
- connected to IC1, IC2, IC3 or IC4, respectively */
-#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /* TIM Input 1, 2, 3 or 4 is selected to be \
- connected to IC2, IC1, IC4 or IC3, respectively. */
-#define TIM_ICSelection_TRC ((uint16_t)0x0003) /* TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */
-
-/* TIM_Input_Capture_Prescaler */
-#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /* Capture performed each time an edge is detected on the capture input. */
-#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /* Capture performed once every 2 events. */
-#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /* Capture performed once every 4 events. */
-#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /* Capture performed once every 8 events. */
-
-/* TIM_interrupt_sources */
-#define TIM_IT_Update ((uint16_t)0x0001)
-#define TIM_IT_CC1 ((uint16_t)0x0002)
-#define TIM_IT_CC2 ((uint16_t)0x0004)
-#define TIM_IT_CC3 ((uint16_t)0x0008)
-#define TIM_IT_CC4 ((uint16_t)0x0010)
-#define TIM_IT_COM ((uint16_t)0x0020)
-#define TIM_IT_Trigger ((uint16_t)0x0040)
-#define TIM_IT_Break ((uint16_t)0x0080)
-
-/* TIM_DMA_Base_address */
-#define TIM_DMABase_CR1 ((uint16_t)0x0000)
-#define TIM_DMABase_CR2 ((uint16_t)0x0001)
-#define TIM_DMABase_SMCR ((uint16_t)0x0002)
-#define TIM_DMABase_DIER ((uint16_t)0x0003)
-#define TIM_DMABase_SR ((uint16_t)0x0004)
-#define TIM_DMABase_EGR ((uint16_t)0x0005)
-#define TIM_DMABase_CCMR1 ((uint16_t)0x0006)
-#define TIM_DMABase_CCMR2 ((uint16_t)0x0007)
-#define TIM_DMABase_CCER ((uint16_t)0x0008)
-#define TIM_DMABase_CNT ((uint16_t)0x0009)
-#define TIM_DMABase_PSC ((uint16_t)0x000A)
-#define TIM_DMABase_ARR ((uint16_t)0x000B)
-#define TIM_DMABase_RCR ((uint16_t)0x000C)
-#define TIM_DMABase_CCR1 ((uint16_t)0x000D)
-#define TIM_DMABase_CCR2 ((uint16_t)0x000E)
-#define TIM_DMABase_CCR3 ((uint16_t)0x000F)
-#define TIM_DMABase_CCR4 ((uint16_t)0x0010)
-#define TIM_DMABase_BDTR ((uint16_t)0x0011)
-#define TIM_DMABase_DCR ((uint16_t)0x0012)
-
-/* TIM_DMA_Burst_Length */
-#define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000)
-#define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100)
-#define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200)
-#define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300)
-#define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400)
-#define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500)
-#define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600)
-#define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700)
-#define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800)
-#define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900)
-#define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00)
-#define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00)
-#define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00)
-#define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00)
-#define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00)
-#define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00)
-#define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000)
-#define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100)
-
-/* TIM_DMA_sources */
-#define TIM_DMA_Update ((uint16_t)0x0100)
-#define TIM_DMA_CC1 ((uint16_t)0x0200)
-#define TIM_DMA_CC2 ((uint16_t)0x0400)
-#define TIM_DMA_CC3 ((uint16_t)0x0800)
-#define TIM_DMA_CC4 ((uint16_t)0x1000)
-#define TIM_DMA_COM ((uint16_t)0x2000)
-#define TIM_DMA_Trigger ((uint16_t)0x4000)
-
-/* TIM_External_Trigger_Prescaler */
-#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000)
-#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000)
-#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000)
-#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000)
-
-/* TIM_Internal_Trigger_Selection */
-#define TIM_TS_ITR0 ((uint16_t)0x0000)
-#define TIM_TS_ITR1 ((uint16_t)0x0010)
-#define TIM_TS_ITR2 ((uint16_t)0x0020)
-#define TIM_TS_ITR3 ((uint16_t)0x0030)
-#define TIM_TS_TI1F_ED ((uint16_t)0x0040)
-#define TIM_TS_TI1FP1 ((uint16_t)0x0050)
-#define TIM_TS_TI2FP2 ((uint16_t)0x0060)
-#define TIM_TS_ETRF ((uint16_t)0x0070)
-
-/* TIM_TIx_External_Clock_Source */
-#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050)
-#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060)
-#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040)
-
-/* TIM_External_Trigger_Polarity */
-#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000)
-#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000)
-
-/* TIM_Prescaler_Reload_Mode */
-#define TIM_PSCReloadMode_Update ((uint16_t)0x0000)
-#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001)
-
-/* TIM_Forced_Action */
-#define TIM_ForcedAction_Active ((uint16_t)0x0050)
-#define TIM_ForcedAction_InActive ((uint16_t)0x0040)
-
-/* TIM_Encoder_Mode */
-#define TIM_EncoderMode_TI1 ((uint16_t)0x0001)
-#define TIM_EncoderMode_TI2 ((uint16_t)0x0002)
-#define TIM_EncoderMode_TI12 ((uint16_t)0x0003)
-
-/* TIM_Event_Source */
-#define TIM_EventSource_Update ((uint16_t)0x0001)
-#define TIM_EventSource_CC1 ((uint16_t)0x0002)
-#define TIM_EventSource_CC2 ((uint16_t)0x0004)
-#define TIM_EventSource_CC3 ((uint16_t)0x0008)
-#define TIM_EventSource_CC4 ((uint16_t)0x0010)
-#define TIM_EventSource_COM ((uint16_t)0x0020)
-#define TIM_EventSource_Trigger ((uint16_t)0x0040)
-#define TIM_EventSource_Break ((uint16_t)0x0080)
-
-/* TIM_Update_Source */
-#define TIM_UpdateSource_Global ((uint16_t)0x0000) /* Source of update is the counter overflow/underflow \
- or the setting of UG bit, or an update generation \
- through the slave mode controller. */
-#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /* Source of update is counter overflow/underflow. */
-
-/* TIM_Output_Compare_Preload_State */
-#define TIM_OCPreload_Enable ((uint16_t)0x0008)
-#define TIM_OCPreload_Disable ((uint16_t)0x0000)
-
-/* TIM_Output_Compare_Fast_State */
-#define TIM_OCFast_Enable ((uint16_t)0x0004)
-#define TIM_OCFast_Disable ((uint16_t)0x0000)
-
-/* TIM_Output_Compare_Clear_State */
-#define TIM_OCClear_Enable ((uint16_t)0x0080)
-#define TIM_OCClear_Disable ((uint16_t)0x0000)
-
-/* TIM_Trigger_Output_Source */
-#define TIM_TRGOSource_Reset ((uint16_t)0x0000)
-#define TIM_TRGOSource_Enable ((uint16_t)0x0010)
-#define TIM_TRGOSource_Update ((uint16_t)0x0020)
-#define TIM_TRGOSource_OC1 ((uint16_t)0x0030)
-#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040)
-#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050)
-#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060)
-#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070)
-
-/* TIM_Slave_Mode */
-#define TIM_SlaveMode_Reset ((uint16_t)0x0004)
-#define TIM_SlaveMode_Gated ((uint16_t)0x0005)
-#define TIM_SlaveMode_Trigger ((uint16_t)0x0006)
-#define TIM_SlaveMode_External1 ((uint16_t)0x0007)
-
-/* TIM_Master_Slave_Mode */
-#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080)
-#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000)
-
-/* TIM_Flags */
-#define TIM_FLAG_Update ((uint16_t)0x0001)
-#define TIM_FLAG_CC1 ((uint16_t)0x0002)
-#define TIM_FLAG_CC2 ((uint16_t)0x0004)
-#define TIM_FLAG_CC3 ((uint16_t)0x0008)
-#define TIM_FLAG_CC4 ((uint16_t)0x0010)
-#define TIM_FLAG_COM ((uint16_t)0x0020)
-#define TIM_FLAG_Trigger ((uint16_t)0x0040)
-#define TIM_FLAG_Break ((uint16_t)0x0080)
-#define TIM_FLAG_CC1OF ((uint16_t)0x0200)
-#define TIM_FLAG_CC2OF ((uint16_t)0x0400)
-#define TIM_FLAG_CC3OF ((uint16_t)0x0800)
-#define TIM_FLAG_CC4OF ((uint16_t)0x1000)
-
-/* TIM_Legacy */
-#define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer
-#define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers
-#define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers
-#define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers
-#define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers
-#define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers
-#define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers
-#define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers
-#define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers
-#define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers
-#define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers
-#define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers
-#define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers
-#define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers
-#define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers
-#define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers
-#define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers
-#define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers
-
-
-/* ch32v00x_usart.h ----------------------------------------------------------*/
-
-/* USART_Word_Length */
-#define USART_WordLength_8b ((uint16_t)0x0000)
-#define USART_WordLength_9b ((uint16_t)0x1000)
-
-/* USART_Stop_Bits */
-#define USART_StopBits_1 ((uint16_t)0x0000)
-#define USART_StopBits_0_5 ((uint16_t)0x1000)
-#define USART_StopBits_2 ((uint16_t)0x2000)
-#define USART_StopBits_1_5 ((uint16_t)0x3000)
-
-/* USART_Parity */
-#define USART_Parity_No ((uint16_t)0x0000)
-#define USART_Parity_Even ((uint16_t)0x0400)
-#define USART_Parity_Odd ((uint16_t)0x0600)
-
-/* USART_Mode */
-#define USART_Mode_Rx ((uint16_t)0x0004)
-#define USART_Mode_Tx ((uint16_t)0x0008)
-
-/* USART_Hardware_Flow_Control */
-#define USART_HardwareFlowControl_None ((uint16_t)0x0000)
-#define USART_HardwareFlowControl_RTS ((uint16_t)0x0100)
-#define USART_HardwareFlowControl_CTS ((uint16_t)0x0200)
-#define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300)
-
-/* USART_Clock */
-#define USART_Clock_Disable ((uint16_t)0x0000)
-#define USART_Clock_Enable ((uint16_t)0x0800)
-
-/* USART_Clock_Polarity */
-#define USART_CPOL_Low ((uint16_t)0x0000)
-#define USART_CPOL_High ((uint16_t)0x0400)
-
-/* USART_Clock_Phase */
-#define USART_CPHA_1Edge ((uint16_t)0x0000)
-#define USART_CPHA_2Edge ((uint16_t)0x0200)
-
-/* USART_Last_Bit */
-#define USART_LastBit_Disable ((uint16_t)0x0000)
-#define USART_LastBit_Enable ((uint16_t)0x0100)
-
-/* USART_Interrupt_definition */
-#define USART_IT_PE ((uint16_t)0x0028)
-#define USART_IT_TXE ((uint16_t)0x0727)
-#define USART_IT_TC ((uint16_t)0x0626)
-#define USART_IT_RXNE ((uint16_t)0x0525)
-#define USART_IT_ORE_RX ((uint16_t)0x0325)
-#define USART_IT_IDLE ((uint16_t)0x0424)
-#define USART_IT_LBD ((uint16_t)0x0846)
-#define USART_IT_CTS ((uint16_t)0x096A)
-#define USART_IT_ERR ((uint16_t)0x0060)
-#define USART_IT_ORE_ER ((uint16_t)0x0360)
-#define USART_IT_NE ((uint16_t)0x0260)
-#define USART_IT_FE ((uint16_t)0x0160)
-
-#define USART_IT_ORE USART_IT_ORE_ER
-
-/* USART_DMA_Requests */
-#define USART_DMAReq_Tx ((uint16_t)0x0080)
-#define USART_DMAReq_Rx ((uint16_t)0x0040)
-
-/* USART_WakeUp_methods */
-#define USART_WakeUp_IdleLine ((uint16_t)0x0000)
-#define USART_WakeUp_AddressMark ((uint16_t)0x0800)
-
-/* USART_LIN_Break_Detection_Length */
-#define USART_LINBreakDetectLength_10b ((uint16_t)0x0000)
-#define USART_LINBreakDetectLength_11b ((uint16_t)0x0020)
-
-/* USART_IrDA_Low_Power */
-#define USART_IrDAMode_LowPower ((uint16_t)0x0004)
-#define USART_IrDAMode_Normal ((uint16_t)0x0000)
-
-/* USART_Flags */
-#define USART_FLAG_CTS ((uint16_t)0x0200)
-#define USART_FLAG_LBD ((uint16_t)0x0100)
-#define USART_FLAG_TXE ((uint16_t)0x0080)
-#define USART_FLAG_TC ((uint16_t)0x0040)
-#define USART_FLAG_RXNE ((uint16_t)0x0020)
-#define USART_FLAG_IDLE ((uint16_t)0x0010)
-#define USART_FLAG_ORE ((uint16_t)0x0008)
-#define USART_FLAG_NE ((uint16_t)0x0004)
-#define USART_FLAG_FE ((uint16_t)0x0002)
-#define USART_FLAG_PE ((uint16_t)0x0001)
-
-/* ch32v00x_wwdg.h -----------------------------------------------------------*/
-
-
-/* WWDG_Prescaler */
-#define WWDG_Prescaler_1 ((uint32_t)0x00000000)
-#define WWDG_Prescaler_2 ((uint32_t)0x00000080)
-#define WWDG_Prescaler_4 ((uint32_t)0x00000100)
-#define WWDG_Prescaler_8 ((uint32_t)0x00000180)
-
-
-/* from debug.h/.c ------------------------------------------------------*/
-
-#ifndef __DEBUG_H
-#define __DEBUG_H
-
-// Functions rewritten by cnlohr
-
-#define DELAY_US_TIME (SYSTEM_CORE_CLOCK / 8000000)
-#define DELAY_MS_TIME (SYSTEM_CORE_CLOCK / 8000)
-
-static void DelaySysTick( uint32_t n )
-{
- SysTick->SR &= ~(1 << 0);
- SysTick->CMP = n;
- SysTick->CNT = 0;
- SysTick->CTLR |=(1 << 0);
- while(!(SysTick->SR & (1 << 0)));
- SysTick->CTLR &= ~(1 << 0);
-}
-
-#define Delay_Us(n) DelaySysTick( n * DELAY_US_TIME )
-#define Delay_Ms(n) DelaySysTick( n * DELAY_MS_TIME )
-
-#endif
-
-
-#ifdef __cplusplus
-};
-#endif
-
-
-
-
-
-#endif /* __CH32V00x_CONF_H */
-
-
-
-
-
diff --git a/attic/ch32v003evt/core_riscv.h b/attic/ch32v003evt/core_riscv.h
deleted file mode 100644
index 2e4382d0b8651e0246c2a7eb5619e8809fc9e51e..0000000000000000000000000000000000000000
--- a/attic/ch32v003evt/core_riscv.h
+++ /dev/null
@@ -1,632 +0,0 @@
-/********************************** (C) COPYRIGHT *******************************
- * File Name : core_riscv.h
- * Author : WCH
- * Version : V1.0.0
- * Date : 2022/08/08
- * Description : RISC-V Core Peripheral Access Layer Header File
- *********************************************************************************
- * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
- * Attention: This software (modified or not) and binary are used for
- * microcontroller manufactured by Nanjing Qinheng Microelectronics.
- *******************************************************************************/
-/*
- * NOTE: This file modified by CNLohr to be fully-header-only.
- */
-
-
-#ifndef __CORE_RISCV_H__
-#define __CORE_RISCV_H__
-
-#include <stdint.h>
-
-/* define compiler specific symbols */
-#if defined(__CC_ARM)
- #define __ASM __asm /*!< asm keyword for ARM Compiler */
- #define __INLINE __inline /*!< inline keyword for ARM Compiler */
-
-#elif defined(__ICCARM__)
- #define __ASM __asm /*!< asm keyword for IAR Compiler */
- #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
-
-#elif defined(__GNUC__)
- #define __ASM __asm /*!< asm keyword for GNU Compiler */
- #define __INLINE inline /*!< inline keyword for GNU Compiler */
-
-#elif defined(__TASKING__)
- #define __ASM __asm /*!< asm keyword for TASKING Compiler */
- #define __INLINE inline /*!< inline keyword for TASKING Compiler */
-
-#endif
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* IO definitions */
-#ifdef __cplusplus
- #define __I volatile /*!< defines 'read only' permissions */
-#else
- #define __I volatile const /*!< defines 'read only' permissions */
-#endif
-#define __O volatile /*!< defines 'write only' permissions */
-#define __IO volatile /*!< defines 'read / write' permissions */
-
-/* Standard Peripheral Library old types (maintained for legacy purpose) */
-typedef __I uint32_t vuc32; /* Read Only */
-typedef __I uint16_t vuc16; /* Read Only */
-typedef __I uint8_t vuc8; /* Read Only */
-
-typedef const uint32_t uc32; /* Read Only */
-typedef const uint16_t uc16; /* Read Only */
-typedef const uint8_t uc8; /* Read Only */
-
-typedef __I int32_t vsc32; /* Read Only */
-typedef __I int16_t vsc16; /* Read Only */
-typedef __I int8_t vsc8; /* Read Only */
-
-typedef const int32_t sc32; /* Read Only */
-typedef const int16_t sc16; /* Read Only */
-typedef const int8_t sc8; /* Read Only */
-
-typedef __IO uint32_t vu32;
-typedef __IO uint16_t vu16;
-typedef __IO uint8_t vu8;
-
-typedef uint32_t u32;
-typedef uint16_t u16;
-typedef uint8_t u8;
-
-typedef __IO int32_t vs32;
-typedef __IO int16_t vs16;
-typedef __IO int8_t vs8;
-
-typedef int32_t s32;
-typedef int16_t s16;
-typedef int8_t s8;
-
-typedef enum {NoREADY = 0, READY = !NoREADY} ErrorStatus;
-
-typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
-
-typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
-
-#define RV_STATIC_INLINE static inline
-
-/* memory mapped structure for Program Fast Interrupt Controller (PFIC) */
-typedef struct{
- __I uint32_t ISR[8];
- __I uint32_t IPR[8];
- __IO uint32_t ITHRESDR;
- __IO uint32_t RESERVED;
- __IO uint32_t CFGR;
- __I uint32_t GISR;
- __IO uint8_t VTFIDR[4];
- uint8_t RESERVED0[12];
- __IO uint32_t VTFADDR[4];
- uint8_t RESERVED1[0x90];
- __O uint32_t IENR[8];
- uint8_t RESERVED2[0x60];
- __O uint32_t IRER[8];
- uint8_t RESERVED3[0x60];
- __O uint32_t IPSR[8];
- uint8_t RESERVED4[0x60];
- __O uint32_t IPRR[8];
- uint8_t RESERVED5[0x60];
- __IO uint32_t IACTR[8];
- uint8_t RESERVED6[0xE0];
- __IO uint8_t IPRIOR[256];
- uint8_t RESERVED7[0x810];
- __IO uint32_t SCTLR;
-}PFIC_Type;
-
-/* memory mapped structure for SysTick */
-typedef struct
-{
- __IO uint32_t CTLR;
- __IO uint32_t SR;
- __IO uint32_t CNT;
- uint32_t RESERVED0;
- __IO uint32_t CMP;
- uint32_t RESERVED1;
-}SysTick_Type;
-
-
-#define PFIC ((PFIC_Type *) 0xE000E000 )
-#define NVIC PFIC
-#define NVIC_KEY1 ((uint32_t)0xFA050000)
-#define NVIC_KEY2 ((uint32_t)0xBCAF0000)
-#define NVIC_KEY3 ((uint32_t)0xBEEF0000)
-
-#define SysTick ((SysTick_Type *) 0xE000F000)
-
-
-/*********************************************************************
- * @fn __enable_irq
- *
- * @brief Enable Global Interrupt
- *
- * @return none
- */
-RV_STATIC_INLINE void __enable_irq()
-{
- uint32_t result;
-
- __asm volatile("csrr %0," "mstatus": "=r"(result));
- result |= 0x88;
- __asm volatile ("csrw mstatus, %0" : : "r" (result) );
-}
-
-/*********************************************************************
- * @fn __disable_irq
- *
- * @brief Disable Global Interrupt
- *
- * @return none
- */
-RV_STATIC_INLINE void __disable_irq()
-{
- uint32_t result;
-
- __asm volatile("csrr %0," "mstatus": "=r"(result));
- result &= ~0x88;
- __asm volatile ("csrw mstatus, %0" : : "r" (result) );
-}
-
-/*********************************************************************
- * @fn __NOP
- *
- * @brief nop
- *
- * @return none
- */
-RV_STATIC_INLINE void __NOP()
-{
- __asm volatile ("nop");
-}
-
-/*********************************************************************
- * @fn NVIC_EnableIRQ
- *
- * @brief Disable Interrupt
- *
- * @param IRQn - Interrupt Numbers
- *
- * @return none
- */
-RV_STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
-{
- NVIC->IENR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
-}
-
-/*********************************************************************
- * @fn NVIC_DisableIRQ
- *
- * @brief Disable Interrupt
- *
- * @param IRQn - Interrupt Numbers
- *
- * @return none
- */
-RV_STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
-{
- NVIC->IRER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
-}
-
-/*********************************************************************
- * @fn NVIC_GetStatusIRQ
- *
- * @brief Get Interrupt Enable State
- *
- * @param IRQn - Interrupt Numbers
- *
- * @return 1 - 1: Interrupt Pending Enable
- * 0 - Interrupt Pending Disable
- */
-RV_STATIC_INLINE uint32_t NVIC_GetStatusIRQ(IRQn_Type IRQn)
-{
- return((uint32_t) ((NVIC->ISR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
-}
-
-/*********************************************************************
- * @fn NVIC_GetPendingIRQ
- *
- * @brief Get Interrupt Pending State
- *
- * @param IRQn - Interrupt Numbers
- *
- * @return 1 - 1: Interrupt Pending Enable
- * 0 - Interrupt Pending Disable
- */
-RV_STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{
- return((uint32_t) ((NVIC->IPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
-}
-
-/*********************************************************************
- * @fn NVIC_SetPendingIRQ
- *
- * @brief Set Interrupt Pending
- *
- * @param IRQn - Interrupt Numbers
- *
- * @return none
- */
-RV_STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{
- NVIC->IPSR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
-}
-
-/*********************************************************************
- * @fn NVIC_ClearPendingIRQ
- *
- * @brief Clear Interrupt Pending
- *
- * @param IRQn - Interrupt Numbers
- *
- * @return none
- */
-RV_STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{
- NVIC->IPRR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
-}
-
-/*********************************************************************
- * @fn NVIC_GetActive
- *
- * @brief Get Interrupt Active State
- *
- * @param IRQn - Interrupt Numbers
- *
- * @return 1 - Interrupt Active
- * 0 - Interrupt No Active
- */
-RV_STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
-{
- return((uint32_t)((NVIC->IACTR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
-}
-
-/*********************************************************************
- * @fn NVIC_SetPriority
- *
- * @brief Set Interrupt Priority
- *
- * @param IRQn - Interrupt Numbers
- * priority: bit7 - pre-emption priority
- * bit6 - subpriority
- * bit[5-0] - reserved
- *
- * @return none
- */
-RV_STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint8_t priority)
-{
- NVIC->IPRIOR[(uint32_t)(IRQn)] = priority;
-}
-
-/*********************************************************************
- * @fn __WFI
- *
- * @brief Wait for Interrupt
- *
- * @return none
- */
-__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFI(void)
-{
- NVIC->SCTLR &= ~(1<<3); // wfi
- asm volatile ("wfi");
-}
-
-/*********************************************************************
- * @fn __WFE
- *
- * @brief Wait for Events
- *
- * @return none
- */
-__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFE(void)
-{
- uint32_t t;
-
- t = NVIC->SCTLR;
- NVIC->SCTLR |= (1<<3)|(1<<5); // (wfi->wfe)+(__sev)
- NVIC->SCTLR = (NVIC->SCTLR & ~(1<<5)) | ( t & (1<<5));
- asm volatile ("wfi");
- asm volatile ("wfi");
-}
-
-/*********************************************************************
- * @fn SetVTFIRQ
- *
- * @brief Set VTF Interrupt
- *
- * @param addr - VTF interrupt service function base address.
- * IRQn - Interrupt Numbers
- * num - VTF Interrupt Numbers
- * NewState - DISABLE or ENABLE
- *
- * @return none
- */
-RV_STATIC_INLINE void SetVTFIRQ(uint32_t addr, IRQn_Type IRQn, uint8_t num, FunctionalState NewState){
- if(num > 1) return ;
-
- if (NewState != DISABLE)
- {
- NVIC->VTFIDR[num] = IRQn;
- NVIC->VTFADDR[num] = ((addr&0xFFFFFFFE)|0x1);
- }
- else{
- NVIC->VTFIDR[num] = IRQn;
- NVIC->VTFADDR[num] = ((addr&0xFFFFFFFE)&(~0x1));
- }
-}
-
-/*********************************************************************
- * @fn NVIC_SystemReset
- *
- * @brief Initiate a system reset request
- *
- * @return none
- */
-RV_STATIC_INLINE void NVIC_SystemReset(void)
-{
- NVIC->CFGR = NVIC_KEY3|(1<<7);
-}
-
-
-
-/*********************************************************************
- * @fn __get_MSTATUS
- *
- * @brief Return the Machine Status Register
- *
- * @return mstatus value
- */
-static inline uint32_t __get_MSTATUS(void)
-{
- uint32_t result;
-
- __ASM volatile("csrr %0," "mstatus": "=r"(result));
- return (result);
-}
-
-/*********************************************************************
- * @fn __set_MSTATUS
- *
- * @brief Set the Machine Status Register
- *
- * @param value - set mstatus value
- *
- * @return none
- */
-static inline void __set_MSTATUS(uint32_t value)
-{
- __ASM volatile("csrw mstatus, %0" : : "r"(value));
-}
-
-/*********************************************************************
- * @fn __get_MISA
- *
- * @brief Return the Machine ISA Register
- *
- * @return misa value
- */
-static inline uint32_t __get_MISA(void)
-{
- uint32_t result;
-
- __ASM volatile("csrr %0,""misa" : "=r"(result));
- return (result);
-}
-
-/*********************************************************************
- * @fn __set_MISA
- *
- * @brief Set the Machine ISA Register
- *
- * @param value - set misa value
- *
- * @return none
- */
-static inline void __set_MISA(uint32_t value)
-{
- __ASM volatile("csrw misa, %0" : : "r"(value));
-}
-
-/*********************************************************************
- * @fn __get_MTVEC
- *
- * @brief Return the Machine Trap-Vector Base-Address Register
- *
- * @return mtvec value
- */
-static inline uint32_t __get_MTVEC(void)
-{
- uint32_t result;
-
- __ASM volatile("csrr %0," "mtvec": "=r"(result));
- return (result);
-}
-
-/*********************************************************************
- * @fn __set_MTVEC
- *
- * @brief Set the Machine Trap-Vector Base-Address Register
- *
- * @param value - set mtvec value
- *
- * @return none
- */
-static inline void __set_MTVEC(uint32_t value)
-{
- __ASM volatile("csrw mtvec, %0":: "r"(value));
-}
-
-/*********************************************************************
- * @fn __get_MSCRATCH
- *
- * @brief Return the Machine Seratch Register
- *
- * @return mscratch value
- */
-static inline uint32_t __get_MSCRATCH(void)
-{
- uint32_t result;
-
- __ASM volatile("csrr %0," "mscratch" : "=r"(result));
- return (result);
-}
-
-/*********************************************************************
- * @fn __set_MSCRATCH
- *
- * @brief Set the Machine Seratch Register
- *
- * @param value - set mscratch value
- *
- * @return none
- */
-static inline void __set_MSCRATCH(uint32_t value)
-{
- __ASM volatile("csrw mscratch, %0" : : "r"(value));
-}
-
-/*********************************************************************
- * @fn __get_MEPC
- *
- * @brief Return the Machine Exception Program Register
- *
- * @return mepc value
- */
-static inline uint32_t __get_MEPC(void)
-{
- uint32_t result;
-
- __ASM volatile("csrr %0," "mepc" : "=r"(result));
- return (result);
-}
-
-/*********************************************************************
- * @fn __set_MEPC
- *
- * @brief Set the Machine Exception Program Register
- *
- * @return mepc value
- */
-static inline void __set_MEPC(uint32_t value)
-{
- __ASM volatile("csrw mepc, %0" : : "r"(value));
-}
-
-/*********************************************************************
- * @fn __get_MCAUSE
- *
- * @brief Return the Machine Cause Register
- *
- * @return mcause value
- */
-static inline uint32_t __get_MCAUSE(void)
-{
- uint32_t result;
-
- __ASM volatile("csrr %0," "mcause": "=r"(result));
- return (result);
-}
-
-/*********************************************************************
- * @fn __set_MCAUSE
- *
- * @brief Set the Machine Cause Register
- *
- * @return mcause value
- */
-static inline void __set_MCAUSE(uint32_t value)
-{
- __ASM volatile("csrw mcause, %0":: "r"(value));
-}
-
-/*********************************************************************
- * @fn __get_MVENDORID
- *
- * @brief Return Vendor ID Register
- *
- * @return mvendorid value
- */
-static inline uint32_t __get_MVENDORID(void)
-{
- uint32_t result;
-
- __ASM volatile("csrr %0,""mvendorid": "=r"(result));
- return (result);
-}
-
-/*********************************************************************
- * @fn __get_MARCHID
- *
- * @brief Return Machine Architecture ID Register
- *
- * @return marchid value
- */
-static inline uint32_t __get_MARCHID(void)
-{
- uint32_t result;
-
- __ASM volatile("csrr %0,""marchid": "=r"(result));
- return (result);
-}
-
-/*********************************************************************
- * @fn __get_MIMPID
- *
- * @brief Return Machine Implementation ID Register
- *
- * @return mimpid value
- */
-static inline uint32_t __get_MIMPID(void)
-{
- uint32_t result;
-
- __ASM volatile("csrr %0,""mimpid": "=r"(result));
- return (result);
-}
-
-/*********************************************************************
- * @fn __get_MHARTID
- *
- * @brief Return Hart ID Register
- *
- * @return mhartid value
- */
-static inline uint32_t __get_MHARTID(void)
-{
- uint32_t result;
-
- __ASM volatile("csrr %0,""mhartid": "=r"(result));
- return (result);
-}
-
-/*********************************************************************
- * @fn __get_SP
- *
- * @brief Return SP Register
- *
- * @return SP value
- */
-static inline uint32_t __get_SP(void)
-{
- uint32_t result;
-
- __ASM volatile("mv %0,""sp": "=r"(result):);
- return (result);
-}
-
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif/* __CORE_RISCV_H__ */
-
-
-
-
-
diff --git a/attic/ch32v003evt/embedlibc.c b/attic/ch32v003evt/embedlibc.c
deleted file mode 100644
index e40632bf5985e02a28e69be7fb87438745b40e97..0000000000000000000000000000000000000000
--- a/attic/ch32v003evt/embedlibc.c
+++ /dev/null
@@ -1,649 +0,0 @@
-// Use with newlib headers.
-// Mixture of weblibc, mini-printf and ???
-
-#include <stdio.h>
-#include <string.h>
-#include <stdarg.h>
-#include <limits.h>
-
-int errno;
-int _write(int fd, const char *buf, int size);
-
-int mini_vsnprintf(char *buffer, unsigned int buffer_len, const char *fmt, va_list va);
-int mini_vpprintf(int (*puts)(char* s, int len, void* buf), void* buf, const char *fmt, va_list va);
-
-static int __puts_uart(char *s, int len, void *buf)
-{
- _write( 0, s, len );
- return len;
-}
-
-int printf(const char* format, ...)
-{
- va_list args;
- va_start( args, format );
- int ret_status = mini_vpprintf(__puts_uart, 0, format, args);
- va_end( args );
- return ret_status;
-}
-
-
-/* Some stuff from MUSL
-
-
-----------------------------------------------------------------------
-Copyright © 2005-2020 Rich Felker, et al.
-
-Permission is hereby granted, free of charge, to any person obtaining
-a copy of this software and associated documentation files (the
-"Software"), to deal in the Software without restriction, including
-without limitation the rights to use, copy, modify, merge, publish,
-distribute, sublicense, and/or sell copies of the Software, and to
-permit persons to whom the Software is furnished to do so, subject to
-the following conditions:
-
-The above copyright notice and this permission notice shall be
-included in all copies or substantial portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-----------------------------------------------------------------------
-
-*/
-
-/*
- * mbstate_t is an opaque object to keep conversion state, during multibyte
- * stream conversions. The content must not be referenced by user programs.
- */
-
-#define CURRENT_UTF8 0
-#define IS_CODEUNIT(c) ((unsigned)(c)-0xdf80 < 0x80)
-#define MB_CUR_MAX (CURRENT_UTF8 ? 4 : 1)
-
-typedef void * mbstate_t;
-
-size_t wcrtomb(char *restrict s, wchar_t wc, mbstate_t *restrict st)
-{
- if (!s) return 1;
- if ((unsigned)wc < 0x80) {
- *s = wc;
- return 1;
- } else if (MB_CUR_MAX == 1) {
- if (!IS_CODEUNIT(wc)) {
- errno = 0x02; // EILSEQ
- return -1;
- }
- *s = wc;
- return 1;
- } else if ((unsigned)wc < 0x800) {
- *s++ = 0xc0 | (wc>>6);
- *s = 0x80 | (wc&0x3f);
- return 2;
- } else if ((unsigned)wc < 0xd800 || (unsigned)wc-0xe000 < 0x2000) {
- *s++ = 0xe0 | (wc>>12);
- *s++ = 0x80 | ((wc>>6)&0x3f);
- *s = 0x80 | (wc&0x3f);
- return 3;
- } else if ((unsigned)wc-0x10000 < 0x100000) {
- *s++ = 0xf0 | (wc>>18);
- *s++ = 0x80 | ((wc>>12)&0x3f);
- *s++ = 0x80 | ((wc>>6)&0x3f);
- *s = 0x80 | (wc&0x3f);
- return 4;
- }
- errno = 0x02;//EILSEQ;
- return -1;
-}
-int wctomb(char *s, wchar_t wc)
-{
- if (!s) return 0;
- return wcrtomb(s, wc, 0);
-}
-size_t strlen(const char *s) { const char *a = s;for (; *s; s++);return s-a; }
-size_t strnlen(const char *s, size_t n) { const char *p = memchr(s, 0, n); return p ? p-s : n;}
-void *memset(void *dest, int c, size_t n) { unsigned char *s = dest; for (; n; n--, s++) *s = c; return dest; }
-char *strcpy(char *d, const char *s) { for (; (*d=*s); s++, d++); return d; }
-char *strncpy(char *d, const char *s, size_t n) { for (; n && (*d=*s); n--, s++, d++); return d; }
-int strcmp(const char *l, const char *r)
-{
- for (; *l==*r && *l; l++, r++);
- return *(unsigned char *)l - *(unsigned char *)r;
-}
-int strncmp(const char *_l, const char *_r, size_t n)
-{
- const unsigned char *l=(void *)_l, *r=(void *)_r;
- if (!n--) return 0;
- for (; *l && *r && n && *l == *r ; l++, r++, n--);
- return *l - *r;
-}
-
-static char *twobyte_strstr(const unsigned char *h, const unsigned char *n)
-{
- uint16_t nw = n[0]<<8 | n[1], hw = h[0]<<8 | h[1];
- for (h++; *h && hw != nw; hw = hw<<8 | *++h);
- return *h ? (char *)h-1 : 0;
-}
-
-static char *threebyte_strstr(const unsigned char *h, const unsigned char *n)
-{
- uint32_t nw = (uint32_t)n[0]<<24 | n[1]<<16 | n[2]<<8;
- uint32_t hw = (uint32_t)h[0]<<24 | h[1]<<16 | h[2]<<8;
- for (h+=2; *h && hw != nw; hw = (hw|*++h)<<8);
- return *h ? (char *)h-2 : 0;
-}
-
-static char *fourbyte_strstr(const unsigned char *h, const unsigned char *n)
-{
- uint32_t nw = (uint32_t)n[0]<<24 | n[1]<<16 | n[2]<<8 | n[3];
- uint32_t hw = (uint32_t)h[0]<<24 | h[1]<<16 | h[2]<<8 | h[3];
- for (h+=3; *h && hw != nw; hw = hw<<8 | *++h);
- return *h ? (char *)h-3 : 0;
-}
-
-#define MAX(a,b) ((a)>(b)?(a):(b))
-#define MIN(a,b) ((a)<(b)?(a):(b))
-
-#define BITOP(a,b,op) \
- ((a)[(size_t)(b)/(8*sizeof *(a))] op (size_t)1<<((size_t)(b)%(8*sizeof *(a))))
-
-static char *twoway_strstr(const unsigned char *h, const unsigned char *n)
-{
- const unsigned char *z;
- size_t l, ip, jp, k, p, ms, p0, mem, mem0;
- size_t byteset[32 / sizeof(size_t)] = { 0 };
- size_t shift[256];
-
- /* Computing length of needle and fill shift table */
- for (l=0; n[l] && h[l]; l++)
- BITOP(byteset, n[l], |=), shift[n[l]] = l+1;
- if (n[l]) return 0; /* hit the end of h */
-
- /* Compute maximal suffix */
- ip = -1; jp = 0; k = p = 1;
- while (jp+k<l) {
- if (n[ip+k] == n[jp+k]) {
- if (k == p) {
- jp += p;
- k = 1;
- } else k++;
- } else if (n[ip+k] > n[jp+k]) {
- jp += k;
- k = 1;
- p = jp - ip;
- } else {
- ip = jp++;
- k = p = 1;
- }
- }
- ms = ip;
- p0 = p;
-
- /* And with the opposite comparison */
- ip = -1; jp = 0; k = p = 1;
- while (jp+k<l) {
- if (n[ip+k] == n[jp+k]) {
- if (k == p) {
- jp += p;
- k = 1;
- } else k++;
- } else if (n[ip+k] < n[jp+k]) {
- jp += k;
- k = 1;
- p = jp - ip;
- } else {
- ip = jp++;
- k = p = 1;
- }
- }
- if (ip+1 > ms+1) ms = ip;
- else p = p0;
-
- /* Periodic needle? */
- if (memcmp(n, n+p, ms+1)) {
- mem0 = 0;
- p = MAX(ms, l-ms-1) + 1;
- } else mem0 = l-p;
- mem = 0;
-
- /* Initialize incremental end-of-haystack pointer */
- z = h;
-
- /* Search loop */
- for (;;) {
- /* Update incremental end-of-haystack pointer */
- if (z-h < l) {
- /* Fast estimate for MAX(l,63) */
- size_t grow = l | 63;
- const unsigned char *z2 = memchr(z, 0, grow);
- if (z2) {
- z = z2;
- if (z-h < l) return 0;
- } else z += grow;
- }
-
- /* Check last byte first; advance by shift on mismatch */
- if (BITOP(byteset, h[l-1], &)) {
- k = l-shift[h[l-1]];
- if (k) {
- if (k < mem) k = mem;
- h += k;
- mem = 0;
- continue;
- }
- } else {
- h += l;
- mem = 0;
- continue;
- }
-
- /* Compare right half */
- for (k=MAX(ms+1,mem); n[k] && n[k] == h[k]; k++);
- if (n[k]) {
- h += k-ms;
- mem = 0;
- continue;
- }
- /* Compare left half */
- for (k=ms+1; k>mem && n[k-1] == h[k-1]; k--);
- if (k <= mem) return (char *)h;
- h += p;
- mem = mem0;
- }
-}
-
-char *strstr(const char *h, const char *n)
-{
- /* Return immediately on empty needle */
- if (!n[0]) return (char *)h;
-
- /* Use faster algorithms for short needles */
- h = strchr(h, *n);
- if (!h || !n[1]) return (char *)h;
- if (!h[1]) return 0;
- if (!n[2]) return twobyte_strstr((void *)h, (void *)n);
- if (!h[2]) return 0;
- if (!n[3]) return threebyte_strstr((void *)h, (void *)n);
- if (!h[3]) return 0;
- if (!n[4]) return fourbyte_strstr((void *)h, (void *)n);
-
- return twoway_strstr((void *)h, (void *)n);
-}
-
-char *strchr(const char *s, int c)
-{
- c = (unsigned char)c;
- if (!c) return (char *)s + strlen(s);
- for (; *s && *(unsigned char *)s != c; s++);
- return (char *)s;
-}
-
-
-void *__memrchr(const void *m, int c, size_t n)
-{
- const unsigned char *s = m;
- c = (unsigned char)c;
- while (n--) if (s[n]==c) return (void *)(s+n);
- return 0;
-}
-
-char *strrchr(const char *s, int c)
-{
- return __memrchr(s, c, strlen(s) + 1);
-}
-
-void *memcpy(void *dest, const void *src, size_t n)
-{
- unsigned char *d = dest;
- const unsigned char *s = src;
- for (; n; n--) *d++ = *s++;
- return dest;
-}
-
-int memcmp(const void *vl, const void *vr, size_t n)
-{
- const unsigned char *l=vl, *r=vr;
- for (; n && *l == *r; n--, l++, r++);
- return n ? *l-*r : 0;
-}
-
-
-void *memmove(void *dest, const void *src, size_t n)
-{
- char *d = dest;
- const char *s = src;
-
- if (d==s) return d;
- if ((uintptr_t)s-(uintptr_t)d-n <= -2*n) return memcpy(d, s, n);
-
- if (d<s) {
- for (; n; n--) *d++ = *s++;
- } else {
- while (n) n--, d[n] = s[n];
- }
-
- return dest;
-}
-void *memchr(const void *src, int c, size_t n)
-{
- const unsigned char *s = src;
- c = (unsigned char)c;
- for (; n && *s != c; s++, n--);
- return n ? (void *)s : 0;
-}
-
-int puts(const char *s)
-{
- int sl = strlen( s );
- _write(0, s, sl );
- _write(0, "\n", 1 );
- return sl + 1;
-}
-
-/*
- * The Minimal snprintf() implementation
- *
- * Copyright (c) 2013,2014 Michal Ludvig <michal@logix.cz>
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- * * Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * * Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- * * Neither the name of the auhor nor the names of its contributors
- * may be used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
- * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * ----
- *
- * This is a minimal snprintf() implementation optimised
- * for embedded systems with a very limited program memory.
- * mini_snprintf() doesn't support _all_ the formatting
- * the glibc does but on the other hand is a lot smaller.
- * Here are some numbers from my STM32 project (.bin file size):
- * no snprintf(): 10768 bytes
- * mini snprintf(): 11420 bytes (+ 652 bytes)
- * glibc snprintf(): 34860 bytes (+24092 bytes)
- * Wasting nearly 24kB of memory just for snprintf() on
- * a chip with 32kB flash is crazy. Use mini_snprintf() instead.
- *
- */
-
-#define mini_strlen strlen
-
-static int
-mini_itoa(long value, unsigned int radix, int uppercase, int unsig,
- char *buffer)
-{
- char *pbuffer = buffer;
- int negative = 0;
- int i, len;
-
- /* No support for unusual radixes. */
- if (radix > 16)
- return 0;
-
- if (value < 0 && !unsig) {
- negative = 1;
- value = -value;
- }
-
- /* This builds the string back to front ... */
- do {
- int digit = value % radix;
- *(pbuffer++) = (digit < 10 ? '0' + digit : (uppercase ? 'A' : 'a') + digit - 10);
- value /= radix;
- } while (value > 0);
-
- if (negative)
- *(pbuffer++) = '-';
-
- *(pbuffer) = '\0';
-
- /* ... now we reverse it (could do it recursively but will
- * conserve the stack space) */
- len = (pbuffer - buffer);
- for (i = 0; i < len / 2; i++) {
- char j = buffer[i];
- buffer[i] = buffer[len-i-1];
- buffer[len-i-1] = j;
- }
-
- return len;
-}
-
-static int
-mini_pad(char* ptr, int len, char pad_char, int pad_to, char *buffer)
-{
- int i;
- int overflow = 0;
- char * pbuffer = buffer;
- if(pad_to == 0) pad_to = len;
- if(len > pad_to) {
- len = pad_to;
- overflow = 1;
- }
- for(i = pad_to - len; i > 0; i --) {
- *(pbuffer++) = pad_char;
- }
- for(i = len; i > 0; i --) {
- *(pbuffer++) = *(ptr++);
- }
- len = pbuffer - buffer;
- if(overflow) {
- for (i = 0; i < 3 && pbuffer > buffer; i ++) {
- *(pbuffer-- - 1) = '*';
- }
- }
- return len;
-}
-
-struct mini_buff {
- char *buffer, *pbuffer;
- unsigned int buffer_len;
-};
-
-static int
-_puts(char *s, int len, void *buf)
-{
- if(!buf) return len;
- struct mini_buff *b = buf;
- char * p0 = b->buffer;
- int i;
- /* Copy to buffer */
- for (i = 0; i < len; i++) {
- if(b->pbuffer == b->buffer + b->buffer_len - 1) {
- break;
- }
- *(b->pbuffer ++) = s[i];
- }
- *(b->pbuffer) = 0;
- return b->pbuffer - p0;
-}
-
-#ifdef MINI_PRINTF_ENABLE_OBJECTS
-static int (*mini_handler) (void* data, void* obj, int ch, int lhint, char** bf) = 0;
-static void (*mini_handler_freeor)(void* data, void*) = 0;
-static void * mini_handler_data = 0;
-
-void mini_printf_set_handler(
- void* data,
- int (*handler)(void* data, void* obj, int ch, int len_hint, char** buf),
- void (*freeor)(void* data, void* buf))
-{
- mini_handler = handler;
- mini_handler_freeor = freeor;
- mini_handler_data = data;
-}
-#endif
-
-int
-mini_vsnprintf(char *buffer, unsigned int buffer_len, const char *fmt, va_list va)
-{
- struct mini_buff b;
- b.buffer = buffer;
- b.pbuffer = buffer;
- b.buffer_len = buffer_len;
- if(buffer_len == 0) buffer = (void*) 0;
- int n = mini_vpprintf(_puts, (buffer != (void*)0)?&b:(void*)0, fmt, va);
- if(buffer == (void*) 0) {
- return n;
- }
- return b.pbuffer - b.buffer;
-}
-
-int
-mini_vpprintf(int (*puts)(char* s, int len, void* buf), void* buf, const char *fmt, va_list va)
-{
- char bf[24];
- char bf2[24];
- char ch;
-#ifdef MINI_PRINTF_ENABLE_OBJECTS
- void* obj;
-#endif
- if(puts == (void*)0) {
- /* run puts in counting mode. */
- puts = _puts; buf = (void*)0;
- }
- int n = 0;
- while ((ch=*(fmt++))) {
- int len;
- if (ch!='%') {
- len = 1;
- len = puts(&ch, len, buf);
- } else {
- char pad_char = ' ';
- int pad_to = 0;
- char l = 0;
- char *ptr;
-
- ch=*(fmt++);
-
- /* Zero padding requested */
- if (ch == '0') pad_char = '0';
- while (ch >= '0' && ch <= '9') {
- pad_to = pad_to * 10 + (ch - '0');
- ch=*(fmt++);
- }
- if(pad_to > (signed int) sizeof(bf)) {
- pad_to = sizeof(bf);
- }
- if (ch == 'l') {
- l = 1;
- ch=*(fmt++);
- }
-
- switch (ch) {
- case 0:
- goto end;
- case 'u':
- case 'd':
- if(l) {
- len = mini_itoa(va_arg(va, unsigned long), 10, 0, (ch=='u'), bf2);
- } else {
- if(ch == 'u') {
- len = mini_itoa((unsigned long) va_arg(va, unsigned int), 10, 0, 1, bf2);
- } else {
- len = mini_itoa((long) va_arg(va, int), 10, 0, 0, bf2);
- }
- }
- len = mini_pad(bf2, len, pad_char, pad_to, bf);
- len = puts(bf, len, buf);
- break;
-
- case 'x':
- case 'X':
- if(l) {
- len = mini_itoa(va_arg(va, unsigned long), 16, (ch=='X'), 1, bf2);
- } else {
- len = mini_itoa((unsigned long) va_arg(va, unsigned int), 16, (ch=='X'), 1, bf2);
- }
- len = mini_pad(bf2, len, pad_char, pad_to, bf);
- len = puts(bf, len, buf);
- break;
-
- case 'c' :
- ch = (char)(va_arg(va, int));
- len = mini_pad(&ch, 1, pad_char, pad_to, bf);
- len = puts(bf, len, buf);
- break;
-
- case 's' :
- ptr = va_arg(va, char*);
- len = mini_strlen(ptr);
- if (pad_to > 0) {
- len = mini_pad(ptr, len, pad_char, pad_to, bf);
- len = puts(bf, len, buf);
- } else {
- len = puts(ptr, len, buf);
- }
- break;
-#ifdef MINI_PRINTF_ENABLE_OBJECTS
- case 'O' : /* Object by content (e.g. str) */
- case 'R' : /* Object by representation (e.g. repr)*/
- obj = va_arg(va, void*);
- len = mini_handler(mini_handler_data, obj, ch, pad_to, &ptr);
- if (pad_to > 0) {
- len = mini_pad(ptr, len, pad_char, pad_to, bf);
- len = puts(bf, len, buf);
- } else {
- len = puts(ptr, len, buf);
- }
- mini_handler_freeor(mini_handler_data, ptr);
- break;
-#endif
- default:
- len = 1;
- len = puts(&ch, len, buf);
- break;
- }
- }
- n = n + len;
- }
-end:
- return n;
-}
-
-
-int
-mini_snprintf(char* buffer, unsigned int buffer_len, const char *fmt, ...)
-{
- int ret;
- va_list va;
- va_start(va, fmt);
- ret = mini_vsnprintf(buffer, buffer_len, fmt, va);
- va_end(va);
-
- return ret;
-}
-
-int
-mini_pprintf(int (*puts)(char*s, int len, void* buf), void* buf, const char *fmt, ...)
-{
- int ret;
- va_list va;
- va_start(va, fmt);
- ret = mini_vpprintf(puts, buf, fmt, va);
- va_end(va);
-
- return ret;
-}
-
diff --git a/attic/ch32v003evt/startup_ch32v003.c b/attic/ch32v003evt/startup_ch32v003.c
deleted file mode 100644
index c52564a2609669df550c496950e6d4c421e8f04b..0000000000000000000000000000000000000000
--- a/attic/ch32v003evt/startup_ch32v003.c
+++ /dev/null
@@ -1,193 +0,0 @@
-/*
- C version of CH32V003 Startup .s file from WCH
- This file is public domain where possible or the following where not:
- Copyright 2023 Charles Lohr, under the MIT-x11 or NewBSD licenses, you choose.
-*/
-
-#include <stdint.h>
-#include <ch32v00x.h>
-
-int main() __attribute__((used));
-void SystemInit( void ) __attribute__((used));
-
-void InterruptVector() __attribute__((naked)) __attribute((section(".init"))) __attribute__((used));
-void handle_reset() __attribute__((naked)) __attribute((section(".text.handle_reset"))) __attribute__((used));
-void DefaultIRQHandler( void ) __attribute__((section(".text.vector_handler"))) __attribute__((naked)) __attribute__((used));
-
-extern uint32_t * _sbss;
-extern uint32_t * _ebss;
-extern uint32_t * _data_lma;
-extern uint32_t * _data_vma;
-extern uint32_t * _edata;
-
-
-// If you don't override a specific handler, it will just spin forever.
-void DefaultIRQHandler( void )
-{
- // Infinite Loop
- asm volatile( "1: j 1b" );
-}
-
-// This makes it so that all of the interrupt handlers just alias to
-// DefaultIRQHandler unless they are individually overridden.
-void NMI_Handler( void ) __attribute__((section(".text.vector_handler"))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used));
-void HardFault_Handler( void ) __attribute__((section(".text.vector_handler"))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used));
-void SysTick_Handler( void ) __attribute__((section(".text.vector_handler"))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used));
-void SW_Handler( void ) __attribute__((section(".text.vector_handler"))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used));
-void WWDG_IRQHandler( void ) __attribute__((section(".text.vector_handler"))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used));
-void PVD_IRQHandler( void ) __attribute__((section(".text.vector_handler"))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used));
-void FLASH_IRQHandler( void ) __attribute__((section(".text.vector_handler"))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used));
-void RCC_IRQHandler( void ) __attribute__((section(".text.vector_handler"))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used));
-void EXTI7_0_IRQHandler( void ) __attribute__((section(".text.vector_handler"))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used));
-void AWU_IRQHandler( void ) __attribute__((section(".text.vector_handler"))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used));
-void DMA1_Channel1_IRQHandler( void ) __attribute__((section(".text.vector_handler"))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used));
-void DMA1_Channel2_IRQHandler( void ) __attribute__((section(".text.vector_handler"))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used));
-void DMA1_Channel3_IRQHandler( void ) __attribute__((section(".text.vector_handler"))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used));
-void DMA1_Channel4_IRQHandler( void ) __attribute__((section(".text.vector_handler"))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used));
-void DMA1_Channel5_IRQHandler( void ) __attribute__((section(".text.vector_handler"))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used));
-void DMA1_Channel6_IRQHandler( void ) __attribute__((section(".text.vector_handler"))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used));
-void DMA1_Channel7_IRQHandler( void ) __attribute__((section(".text.vector_handler"))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used));
-void ADC1_IRQHandler( void ) __attribute__((section(".text.vector_handler"))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used));
-void I2C1_EV_IRQHandler( void ) __attribute__((section(".text.vector_handler"))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used));
-void I2C1_ER_IRQHandler( void ) __attribute__((section(".text.vector_handler"))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used));
-void USART1_IRQHandler( void ) __attribute__((section(".text.vector_handler"))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used));
-void SPI1_IRQHandler( void ) __attribute__((section(".text.vector_handler"))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used));
-void TIM1_BRK_IRQHandler( void ) __attribute__((section(".text.vector_handler"))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used));
-void TIM1_UP_IRQHandler( void ) __attribute__((section(".text.vector_handler"))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used));
-void TIM1_TRG_COM_IRQHandler( void ) __attribute__((section(".text.vector_handler"))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used));
-void TIM1_CC_IRQHandler( void ) __attribute__((section(".text.vector_handler"))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used));
-void TIM2_IRQHandler( void ) __attribute__((section(".text.vector_handler"))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used));
-
-void InterruptVector()
-{
- asm volatile( "\n\
- .align 2\n\
- .option norvc;\n\
- j handle_reset\n\
- .word 0\n\
- .word NMI_Handler /* NMI Handler */ \n\
- .word HardFault_Handler /* Hard Fault Handler */ \n\
- .word 0\n\
- .word 0\n\
- .word 0\n\
- .word 0\n\
- .word 0\n\
- .word 0\n\
- .word 0\n\
- .word 0\n\
- .word SysTick_Handler /* SysTick Handler */ \n\
- .word 0\n\
- .word SW_Handler /* SW Handler */ \n\
- .word 0\n\
- /* External Interrupts */ \n\
- .word WWDG_IRQHandler /* Window Watchdog */ \n\
- .word PVD_IRQHandler /* PVD through EXTI Line detect */ \n\
- .word FLASH_IRQHandler /* Flash */ \n\
- .word RCC_IRQHandler /* RCC */ \n\
- .word EXTI7_0_IRQHandler /* EXTI Line 7..0 */ \n\
- .word AWU_IRQHandler /* AWU */ \n\
- .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ \n\
- .word DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */ \n\
- .word DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */ \n\
- .word DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */ \n\
- .word DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */ \n\
- .word DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */ \n\
- .word DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */ \n\
- .word ADC1_IRQHandler /* ADC1 */ \n\
- .word I2C1_EV_IRQHandler /* I2C1 Event */ \n\
- .word I2C1_ER_IRQHandler /* I2C1 Error */ \n\
- .word USART1_IRQHandler /* USART1 */ \n\
- .word SPI1_IRQHandler /* SPI1 */ \n\
- .word TIM1_BRK_IRQHandler /* TIM1 Break */ \n\
- .word TIM1_UP_IRQHandler /* TIM1 Update */ \n\
- .word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation */ \n\
- .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ \n\
- .word TIM2_IRQHandler /* TIM2 */ \n");
-}
-
-
-
-void handle_reset()
-{
- asm volatile( "\n\
-.option push\n\
-.option norelax\n\
- la gp, __global_pointer$\n\
-.option pop\n\
- la sp, _eusrstack\n"
- // Setup the interrupt vector, processor status and INTSYSCR.
-" li t0, 0x80\n\
- csrw mstatus, t0\n\
- li t0, 0x3\n\
- csrw 0x804, t0\n\
- la t0, InterruptVector\n\
- ori t0, t0, 3\n\
- csrw mtvec, t0\n"
- );
-
- // Careful: Use registers to prevent overwriting of self-data.
- // This clears out BSS.
- register uint32_t * tempout = _sbss;
- register uint32_t * tempend = _ebss;
- while( tempout < tempend )
- *(tempout++) = 0;
-
- // Once we get here, it should be safe to execute regular C code.
-
- // Load data section from flash to RAM
- register uint32_t * tempin = _data_lma;
- tempout = _data_vma;
- tempend = _edata;
- while( tempout != tempend )
- *(tempout++) = *(tempin++);
-
- __set_MEPC( (uint32_t)main );
-
- // set mepc to be main as the root app.
- asm volatile( "mret\n" );
-}
-
-void SystemInit48HSI( void )
-{
- // Values lifted from the EVT. There is little to no documentation on what this does.
- RCC->CTLR = RCC_HSION | RCC_PLLON; // Use HSI, but enable PLL.
- RCC->CFGR0 = RCC_HPRE_DIV1 | RCC_PLLSRC_HSI_Mul2; // PLLCLK = HSI * 2 = 48 MHz; HCLK = SYSCLK = APB1
- FLASH->ACTLR = FLASH_ACTLR_LATENCY_1; // 1 Cycle Latency
- RCC->INTR = 0x009F0000; // Clear PLL, CSSC, HSE, HSI and LSI ready flags.
-
- // From SetSysClockTo_48MHZ_HSI
- while((RCC->CTLR & RCC_PLLRDY) == 0); // Wait till PLL is ready
- RCC->CFGR0 = ( RCC->CFGR0 & ((uint32_t)~(RCC_SW))) | (uint32_t)RCC_SW_PLL; // Select PLL as system clock source
- while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08); // Wait till PLL is used as system clock source
-}
-
-void SetupUART( int uartBRR )
-{
- // Enable GPIOD and UART.
- RCC->APB2PCENR |= RCC_APB2Periph_GPIOD | RCC_APB2Periph_USART1;
-
- // Push-Pull, 10MHz Output, GPIO D5, with AutoFunction
- GPIOD->CFGLR &= ~(0xf<<(4*5));
- GPIOD->CFGLR |= (GPIO_Speed_10MHz | GPIO_CNF_OUT_PP_AF)<<(4*5);
-
- // 115200, 8n1. Note if you don't specify a mode, UART remains off even when UE_Set.
- USART1->CTLR1 = USART_WordLength_8b | USART_Parity_No | USART_Mode_Tx;
- USART1->CTLR2 = USART_StopBits_1;
- USART1->CTLR3 = USART_HardwareFlowControl_None;
-
- USART1->BRR = uartBRR;
- USART1->CTLR1 |= CTLR1_UE_Set;
-}
-
-
-// For debug writing to the UART.
-int _write(int fd, char *buf, int size)
-{
- for(int i = 0; i < size; i++){
- while( !(USART1->STATR & USART_FLAG_TC));
- USART1->DATAR = *buf++;
- }
- return size;
-}
-
-
diff --git a/attic/ch32v003evt/system_ch32v00x.h b/attic/ch32v003evt/system_ch32v00x.h
deleted file mode 100644
index 04d516e36e3866d25810a8192b4d265e38c88144..0000000000000000000000000000000000000000
--- a/attic/ch32v003evt/system_ch32v00x.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/********************************** (C) COPYRIGHT *******************************
- * File Name : system_ch32v00x.h
- * Author : WCH
- * Version : V1.0.0
- * Date : 2022/08/08
- * Description : CH32V00x Device Peripheral Access Layer System Header File.
-*********************************************************************************
-* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
-* Attention: This software (modified or not) and binary are used for
-* microcontroller manufactured by Nanjing Qinheng Microelectronics.
-*******************************************************************************/
-#ifndef __SYSTEM_CH32V00x_H
-#define __SYSTEM_CH32V00x_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-// Stub
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__CH32V00x_SYSTEM_H */
-
-
-
diff --git a/attic/cnlohr-notes.txt b/attic/cnlohr-notes.txt
deleted file mode 100644
index 91e28ea9ff88f30c531b8d62a9c7773ceb227d68..0000000000000000000000000000000000000000
--- a/attic/cnlohr-notes.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-
-Overvolting notes:
- * Tests done at 24MHz, no PLL.
- * If running from flash, browns out at around 8V.
- * If running from RAM, can go up to around 10V before it blows up.
- * IN SPITE of PC5/PC6 being listed as FT inputs, Applying about >2.5V higher than VCC will blow up the chip.
- * Trying to run off LDO - still blows up at 10.5V.
diff --git a/attic/dont_use_wch_printf.c b/attic/dont_use_wch_printf.c
deleted file mode 100644
index 8c53e6c05dac2e8b43fdc5c53f0b1786b8c894ab..0000000000000000000000000000000000000000
--- a/attic/dont_use_wch_printf.c
+++ /dev/null
@@ -1,84 +0,0 @@
-#include <stdio.h>
-#include "wch_link_base.h"
-
-// TESTED
-
-int main()
-{
- libusb_device_handle * devh = wch_link_base_setup(1);
-
- // Place part into reset.
- wch_link_command( devh, "\x81\x0d\x01\x01", 4, 0, 0, 0 ); // Reply is: "\x82\x0d\x04\x02\x08\x02\x00"
- // TODO: What in the world is this? It doesn't appear to be needed.
- wch_link_command( devh, "\x81\x0c\x02\x09\x02", 5, 0, 0, 0 ); //Reply is: 820c0101
-
-// // This puts the processor on hold to allow the debugger to run.
-// wch_link_command( devh, "\x81\x0d\x01\x02", 4, 0, 0, 0 ); // Reply: Ignored, 820d050900300500
-
- wch_link_command( devh, "\x81\x0d\x01\x02", 4, 0, 0, 0 );
-
- // Issue reset
-// wch_link_command( devh, "\x81\x0b\x01\x01", 4, 0, 0, 0 );
- // Why does db[1] = 6 appear to be some sort of query?
- // Also 0x0b appears to be a query. But it wrecks up the chip.
- // db[1] = 0xd DOES WRITE TO 0xe0000000. But is it predictable?
- // db[1] = 8 => get some sort of status back. This is VERY INTERESTING
- // db[11]=Get chip status. Only works in reboot mode.
- // DO NOT 0x0f!
-
- // when in pause mode
- // d 0 2 => Go into reset mode,and do more stuff.
- // d 0 10 => Force chip into mode but no preamble.
- // Found one: 0x0d 0x00 0x03 will write something into the data reg when in debug mode.
- // Will write other data into the debug register.
-
- // 0x81, 0x00 = ??? No ops.
- // 0x81, 0x01 = ??? No ops.
- // 0x81, 0x01 = ??? No ops.
- // 0x81, 0x02 = Lots of ops, if in debug mode, wacks chip. If regular, no bug.
- // 0x81, 0x03 = ??? No ops.
- // 0x81, 0x04 = ??? No ops.
- // 0x81, 0x05 = ??? No ops.
- // 0x81, 0x06 = Lots of ops ,no clarity.
- // 0x81, 0x07 = ??? No ops.
- // 0x81, 0x08 = Lots of ops.
- // In debug mode: 82 08 06 00 00 00 00 00 00
- // In run mode: 82 08 06 7f ff ff ff ff 03
- // 0x81, 0x09 = ??? No ops.
- // 0x81, 0x0a = ??? No ops
- // 0x81, 0x0b = Lots of chatter but no go.
- // 0x81, 0x0c = ??? No ops
- // 0x81, 0x0d, 0x00, 0x01 --> Halts in such a way d,1,ff does't unhalt.
- // 0x81, 0x0d, 0x01, 0x01 --> Halts in such a way d,1,ff does't unhalt.
- // 0x81, 0x0d, 0x01, 0x02 --> Normal Halt.
- // 0x81, 0x0d, 0x00, 0x03 --> If in debug mode, will write cdef89ab into f4 (data0)
- // 0x81, 0x0e = ??? No ops
- // 0x81, 0x10 = ??? No ops
- // 0x81, 0x11, 0, 0: ==> 20: 82 0d 04 02 08 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00
- // or sometimes ==> 20: 82 0d 04 02 08 02 00 00 88 b3 bc 48 ff ff ff ff 00 30 05 00
- // Point is 0x11 actually comms with the device in non-reset mode.
- // 0x81, 0x12 = ??? No ops
- // 0x81, 0x13 = ??? No ops
- // 0x81, 0x14 = ??? No ops
- // 0x81, 0x15 = ??? No ops
-
- unsigned char databuff[11] = { 0x81, 0x08, 0x08, 0x07, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
- unsigned char rbuff[1024];
- int i, j;
-// for( i = 0; i < 20; i++ )
-// for( j = 0; j < 20; j++ )
- {
- databuff[2] = i;
- databuff[3] = j;
- int transferred;
- wch_link_command( devh, databuff, 11, &transferred, rbuff, 1024 );
- int k;
- printf( "%d, %d: %d: ", i, j, transferred );
- for( k = 0; k < transferred; k++ ) printf( "%02x ", rbuff[k] );
- printf( "\n" );
- usleep(10000);
- }
-
- // Close out.
- wch_link_command( devh, "\x81\x0d\x01\xff", 4, 0, 0, 0 );
-}
diff --git a/attic/external_crystal_run_from_ram_turbo.c b/attic/external_crystal_run_from_ram_turbo.c
deleted file mode 100644
index 895125285a5c8655773e20d030814416f49d7102..0000000000000000000000000000000000000000
--- a/attic/external_crystal_run_from_ram_turbo.c
+++ /dev/null
@@ -1,54 +0,0 @@
-// Could be defined here, or in the processor defines.
-#define SYSTEM_CORE_CLOCK 24000000
-
-#include "ch32v003fun.h"
-#include <stdio.h>
-
-uint32_t count;
-
-void RamFunction() __attribute__((naked));
-void RamFunction()
-{
- asm volatile("\n\
- li a0, 1 | (1<<4)\n\
- li a1, (1<<16) | (1<<(16+4))\n\
- la a2, 0x40011410\n\
-1:\n\
- c.sw a0, 0(a2)\n\
- c.sw a1, 0(a2)\n\
- c.sw a0, 0(a2)\n\
- c.sw a1, 0(a2)\n\
- c.sw a0, 0(a2)\n\
- c.sw a1, 0(a2)\n\
- c.sw a0, 0(a2)\n\
- c.sw a1, 0(a2)\n\
- j 1b" );
-}
-
-uint8_t rambuffer[128];
-
-int main()
-{
- EXTEN->EXTEN_CTR = EXTEN_LDO_TRIM; // Boost LDO.
- SystemInitHSEPLL( RCC_HSEBYP );
- // When running from RAM appears to go up to about 96MHz.
-
- // Enable GPIOD.
- RCC->APB2PCENR |= RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOC;
-
- // GPIO D0 Push-Pull, 10MHz Output
- GPIOD->CFGLR &= ~(0xf<<(4*0));
- GPIOD->CFGLR |= (GPIO_Speed_10MHz | GPIO_CNF_OUT_PP)<<(4*0);
-
- // GPIO D0 Push-Pull, 10MHz Output
- GPIOD->CFGLR &= ~(0xf<<(4*4));
- GPIOD->CFGLR |= (GPIO_Speed_10MHz | GPIO_CNF_OUT_PP)<<(4*4);
-
- // GPIO D0 Push-Pull, 10MHz Output
- GPIOC->CFGLR &= ~(0xf<<(4*4));
- GPIOC->CFGLR |= (GPIO_Speed_10MHz | GPIO_CNF_OUT_PP)<<(4*4);
-
-memcpy( rambuffer, RamFunction, 128 );
- void (*fn)() = (void*) rambuffer;
- fn();
-}
diff --git a/attic/flashtests/wch_erase.c b/attic/flashtests/wch_erase.c
deleted file mode 100644
index 27722897319cc141b88bbaf0f8a321f1334dfd78..0000000000000000000000000000000000000000
--- a/attic/flashtests/wch_erase.c
+++ /dev/null
@@ -1,18 +0,0 @@
-#include <stdio.h>
-#include "wch_link_base.h"
-
-// UNTESTED
-
-int main()
-{
- uint8_t rbuff[1024];
- libusb_device_handle * devh = wch_link_base_setup(0);
- int transferred;
- int status;
- WCHCHECK( libusb_bulk_transfer( devh, 0x01, "\x81\x02\x01\x01", 4, &transferred, WCHTIMEOUT) );
- WCHCHECK( libusb_bulk_transfer( devh, 0x81, rbuff, 1024, &transferred, 500 ) ); // Ignore respone.
- WCHCHECK( libusb_bulk_transfer( devh, 0x01, "\x81\x0d\x01\x02", 4, &transferred, WCHTIMEOUT) );
- WCHCHECK( libusb_bulk_transfer( devh, 0x81, rbuff, 1024, &transferred, 500 ) ); // Ignore respone.
- WCHCHECK( libusb_bulk_transfer( devh, 0x01, "\x81\x0d\x01\xff", 4, &transferred, WCHTIMEOUT) );
- WCHCHECK( libusb_bulk_transfer( devh, 0x81, rbuff, 1024, &transferred, 500 ) ); // Ignore respone.
-}
diff --git a/attic/flashtests/wch_printf.c b/attic/flashtests/wch_printf.c
deleted file mode 100644
index 1d78ee8befd5eb0d9ea5deb226dabfee5615beec..0000000000000000000000000000000000000000
--- a/attic/flashtests/wch_printf.c
+++ /dev/null
@@ -1,35 +0,0 @@
-#include <stdio.h>
-#include "wch_link_base.h"
-
-// TESTED
-
-int main()
-{
- libusb_device_handle * devh = wch_link_base_setup();
-
- // Issue reset
-// wch_link_command( devh, "\x81\x0b\x01\x01", 4, 0, 0, 0 );
- // Why does db[1] = 6 appear to be some sort of query?
- // Also 0x0b appears to be a query. But it wrecks up the chip.
- // db[1] = 0xd DOES WRITE TO 0xe0000000. But is it predictable?
- // DO NOT 0x0f!
- unsigned char databuff[11] = { 0x81, 0x0d, 0x08, 0x07, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
- unsigned char rbuff[1024];
- int i, j;
- for( i = 1; i < 20; i++ )
- for( j = 1; j < 20; j++ )
- {
- databuff[2] = i;
- databuff[3] = j;
- int transferred;
- wch_link_command( devh, databuff, 11, &transferred, rbuff, 1024 );
- int k;
- printf( "%d, %d: %d: ", i, j, transferred );
- for( k = 0; k < transferred; k++ ) printf( "%02x ", rbuff[k] );
- printf( "\n" );
- usleep(10000);
- }
-
- // Close out.
- wch_link_command( devh, "\x81\x0d\x01\xff", 4, 0, 0, 0 );
-}
diff --git a/attic/flashtests/wch_query.c b/attic/flashtests/wch_query.c
deleted file mode 100644
index 2bab1f74c2761040bda80c2697c230026ebab0f0..0000000000000000000000000000000000000000
--- a/attic/flashtests/wch_query.c
+++ /dev/null
@@ -1,39 +0,0 @@
-#include <stdio.h>
-#include "wch_link_base.h"
-
-// TODO Make me actually query data!
-
-int main()
-{
-
- libusb_device_handle * devh = wch_link_base_setup(0);
- int transferred;
- int status;
- char rbuff[1024];
-
- WCHCHECK( libusb_bulk_transfer( devh, 0x01, "\x81\x06\x01\x01", 4, &transferred, WCHTIMEOUT) );
- WCHCHECK( libusb_bulk_transfer( devh, 0x81, rbuff, 1024, &transferred, 500 ) ); // Ignore respone.
-//"\x82\x06\x01\x02" << back in
-
- WCHCHECK( libusb_bulk_transfer( devh, 0x01, "\x81\x11\x01\x09", 4, &transferred, WCHTIMEOUT) ); // Checkme with BULK_IN
- WCHCHECK( libusb_bulk_transfer( devh, 0x81, rbuff, 1024, &transferred, WCHTIMEOUT) ); // Checkme with BULK_IN
- printf( "Query data: %d\n", transferred );
- int i;
- for( i = 0; i < transferred; i++ )
- {
- printf( "%02x ", (unsigned char)rbuff[i] );
- }
- printf( "\n" );
-
-// Note this is for CH32V003, MCU UID 20-9e-ab-cd-88-b3-bc-84
-//Respone is:
-//"\xff\xff\x00\x10\x20\x9e\xab\xcd\x88\xb3\xbc\x48\xff\xff\xff\xff" \
-
-//"\x00\x30\x05\x00" << Back in. <<<< QUERY DATA.
- WCHCHECK( libusb_bulk_transfer( devh, 0x01, "\x81\x0d\x01\x04", 4, &transferred, WCHTIMEOUT) ); // Odd that it did it twice - maybe something took too long on the proc.
- WCHCHECK( libusb_bulk_transfer( devh, 0x81, rbuff, 1024, &transferred, 500 ) ); // Ignore respone.
-//"\x82\x0d\x01\x03" <<< Streamed back in.
- WCHCHECK( libusb_bulk_transfer( devh, 0x01, "\x81\x0d\x01\xff", 4, &transferred, WCHTIMEOUT) ); // Odd that it did it twice - maybe something took too long on the proc.
- WCHCHECK( libusb_bulk_transfer( devh, 0x81, rbuff, 1024, &transferred, 500 ) ); // Ignore respone.
-//"\x82\x0d\x01\xff" <<< Streamed back in.
-}
diff --git a/attic/flashtests/wch_reset.c b/attic/flashtests/wch_reset.c
deleted file mode 100644
index df8cadb7c3fcd2ab738482b3002260f8787e8a62..0000000000000000000000000000000000000000
--- a/attic/flashtests/wch_reset.c
+++ /dev/null
@@ -1,15 +0,0 @@
-#include <stdio.h>
-#include "wch_link_base.h"
-
-// TESTED
-
-int main()
-{
- libusb_device_handle * devh = wch_link_base_setup(0);
-
- // Issue reset
- wch_link_command( devh, "\x81\x0b\x01\x01", 4, 0, 0, 0 );
-
- // Close out.
- wch_link_command( devh, "\x81\x0d\x01\xff", 4, 0, 0, 0 );
-}
diff --git a/attic/flashtests/wch_write_simple.c b/attic/flashtests/wch_write_simple.c
deleted file mode 100644
index 838a881fd2f9fa19f5fdefe798b31622713b120a..0000000000000000000000000000000000000000
--- a/attic/flashtests/wch_write_simple.c
+++ /dev/null
@@ -1,125 +0,0 @@
-#include <stdio.h>
-#include "wch_link_base.h"
-
-// tested
-// Having some difficulty with the base.
-
-const uint8_t * bootloader = (const uint8_t*)
-"\x21\x11\x22\xca\x26\xc8\x93\x77\x15\x00\x99\xcf\xb7\x06\x67\x45" \
-"\xb7\x27\x02\x40\x93\x86\x36\x12\x37\x97\xef\xcd\xd4\xc3\x13\x07" \
-"\xb7\x9a\xd8\xc3\xd4\xd3\xd8\xd3\x93\x77\x25\x00\x9d\xc7\xb7\x27" \
-"\x02\x40\x98\x4b\xad\x66\x37\x33\x00\x40\x13\x67\x47\x00\x98\xcb" \
-"\x98\x4b\x93\x86\xa6\xaa\x13\x67\x07\x04\x98\xcb\xd8\x47\x05\x8b" \
-"\x63\x16\x07\x10\x98\x4b\x6d\x9b\x98\xcb\x93\x77\x45\x00\xa9\xcb" \
-"\x93\x07\xf6\x03\x99\x83\x2e\xc0\x2d\x63\x81\x76\x3e\xc4\xb7\x32" \
-"\x00\x40\xb7\x27\x02\x40\x13\x03\xa3\xaa\xfd\x16\x98\x4b\xb7\x03" \
-"\x02\x00\x33\x67\x77\x00\x98\xcb\x02\x47\xd8\xcb\x98\x4b\x13\x67" \
-"\x07\x04\x98\xcb\xd8\x47\x05\x8b\x69\xe7\x98\x4b\x75\x8f\x98\xcb" \
-"\x02\x47\x13\x07\x07\x04\x3a\xc0\x22\x47\x7d\x17\x3a\xc4\x79\xf7" \
-"\x93\x77\x85\x00\xf1\xcf\x93\x07\xf6\x03\x2e\xc0\x99\x83\x37\x27" \
-"\x02\x40\x3e\xc4\x1c\x4b\xc1\x66\x2d\x63\xd5\x8f\x1c\xcb\x37\x07" \
-"\x00\x20\x13\x07\x07\x20\xb7\x27\x02\x40\xb7\x03\x08\x00\xb7\x32" \
-"\x00\x40\x13\x03\xa3\xaa\x94\x4b\xb3\xe6\x76\x00\x94\xcb\xd4\x47" \
-"\x85\x8a\xf5\xfe\x82\x46\xba\x84\x37\x04\x04\x00\x36\xc2\xc1\x46" \
-"\x36\xc6\x92\x46\x84\x40\x11\x07\x84\xc2\x94\x4b\xc1\x8e\x94\xcb" \
-"\xd4\x47\x85\x8a\xb1\xea\x92\x46\xba\x84\x91\x06\x36\xc2\xb2\x46" \
-"\xfd\x16\x36\xc6\xf9\xfe\x82\x46\xd4\xcb\x94\x4b\x93\xe6\x06\x04" \
-"\x94\xcb\xd4\x47\x85\x8a\x85\xee\xd4\x47\xc1\x8a\x85\xce\xd8\x47" \
-"\xb7\x06\xf3\xff\xfd\x16\x13\x67\x07\x01\xd8\xc7\x98\x4b\x21\x45" \
-"\x75\x8f\x98\xcb\x52\x44\xc2\x44\x61\x01\x02\x90\x23\x20\xd3\x00" \
-"\xf5\xb5\x23\xa0\x62\x00\x3d\xb7\x23\xa0\x62\x00\x55\xb7\x23\xa0" \
-"\x62\x00\xc1\xb7\x82\x46\x93\x86\x06\x04\x36\xc0\xa2\x46\xfd\x16" \
-"\x36\xc4\xb5\xf2\x98\x4b\xb7\x06\xf3\xff\xfd\x16\x75\x8f\x98\xcb" \
-"\x41\x89\x05\xcd\x2e\xc0\x0d\x06\x02\xc4\x09\x82\xb7\x07\x00\x20" \
-"\x32\xc6\x93\x87\x07\x20\x98\x43\x13\x86\x47\x00\xa2\x47\x82\x46" \
-"\x8a\x07\xb6\x97\x9c\x43\x63\x1c\xf7\x00\xa2\x47\x85\x07\x3e\xc4" \
-"\xa2\x46\x32\x47\xb2\x87\xe3\xe0\xe6\xfe\x01\x45\x61\xb7\x41\x45" \
-"\x51\xb7\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff" \
-"\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff" \
-"\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff";
-
-int bootloader_len = 512;
-
-
-int main( int argc, char ** argv )
-{
- int i;
- int status;
- uint8_t rbuff[1024];
-
- if( argc != 2 )
- {
- fprintf( stderr, "Usage: wch_write_simple [binfile]\n" );
- }
-
- FILE * f = fopen( argv[1], "rb" );
- fseek( f, 0, SEEK_END );
- int len = ftell( f );
- fseek( f, 0, SEEK_SET );
- int padlen = ((len-1) & (~0x3f)) + 0x40;
- char * image = malloc( padlen );
- memset( image, 0xff, padlen );
- status = fread( image, len, 1, f );
- fclose( f );
-
- if( status != 1 )
- {
- fprintf( stderr, "Error: File I/O Fault.\n" );
- return -10;
- }
- if( len > 16384 )
- {
- fprintf( stderr, "Error: Image for CH32V003 too large\n" );
- return -9;
- }
-
- libusb_device_handle * devh = wch_link_base_setup(0);
- int transferred;
- wch_link_command( devh, "\x81\x06\x01\x01", 4, 0, 0, 0 );
- wch_link_command( devh, "\x81\x06\x01\x01", 4, 0, 0, 0 ); // Not sure why but it seems to work better when we request twice.
-
- // This contains the write data quantity, in bytes. (The last 2 octets)
- // Then it just rollllls on in.
- char rksbuff[11] = { 0x81, 0x01, 0x08, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
- rksbuff[9] = len >> 8;
- rksbuff[10] = len & 0xff;
- wch_link_command( devh, rksbuff, 11, 0, 0, 0 );
-
- wch_link_command( devh, "\x81\x02\x01\x05", 4, 0, 0, 0 );
-
- int pplace = 0;
- for( pplace = 0; pplace < bootloader_len; pplace += 64 )
- {
- WCHCHECK( libusb_bulk_transfer( devh, 0x02, (uint8_t*)(bootloader+pplace), 64, &transferred, WCHTIMEOUT ) );
- }
-
- for( i = 0; i < 10; i++ )
- {
- wch_link_command( devh, "\x81\x02\x01\x07", 4, &transferred, rbuff, 1024 );
- if( transferred == 4 && rbuff[0] == 0x82 && rbuff[1] == 0x02 && rbuff[2] == 0x01 && rbuff[3] == 0x07 )
- {
- break;
- }
- }
- if( i == 10 )
- {
- fprintf( stderr, "Error, confusing respones to 02/01/07\n" );
- exit( -109 );
- }
-
- wch_link_command( devh, "\x81\x02\x01\x02", 4, 0, 0, 0 );
-
- for( pplace = 0; pplace < padlen; pplace += 64 )
- {
- WCHCHECK( libusb_bulk_transfer( devh, 0x02,image+pplace, 64, &transferred, WCHTIMEOUT ) );
- }
-
- // Waiting or something on 2.46.2??????? I don't know why the main system does this.
-// WCHCHECK( libusb_bulk_transfer( devh, 0x82, rbuff, 1024, &transferred, 2000 ) ); // Ignore respone.
-
- // Issue reset (this is optional)
- wch_link_command( devh, "\x81\x0b\x01\x01", 4, 0, 0, 0 );
-
- // Closeout
- wch_link_command( devh, "\x81\x0d\x01\xff", 4, 0, 0, 0);
-}
diff --git a/attic/on-wire-protocol-notes.txt b/attic/on-wire-protocol-notes.txt
deleted file mode 100644
index 70580c59c14ade0947c77f3e1eb1a15366168ffe..0000000000000000000000000000000000000000
--- a/attic/on-wire-protocol-notes.txt
+++ /dev/null
@@ -1,175 +0,0 @@
-Genearl Procedure:
-
-Watch the signal.
- -> One wire
- -> Measure timing
- -> Count bulk numbers of bits?
- -> Is it encoded funny
- -> Same timing for several bits?
- -> Same number of edges for bits?
- -> Write out 1's and 0's
- -> Find a "counting" thing to discover MSBit first.
- -> Write it out in Notepad++
- -> Look for which bits change and which ones don't.
- -> Seeing slight variations on timing to identify whether it's host or client talking.
- This is with Part ID 20-9e-ab-cd-88-b3-bc-48 <<
- -> By knowing the part ID we can search for it in what we think are the replies from the chip.
- -> Once found we can make more sense of the rest of the protocol.
- -> Also, look at the USB protocol to the WCH-Link
- -> Ok, that was worthless.
- -> Try running the programmer without a processor connected.
- -> wow! Turns out the processor doesn't "send data back"
- -> Instead, the host drives a line low then goes high-z
- -> Then the chip decides to "drive the line high" if it's a 1.
-
-
-There is an initial training pattern.
-
-Start with line high.
-
-FIRST:
- low for 8.2us
- high for 3.1us
- low for 9.2us
- high for 3.1us
- low for 102.3us
- high for 95.3us
-
-Then repeat this, 199 times
- low for 4.07s
- high for 3.1us
- low for 8.26us
- high for 3.1us
- low for 9.3us
- high for 3.1us
- low for 102.3us
- high for 95.1us
-
-Then, repeat this 10x
- low for 4.1us
- high for 210us
- low for 6.3us
- high for 2us
- low for 8.4us
- high for 2us
- low for 6.2us
- high for 2.4us
- low for 5.2us
- high for 2.1us
- low for 62.3us
- high for 2.1us
- low for 8.5us
- high for 5.3us
- low for 2us
- high for 8.4us
- low for 6.3us
- high for 2.1us
- low for 8.4us
- high for 2.1us
- low for 6.9us
- high for 1.7us
- low for 5.3us
- high for 2.1us
- low for 63.3us
- high for 2.1us
- low for 8.4us
- high for 5.3us
- low for 2us
- high for 5.8us
- low for 6.3us
- high for 2.1us
- low for 6.3us
- high for 2.1us
- low for 8us
- high for 1.6us
- low for 6.6us
- high for 80us << Actually this goes "high-z" the last time. The target chip will drive it high if present until... <This doesn't seem to be crucial>
-
-
-low for 2us
-high for 5.3us
-
-then the break.
-
-
-*** 2ms low break ***
-
-
-line goes high for 620ns and BOOM we begin our session.
-
-Then, there is a one-wire like protocol for data comms. Thanks, Spirit.
-
-Sending data goes:
- 0: on-for-250-ns off-for-1000-ns
- 1: on-for-250-ns off-for-250-ns
-
-For replies from the processor:
- The clocking is still controlled by the host.
- The host drives the line low, goes high Z with pull-up.
- The processor can drive the line low for this period to indicate a 0.
- 0: on-for-320us off-for-790ns / Total: 1100ns
- 1: on-for-320us off-for-420ns / Total: 740ns
-
-
-"/" indicates flip to chip instead of programmer
-
-Then the data starts.
-
-"Issue Chip Reset":
-
-11 1111101 01011010 10100101 00000100 00000000
-11 1111011 01011010 10100101 00000100 00000000
-11 1111000/00000000 00000001 00000100 00000011 << I thought this was "turned around" but it seems the main uc controls the clocking and it's up to the uc to drive high.
-1 0010001 0/00000000 01001111 00000011 10000010
-1 0010000 1 10000000 00000000 00000000 00000001
-1 0010000 1 10000000 00000000 00000000 00000001
-1 0010110 0/00001000 00000000 00000000 00000010
---
-10 0100010/00000000 01001111 00000011 10000010
-11 1111110/00000000 00110000 00000101 00000000
-10 0001011 00011111 11111111 11110111 11000100
-10 0101111 00000000 00000100 00000000 00000000
-10 0001000/00000000 00110000 00000101 00000000
-10 0001001 00000000 00000000 00000011 00000111
-10 0101111 00000000 00100011 00000111 11000000
---
-10 0001011 00011111 11111111 11110111 11100000
-10 0101111 00000000 00000100 00000000 00000000
-10 0001000/11111111 11111111 00000000 00010000 <<<< CAPACITY First 4 bytes of the response from "\x81\x11\x01\x09"
-10 0001011 00011111 11111111 11110111 11101000
-10 0101111 00000000 00000100 00000000 00000000
-10 0001000/00100000 10011110 10101011 11001101 <<<< CHIP UID
-10 0001011 00011111 11111111 11110111 11101100
-10 0101111 00000000 00000100 00000000 00000000
-10 0001000/10001000 10110011 10111100 01001000 <<<< CHIP UID
-10 0001011 00011111 11111111 11110111 11110000
-10 0101111 00000000 00000100 00000000 00000000
-10 0001000/00000000 00000000 00000000 00000000 *** UNSURE ABOUT THIS LINE >> Actually probably all 1's ***
-10 0001011 00011111 11111111 11110111 11000100
-10 0101111 00000000 00000100 00000000 00000000
-10 0001000/00000000 00110000 00000101 00000000
-
-10 0100010 00000000 01001111 00000011 10000010
-10 0100011 00000000 00000000 00000000 00000001
-10 0100001 10000000 00000000 00000000 00000001
-10 0101100 00001000 00000000 00000000 00000010
-
-10 0100010 00000000 01001111 00000011 10000010
-10 0001011 11100000 00000000 11100000 01001000
-10 0001001 10111110 11101111 00000000 10000000
-10 1000001 01111011 00100101 00010000 01110011
-10 1000011 01111011 00110101 10010000 01110011
-10 1000101 11100000 00000000 00000101 00110111
-10 1000111 00001111 10000101 00100101 10000011
-10 1001011 00100101 01110011 11000001 10001000
-10 1001101 00100101 11110011 01111011 00100000
-10 1001111 10010000 00000010 01111011 00110000
-10 0101111 00000000 00000100 00000000 00000000
-
-
-wch_link_command( devh, "\x81\x0d\x01\xff", 4, 0, 0, 0);
-10 0100001 01000000 00000000 00000000 00000001
-10 0100001 01000000 00000000 00000000 00000000
-10 0100010 00000000 01001100 00001100 10000010
-
-
diff --git a/attic/wch_dump_flash.c b/attic/wch_dump_flash.c
deleted file mode 100644
index 5105e09399ef15581f916d891c2945e3a937528b..0000000000000000000000000000000000000000
--- a/attic/wch_dump_flash.c
+++ /dev/null
@@ -1,54 +0,0 @@
-#include <stdio.h>
-#include "wch_link_base.h"
-
-// TODO Make me actually query data!
-
-int main()
-{
- int i;
- int transferred;
- int status;
- char rbuff[1024];
- libusb_device_handle * devh = wch_link_base_setup(0);
-
- wch_link_command( devh, "\x81\x06\x01\x01", 4, 0, 0, 0 );
-
- // Flush out any pending data.
- libusb_bulk_transfer( devh, 0x82, rbuff, 1024, &transferred, 1 );
-
- // 3/8 = Read Memory
- // First 4 bytes are big-endian location.
- // Next 4 bytes are big-endian amount.
- uint8_t readop[11] = { 0x81, 0x03, 0x08, };
- uint32_t readptr = 0x08000000;
- uint32_t amount = 16384;
-
- readop[3] = (readptr>>24)&0xff;
- readop[4] = (readptr>>16)&0xff;
- readop[5] = (readptr>>8)&0xff;
- readop[6] = (readptr>>0)&0xff;
-
- readop[7] = (amount>>24)&0xff;
- readop[8] = (amount>>16)&0xff;
- readop[9] = (amount>>8)&0xff;
- readop[10] = (amount>>0)&0xff;
-
- wch_link_command( devh, readop, 11, 0, 0, 0 );
-
- // Perform operation
- wch_link_command( devh, "\x81\x02\x01\x0c", 4, 0, 0, 0 );
-
- printf( "WARNING ENDIAN WILL BE REVERSED\n" );
-
- uint32_t remain = amount;
- while( remain )
- {
- WCHCHECK( libusb_bulk_transfer( devh, 0x82, rbuff, 1024, &transferred, WCHTIMEOUT ) );
- for( i = 0; i < transferred; i++ )
- printf( "%08x", (uint8_t)rbuff[i] );
- printf( "\n" );
- remain -= transferred;
- }
-
- wch_link_command( devh, "\x81\x0d\x01\xff", 4, 0, 0, 0 );
-}
diff --git a/attic/factory_bootloader.bin b/misc/factory_bootloader.bin
similarity index 100%
rename from attic/factory_bootloader.bin
rename to misc/factory_bootloader.bin