From e08eda486bdfdf864ef90492a4bbdba5449f4f0c Mon Sep 17 00:00:00 2001
From: Alexander Mandera <alexander@mandera.eu>
Date: Tue, 27 Jun 2023 00:11:57 +0200
Subject: [PATCH] Add untested V10x support
---
ch32v003fun/ch32v003fun.c | 129 ++++-
ch32v003fun/ch32v003fun.h | 1034 ++++++++++++++++++++++++++++++----
ch32v003fun/ch32v10xfun.ld | 166 ++++++
ch32v003fun/ch32v10xfun.mk | 59 ++
examples_v10x/blink/Makefile | 10 +
examples_v10x/blink/blink.c | 26 +
6 files changed, 1299 insertions(+), 125 deletions(-)
create mode 100644 ch32v003fun/ch32v10xfun.ld
create mode 100644 ch32v003fun/ch32v10xfun.mk
create mode 100644 examples_v10x/blink/Makefile
create mode 100644 examples_v10x/blink/blink.c
diff --git a/ch32v003fun/ch32v003fun.c b/ch32v003fun/ch32v003fun.c
index fa95f79..7ca8ee1 100644
--- a/ch32v003fun/ch32v003fun.c
+++ b/ch32v003fun/ch32v003fun.c
@@ -699,7 +699,7 @@ void SysTick_Handler( void ) __attribute__((section(".text.vector_ha
void SW_Handler( void ) __attribute__((section(".text.vector_handler"))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used));
void WWDG_IRQHandler( void ) __attribute__((section(".text.vector_handler"))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used));
void PVD_IRQHandler( void ) __attribute__((section(".text.vector_handler"))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used));
-#if defined(CH32V20x) || defined(CH32V30x)
+#if defined(CH32V20x) || defined(CH32V30x) || defined(CH32V10x)
void TAMPER_IRQHandler( void ) __attribute__((section(".text.vector_handler"))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used));
void RTC_IRQHandler( void ) __attribute__((section(".text.vector_handler"))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used));
#endif
@@ -708,7 +708,7 @@ void RCC_IRQHandler( void ) __attribute__((section(".text.vector_ha
#ifdef CH32V003
void EXTI7_0_IRQHandler( void ) __attribute__((section(".text.vector_handler"))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used));
void AWU_IRQHandler( void ) __attribute__((section(".text.vector_handler"))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used));
-#elif defined(CH32V20x) || defined(CH32V30x)
+#elif defined(CH32V20x) || defined(CH32V30x) || defined(CH32V10x)
void EXTI0_IRQHandler( void ) __attribute__((section(".text.vector_handler"))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used));
void EXTI1_IRQHandler( void ) __attribute__((section(".text.vector_handler"))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used));
void EXTI2_IRQHandler( void ) __attribute__((section(".text.vector_handler"))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used));
@@ -724,12 +724,16 @@ void DMA1_Channel6_IRQHandler( void ) __attribute__((section(".text.vector_ha
void DMA1_Channel7_IRQHandler( void ) __attribute__((section(".text.vector_handler"))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used));
#ifdef CH32V003
void ADC1_IRQHandler( void ) __attribute__((section(".text.vector_handler"))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used));
-#elif defined(CH32V20x) || defined(CH32V30x)
+#elif defined(CH32V20x) || defined(CH32V30x) || defined(CH32V10x)
void ADC1_2_IRQHandler( void ) __attribute__((section(".text.vector_handler"))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used));
+#endif
+#if defined(CH32V20x) || defined(CH32V30x)
void USB_HP_CAN1_TX_IRQHandler( void ) __attribute__((section(".text.vector_handler"))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used));
void USB_LP_CAN1_RX0_IRQHandler( void ) __attribute__((section(".text.vector_handler"))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used));
void CAN1_RX1_IRQHandler( void ) __attribute__((section(".text.vector_handler"))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used));
void CAN1_SCE_IRQHandler( void ) __attribute__((section(".text.vector_handler"))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used));
+#endif
+#if defined(CH32V20x) || defined(CH32V30x) || defined(CH32V10x)
void EXTI9_5_IRQHandler( void ) __attribute__((section(".text.vector_handler"))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used));
#endif
void TIM1_BRK_IRQHandler( void ) __attribute__((section(".text.vector_handler"))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used));
@@ -737,7 +741,7 @@ void TIM1_UP_IRQHandler( void ) __attribute__((section(".text.vector_ha
void TIM1_TRG_COM_IRQHandler( void ) __attribute__((section(".text.vector_handler"))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used));
void TIM1_CC_IRQHandler( void ) __attribute__((section(".text.vector_handler"))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used));
void TIM2_IRQHandler( void ) __attribute__((section(".text.vector_handler"))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used));
-#if defined(CH32V20x) || defined(CH32V30x)
+#if defined(CH32V20x) || defined(CH32V30x) || defined(CH32V10x)
void TIM3_IRQHandler( void ) __attribute__((section(".text.vector_handler"))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used));
void TIM4_IRQHandler( void ) __attribute__((section(".text.vector_handler"))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used));
#endif
@@ -746,7 +750,7 @@ void I2C1_ER_IRQHandler( void ) __attribute__((section(".text.vector_ha
#ifdef CH32V003
void USART1_IRQHandler( void ) __attribute__((section(".text.vector_handler"))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used));
void SPI1_IRQHandler( void ) __attribute__((section(".text.vector_handler"))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used));
-#elif defined(CH32V20x) || defined(CH32V30x)
+#elif defined(CH32V20x) || defined(CH32V30x) || defined(CH32V10x)
void I2C2_EV_IRQHandler( void ) __attribute__((section(".text.vector_handler"))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used));
void I2C2_ER_IRQHandler( void ) __attribute__((section(".text.vector_handler"))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used));
void SPI1_IRQHandler( void ) __attribute__((section(".text.vector_handler"))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used));
@@ -757,9 +761,11 @@ void USART3_IRQHandler( void ) __attribute__((section(".text.vector_handler"
void EXTI15_10_IRQHandler( void ) __attribute__((section(".text.vector_handler"))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used));
void RTCAlarm_IRQHandler( void ) __attribute__((section(".text.vector_handler"))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used));
#endif
-#if defined(CH32V20x)
+#if defined(CH32V20x) || defined(CH32V10x)
void USBWakeUp_IRQHandler( void ) __attribute__((section(".text.vector_handler"))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used));
void USBHD_IRQHandler( void ) __attribute__((section(".text.vector_handler"))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used));
+#endif
+#if defined(CH32V20x)
void USBHDWakeUp_IRQHandler( void ) __attribute__((section(".text.vector_handler"))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used));
void ETH_IRQHandler( void ) __attribute__((section(".text.vector_handler"))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used));
void ETHWakeUp_IRQHandler( void ) __attribute__((section(".text.vector_handler"))) __attribute((weak,alias("DefaultIRQHandler"))) __attribute__((used));
@@ -973,7 +979,7 @@ void SystemInitHSEPLL( int HSEBYP )
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08); // Wait till PLL is used as system clock source
}
-#elif defined(CH32V20x) || defined(CH32V30x)
+#elif defined(CH32V20x) || defined(CH32V30x) || defined(CH32V10x)
void Init() __attribute((section(".init")));
void InterruptVector() __attribute__((naked)) __attribute((section(".vector"))) __attribute((weak,alias("InterruptVectorDefault")));
@@ -1011,15 +1017,25 @@ void InterruptVectorDefault()
.word 0 \n\
.word NMI_Handler /* NMI */ \n\
.word HardFault_Handler /* Hard Fault */ \n\
- .word 0 \n\
- .word Ecall_M_Mode_Handler /* Ecall M Mode */ \n\
+ .word 0 \n"
+#if !defined(CH32V10x)
+" .word Ecall_M_Mode_Handler /* Ecall M Mode */ \n\
.word 0 \n\
.word 0 \n\
.word Ecall_U_Mode_Handler /* Ecall U Mode */ \n\
.word Break_Point_Handler /* Break Point */ \n\
.word 0 \n\
+ .word 0 \n"
+#else
+" .word 0 \n\
+ .word 0 \n\
+ .word 0 \n\
+ .word 0 \n\
.word 0 \n\
- .word SysTick_Handler /* SysTick */ \n\
+ .word 0 \n\
+ .word 0 \n"
+#endif
+" .word SysTick_Handler /* SysTick */ \n\
.word 0 \n\
.word SW_Handler /* SW */ \n\
.word 0 \n\
@@ -1042,12 +1058,19 @@ void InterruptVectorDefault()
.word DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */ \n\
.word DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */ \n\
.word DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */ \n\
- .word ADC1_2_IRQHandler /* ADC1_2 */ \n\
- .word USB_HP_CAN1_TX_IRQHandler /* USB HP and CAN1 TX */ \n\
+ .word ADC1_2_IRQHandler /* ADC1_2 */ \n"
+#if !defined(CH32V10x)
+" .word USB_HP_CAN1_TX_IRQHandler /* USB HP and CAN1 TX */ \n\
.word USB_LP_CAN1_RX0_IRQHandler /* USB LP and CAN1RX0 */ \n\
.word CAN1_RX1_IRQHandler /* CAN1 RX1 */ \n\
- .word CAN1_SCE_IRQHandler /* CAN1 SCE */ \n\
- .word EXTI9_5_IRQHandler /* EXTI Line 9..5 */ \n\
+ .word CAN1_SCE_IRQHandler /* CAN1 SCE */ \n"
+#else
+" .word 0 \n\
+ .word 0 \n\
+ .word 0 \n\
+ .word 0 \n"
+#endif
+" .word EXTI9_5_IRQHandler /* EXTI Line 9..5 */ \n\
.word TIM1_BRK_IRQHandler /* TIM1 Break */ \n\
.word TIM1_UP_IRQHandler /* TIM1 Update */ \n\
.word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation */ \n\
@@ -1066,10 +1089,12 @@ void InterruptVectorDefault()
.word USART3_IRQHandler /* USART3 */ \n\
.word EXTI15_10_IRQHandler /* EXTI Line 15..10 */ \n\
.word RTCAlarm_IRQHandler /* RTC Alarm through EXTI Line */ \n"
-#if defined(CH32V20x)
+#if defined(CH32V20x) || defined(CH32V10x)
" .word USBWakeUp_IRQHandler /* USB Wake up from suspend */ \n\
- .word USBHD_IRQHandler /* USBHD Break */ \n\
- .word USBHDWakeUp_IRQHandler /* USBHD Wake up from suspend */ \n\
+ .word USBHD_IRQHandler /* USBHD Break */ \n"
+#endif
+#if defined(CH32V20x)
+" .word USBHDWakeUp_IRQHandler /* USBHD Wake up from suspend */ \n\
.word ETH_IRQHandler /* ETH global */ \n\
.word ETHWakeUp_IRQHandler /* ETH Wake up */ \n\
.word 0 /* BLE BB */ \n\
@@ -1205,6 +1230,10 @@ void handle_reset( void )
" mret\n" : : [main]"r"(main) );
}
+#endif
+
+#if defined(CH32V30x) || defined(CH32V20x)
+
void SystemInit144HSI( void )
{
EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
@@ -1262,6 +1291,69 @@ void SystemInit144HSE( void )
#endif
+#if defined(CH32V10x)
+
+void SystemInit72HSI( void )
+{
+ EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
+
+ /* Enable Prefetch Buffer */
+ FLASH->ACTLR |= FLASH_ACTLR_PRFTBE;
+
+ /* Flash 1 wait state */
+ FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY);
+ FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_1;
+
+ RCC->CFGR0 = RCC_HPRE_DIV1 | RCC_PPRE2_DIV1 | RCC_PPRE1_DIV2;
+ RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+ RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL9);
+
+ /* Enable PLL */
+ RCC->CTLR |= RCC_PLLON;
+
+ /* Wait till PLL is ready */
+ while((RCC->CTLR & RCC_PLLRDY) == 0) {}
+
+ /* Select PLL as system clock source */
+ RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+ RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+
+ /* Wait till PLL is used as system clock source */
+ while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) {}
+}
+
+void SystemInit72HSE( void )
+{
+ RCC->CTLR |= ((uint32_t)RCC_HSEON);
+ while(!(RCC->CTLR&RCC_HSERDY));
+
+ /* Enable Prefetch Buffer */
+ FLASH->ACTLR |= FLASH_ACTLR_PRFTBE;
+
+ /* Flash 2 wait state */
+ FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY);
+ FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_2;
+
+ RCC->CFGR0 = RCC_HPRE_DIV1 | RCC_PPRE2_DIV1 | RCC_PPRE1_DIV2;
+ RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
+ RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLMULL9);
+
+ /* Enable PLL */
+ RCC->CTLR |= RCC_PLLON;
+
+ /* Wait till PLL is ready */
+ while((RCC->CTLR & RCC_PLLRDY) == 0) {}
+
+ /* Select PLL as system clock source */
+ RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
+ RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
+
+ /* Wait till PLL is used as system clock source */
+ while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) {}
+}
+
+#endif
+
#ifdef CH32V003
void SetupUART( int uartBRR )
@@ -1416,6 +1508,9 @@ void DelaySysTick( uint32_t n )
#elif defined(CH32V20x) || defined(CH32V30x)
uint64_t targend = SysTick->CNT + n;
while( ((int64_t)( SysTick->CNT - targend )) < 0 );
+#elif defined(CH32V10x)
+ uint32_t targend = SysTick->CNTL + n;
+ while( ((int32_t)( SysTick->CNTL - targend )) < 0 );
#endif
}
diff --git a/ch32v003fun/ch32v003fun.h b/ch32v003fun/ch32v003fun.h
index 715c4d4..da9eb05 100644
--- a/ch32v003fun/ch32v003fun.h
+++ b/ch32v003fun/ch32v003fun.h
@@ -2,7 +2,7 @@
#pragma once
// Default: CH32V003
-#if !defined(CH32V003) && !defined(CH32V20x) && !defined(CH32V30x)
+#if !defined(CH32V003) && !defined(CH32V20x) && !defined(CH32V30x) && !defined(CH32V10x)
#define CH32V003
#endif
@@ -101,6 +101,15 @@ extern "C" {
#define HSI_VALUE ((uint32_t)8000000) /* Value of the Internal oscillator in Hz */
+#elif defined(CH32V10x)
+
+#define HSE_VALUE ((uint32_t)8000000) /* Value of the External oscillator in Hz */
+
+/* In the following line adjust the External High Speed oscillator (HSE) Startup Timeout value */
+#define HSE_STARTUP_TIMEOUT ((uint16_t)0x500) /* Time out for HSE start up */
+
+#define HSI_VALUE ((uint32_t)8000000) /* Value of the Internal oscillator in Hz */
+
#endif
#ifndef HSITRIM
@@ -148,7 +157,7 @@ typedef enum IRQn
TIM1_TRG_COM_IRQn = 36, /* TIM1 Trigger and Commutation Interrupt */
TIM1_CC_IRQn = 37, /* TIM1 Capture Compare Interrupt */
TIM2_IRQn = 38, /* TIM2 global Interrupt */
-#elif defined(CH32V20x) || defined(CH32V30x)
+#elif defined(CH32V20x) || defined(CH32V30x) || defined(CH32V10x)
/****** RISC-V specific Interrupt Numbers *********************************************************/
WWDG_IRQn = 16, /* Window WatchDog Interrupt */
PVD_IRQn = 17, /* PVD through EXTI Line detection Interrupt */
@@ -169,10 +178,12 @@ typedef enum IRQn
DMA1_Channel6_IRQn = 32, /* DMA1 Channel 6 global Interrupt */
DMA1_Channel7_IRQn = 33, /* DMA1 Channel 7 global Interrupt */
ADC_IRQn = 34, /* ADC1 and ADC2 global Interrupt */
+#if !defined(CH32V10x)
USB_HP_CAN1_TX_IRQn = 35, /* USB Device High Priority or CAN1 TX Interrupts */
USB_LP_CAN1_RX0_IRQn = 36, /* USB Device Low Priority or CAN1 RX0 Interrupts */
CAN1_RX1_IRQn = 37, /* CAN1 RX1 Interrupt */
CAN1_SCE_IRQn = 38, /* CAN1 SCE Interrupt */
+#endif
EXTI9_5_IRQn = 39, /* External Line[9:5] Interrupts */
TIM1_BRK_IRQn = 40, /* TIM1 Break Interrupt */
TIM1_UP_IRQn = 41, /* TIM1 Update Interrupt */
@@ -193,10 +204,11 @@ typedef enum IRQn
EXTI15_10_IRQn = 56, /* External Line[15:10] Interrupts */
RTCAlarm_IRQn = 57, /* RTC Alarm through EXTI Line Interrupt */
#endif
-#if defined(CH32V20x)
-
+#if defined(CH32V20x) || defined(CH32V10x)
USBWakeUp_IRQn = 58, /* USB Device WakeUp from suspend through EXTI Line Interrupt */
USBHD_IRQn = 59, /* USBHD global Interrupt */
+#endif
+#if defined(CH32V20x)
USBHDWakeUp_IRQn = 60, /* USB Host/Device WakeUp Interrupt */
#ifdef CH32V20x_D6
@@ -325,7 +337,7 @@ typedef enum IRQn
#define HardFault_IRQn EXC_IRQn
-#if defined(CH32V20x) || defined(CH32V30x)
+#if defined(CH32V20x) || defined(CH32V30x) || defined(CH32V10x)
#define ADC1_2_IRQn ADC_IRQn
#endif
@@ -363,7 +375,7 @@ typedef struct
#endif
} ADC_TypeDef;
-#if defined(CH32V20x) || defined(CH32V30x)
+#if defined(CH32V20x) || defined(CH32V30x) || defined(CH32V10x)
/* Backup Registers */
typedef struct
{
@@ -459,7 +471,9 @@ typedef struct
__IO uint16_t DATAR42;
uint16_t RESERVED45;
} BKP_TypeDef;
+#endif
+#if defined(CH32V20x) || defined(CH32V30x)
/* Controller Area Network TxMailBox */
typedef struct
{
@@ -511,6 +525,7 @@ typedef struct
uint32_t RESERVED5[8];
CAN_FilterRegister_TypeDef sFilterRegister[28];
} CAN_TypeDef;
+#endif
/* CRC Calculation Unit */
typedef struct
@@ -523,7 +538,7 @@ typedef struct
} CRC_TypeDef;
#endif
-#if defined(CH32V30x)
+#if defined(CH32V30x) || defined(CH32V10x)
/* Digital to Analog Converter */
typedef struct
{
@@ -603,7 +618,7 @@ typedef struct
__IO uint16_t Data1;
__IO uint16_t WRPR0;
__IO uint16_t WRPR1;
-#if defined(CH32V20x) || defined(CH32V30x)
+#if defined(CH32V20x) || defined(CH32V30x) || defined(CH32V10x)
__IO uint16_t WRPR2;
__IO uint16_t WRPR3;
#endif
@@ -769,7 +784,7 @@ typedef struct
uint32_t RESERVED0;
__IO uint32_t PCFR1;
__IO uint32_t EXTICR;
-#elif defined(CH32V20x) || defined(CH32V30x)
+#elif defined(CH32V20x) || defined(CH32V30x) || defined(CH32V10x)
__IO uint32_t ECR;
__IO uint32_t PCFR1;
__IO uint32_t EXTICR[4];
@@ -797,7 +812,7 @@ typedef struct
uint16_t RESERVED6;
__IO uint16_t CKCFGR;
uint16_t RESERVED7;
-#if defined(CH32V20x) || defined(CH32V30x)
+#if defined(CH32V20x) || defined(CH32V30x) || defined(CH32V10x)
__IO uint16_t RTR;
uint16_t RESERVED8;
#endif
@@ -838,16 +853,17 @@ typedef struct
#ifdef CH32V003
__IO uint32_t RESERVED0;
__IO uint32_t RSTSCKR;
-#elif defined(CH32V20x) || defined(CH32V30x)
+#elif defined(CH32V20x) || defined(CH32V30x) || defined(CH32V10x)
__IO uint32_t BDCTLR;
__IO uint32_t RSTSCKR;
-
+#endif
+#if defined(CH32V20x) || defined(CH32V30x)
__IO uint32_t AHBRSTR;
__IO uint32_t CFGR2;
#endif
} RCC_TypeDef;
-#if defined(CH32V20x) || defined(CH32V30x)
+#if defined(CH32V20x) || defined(CH32V30x) || defined(CH32V10x)
/* Real-Time Clock */
typedef struct
{
@@ -921,14 +937,16 @@ typedef struct
#ifdef CH32V003
uint32_t RESERVED7;
uint32_t RESERVED8;
-#elif defined(CH32V20x) || defined(CH32V30x)
+#elif defined(CH32V20x) || defined(CH32V30x) || defined(CH32V10x)
__IO uint16_t I2SCFGR;
uint16_t RESERVED7;
__IO uint16_t I2SPR;
uint16_t RESERVED8;
#endif
+#if !defined(CH32V10x)
__IO uint16_t HSCR;
uint16_t RESERVED9;
+#endif
} SPI_TypeDef;
/* TIM */
@@ -971,7 +989,7 @@ typedef struct
uint16_t RESERVED14;
__IO uint16_t DMAADR;
uint16_t RESERVED15;
-#elif defined(CH32V20x) || defined(CH32V30x)
+#elif defined(CH32V20x) || defined(CH32V30x) || defined(CH32V10x)
__IO uint16_t CH1CVR;
uint16_t RESERVED13;
__IO uint16_t CH2CVR;
@@ -1502,7 +1520,6 @@ typedef struct
__IO uint8_t LSI32K_CAL_CTRL;
} OSC_TypeDef;
-#endif
#endif
#endif
@@ -1531,7 +1548,7 @@ typedef struct
#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
#define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
-#if defined(CH32V20x) || defined(CH32V30x)
+#if defined(CH32V20x) || defined(CH32V30x) || defined(CH32V10x)
#define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
#define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
@@ -1542,33 +1559,44 @@ typedef struct
#define UART7_BASE (APB1PERIPH_BASE + 0x1C00)
#define UART8_BASE (APB1PERIPH_BASE + 0x2000)
#endif
+#if defined(CH32V10x)
+#define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
+#define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
+#define TIM12_BASE (APB1PERIPH_BASE + 0x1800)
+#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00)
+#define TIM14_BASE (APB1PERIPH_BASE + 0x2000)
+#endif
#define RTC_BASE (APB1PERIPH_BASE + 0x2800)
#endif
#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
#define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
-#if defined(CH32V20x) || defined(CH32V30x)
+#if defined(CH32V20x) || defined(CH32V30x) || defined(CH32V10x)
#define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
-#if defined(CH32V30x)
+#if defined(CH32V30x) || defined(CH32V10x)
#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
#endif
#define USART2_BASE (APB1PERIPH_BASE + 0x4400)
#define USART3_BASE (APB1PERIPH_BASE + 0x4800)
#define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
-#if defined(CH32V30x)
-#define UART5_BASE (APB1PERIPH_BASE + 0x5000)
+#if defined(CH32V30x) || defined(CH32V10x)
+#define UART5_BASE (APB1PERIPH_BASE + 0x5000)
#endif
#endif
#define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
-#if defined(CH32V20x) || defined(CH32V30x)
+#if defined(CH32V20x) || defined(CH32V30x) || defined(CH32V10x)
#define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
+#endif
+#if defined(CH32V20x) || defined(CH32V30x)
#define CAN1_BASE (APB1PERIPH_BASE + 0x6400)
+#endif
#if defined(CH32V30x)
#define CAN2_BASE (APB1PERIPH_BASE + 0x6800)
#endif
+#if defined(CH32V20x) || defined(CH32V30x) || defined(CH32V10x)
#define BKP_BASE (APB1PERIPH_BASE + 0x6C00)
#endif
#define PWR_BASE (APB1PERIPH_BASE + 0x7000)
-#if defined(CH32V30x)
+#if defined(CH32V30x) || defined(CH32V10x)
#define DAC_BASE (APB1PERIPH_BASE + 0x7400)
#endif
@@ -1577,22 +1605,22 @@ typedef struct
#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800)
#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000)
#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400)
-#if defined(CH32V20x) || defined(CH32V30x)
+#if defined(CH32V20x) || defined(CH32V30x) || defined(CH32V10x)
#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800)
#define GPIOF_BASE (APB2PERIPH_BASE + 0x1C00)
#define GPIOG_BASE (APB2PERIPH_BASE + 0x2000)
#endif
#define ADC1_BASE (APB2PERIPH_BASE + 0x2400)
-#if defined(CH32V20x) || defined(CH32V30x)
+#if defined(CH32V20x) || defined(CH32V30x) || defined(CH32V10x)
#define ADC2_BASE (APB2PERIPH_BASE + 0x2800)
#endif
#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00)
#define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
-#if defined(CH32V30x)
+#if defined(CH32V30x) || defined(CH32V10x)
#define TIM8_BASE (APB2PERIPH_BASE + 0x3400)
#endif
#define USART1_BASE (APB2PERIPH_BASE + 0x3800)
-#if defined(CH32V30x)
+#if defined(CH32V30x) || defined(CH32V10x)
#define ADC3_BASE (APB2PERIPH_BASE + 0x3C00)
#define TIM15_BASE (APB2PERIPH_BASE + 0x4000)
#define TIM16_BASE (APB2PERIPH_BASE + 0x4400)
@@ -1600,6 +1628,8 @@ typedef struct
#define TIM9_BASE (APB2PERIPH_BASE + 0x4C00)
#define TIM10_BASE (APB2PERIPH_BASE + 0x5000)
#define TIM11_BASE (APB2PERIPH_BASE + 0x5400)
+#endif
+#if defined(CH32V30x)
#define SDIO_BASE (APB2PERIPH_BASE + 0x8000)
#endif
@@ -1614,13 +1644,14 @@ typedef struct
#if defined(CH32V20x)
#define DMA1_Channel8_BASE (AHBPERIPH_BASE + 0x0094)
#endif
-#if defined(CH32V30x)
+#if defined(CH32V30x) || defined(CH32V10x)
#define DMA2_BASE (AHBPERIPH_BASE + 0x0400)
#define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408)
#define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x041C)
#define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x0430)
#define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x0444)
#define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458)
+#if defined(CH32V30x)
#define DMA2_Channel6_BASE (AHBPERIPH_BASE + 0x046C)
#define DMA2_Channel7_BASE (AHBPERIPH_BASE + 0x0480)
#define DMA2_Channel8_BASE (AHBPERIPH_BASE + 0x0490)
@@ -1629,6 +1660,7 @@ typedef struct
#define DMA2_Channel11_BASE (AHBPERIPH_BASE + 0x04C0)
#define DMA2_EXTEN_BASE (AHBPERIPH_BASE + 0x04D0)
#endif
+#endif
#define RCC_BASE (AHBPERIPH_BASE + 0x1000)
#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /* Flash registers base address */
@@ -1656,11 +1688,14 @@ typedef struct
#define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000)
#define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104)
#define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060)
+#elif defined(CH32V10x)
+#define CRC_BASE (AHBPERIPH_BASE + 0x3000)
+#define DBGMCU_BASE ((uint32_t)0xE000D000)
#endif
#define OB_BASE ((uint32_t)0x1FFFF800) /* Flash Option Bytes base address */
-#ifdef CH32V003
+#if defined(CH32V003) || defined(CH32V10x)
#define EXTEN_BASE ((uint32_t)0x40023800)
#elif defined(CH32V20x) || defined(CH32V30x)
#define EXTEN_BASE (AHBPERIPH_BASE + 0x3800)
@@ -1674,7 +1709,7 @@ typedef struct
/* Peripheral declaration */
#define TIM2 ((TIM_TypeDef *)TIM2_BASE)
-#if defined(CH32V20x) || defined(CH32V30x)
+#if defined(CH32V20x) || defined(CH32V30x) || defined(CH32V10x)
#define TIM3 ((TIM_TypeDef *)TIM3_BASE)
#define TIM4 ((TIM_TypeDef *)TIM4_BASE)
#define TIM5 ((TIM_TypeDef *)TIM5_BASE)
@@ -1685,33 +1720,44 @@ typedef struct
#define UART7 ((USART_TypeDef *) UART7_BASE)
#define UART8 ((USART_TypeDef *) UART8_BASE)
#endif
+#if defined(CH32V10x)
+#define TIM6 ((TIM_TypeDef *)TIM6_BASE)
+#define TIM7 ((TIM_TypeDef *)TIM7_BASE)
+#define TIM12 ((TIM_TypeDef *)TIM12_BASE)
+#define TIM13 ((TIM_TypeDef *)TIM13_BASE)
+#define TIM14 ((TIM_TypeDef *)TIM14_BASE)
+#endif
#define RTC ((RTC_TypeDef *)RTC_BASE)
#endif
#define WWDG ((WWDG_TypeDef *)WWDG_BASE)
#define IWDG ((IWDG_TypeDef *)IWDG_BASE)
-#if defined(CH32V20x) || defined(CH32V30x)
+#if defined(CH32V20x) || defined(CH32V30x) || defined(CH32V10x)
#define SPI2 ((SPI_TypeDef *)SPI2_BASE)
-#if defined(CH32V30x)
+#if defined(CH32V30x) || defined(CH32V10x)
#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
#endif
#define USART2 ((USART_TypeDef *)USART2_BASE)
#define USART3 ((USART_TypeDef *)USART3_BASE)
#define UART4 ((USART_TypeDef *)UART4_BASE)
-#if defined(CH32V30x)
+#if defined(CH32V30x) || defined(CH32V10x)
#define UART5 ((USART_TypeDef *) UART5_BASE)
#endif
#endif
#define I2C1 ((I2C_TypeDef *)I2C1_BASE)
-#if defined(CH32V20x) || defined(CH32V30x)
+#if defined(CH32V20x) || defined(CH32V30x) || defined(CH32V10x)
#define I2C2 ((I2C_TypeDef *)I2C2_BASE)
+#endif
+#if defined(CH32V20x) || defined(CH32V30x)
#define CAN1 ((CAN_TypeDef *)CAN1_BASE)
+#endif
#if defined(CH32V30x)
#define CAN2 ((CAN_TypeDef *) CAN2_BASE)
#endif
+#if defined(CH32V20x) || defined(CH32V30x) || defined(CH32V10x)
#define BKP ((BKP_TypeDef *)BKP_BASE)
#endif
#define PWR ((PWR_TypeDef *)PWR_BASE)
-#if defined(CH32V30x)
+#if defined(CH32V30x) || defined(CH32V10x)
#define DAC ((DAC_TypeDef *) DAC_BASE)
#endif
@@ -1720,24 +1766,26 @@ typedef struct
#define GPIOA ((GPIO_TypeDef *)GPIOA_BASE)
#define GPIOC ((GPIO_TypeDef *)GPIOC_BASE)
#define GPIOD ((GPIO_TypeDef *)GPIOD_BASE)
-#if defined(CH32V20x) || defined(CH32V30x)
+#if defined(CH32V20x) || defined(CH32V30x) || defined(CH32V10x)
#define GPIOE ((GPIO_TypeDef *)GPIOE_BASE)
#define GPIOF ((GPIO_TypeDef *)GPIOF_BASE)
#define GPIOG ((GPIO_TypeDef *)GPIOG_BASE)
#endif
#define ADC1 ((ADC_TypeDef *)ADC1_BASE)
-#if defined(CH32V20x) || defined(CH32V30x)
+#if defined(CH32V20x) || defined(CH32V30x) || defined(CH32V10x)
#define ADC2 ((ADC_TypeDef *)ADC2_BASE)
+#endif
+#if defined(CH32V20x) || defined(CH32V30x)
#define TKey1 ((ADC_TypeDef *)ADC1_BASE)
#define TKey2 ((ADC_TypeDef *)ADC2_BASE)
#endif
#define TIM1 ((TIM_TypeDef *)TIM1_BASE)
#define SPI1 ((SPI_TypeDef *)SPI1_BASE)
-#if defined(CH32V30x)
+#if defined(CH32V30x) || defined(CH32V10x)
#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
#endif
#define USART1 ((USART_TypeDef *)USART1_BASE)
-#if defined(CH32V30x)
+#if defined(CH32V30x) || defined(CH32V10x)
#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
#define TIM15 ((TIM_TypeDef *) TIM15_BASE)
#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
@@ -1745,6 +1793,8 @@ typedef struct
#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
#define TIM10 ((TIM_TypeDef *) TIM10_BASE)
#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
+#endif
+#if defined(CH32V30x)
#define SDIO ((SDIO_TypeDef *) SDIO_BASE)
#endif
@@ -1759,7 +1809,7 @@ typedef struct
#if defined(CH32V20x)
#define DMA1_Channel8 ((DMA_Channel_TypeDef *)DMA1_Channel8_BASE)
#endif
-#if defined(CH32V30x)
+#if defined(CH32V30x) || defined(CH32V10x)
#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
#define DMA2_EXTEN ((DMA_TypeDef *) DMA2_EXTEN_BASE)
#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
@@ -1767,6 +1817,7 @@ typedef struct
#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
+#if defined(CH32V30x)
#define DMA2_Channel6 ((DMA_Channel_TypeDef *) DMA2_Channel6_BASE)
#define DMA2_Channel7 ((DMA_Channel_TypeDef *) DMA2_Channel7_BASE)
#define DMA2_Channel8 ((DMA_Channel_TypeDef *) DMA2_Channel8_BASE)
@@ -1774,10 +1825,13 @@ typedef struct
#define DMA2_Channel10 ((DMA_Channel_TypeDef *) DMA2_Channel10_BASE)
#define DMA2_Channel11 ((DMA_Channel_TypeDef *) DMA2_Channel11_BASE)
#endif
+#endif
#define RCC ((RCC_TypeDef *)RCC_BASE)
#define FLASH ((FLASH_TypeDef *)FLASH_R_BASE)
-#if defined(CH32V20x) || defined(CH32V30x)
+#if defined(CH32V20x) || defined(CH32V30x) || defined(CH32V10x)
#define CRC ((CRC_TypeDef *)CRC_BASE)
+#endif
+#if defined(CH32V20x) || defined(CH32V30x)
#if defined(CH32V30x)
#define USBHSD ((USBHSD_TypeDef *) USBHS_BASE)
#define USBHSH ((USBHSH_TypeDef *) USBHS_BASE)
@@ -1809,6 +1863,10 @@ typedef struct
#define FSMC_Bank2 ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE)
#endif
+#if defined(CH32V10x)
+#define DBGMCU ((DBGMCU_TypeDef *)DBGMCU_BASE)
+#endif
+
/******************************************************************************/
/* Peripheral Registers Bits Definition */
/******************************************************************************/
@@ -4120,7 +4178,7 @@ typedef struct
/* FLASH and Option Bytes Registers */
/******************************************************************************/
-#ifdef CH32V003
+#if defined(CH32V003) || defined(CH32V10x)
/******************* Bit definition for FLASH_ACTLR register ******************/
#define FLASH_ACTLR_LATENCY ((uint8_t)0x03) /* LATENCY[2:0] bits (Latency) */
#define FLASH_ACTLR_LATENCY_0 ((uint8_t)0x00) /* Bit 0 */
@@ -4128,6 +4186,12 @@ typedef struct
#define FLASH_ACTLR_LATENCY_2 ((uint8_t)0x02) /* Bit 1 */
#endif
+#if defined(CH32V10x)
+#define FLASH_ACTLR_HLFCYA ((uint8_t)0x08) /* Flash Half Cycle Access Enable */
+#define FLASH_ACTLR_PRFTBE ((uint8_t)0x10) /* Prefetch Buffer Enable */
+#define FLASH_ACTLR_PRFTBS ((uint8_t)0x20) /* Prefetch Buffer Status */
+#endif
+
/****************** Bit definition for FLASH_KEYR register ******************/
#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /* FPEC Key */
@@ -4136,7 +4200,7 @@ typedef struct
/****************** Bit definition for FLASH_STATR register *******************/
#define FLASH_STATR_BSY ((uint8_t)0x01) /* Busy */
-#if defined(CH32V20x) || defined(CH32V30x)
+#if defined(CH32V20x) || defined(CH32V30x) || defined(CH32V10x)
#define FLASH_STATR_PGERR ((uint8_t)0x04) /* Programming Error */
#endif
#define FLASH_STATR_WRPRTERR ((uint8_t)0x10) /* Write Protection Error */
@@ -4207,7 +4271,7 @@ typedef struct
#define FLASH_WRPR1_WRPR1 ((uint32_t)0x00FF0000) /* Flash memory write protection option bytes */
#define FLASH_WRPR1_nWRPR1 ((uint32_t)0xFF000000) /* Flash memory write protection complemented option bytes */
-#if defined(CH32V20x) || defined(CH32V30x)
+#if defined(CH32V20x) || defined(CH32V30x) || defined(CH32V10x)
/****************** Bit definition for FLASH_WRPR2 register ******************/
#define FLASH_WRPR2_WRPR2 ((uint32_t)0x000000FF) /* Flash memory write protection option bytes */
#define FLASH_WRPR2_nWRPR2 ((uint32_t)0x0000FF00) /* Flash memory write protection complemented option bytes */
@@ -4467,7 +4531,7 @@ typedef struct
#define GPIO_LCK15 ((uint32_t)0x00008000) /* Port x Lock bit 15 */
#define GPIO_LCKK ((uint32_t)0x00010000) /* Lock key */
-#if defined(CH32V20x) || defined(CH32V30x)
+#if defined(CH32V20x) || defined(CH32V30x) || defined(CH32V10x)
/****************** Bit definition for AFIO_ECR register *******************/
#define AFIO_ECR_PIN ((uint8_t)0x0F) /* PIN[3:0] bits (Pin selection) */
#define AFIO_ECR_PIN_0 ((uint8_t)0x01) /* Bit 0 */
@@ -4614,7 +4678,7 @@ typedef struct
#define AFIO_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /* PF[3] pin */
#define AFIO_EXTICR1_EXTI3_PG ((uint16_t)0x6000) /* PG[3] pin */
-#if defined(CH32V20x) || defined(CH32V30x)
+#if defined(CH32V20x) || defined(CH32V30x) || defined(CH32V10x)
/***************** Bit definition for AFIO_EXTICR2 register *****************/
#define AFIO_EXTICR2_EXTI4 ((uint16_t)0x000F) /* EXTI 4 configuration */
#define AFIO_EXTICR2_EXTI5 ((uint16_t)0x00F0) /* EXTI 5 configuration */
@@ -4840,7 +4904,7 @@ typedef struct
#define I2C_CKCFGR_DUTY ((uint16_t)0x4000) /* Fast Mode Duty Cycle */
#define I2C_CKCFGR_FS ((uint16_t)0x8000) /* I2C Master Mode Selection */
-#if defined(CH32V20x) || defined(CH32V30x)
+#if defined(CH32V20x) || defined(CH32V30x) || defined(CH32V10x)
/****************** Bit definition for I2C_RTR register *******************/
#define I2C_RTR_TRISE ((uint8_t)0x3F) /* Maximum Rise Time in Fast/Standard mode (Master mode) */
#endif
@@ -4931,7 +4995,7 @@ typedef struct
#define RCC_HPRE_DIV64 ((uint32_t)0x000000D0) /* SYSCLK divided by 64 */
#define RCC_HPRE_DIV128 ((uint32_t)0x000000E0) /* SYSCLK divided by 128 */
#define RCC_HPRE_DIV256 ((uint32_t)0x000000F0) /* SYSCLK divided by 256 */
-#elif defined(CH32V20x) || defined(CH32V30x)
+#elif defined(CH32V20x) || defined(CH32V30x) || defined(CH32V10x)
#define RCC_HPRE_DIV1 ((uint32_t)0x00000000) /* SYSCLK not divided */
#define RCC_HPRE_DIV2 ((uint32_t)0x00000080) /* SYSCLK divided by 2 */
#define RCC_HPRE_DIV4 ((uint32_t)0x00000090) /* SYSCLK divided by 4 */
@@ -4987,7 +5051,7 @@ typedef struct
#ifdef CH32V003
#define RCC_PLLSRC_HSI_Mul2 ((uint32_t)0x00000000) /* HSI clock*2 selected as PLL entry clock source */
#define RCC_PLLSRC_HSE_Mul2 ((uint32_t)0x00010000) /* HSE clock*2 selected as PLL entry clock source */
-#elif defined(CH32V20x) || defined(CH32V30x)
+#elif defined(CH32V20x) || defined(CH32V30x) || defined(CH32V10x)
#define RCC_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /* HSI clock divided by 2 selected as PLL entry clock source */
#define RCC_PLLSRC_HSE ((uint32_t)0x00010000) /* HSE clock selected as PLL entry clock source */
#endif
@@ -5134,7 +5198,7 @@ typedef struct
#define RCC_USBEN ((uint32_t)0x00800000) /* USB Device clock enable */
-#if defined(CH32V20x) || defined(CH32V30x)
+#if defined(CH32V20x) || defined(CH32V30x) || defined(CH32V10x)
/******************* Bit definition for RCC_BDCTLR register *******************/
#define RCC_LSEON ((uint32_t)0x00000001) /* External Low Speed oscillator enable */
#define RCC_LSERDY ((uint32_t)0x00000002) /* External Low Speed oscillator Ready */
@@ -5180,7 +5244,7 @@ typedef struct
#define RNG_SR_SEIS ((uint32_t)0x00000040)
#endif
-#if defined(CH32V20x) || defined(CH32V30x)
+#if defined(CH32V20x) || defined(CH32V30x) || defined(CH32V10x)
/******************************************************************************/
/* Real-Time Clock */
/******************************************************************************/
@@ -5277,7 +5341,7 @@ typedef struct
/****************** Bit definition for SPI_TCRCR register ******************/
#define SPI_TCRCR_TXCRC ((uint16_t)0xFFFF) /* Tx CRC Register */
-#if defined(CH32V20x) || defined(CH32V30x)
+#if defined(CH32V20x) || defined(CH32V30x) || defined(CH32V10x)
/****************** Bit definition for SPI_I2SCFGR register *****************/
#define SPI_I2SCFGR_CHLEN ((uint16_t)0x0001) /* Channel length (number of bits per audio channel) */
@@ -5714,7 +5778,7 @@ typedef struct
/******************************************************************************/
/**************************** Enhanced register *****************************/
-#if defined(CH32V20x) || defined(CH32V30x)
+#if defined(CH32V20x) || defined(CH32V30x) || defined(CH32V10x)
#define EXTEN_USBD_LS ((uint32_t)0x00000001) /* Bit 0 */
#define EXTEN_USBD_PU_EN ((uint32_t)0x00000002) /* Bit 1 */
#define EXTEN_ETH_10M_EN ((uint32_t)0x00000004) /* Bit 2 */
@@ -5723,18 +5787,33 @@ typedef struct
#define EXTEN_LOCKUP_EN ((uint32_t)0x00000040) /* Bit 5 */
#define EXTEN_LOCKUP_RSTF ((uint32_t)0x00000080) /* Bit 7 */
-#if defined(CH32V20x) || defined(CH32V30x)
+#if defined(CH32V20x) || defined(CH32V30x) || defined(CH32V10x)
#define EXTEN_ULLDO_TRIM ((uint32_t)0x00000300) /* ULLDO_TRIM[1:0] bits */
#define EXTEN_ULLDO_TRIM0 ((uint32_t)0x00000100) /* Bit 0 */
#define EXTEN_ULLDO_TRIM1 ((uint32_t)0x00000200) /* Bit 1 */
#endif
+#if !defined(CH32V10x)
+
#define EXTEN_LDO_TRIM ((uint32_t)0x00000400) /* Bit 10 */
#if defined(CH32V20x) || defined(CH32V30x)
#define EXTEN_LDO_TRIM0 ((uint32_t)0x00000400) /* Bit 0 */
#define EXTEN_LDO_TRIM1 ((uint32_t)0x00000800) /* Bit 1 */
#endif
+#else
+
+#define EXTEN_IDO_TRIM ((uint32_t)0x00000400) /* Bit 10 */
+#define EXTEN_WRITE_EN ((uint32_t)0x00004000) /* Bit 14 */
+#define EXTEN_SHORT_WAKE ((uint32_t)0x00008000) /* Bit 15 */
+
+#define EXTEN_FLASH_CLK_TRIM ((uint32_t)0x00070000) /* FLASH_CLK_TRIM[2:0] bits */
+#define EXTEN_FLASH_CLK_TRIM0 ((uint32_t)0x00010000) /* Bit 0 */
+#define EXTEN_FLASH_CLK_TRIM1 ((uint32_t)0x00020000) /* Bit 1 */
+#define EXTEN_FLASH_CLK_TRIM2 ((uint32_t)0x00040000) /* Bit 2 */
+
+#endif
+
#if defined(CH32V003)
#define EXTEN_OPA_EN ((uint32_t)0x00010000)
#define EXTEN_OPA_NSEL ((uint32_t)0x00020000)
@@ -5999,7 +6078,7 @@ extern "C" {
/* ch32v00x_gpio.c -----------------------------------------------------------*/
/* MASK */
-#if defined(CH32V20x) || defined(CH32V30x)
+#if defined(CH32V20x) || defined(CH32V30x) || defined(CH32V10x)
#define ECR_PORTPINCONFIG_MASK ((uint16_t)0xFF80)
#endif
#define LSB_MASK ((uint16_t)0xFFFF)
@@ -6104,7 +6183,7 @@ extern "C" {
/* ADC IDATARx registers offset */
#define IDATAR_Offset ((uint8_t)0x28)
-#if defined(CH32V20x) || defined(CH32V30x)
+#if defined(CH32V20x) || defined(CH32V30x) || defined(CH32V10x)
/* ADC1 RDATAR register base address */
#define RDATAR_ADDRESS ((uint32_t)0x4001244C)
@@ -6113,6 +6192,9 @@ extern "C" {
#define OCTLR_CAL_MASK ((uint16_t)0xFF80)
#define OCTLR_MASK ((uint16_t)0xFC7F)
+#endif
+
+#if defined(CH32V20x) || defined(CH32V30x)
/* ch32v20x_can.c ------------------------------------------------------------*/
/* CAN CTLR Register bits */
#define CTLR_DBF ((uint32_t)0x00010000)
@@ -6194,6 +6276,8 @@ extern "C" {
#define DMA2_Channel3_IT_Mask ((uint32_t)(DMA_GIF3 | DMA_TCIF3 | DMA_HTIF3 | DMA_TEIF3))
#define DMA2_Channel4_IT_Mask ((uint32_t)(DMA_GIF4 | DMA_TCIF4 | DMA_HTIF4 | DMA_TEIF4))
#define DMA2_Channel5_IT_Mask ((uint32_t)(DMA_GIF5 | DMA_TCIF5 | DMA_HTIF5 | DMA_TEIF5))
+#endif
+#if defined(CH32V30x) || defined(CH32V10x)
#define DMA2_Channel6_IT_Mask ((uint32_t)(DMA_GIF6 | DMA_TCIF6 | DMA_HTIF6 | DMA_TEIF6))
#define DMA2_Channel7_IT_Mask ((uint32_t)(DMA_GIF7 | DMA_TCIF7 | DMA_HTIF7 | DMA_TEIF7))
#define DMA2_Channel8_IT_Mask ((uint32_t)(DMA_GIF8 | DMA_TCIF8 | DMA_HTIF8 | DMA_TEIF8))
@@ -6220,11 +6304,17 @@ extern "C" {
/* ch32v00x_flash.c ----------------------------------------------------------*/
-#ifdef CH32V003
+#if defined(CH32V003) || defined(CH32V10x)
/* Flash Access Control Register bits */
#define ACR_LATENCY_Mask ((uint32_t)0x00000038)
#endif
+#if defined(CH32V10x)
+#define ACR_HLFCYA_Mask ((uint32_t)0xFFFFFFF7)
+#define ACR_PRFTBE_Mask ((uint32_t)0xFFFFFFEF)
+#define ACR_PRFTBS_Mask ((uint32_t)0x00000020)
+#endif
+
/* Flash Control Register bits */
#define CR_PG_Set ((uint32_t)0x00000001)
#define CR_PG_Reset ((uint32_t)0xFFFFFFFE)
@@ -6238,12 +6328,12 @@ extern "C" {
#define CR_OPTER_Reset ((uint32_t)0xFFFFFFDF)
#define CR_STRT_Set ((uint32_t)0x00000040)
#define CR_LOCK_Set ((uint32_t)0x00000080)
-#if defined(CH32V20x) || defined(CH32V30x)
+#if defined(CH32V20x) || defined(CH32V30x) || defined(CH32V10x)
#define CR_FAST_LOCK_Set ((uint32_t)0x00008000)
#endif
#define CR_PAGE_PG ((uint32_t)0x00010000)
#define CR_PAGE_ER ((uint32_t)0x00020000)
-#ifdef CH32V003
+#if defined(CH32V003) || defined(CH32V10x)
#define CR_BUF_LOAD ((uint32_t)0x00040000)
#define CR_BUF_RST ((uint32_t)0x00080000)
#elif defined(CH32V20x) || defined(CH32V30x)
@@ -6257,6 +6347,9 @@ extern "C" {
#if defined(CH32V20x) || defined(CH32V30x)
#define SR_WR_BSY ((uint32_t)0x00000002)
#endif
+#if defined(CH32V10x)
+#define SR_PGERR ((uint32_t)0x00000004)
+#endif
#define SR_WRPRTERR ((uint32_t)0x00000010)
#define SR_EOP ((uint32_t)0x00000020)
@@ -6266,7 +6359,7 @@ extern "C" {
#define WRP1_Mask ((uint32_t)0x0000FF00)
#define WRP2_Mask ((uint32_t)0x00FF0000)
#define WRP3_Mask ((uint32_t)0xFF000000)
-#if defined(CH32V20x) || defined(CH32V30x)
+#if defined(CH32V20x) || defined(CH32V30x) || defined(CH32V10x)
#define OB_USER_BFB2 ((uint16_t)0x0008)
#endif
@@ -6285,7 +6378,7 @@ extern "C" {
/* Delay definition */
#define EraseTimeout ((uint32_t)0x000B0000)
-#if defined(CH32V003) || defined(CH32V20x)
+#if defined(CH32V003) || defined(CH32V20x) || defined(CH32V10x)
#define ProgramTimeout ((uint32_t)0x00002000)
#elif defined(CH32V30x)
#define ProgramTimeout ((uint32_t)0x00005000)
@@ -6293,7 +6386,11 @@ extern "C" {
/* Flash Program Valid Address */
#define ValidAddrStart (FLASH_BASE)
+#if !defined(CH32V10x)
#define ValidAddrEnd (FLASH_BASE + 0x4000)
+#else
+#define ValidAddrEnd (FLASH_BASE + 0x10000)
+#endif
#if defined(CH32V30x)
@@ -6414,7 +6511,11 @@ extern "C" {
/* PWR registers bit mask */
/* CTLR register bit mask */
+#if !defined(CH32V10x)
#define CTLR_DS_MASK ((uint32_t)0xFFFFFFFD)
+#else
+#define CTLR_DS_MASK ((uint32_t)0xFFFFFFFC)
+#endif
#define CTLR_PLS_MASK ((uint32_t)0xFFFFFF1F)
#if defined(CH32V003)
#define AWUPSC_MASK ((uint32_t)0xFFFFFFF0)
@@ -6485,13 +6586,13 @@ extern "C" {
#ifdef CH32V003
static __I uint8_t APBAHBPrescTable[16] = {1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8};
static __I uint8_t ADCPrescTable[20] = {2, 4, 6, 8, 4, 8, 12, 16, 8, 16, 24, 32, 16, 32, 48, 64, 32, 64, 96, 128};
-#elif defined(CH32V20x) || defined(CH32V30x)
+#elif defined(CH32V20x) || defined(CH32V30x) || defined(CH32V10x)
static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
static __I uint8_t ADCPrescTable[4] = {2, 4, 6, 8};
#endif
#endif
-#if defined(CH32V20x) || defined(CH32V30x)
+#if defined(CH32V20x) || defined(CH32V30x) || defined(CH32V10x)
/* ch32v20x_rtc.c ------------------------------------------------------------*/
@@ -6529,7 +6630,7 @@ static __I uint8_t ADCPrescTable[4] = {2, 4, 6, 8};
#define CTLR1_SPE_Set ((uint16_t)0x0040)
#define CTLR1_SPE_Reset ((uint16_t)0xFFBF)
-#if defined(CH32V20x) || defined(CH32V30x)
+#if defined(CH32V20x) || defined(CH32V30x) || defined(CH32V10x)
/* I2S I2SE mask */
#define I2SCFGR_I2SE_Set ((uint16_t)0x0400)
#define I2SCFGR_I2SE_Reset ((uint16_t)0xFBFF)
@@ -6551,7 +6652,7 @@ static __I uint8_t ADCPrescTable[4] = {2, 4, 6, 8};
#define SPI_CTLR1_CLEAR_Mask ((uint16_t)0x3040)
#define I2SCFGR_CLEAR_Mask ((uint16_t)0xF040)
-#if defined(CH32V20x) || defined(CH32V30x)
+#if defined(CH32V20x) || defined(CH32V30x) || defined(CH32V10x)
/* SPI or I2S mode selection masks */
#define SPI_Mode_Select ((uint16_t)0xF7FF)
#define I2S_Mode_Select ((uint16_t)0x0800)
@@ -6622,7 +6723,6 @@ static __I uint8_t ADCPrescTable[4] = {2, 4, 6, 8};
/* ch32v00x_wwdg.c ------------------------------------------------------------*/
-
/* CTLR register bit mask */
#define CTLR_WDGA_Set ((uint32_t)0x00000080)
@@ -6634,11 +6734,9 @@ static __I uint8_t ADCPrescTable[4] = {2, 4, 6, 8};
/* ch32v00x_adc.h ------------------------------------------------------------*/
-
-
/* ADC_mode */
#define ADC_Mode_Independent ((uint32_t)0x00000000)
-#if defined(CH32V20x) || defined(CH32V30x)
+#if defined(CH32V20x) || defined(CH32V30x) || defined(CH32V10x)
#define ADC_Mode_RegInjecSimult ((uint32_t)0x00010000)
#define ADC_Mode_RegSimult_AlterTrig ((uint32_t)0x00020000)
#define ADC_Mode_InjecSimult_FastInterl ((uint32_t)0x00030000)
@@ -6662,7 +6760,7 @@ static __I uint8_t ADCPrescTable[4] = {2, 4, 6, 8};
#define ADC_ExternalTrigConv_Ext_PD3_PC2 ((uint32_t)0x000C0000)
#define ADC_ExternalTrigConv_None ((uint32_t)0x000E0000)
-#elif defined(CH32V20x) || defined(CH32V30x)
+#elif defined(CH32V20x) || defined(CH32V30x) || defined(CH32V10x)
#define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00000000)
#define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x00020000)
@@ -6674,6 +6772,10 @@ static __I uint8_t ADCPrescTable[4] = {2, 4, 6, 8};
#define ADC_ExternalTrigConv_T1_CC3 ((uint32_t)0x00040000)
#define ADC_ExternalTrigConv_None ((uint32_t)0x000E0000)
+#endif
+
+#if defined(CH32V20x) || defined(CH32V30x)
+
#define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x00000000)
#define ADC_ExternalTrigConv_T2_CC3 ((uint32_t)0x00020000)
#define ADC_ExternalTrigConv_T8_CC1 ((uint32_t)0x00060000)
@@ -6698,7 +6800,7 @@ static __I uint8_t ADCPrescTable[4] = {2, 4, 6, 8};
#define ADC_Channel_7 ((uint8_t)0x07)
#define ADC_Channel_8 ((uint8_t)0x08)
#define ADC_Channel_9 ((uint8_t)0x09)
-#if defined(CH32V20x) || defined(CH32V30x)
+#if defined(CH32V20x) || defined(CH32V30x) || defined(CH32V10x)
#define ADC_Channel_10 ((uint8_t)0x0A)
#define ADC_Channel_11 ((uint8_t)0x0B)
#define ADC_Channel_12 ((uint8_t)0x0C)
@@ -6712,7 +6814,7 @@ static __I uint8_t ADCPrescTable[4] = {2, 4, 6, 8};
#ifdef CH32V003
#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_8)
#define ADC_Channel_Vcalint ((uint8_t)ADC_Channel_9)
-#elif defined(CH32V20x) || defined(CH32V30x)
+#elif defined(CH32V20x) || defined(CH32V30x) || defined(CH32V10x)
#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16)
#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17)
#endif
@@ -6739,7 +6841,7 @@ static __I uint8_t ADCPrescTable[4] = {2, 4, 6, 8};
#define ADC_SampleTime_57Cycles ((uint8_t)0x05)
#define ADC_SampleTime_73Cycles ((uint8_t)0x06)
#define ADC_SampleTime_241Cycles ((uint8_t)0x07)
-#elif defined(CH32V20x) || defined(CH32V30x)
+#elif defined(CH32V20x) || defined(CH32V30x) || defined(CH32V10x)
#define ADC_SampleTime_1Cycles5 ((uint8_t)0x00)
#define ADC_SampleTime_7Cycles5 ((uint8_t)0x01)
#define ADC_SampleTime_13Cycles5 ((uint8_t)0x02)
@@ -6758,7 +6860,7 @@ static __I uint8_t ADCPrescTable[4] = {2, 4, 6, 8};
#define ADC_ExternalTrigInjecConv_T2_CC4 ((uint32_t)0x00003000)
#define ADC_ExternalTrigInjecConv_Ext_PD1_PA2 ((uint32_t)0x00006000)
#define ADC_ExternalTrigInjecConv_None ((uint32_t)0x00007000)
-#elif defined(CH32V20x) || defined(CH32V30x)
+#elif defined(CH32V20x) || defined(CH32V30x) || defined(CH32V10x)
#define ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00002000)
#define ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00003000)
#define ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00004000)
@@ -6768,7 +6870,9 @@ static __I uint8_t ADCPrescTable[4] = {2, 4, 6, 8};
#define ADC_ExternalTrigInjecConv_T1_TRGO ((uint32_t)0x00000000)
#define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00001000)
#define ADC_ExternalTrigInjecConv_None ((uint32_t)0x00007000)
+#endif
+#if defined(CH32V20x) || defined(CH32V30x)
#define ADC_ExternalTrigInjecConv_T4_CC3 ((uint32_t)0x00002000)
#define ADC_ExternalTrigInjecConv_T8_CC2 ((uint32_t)0x00003000)
#define ADC_ExternalTrigInjecConv_T8_CC4 ((uint32_t)0x00004000)
@@ -6813,9 +6917,9 @@ static __I uint8_t ADCPrescTable[4] = {2, 4, 6, 8};
#define ADC_ExternalTrigInjec_DLY ((uint32_t)0x00020000)
#endif
-#if defined(CH32V20x)
+#if defined(CH32V20x) || defined(CH32V10x)
-/* ch32v00x_bkp.h ------------------------------------------------------------*/
+/* ch32v20x_bkp.h ------------------------------------------------------------*/
/* Tamper_Pin_active_level */
#define BKP_TamperPinLevel_High ((uint16_t)0x0000)
@@ -6871,7 +6975,11 @@ static __I uint8_t ADCPrescTable[4] = {2, 4, 6, 8};
#define BKP_DR41 ((uint16_t)0x00B8)
#define BKP_DR42 ((uint16_t)0x00BC)
-/* ch32v00x_can.h ------------------------------------------------------------*/
+#endif
+
+#if defined(CH32V20x)
+
+/* ch32v20x_can.h ------------------------------------------------------------*/
/* CAN_sleep_constants */
#define CAN_InitStatus_Failed ((uint8_t)0x00) /* CAN initialization failed */
@@ -7148,6 +7256,18 @@ static __I uint8_t ADCPrescTable[4] = {2, 4, 6, 8};
#define DBGMCU_CAN2_STOP ((uint32_t)0x00200000)
#define DBGMCU_TIM9_STOP ((uint32_t)0x00400000)
#define DBGMCU_TIM10_STOP ((uint32_t)0x00800000)
+#elif defined(CH32V10x)
+#define DBGMCU_IWDG_STOP ((uint32_t)0x00000001)
+#define DBGMCU_WWDG_STOP ((uint32_t)0x00000002)
+#define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00000004)
+#define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00000008)
+#define DBGMCU_TIM1_STOP ((uint32_t)0x00000010)
+#define DBGMCU_TIM2_STOP ((uint32_t)0x00000020)
+#define DBGMCU_TIM3_STOP ((uint32_t)0x00000040)
+#define DBGMCU_TIM4_STOP ((uint32_t)0x00000080)
+#define DBGMCU_SLEEP ((uint32_t)0x00000001)
+#define DBGMCU_STOP ((uint32_t)0x00000002)
+#define DBGMCU_STANDBY ((uint32_t)0x00000004)
#endif
/* ch32v00x_dma.h ------------------------------------------------------------*/
@@ -7228,7 +7348,7 @@ static __I uint8_t ADCPrescTable[4] = {2, 4, 6, 8};
#define DMA1_IT_TE8 ((uint32_t)0x80000000)
#endif
-#if defined(CH32V30x)
+#if defined(CH32V30x) || defined(CH32V10x)
#define DMA2_IT_GL1 ((uint32_t)0x10000001)
#define DMA2_IT_TC1 ((uint32_t)0x10000002)
#define DMA2_IT_HT1 ((uint32_t)0x10000004)
@@ -7249,6 +7369,8 @@ static __I uint8_t ADCPrescTable[4] = {2, 4, 6, 8};
#define DMA2_IT_TC5 ((uint32_t)0x10020000)
#define DMA2_IT_HT5 ((uint32_t)0x10040000)
#define DMA2_IT_TE5 ((uint32_t)0x10080000)
+#endif
+#if defined(CH32V30x)
#define DMA2_IT_GL6 ((uint32_t)0x10100000)
#define DMA2_IT_TC6 ((uint32_t)0x10200000)
#define DMA2_IT_HT6 ((uint32_t)0x10400000)
@@ -7312,7 +7434,7 @@ static __I uint8_t ADCPrescTable[4] = {2, 4, 6, 8};
#define DMA1_FLAG_TE8 ((uint32_t)0x80000000)
#endif
-#if defined(CH32V30x)
+#if defined(CH32V30x) || defined(CH32V10x)
#define DMA2_FLAG_GL1 ((uint32_t)0x10000001)
#define DMA2_FLAG_TC1 ((uint32_t)0x10000002)
#define DMA2_FLAG_HT1 ((uint32_t)0x10000004)
@@ -7333,6 +7455,9 @@ static __I uint8_t ADCPrescTable[4] = {2, 4, 6, 8};
#define DMA2_FLAG_TC5 ((uint32_t)0x10020000)
#define DMA2_FLAG_HT5 ((uint32_t)0x10040000)
#define DMA2_FLAG_TE5 ((uint32_t)0x10080000)
+#endif
+
+#if defined(CH32V30x)
#define DMA2_FLAG_GL6 ((uint32_t)0x10100000)
#define DMA2_FLAG_TC6 ((uint32_t)0x10200000)
#define DMA2_FLAG_HT6 ((uint32_t)0x10400000)
@@ -8427,6 +8552,8 @@ typedef enum
#define EXTI_Line13 ((uint32_t)0x02000) /* External interrupt line 13 */
#define EXTI_Line14 ((uint32_t)0x04000) /* External interrupt line 14 */
#define EXTI_Line15 ((uint32_t)0x08000) /* External interrupt line 15 */
+#endif
+#if defined(CH32V20x) || defined(CH32V30x)
#define EXTI_Line16 ((uint32_t)0x10000) /* External interrupt line 16 Connected to the PVD Output */
#define EXTI_Line17 ((uint32_t)0x20000) /* External interrupt line 17 Connected to the RTC Alarm event */
#define EXTI_Line18 ((uint32_t)0x40000) /* External interrupt line 18 Connected to the USBD Device \
@@ -8437,6 +8564,12 @@ typedef enum
#if defined(CH32V20x_D8) || defined(CH32V20x_D8W)
#define EXTI_Line21 ((uint32_t)0x200000) /* External interrupt line 21 Connected to the OSCCAL Wakeup event */
#endif
+
+#elif defined(CH32V10x)
+#define EXTI_Line16 ((uint32_t)0x10000) /* External interrupt line 16 Connected to the PVD Output */
+#define EXTI_Line17 ((uint32_t)0x20000) /* External interrupt line 17 Connected to the RTC Alarm event */
+#define EXTI_Line18 ((uint32_t)0x40000)
+#define EXTI_Line19 ((uint32_t)0x80000) /* External interrupt line 19 Connected to the USBHD Wakeup event */
#endif
/* ch32v00x_flash.h ----------------------------------------------------------*/
@@ -8454,12 +8587,24 @@ typedef enum
} FLASH_Status;
#endif
-#ifdef CH32V003
+#if defined(CH32V003) || defined(CH32V10x)
/* Flash_Latency */
#define FLASH_Latency_0 ((uint32_t)0x00000000) /* FLASH Zero Latency cycle */
#define FLASH_Latency_1 ((uint32_t)0x00000001) /* FLASH One Latency cycle */
#define FLASH_Latency_2 ((uint32_t)0x00000002) /* FLASH Two Latency cycles */
+#endif
+#if defined(CH32V10x)
+/* Half_Cycle_Enable_Disable */
+#define FLASH_HalfCycleAccess_Enable ((uint32_t)0x00000008) /* FLASH Half Cycle Enable */
+#define FLASH_HalfCycleAccess_Disable ((uint32_t)0x00000000) /* FLASH Half Cycle Disable */
+
+/* Prefetch_Buffer_Enable_Disable */
+#define FLASH_PrefetchBuffer_Enable ((uint32_t)0x00000010) /* FLASH Prefetch Buffer Enable */
+#define FLASH_PrefetchBuffer_Disable ((uint32_t)0x00000000) /* FLASH Prefetch Buffer Disable */
+#endif
+
+#ifdef CH32V003
/* Values to be used with CH32V00x devices (1page = 64Byte) */
#define FLASH_WRProt_Pages0to15 ((uint32_t)0x00000001) /* CH32 Low and Medium density devices: Write protection of page 0 to 15 */
#define FLASH_WRProt_Pages16to31 ((uint32_t)0x00000002) /* CH32 Low and Medium density devices: Write protection of page 16 to 31 */
@@ -8480,7 +8625,7 @@ typedef enum
#define FLASH_WRProt_AllPages ((uint32_t)0x0000FFFF) /* Write protection of all Pages */
-#elif defined(CH32V20x)
+#elif defined(CH32V20x) || defined(CH32V30x)
/* Write Protect */
#define FLASH_WRProt_Sectors0 ((uint32_t)0x00000001) /* Write protection of setor 0 */
#define FLASH_WRProt_Sectors1 ((uint32_t)0x00000002) /* Write protection of setor 0 */
@@ -8516,6 +8661,48 @@ typedef enum
#define FLASH_WRProt_Sectors31to127 ((uint32_t)0x80000000) /* Write protection of page 62 to 255 */
#define FLASH_WRProt_AllSectors ((uint32_t)0xFFFFFFFF) /* Write protection of all Sectors */
+
+#elif defined(CH32V10x)
+/* Values to be used with CH32V10x Low and Medium density devices */
+#define FLASH_WRProt_Pages0to3 ((uint32_t)0x00000001) /* CH32 Low and Medium density devices: Write protection of page 0 to 3 */
+#define FLASH_WRProt_Pages4to7 ((uint32_t)0x00000002) /* CH32 Low and Medium density devices: Write protection of page 4 to 7 */
+#define FLASH_WRProt_Pages8to11 ((uint32_t)0x00000004) /* CH32 Low and Medium density devices: Write protection of page 8 to 11 */
+#define FLASH_WRProt_Pages12to15 ((uint32_t)0x00000008) /* CH32 Low and Medium density devices: Write protection of page 12 to 15 */
+#define FLASH_WRProt_Pages16to19 ((uint32_t)0x00000010) /* CH32 Low and Medium density devices: Write protection of page 16 to 19 */
+#define FLASH_WRProt_Pages20to23 ((uint32_t)0x00000020) /* CH32 Low and Medium density devices: Write protection of page 20 to 23 */
+#define FLASH_WRProt_Pages24to27 ((uint32_t)0x00000040) /* CH32 Low and Medium density devices: Write protection of page 24 to 27 */
+#define FLASH_WRProt_Pages28to31 ((uint32_t)0x00000080) /* CH32 Low and Medium density devices: Write protection of page 28 to 31 */
+
+/* Values to be used with CH32V10x Medium-density devices */
+#define FLASH_WRProt_Pages32to35 ((uint32_t)0x00000100) /* CH32 Medium-density devices: Write protection of page 32 to 35 */
+#define FLASH_WRProt_Pages36to39 ((uint32_t)0x00000200) /* CH32 Medium-density devices: Write protection of page 36 to 39 */
+#define FLASH_WRProt_Pages40to43 ((uint32_t)0x00000400) /* CH32 Medium-density devices: Write protection of page 40 to 43 */
+#define FLASH_WRProt_Pages44to47 ((uint32_t)0x00000800) /* CH32 Medium-density devices: Write protection of page 44 to 47 */
+#define FLASH_WRProt_Pages48to51 ((uint32_t)0x00001000) /* CH32 Medium-density devices: Write protection of page 48 to 51 */
+#define FLASH_WRProt_Pages52to55 ((uint32_t)0x00002000) /* CH32 Medium-density devices: Write protection of page 52 to 55 */
+#define FLASH_WRProt_Pages56to59 ((uint32_t)0x00004000) /* CH32 Medium-density devices: Write protection of page 56 to 59 */
+#define FLASH_WRProt_Pages60to63 ((uint32_t)0x00008000) /* CH32 Medium-density devices: Write protection of page 60 to 63 */
+#define FLASH_WRProt_Pages64to67 ((uint32_t)0x00010000) /* CH32 Medium-density devices: Write protection of page 64 to 67 */
+#define FLASH_WRProt_Pages68to71 ((uint32_t)0x00020000) /* CH32 Medium-density devices: Write protection of page 68 to 71 */
+#define FLASH_WRProt_Pages72to75 ((uint32_t)0x00040000) /* CH32 Medium-density devices: Write protection of page 72 to 75 */
+#define FLASH_WRProt_Pages76to79 ((uint32_t)0x00080000) /* CH32 Medium-density devices: Write protection of page 76 to 79 */
+#define FLASH_WRProt_Pages80to83 ((uint32_t)0x00100000) /* CH32 Medium-density devices: Write protection of page 80 to 83 */
+#define FLASH_WRProt_Pages84to87 ((uint32_t)0x00200000) /* CH32 Medium-density devices: Write protection of page 84 to 87 */
+#define FLASH_WRProt_Pages88to91 ((uint32_t)0x00400000) /* CH32 Medium-density devices: Write protection of page 88 to 91 */
+#define FLASH_WRProt_Pages92to95 ((uint32_t)0x00800000) /* CH32 Medium-density devices: Write protection of page 92 to 95 */
+#define FLASH_WRProt_Pages96to99 ((uint32_t)0x01000000) /* CH32 Medium-density devices: Write protection of page 96 to 99 */
+#define FLASH_WRProt_Pages100to103 ((uint32_t)0x02000000) /* CH32 Medium-density devices: Write protection of page 100 to 103 */
+#define FLASH_WRProt_Pages104to107 ((uint32_t)0x04000000) /* CH32 Medium-density devices: Write protection of page 104 to 107 */
+#define FLASH_WRProt_Pages108to111 ((uint32_t)0x08000000) /* CH32 Medium-density devices: Write protection of page 108 to 111 */
+#define FLASH_WRProt_Pages112to115 ((uint32_t)0x10000000) /* CH32 Medium-density devices: Write protection of page 112 to 115 */
+#define FLASH_WRProt_Pages116to119 ((uint32_t)0x20000000) /* CH32 Medium-density devices: Write protection of page 115 to 119 */
+#define FLASH_WRProt_Pages120to123 ((uint32_t)0x40000000) /* CH32 Medium-density devices: Write protection of page 120 to 123 */
+#define FLASH_WRProt_Pages124to127 ((uint32_t)0x80000000) /* CH32 Medium-density devices: Write protection of page 124 to 127 */
+
+#define FLASH_WRProt_Pages62to255 ((uint32_t)0x80000000) /* CH32 Medium-density devices: Write protection of page 62 to 255 */
+
+#define FLASH_WRProt_AllPages ((uint32_t)0xFFFFFFFF) /* Write protection of all Pages */
+
#endif
/* Option_Bytes_IWatchdog */
@@ -8547,11 +8734,17 @@ typedef enum
/* FLASH_Flags */
#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /* FLASH Busy flag */
#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /* FLASH End of Operation flag */
+#if defined(CH32V10x)
+#define FLASH_FLAG_PGERR ((uint32_t)0x00000004) /* FLASH Program error flag */
+#endif
#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /* FLASH Write protected error flag */
#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /* FLASH Option Byte error flag */
#define FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY /* FLASH BANK1 Busy flag*/
#define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP /* FLASH BANK1 End of Operation flag */
+#if defined(CH32V10x)
+#define FLASH_FLAG_BANK1_PGERR FLASH_FLAG_PGERR /* FLASH BANK1 Program error flag */
+#endif
#define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /* FLASH BANK1 Write protected error flag */
#if defined(CH32V20x) || defined(CH32V30x)
@@ -8718,7 +8911,7 @@ typedef enum
#define GPIO_Pin_5 ((uint16_t)0x0020) /* Pin 5 selected */
#define GPIO_Pin_6 ((uint16_t)0x0040) /* Pin 6 selected */
#define GPIO_Pin_7 ((uint16_t)0x0080) /* Pin 7 selected */
-#if defined(CH32V20x) || defined(CH32V30x)
+#if defined(CH32V20x) || defined(CH32V30x) || defined(CH32V10x)
#define GPIO_Pin_8 ((uint16_t)0x0100) /* Pin 8 selected */
#define GPIO_Pin_9 ((uint16_t)0x0200) /* Pin 9 selected */
#define GPIO_Pin_10 ((uint16_t)0x0400) /* Pin 10 selected */
@@ -8805,13 +8998,44 @@ typedef enum
#define GPIO_FullRemap_USART8 ((uint32_t)0x80380200) /* USART8 Full Alternate Function mapping */
#define GPIO_Remap_USART1_HighBit ((uint32_t)0x80200400) /* USART1 Alternate Function mapping high bit */
+#elif defined(CH32V10x)
+
+/* GPIO_Remap_define */
+#define GPIO_Remap_SPI1 ((uint32_t)0x00000001) /* SPI1 Alternate Function mapping */
+#define GPIO_Remap_I2C1 ((uint32_t)0x00000002) /* I2C1 Alternate Function mapping */
+#define GPIO_Remap_USART1 ((uint32_t)0x00000004) /* USART1 Alternate Function mapping */
+#define GPIO_Remap_USART2 ((uint32_t)0x00000008) /* USART2 Alternate Function mapping */
+#define GPIO_PartialRemap_USART3 ((uint32_t)0x00140010) /* USART3 Partial Alternate Function mapping */
+#define GPIO_FullRemap_USART3 ((uint32_t)0x00140030) /* USART3 Full Alternate Function mapping */
+#define GPIO_PartialRemap_TIM1 ((uint32_t)0x00160040) /* TIM1 Partial Alternate Function mapping */
+#define GPIO_FullRemap_TIM1 ((uint32_t)0x001600C0) /* TIM1 Full Alternate Function mapping */
+#define GPIO_PartialRemap1_TIM2 ((uint32_t)0x00180100) /* TIM2 Partial1 Alternate Function mapping */
+#define GPIO_PartialRemap2_TIM2 ((uint32_t)0x00180200) /* TIM2 Partial2 Alternate Function mapping */
+#define GPIO_FullRemap_TIM2 ((uint32_t)0x00180300) /* TIM2 Full Alternate Function mapping */
+#define GPIO_PartialRemap_TIM3 ((uint32_t)0x001A0800) /* TIM3 Partial Alternate Function mapping */
+#define GPIO_FullRemap_TIM3 ((uint32_t)0x001A0C00) /* TIM3 Full Alternate Function mapping */
+#define GPIO_Remap_TIM4 ((uint32_t)0x00001000) /* TIM4 Alternate Function mapping */
+#define GPIO_Remap1_CAN1 ((uint32_t)0x001D4000) /* CAN1 Alternate Function mapping */
+#define GPIO_Remap2_CAN1 ((uint32_t)0x001D6000) /* CAN1 Alternate Function mapping */
+#define GPIO_Remap_PD01 ((uint32_t)0x00008000) /* PD01 Alternate Function mapping */
+#define GPIO_Remap_ADC1_ETRGINJ ((uint32_t)0x00200002) /* ADC1 External Trigger Injected Conversion remapping */
+#define GPIO_Remap_ADC1_ETRGREG ((uint32_t)0x00200004) /* ADC1 External Trigger Regular Conversion remapping */
+#define GPIO_Remap_SWJ_Disable ((uint32_t)0x00300400) /* Full SWJ Disabled (JTAG-DP + SW-DP) */
+#define GPIO_Remap_TIM2ITR1_PTP_SOF ((uint32_t)0x00202000) /* Ethernet PTP output or USB OTG SOF (Start of Frame) connected \
+ to TIM2 Internal Trigger 1 for calibration \
+ (only for Connectivity line devices) */
+#define GPIO_Remap_TIM1_DMA ((uint32_t)0x80000010) /* TIM1 DMA requests mapping (only for Value line devices) */
+#define GPIO_Remap_TIM67_DAC_DMA ((uint32_t)0x80000800) /* TIM6/TIM7 and DAC DMA requests remapping (only for High density Value line devices) */
+#define GPIO_Remap_MISC ((uint32_t)0x80002000) /* Miscellaneous Remap (DMA2 Channel5 Position and DAC Trigger remapping, \
+ only for High density Value line devices) */
+
#endif
/* GPIO_Port_Sources */
#define GPIO_PortSourceGPIOA ((uint8_t)0x00)
#define GPIO_PortSourceGPIOC ((uint8_t)0x02)
#define GPIO_PortSourceGPIOD ((uint8_t)0x03)
-#if defined(CH32V20x) || defined(CH32V30x)
+#if defined(CH32V20x) || defined(CH32V30x) || defined(CH32V10x)
#define GPIO_PortSourceGPIOB ((uint8_t)0x01)
#define GPIO_PortSourceGPIOD ((uint8_t)0x03)
#define GPIO_PortSourceGPIOE ((uint8_t)0x04)
@@ -8828,7 +9052,7 @@ typedef enum
#define GPIO_PinSource5 ((uint8_t)0x05)
#define GPIO_PinSource6 ((uint8_t)0x06)
#define GPIO_PinSource7 ((uint8_t)0x07)
-#if defined(CH32V20x) || defined(CH32V30x)
+#if defined(CH32V20x) || defined(CH32V30x) || defined(CH32V10x)
#define GPIO_PinSource8 ((uint8_t)0x08)
#define GPIO_PinSource9 ((uint8_t)0x09)
#define GPIO_PinSource10 ((uint8_t)0x0A)
@@ -8837,7 +9061,9 @@ typedef enum
#define GPIO_PinSource13 ((uint8_t)0x0D)
#define GPIO_PinSource14 ((uint8_t)0x0E)
#define GPIO_PinSource15 ((uint8_t)0x0F)
+#endif
+#if defined(CH32V20x) || defined(CH32V30x)
/* Ethernet_Media_Interface */
#define GPIO_ETH_MediaInterface_MII ((u32)0x00000000)
#define GPIO_ETH_MediaInterface_RMII ((u32)0x00000001)
@@ -8847,7 +9073,7 @@ typedef enum
/* I2C_mode */
#define I2C_Mode_I2C ((uint16_t)0x0000)
-#if defined(CH32V20x) || defined(CH32V30x)
+#if defined(CH32V20x) || defined(CH32V30x) || defined(CH32V10x)
#define I2C_Mode_SMBusDevice ((uint16_t)0x0002)
#define I2C_Mode_SMBusHost ((uint16_t)0x000A)
#endif
@@ -8877,7 +9103,7 @@ typedef enum
#define I2C_Register_STAR1 ((uint8_t)0x14)
#define I2C_Register_STAR2 ((uint8_t)0x18)
#define I2C_Register_CKCFGR ((uint8_t)0x1C)
-#if defined(CH32V20x) || defined(CH32V30x)
+#if defined(CH32V20x) || defined(CH32V30x) || defined(CH32V10x)
#define I2C_Register_RTR ((uint8_t)0x20)
/* I2C_SMBus_alert_pin_level */
@@ -8914,7 +9140,7 @@ typedef enum
/* SR2 register flags */
#define I2C_FLAG_DUALF ((uint32_t)0x00800000)
-#if defined(CH32V20x) || defined(CH32V30x)
+#if defined(CH32V20x) || defined(CH32V30x) || defined(CH32V10x)
#define I2C_FLAG_SMBHOST ((uint32_t)0x00400000)
#define I2C_FLAG_SMBDEFAULT ((uint32_t)0x00200000)
#endif
@@ -8924,7 +9150,7 @@ typedef enum
#define I2C_FLAG_MSL ((uint32_t)0x00010000)
/* SR1 register flags */
-#if defined(CH32V20x) || defined(CH32V30x)
+#if defined(CH32V20x) || defined(CH32V30x) || defined(CH32V10x)
#define I2C_FLAG_SMBALERT ((uint32_t)0x10008000)
#define I2C_FLAG_TIMEOUT ((uint32_t)0x10004000)
#endif
@@ -9135,7 +9361,7 @@ typedef enum
#define NVIC_PriorityGroup_3 ((uint32_t)0x03)
#define NVIC_PriorityGroup_4 ((uint32_t)0x04)
-
+#if !defined(CH32V10x)
/* ch32v00x_opa.h ------------------------------------------------------------*/
/* Editor's note: I don't know if this is actually useful */
@@ -9193,6 +9419,7 @@ typedef struct
} OPA_InitTypeDef;
#endif
+#endif
/* ch32v00x_pwr.h ------------------------------------------------------------*/
@@ -9234,7 +9461,7 @@ typedef struct
/* PWR_Flag */
#define PWR_FLAG_PVDO ((uint32_t)0x00000004)
-#elif defined(CH32V20x)
+#elif defined(CH32V20x) || defined(CH32V30x) || defined(CH32V10x)
/* PVD_detection_level */
#define PWR_PVDLevel_2V2 ((uint32_t)0x00000000)
@@ -9276,12 +9503,12 @@ typedef struct
#define RCC_PLLSource_HSI_MUL2 ((uint32_t)0x00000000)
#define RCC_PLLSource_HSE_MUL2 ((uint32_t)0x00030000)
-#elif defined(CH32V20x) || defined(CH32V30x)
+#elif defined(CH32V20x) || defined(CH32V30x) || defined(CH32V10x)
/* PLL_entry_clock_source */
#define RCC_PLLSource_HSI_Div2 ((uint32_t)0x00000000)
-#if defined(CH32V20x) || defined(CH32V30x_D8)
+#if defined(CH32V20x) || defined(CH32V30x_D8) || defined(CH32V10x)
#define RCC_PLLSource_HSE_Div1 ((uint32_t)0x00010000)
#define RCC_PLLSource_HSE_Div2 ((uint32_t)0x00030000)
@@ -9292,7 +9519,7 @@ typedef struct
#endif
-#if defined(CH32V20x) || defined(CH32V30x_D8)
+#if defined(CH32V20x) || defined(CH32V30x_D8) || defined(CH32V10x)
/* PLL_multiplication_factor for other CH32V20x */
#define RCC_PLLMul_2 ((uint32_t)0x00000000)
@@ -9310,7 +9537,10 @@ typedef struct
#define RCC_PLLMul_14 ((uint32_t)0x00300000)
#define RCC_PLLMul_15 ((uint32_t)0x00340000)
#define RCC_PLLMul_16 ((uint32_t)0x00380000)
+
+#if !defined(CH32V10x)
#define RCC_PLLMul_18 ((uint32_t)0x003C0000)
+#endif
#else
@@ -9358,7 +9588,6 @@ typedef struct
#ifdef CH32V30x_D8C
#define RCC_PREDIV1_Source_HSE ((uint32_t)0x00000000)
#define RCC_PREDIV1_Source_PLL2 ((uint32_t)0x00010000)
-
#endif
/* PREDIV2_division_factor */
@@ -9379,7 +9608,6 @@ typedef struct
#define RCC_PREDIV2_Div14 ((uint32_t)0x000000D0)
#define RCC_PREDIV2_Div15 ((uint32_t)0x000000E0)
#define RCC_PREDIV2_Div16 ((uint32_t)0x000000F0)
-
#endif
/* PLL2_multiplication_factor */
@@ -9400,7 +9628,6 @@ typedef struct
#define RCC_PLL2Mul_15 ((uint32_t)0x00000D00)
#define RCC_PLL2Mul_16 ((uint32_t)0x00000E00)
#define RCC_PLL2Mul_20 ((uint32_t)0x00000F00)
-
#endif
/* PLL3_multiplication_factor */
@@ -9421,7 +9648,6 @@ typedef struct
#define RCC_PLL3Mul_15 ((uint32_t)0x0000D000)
#define RCC_PLL3Mul_16 ((uint32_t)0x0000E000)
#define RCC_PLL3Mul_20 ((uint32_t)0x0000F000)
-
#endif
#endif
@@ -9448,7 +9674,7 @@ typedef struct
#define RCC_SYSCLK_Div128 ((uint32_t)0x000000E0)
#define RCC_SYSCLK_Div256 ((uint32_t)0x000000F0)
-#elif defined(CH32V20x) || defined(CH32V30x)
+#elif defined(CH32V20x) || defined(CH32V30x) || defined(CH32V10x)
/* AHB_clock_source */
#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000)
@@ -9472,7 +9698,7 @@ typedef struct
/* RCC_Interrupt_source */
#define RCC_IT_LSIRDY ((uint8_t)0x01)
-#if defined(CH32V20x) || defined(CH32V30x)
+#if defined(CH32V20x) || defined(CH32V30x) || defined(CH32V10x)
#define RCC_IT_LSERDY ((uint8_t)0x02)
#endif
#define RCC_IT_HSIRDY ((uint8_t)0x04)
@@ -9498,6 +9724,12 @@ typedef struct
#endif
+#if defined(CH32V10x)
+/* USB_Device_clock_source */
+#define RCC_USBCLKSource_PLLCLK_1Div5 ((uint8_t)0x00)
+#define RCC_USBCLKSource_PLLCLK_Div1 ((uint8_t)0x01)
+#endif
+
#if defined(CH32V30x)
/* USB_OTG_FS_clock_source */
@@ -9535,7 +9767,7 @@ typedef struct
#define RCC_PCLK2_Div96 ((uint32_t)0x0000B800)
#define RCC_PCLK2_Div128 ((uint32_t)0x0000F800)
-#elif defined(CH32V20x) || defined(CH32V30x)
+#elif defined(CH32V20x) || defined(CH32V30x) || defined(CH32V10x)
/* ADC_clock_source */
#define RCC_PCLK2_Div2 ((uint32_t)0x00000000)
@@ -9577,18 +9809,27 @@ typedef struct
#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000)
#define RCC_APB1Periph_PWR ((uint32_t)0x10000000)
-#elif defined(CH32V20x) || defined(CH32V30x)
+#elif defined(CH32V20x) || defined(CH32V30x) || defined(CH32V10x)
/* AHB_peripheral */
#define RCC_AHBPeriph_DMA1 ((uint32_t)0x00000001)
#define RCC_AHBPeriph_DMA2 ((uint32_t)0x00000002)
#define RCC_AHBPeriph_SRAM ((uint32_t)0x00000004)
+#if defined(CH32V10x)
+#define RCC_AHBPeriph_FLITF ((uint32_t)0x00000010)
+#endif
#define RCC_AHBPeriph_CRC ((uint32_t)0x00000040)
#define RCC_AHBPeriph_FSMC ((uint32_t)0x00000100)
+#if !defined(CH32V10x)
#define RCC_AHBPeriph_RNG ((uint32_t)0x00000200)
+#endif
#define RCC_AHBPeriph_SDIO ((uint32_t)0x00000400)
+#if !defined(CH32V10x)
#define RCC_AHBPeriph_USBHS ((uint32_t)0x00000800)
#define RCC_AHBPeriph_OTG_FS ((uint32_t)0x00001000)
+#else
+#define RCC_AHBPeriph_USBHD ((uint32_t)0x00001000)
+#endif
#if defined(CH32V30x)
#define RCC_AHBPeriph_DVP ((uint32_t)0x00002000)
@@ -9614,8 +9855,18 @@ typedef struct
#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000)
#define RCC_APB2Periph_TIM8 ((uint32_t)0x00002000)
#define RCC_APB2Periph_USART1 ((uint32_t)0x00004000)
+#if !defined(CH32V10x)
#define RCC_APB2Periph_TIM9 ((uint32_t)0x00080000)
#define RCC_APB2Periph_TIM10 ((uint32_t)0x00100000)
+#else
+#define RCC_APB2Periph_ADC3 ((uint32_t)0x00008000)
+#define RCC_APB2Periph_TIM15 ((uint32_t)0x00010000)
+#define RCC_APB2Periph_TIM16 ((uint32_t)0x00020000)
+#define RCC_APB2Periph_TIM17 ((uint32_t)0x00040000)
+#define RCC_APB2Periph_TIM9 ((uint32_t)0x00080000)
+#define RCC_APB2Periph_TIM10 ((uint32_t)0x00100000)
+#define RCC_APB2Periph_TIM11 ((uint32_t)0x00200000)
+#endif
/* APB1_peripheral */
#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001)
@@ -9624,9 +9875,15 @@ typedef struct
#define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008)
#define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010)
#define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020)
+#if !defined(CH32V10x)
#define RCC_APB1Periph_UART6 ((uint32_t)0x00000040)
#define RCC_APB1Periph_UART7 ((uint32_t)0x00000080)
#define RCC_APB1Periph_UART8 ((uint32_t)0x00000100)
+#else
+#define RCC_APB1Periph_TIM12 ((uint32_t)0x00000040)
+#define RCC_APB1Periph_TIM13 ((uint32_t)0x00000080)
+#define RCC_APB1Periph_TIM14 ((uint32_t)0x00000100)
+#endif
#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800)
#define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000)
#define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000)
@@ -9642,6 +9899,9 @@ typedef struct
#define RCC_APB1Periph_BKP ((uint32_t)0x08000000)
#define RCC_APB1Periph_PWR ((uint32_t)0x10000000)
#define RCC_APB1Periph_DAC ((uint32_t)0x20000000)
+#if defined(CH32V10x)
+#define RCC_APB1Periph_CEC ((uint32_t)0x40000000)
+#endif
#endif
@@ -9652,7 +9912,7 @@ typedef struct
#define RCC_MCO_HSE ((uint8_t)0x06)
#ifdef CH32V003
#define RCC_MCO_PLLCLK ((uint8_t)0x07)
-#elif defined(CH32V20x) || defined(CH32V30x)
+#elif defined(CH32V20x) || defined(CH32V30x) || defined(CH32V10x)
#define RCC_MCO_PLLCLK_Div2 ((uint8_t)0x07)
#endif
@@ -9667,7 +9927,7 @@ typedef struct
#define RCC_FLAG_HSIRDY ((uint8_t)0x21)
#define RCC_FLAG_HSERDY ((uint8_t)0x31)
#define RCC_FLAG_PLLRDY ((uint8_t)0x39)
-#if defined(CH32V20x) || defined(CH32V30x)
+#if defined(CH32V20x) || defined(CH32V30x) || defined(CH32V10x)
#define RCC_FLAG_LSERDY ((uint8_t)0x41)
#endif
#define RCC_FLAG_LSIRDY ((uint8_t)0x61)
@@ -9772,7 +10032,7 @@ typedef struct
#endif
-#if defined(CH32V20x) || defined(CH32V30x)
+#if defined(CH32V20x) || defined(CH32V30x) || defined(CH32V10x)
/* ch32v00x_rtc.h ------------------------------------------------------------*/
/* RTC_interrupts_define */
@@ -9996,11 +10256,11 @@ typedef struct
/* SPI_MSB transmission */
#define SPI_FirstBit_MSB ((uint16_t)0x0000)
-#if defined(CH32V20x) || defined(CH32V30x)
+#if defined(CH32V20x) || defined(CH32V30x) || defined(CH32V10x)
#define SPI_FirstBit_LSB ((uint16_t)0x0080)
#endif
-#if defined(CH32V20x) || defined(CH32V30x)
+#if defined(CH32V20x) || defined(CH32V30x) || defined(CH32V10x)
/* I2S_Mode */
#define I2S_Mode_SlaveTx ((uint16_t)0x0000)
@@ -10455,6 +10715,546 @@ typedef struct
#define USART_FLAG_FE ((uint16_t)0x0002)
#define USART_FLAG_PE ((uint16_t)0x0001)
+#if defined(CH32V10x)
+/* ch32v10x_usb.h ------------------------------------------------------------*/
+
+#ifndef NULL
+ #define NULL 0
+#endif
+
+#ifndef VOID
+ #define VOID void
+#endif
+#ifndef CONST
+ #define CONST const
+#endif
+#ifndef BOOL
+typedef unsigned char BOOL;
+#endif
+#ifndef BOOLEAN
+typedef unsigned char BOOLEAN;
+#endif
+#ifndef CHAR
+typedef char CHAR;
+#endif
+#ifndef INT8
+typedef char INT8;
+#endif
+#ifndef INT16
+typedef short INT16;
+#endif
+#ifndef INT32
+typedef long INT32;
+#endif
+#ifndef UINT8
+typedef unsigned char UINT8;
+#endif
+#ifndef UINT16
+typedef unsigned short UINT16;
+#endif
+#ifndef UINT32
+typedef unsigned long UINT32;
+#endif
+#ifndef UINT8V
+typedef unsigned char volatile UINT8V;
+#endif
+#ifndef UINT16V
+typedef unsigned short volatile UINT16V;
+#endif
+#ifndef UINT32V
+typedef unsigned long volatile UINT32V;
+#endif
+
+#ifndef PVOID
+typedef void *PVOID;
+#endif
+#ifndef PCHAR
+typedef char *PCHAR;
+#endif
+#ifndef PCHAR
+typedef const char *PCCHAR;
+#endif
+#ifndef PINT8
+typedef char *PINT8;
+#endif
+#ifndef PINT16
+typedef short *PINT16;
+#endif
+#ifndef PINT32
+typedef long *PINT32;
+#endif
+#ifndef PUINT8
+typedef unsigned char *PUINT8;
+#endif
+#ifndef PUINT16
+typedef unsigned short *PUINT16;
+#endif
+#ifndef PUINT32
+typedef unsigned long *PUINT32;
+#endif
+#ifndef PUINT8V
+typedef volatile unsigned char *PUINT8V;
+#endif
+#ifndef PUINT16V
+typedef volatile unsigned short *PUINT16V;
+#endif
+#ifndef PUINT32V
+typedef volatile unsigned long *PUINT32V;
+#endif
+
+/******************************************************************************/
+/* Peripheral memory map */
+/******************************************************************************/
+/* USB */
+#define R32_USB_CONTROL (*((PUINT32V)(0x40023400))) // USB control & interrupt enable & device address
+#define R8_USB_CTRL (*((PUINT8V)(0x40023400))) // USB base control
+#define RB_UC_HOST_MODE 0x80 // enable USB host mode: 0=device mode, 1=host mode
+#define RB_UC_LOW_SPEED 0x40 // enable USB low speed: 0=12Mbps, 1=1.5Mbps
+#define RB_UC_DEV_PU_EN 0x20 // USB device enable and internal pullup resistance enable
+#define RB_UC_SYS_CTRL1 0x20 // USB system control high bit
+#define RB_UC_SYS_CTRL0 0x10 // USB system control low bit
+#define MASK_UC_SYS_CTRL 0x30 // bit mask of USB system control
+// bUC_HOST_MODE & bUC_SYS_CTRL1 & bUC_SYS_CTRL0: USB system control
+// 0 00: disable USB device and disable internal pullup resistance
+// 0 01: enable USB device and disable internal pullup resistance, need external pullup resistance
+// 0 1x: enable USB device and enable internal pullup resistance
+// 1 00: enable USB host and normal status
+// 1 01: enable USB host and force UDP/UDM output SE0 state
+// 1 10: enable USB host and force UDP/UDM output J state
+// 1 11: enable USB host and force UDP/UDM output resume or K state
+#define RB_UC_INT_BUSY 0x08 // enable automatic responding busy for device mode or automatic pause for host mode during interrupt flag UIF_TRANSFER valid
+#define RB_UC_RESET_SIE 0x04 // force reset USB SIE, need software clear
+#define RB_UC_CLR_ALL 0x02 // force clear FIFO and count of USB
+#define RB_UC_DMA_EN 0x01 // DMA enable and DMA interrupt enable for USB
+
+#define R8_UDEV_CTRL (*((PUINT8V)(0x40023401))) // USB device physical prot control
+#define RB_UD_PD_DIS 0x80 // disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable
+#define RB_UD_DP_PIN 0x20 // ReadOnly: indicate current UDP pin level
+#define RB_UD_DM_PIN 0x10 // ReadOnly: indicate current UDM pin level
+#define RB_UD_LOW_SPEED 0x04 // enable USB physical port low speed: 0=full speed, 1=low speed
+#define RB_UD_GP_BIT 0x02 // general purpose bit
+#define RB_UD_PORT_EN 0x01 // enable USB physical port I/O: 0=disable, 1=enable
+
+#define R8_UHOST_CTRL R8_UDEV_CTRL // USB host physical prot control
+#define RB_UH_PD_DIS 0x80 // disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable
+#define RB_UH_DP_PIN 0x20 // ReadOnly: indicate current UDP pin level
+#define RB_UH_DM_PIN 0x10 // ReadOnly: indicate current UDM pin level
+#define RB_UH_LOW_SPEED 0x04 // enable USB port low speed: 0=full speed, 1=low speed
+#define RB_UH_BUS_RESET 0x02 // control USB bus reset: 0=normal, 1=force bus reset
+#define RB_UH_PORT_EN 0x01 // enable USB port: 0=disable, 1=enable port, automatic disabled if USB device detached
+
+#define R8_USB_INT_EN (*((PUINT8V)(0x40023402))) // USB interrupt enable
+#define RB_UIE_DEV_SOF 0x80 // enable interrupt for SOF received for USB device mode
+#define RB_UIE_DEV_NAK 0x40 // enable interrupt for NAK responded for USB device mode
+#define RB_UIE_FIFO_OV 0x10 // enable interrupt for FIFO overflow
+#define RB_UIE_HST_SOF 0x08 // enable interrupt for host SOF timer action for USB host mode
+#define RB_UIE_SUSPEND 0x04 // enable interrupt for USB suspend or resume event
+#define RB_UIE_TRANSFER 0x02 // enable interrupt for USB transfer completion
+#define RB_UIE_DETECT 0x01 // enable interrupt for USB device detected event for USB host mode
+#define RB_UIE_BUS_RST 0x01 // enable interrupt for USB bus reset event for USB device mode
+
+#define R8_USB_DEV_AD (*((PUINT8V)(0x40023403))) // USB device address
+#define RB_UDA_GP_BIT 0x80 // general purpose bit
+#define MASK_USB_ADDR 0x7F // bit mask for USB device address
+
+#define R32_USB_STATUS (*((PUINT32V)(0x40023404))) // USB miscellaneous status & interrupt flag & interrupt status
+#define R8_USB_MIS_ST (*((PUINT8V)(0x40023405))) // USB miscellaneous status
+#define RB_UMS_SOF_PRES 0x80 // RO, indicate host SOF timer presage status
+#define RB_UMS_SOF_ACT 0x40 // RO, indicate host SOF timer action status for USB host
+#define RB_UMS_SIE_FREE 0x20 // RO, indicate USB SIE free status
+#define RB_UMS_R_FIFO_RDY 0x10 // RO, indicate USB receiving FIFO ready status (not empty)
+#define RB_UMS_BUS_RESET 0x08 // RO, indicate USB bus reset status
+#define RB_UMS_SUSPEND 0x04 // RO, indicate USB suspend status
+#define RB_UMS_DM_LEVEL 0x02 // RO, indicate UDM level saved at device attached to USB host
+#define RB_UMS_DEV_ATTACH 0x01 // RO, indicate device attached status on USB host
+
+#define R8_USB_INT_FG (*((PUINT8V)(0x40023406))) // USB interrupt flag
+#define RB_U_IS_NAK 0x80 // RO, indicate current USB transfer is NAK received
+#define RB_U_TOG_OK 0x40 // RO, indicate current USB transfer toggle is OK
+#define RB_U_SIE_FREE 0x20 // RO, indicate USB SIE free status
+#define RB_UIF_FIFO_OV 0x10 // FIFO overflow interrupt flag for USB, direct bit address clear or write 1 to clear
+#define RB_UIF_HST_SOF 0x08 // host SOF timer interrupt flag for USB host, direct bit address clear or write 1 to clear
+#define RB_UIF_SUSPEND 0x04 // USB suspend or resume event interrupt flag, direct bit address clear or write 1 to clear
+#define RB_UIF_TRANSFER 0x02 // USB transfer completion interrupt flag, direct bit address clear or write 1 to clear
+#define RB_UIF_DETECT 0x01 // device detected event interrupt flag for USB host mode, direct bit address clear or write 1 to clear
+#define RB_UIF_BUS_RST 0x01 // bus reset event interrupt flag for USB device mode, direct bit address clear or write 1 to clear
+
+#define R8_USB_INT_ST (*((PUINT8V)(0x40023407))) // USB interrupt status
+#define RB_UIS_IS_NAK 0x80 // RO, indicate current USB transfer is NAK received for USB device mode
+#define RB_UIS_TOG_OK 0x40 // RO, indicate current USB transfer toggle is OK
+#define RB_UIS_TOKEN1 0x20 // RO, current token PID code bit 1 received for USB device mode
+#define RB_UIS_TOKEN0 0x10 // RO, current token PID code bit 0 received for USB device mode
+#define MASK_UIS_TOKEN 0x30 // RO, bit mask of current token PID code received for USB device mode
+#define UIS_TOKEN_OUT 0x00
+#define UIS_TOKEN_SOF 0x10
+#define UIS_TOKEN_IN 0x20
+#define UIS_TOKEN_SETUP 0x30
+// bUIS_TOKEN1 & bUIS_TOKEN0: current token PID code received for USB device mode
+// 00: OUT token PID received
+// 01: SOF token PID received
+// 10: IN token PID received
+// 11: SETUP token PID received
+#define MASK_UIS_ENDP 0x0F // RO, bit mask of current transfer endpoint number for USB device mode
+#define MASK_UIS_H_RES 0x0F // RO, bit mask of current transfer handshake response for USB host mode: 0000=no response, time out from device, others=handshake response PID received
+
+#define R16_USB_RX_LEN (*((PUINT16V)(0x40023408))) // USB receiving length
+#define MASK_UIS_RX_LEN 0x3FF // RO, bit mask of current receive length(10 bits for ch32v10x)
+#define R32_USB_BUF_MODE (*((PUINT32V)(0x4002340c))) // USB endpoint buffer mode
+#define R8_UEP4_1_MOD (*((PUINT8V)(0x4002340c))) // endpoint 4/1 mode
+#define RB_UEP1_RX_EN 0x80 // enable USB endpoint 1 receiving (OUT)
+#define RB_UEP1_TX_EN 0x40 // enable USB endpoint 1 transmittal (IN)
+#define RB_UEP1_BUF_MOD 0x10 // buffer mode of USB endpoint 1
+// bUEPn_RX_EN & bUEPn_TX_EN & bUEPn_BUF_MOD: USB endpoint 1/2/3 buffer mode, buffer start address is UEPn_DMA
+// 0 0 x: disable endpoint and disable buffer
+// 1 0 0: 64 bytes buffer for receiving (OUT endpoint)
+// 1 0 1: dual 64 bytes buffer by toggle bit bUEP_R_TOG selection for receiving (OUT endpoint), total=128bytes
+// 0 1 0: 64 bytes buffer for transmittal (IN endpoint)
+// 0 1 1: dual 64 bytes buffer by toggle bit bUEP_T_TOG selection for transmittal (IN endpoint), total=128bytes
+// 1 1 0: 64 bytes buffer for receiving (OUT endpoint) + 64 bytes buffer for transmittal (IN endpoint), total=128bytes
+// 1 1 1: dual 64 bytes buffer by bUEP_R_TOG selection for receiving (OUT endpoint) + dual 64 bytes buffer by bUEP_T_TOG selection for transmittal (IN endpoint), total=256bytes
+#define RB_UEP4_RX_EN 0x08 // enable USB endpoint 4 receiving (OUT)
+#define RB_UEP4_TX_EN 0x04 // enable USB endpoint 4 transmittal (IN)
+// bUEP4_RX_EN & bUEP4_TX_EN: USB endpoint 4 buffer mode, buffer start address is UEP0_DMA
+// 0 0: single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint)
+// 1 0: single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) + 64 bytes buffer for endpoint 4 receiving (OUT endpoint), total=128bytes
+// 0 1: single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) + 64 bytes buffer for endpoint 4 transmittal (IN endpoint), total=128bytes
+// 1 1: single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint)
+// + 64 bytes buffer for endpoint 4 receiving (OUT endpoint) + 64 bytes buffer for endpoint 4 transmittal (IN endpoint), total=192bytes
+
+#define R8_UEP2_3_MOD (*((PUINT8V)(0x4002340d))) // endpoint 2/3 mode
+#define RB_UEP3_RX_EN 0x80 // enable USB endpoint 3 receiving (OUT)
+#define RB_UEP3_TX_EN 0x40 // enable USB endpoint 3 transmittal (IN)
+#define RB_UEP3_BUF_MOD 0x10 // buffer mode of USB endpoint 3
+#define RB_UEP2_RX_EN 0x08 // enable USB endpoint 2 receiving (OUT)
+#define RB_UEP2_TX_EN 0x04 // enable USB endpoint 2 transmittal (IN)
+#define RB_UEP2_BUF_MOD 0x01 // buffer mode of USB endpoint 2
+
+#define R8_UH_EP_MOD R8_UEP2_3_MOD //host endpoint mode
+#define RB_UH_EP_TX_EN 0x40 // enable USB host OUT endpoint transmittal
+#define RB_UH_EP_TBUF_MOD 0x10 // buffer mode of USB host OUT endpoint
+// bUH_EP_TX_EN & bUH_EP_TBUF_MOD: USB host OUT endpoint buffer mode, buffer start address is UH_TX_DMA
+// 0 x: disable endpoint and disable buffer
+// 1 0: 64 bytes buffer for transmittal (OUT endpoint)
+// 1 1: dual 64 bytes buffer by toggle bit bUH_T_TOG selection for transmittal (OUT endpoint), total=128bytes
+#define RB_UH_EP_RX_EN 0x08 // enable USB host IN endpoint receiving
+#define RB_UH_EP_RBUF_MOD 0x01 // buffer mode of USB host IN endpoint
+// bUH_EP_RX_EN & bUH_EP_RBUF_MOD: USB host IN endpoint buffer mode, buffer start address is UH_RX_DMA
+// 0 x: disable endpoint and disable buffer
+// 1 0: 64 bytes buffer for receiving (IN endpoint)
+// 1 1: dual 64 bytes buffer by toggle bit bUH_R_TOG selection for receiving (IN endpoint), total=128bytes
+
+#define R8_UEP5_6_MOD (*((PUINT8V)(0x4002340e))) // endpoint 5/6 mode
+#define RB_UEP6_RX_EN 0x80 // enable USB endpoint 6 receiving (OUT)
+#define RB_UEP6_TX_EN 0x40 // enable USB endpoint 6 transmittal (IN)
+#define RB_UEP6_BUF_MOD 0x10 // buffer mode of USB endpoint 6
+#define RB_UEP5_RX_EN 0x08 // enable USB endpoint 5 receiving (OUT)
+#define RB_UEP5_TX_EN 0x04 // enable USB endpoint 5 transmittal (IN)
+#define RB_UEP5_BUF_MOD 0x01 // buffer mode of USB endpoint 5
+
+#define R8_UEP7_MOD (*((PUINT8V)(0x4002340f))) // endpoint 7 mode
+#define RB_UEP7_RX_EN 0x08 // enable USB endpoint 7 receiving (OUT)
+#define RB_UEP7_TX_EN 0x04 // enable USB endpoint 7 transmittal (IN)
+#define RB_UEP7_BUF_MOD 0x01 // buffer mode of USB endpoint 7
+
+#define R16_UEP0_DMA (*((PUINT16V)(0x40023410))) // endpoint 0 DMA buffer address
+#define R16_UEP1_DMA (*((PUINT16V)(0x40023414))) // endpoint 1 DMA buffer address
+#define R16_UEP2_DMA (*((PUINT16V)(0x40023418))) // endpoint 2 DMA buffer address
+#define R16_UH_RX_DMA R16_UEP2_DMA // host rx endpoint buffer high address
+#define R16_UEP3_DMA (*((PUINT16V)(0x4002341c))) // endpoint 3 DMA buffer address
+
+#define R16_UEP4_DMA (*((PUINT16V)(0x40023420))) // endpoint 4 DMA buffer address
+#define R16_UEP5_DMA (*((PUINT16V)(0x40023424))) // endpoint 5 DMA buffer address
+#define R16_UEP6_DMA (*((PUINT16V)(0x40023428))) // endpoint 6 DMA buffer address
+#define R16_UEP7_DMA (*((PUINT16V)(0x4002342c))) // endpoint 7 DMA buffer address
+
+#define R16_UH_TX_DMA R16_UEP3_DMA // host tx endpoint buffer high address
+#define R32_USB_EP0_CTRL (*((PUINT32V)(0x40023430))) // endpoint 0 control & transmittal length
+#define R8_UEP0_T_LEN (*((PUINT8V)(0x40023430))) // endpoint 0 transmittal length
+#define R8_UEP0_CTRL (*((PUINT8V)(0x40023432))) // endpoint 0 control
+#define R32_USB_EP1_CTRL (*((PUINT32V)(0x40023434))) // endpoint 1 control & transmittal length
+#define R16_UEP1_T_LEN (*((PUINT16V)(0x40023434))) // endpoint 1 transmittal length(16-bits for ch32v10x)
+#define R8_UEP1_CTRL (*((PUINT8V)(0x40023436))) // endpoint 1 control
+#define RB_UEP_R_TOG 0x80 // expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1
+#define RB_UEP_T_TOG 0x40 // prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1
+#define RB_UEP_AUTO_TOG 0x10 // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle
+#define RB_UEP_R_RES1 0x08 // handshake response type high bit for USB endpoint X receiving (OUT)
+#define RB_UEP_R_RES0 0x04 // handshake response type low bit for USB endpoint X receiving (OUT)
+#define MASK_UEP_R_RES 0x0C // bit mask of handshake response type for USB endpoint X receiving (OUT)
+#define UEP_R_RES_ACK 0x00
+#define UEP_R_RES_TOUT 0x04
+#define UEP_R_RES_NAK 0x08
+#define UEP_R_RES_STALL 0x0C
+// RB_UEP_R_RES1 & RB_UEP_R_RES0: handshake response type for USB endpoint X receiving (OUT)
+// 00: ACK (ready)
+// 01: no response, time out to host, for non-zero endpoint isochronous transactions
+// 10: NAK (busy)
+// 11: STALL (error)
+#define RB_UEP_T_RES1 0x02 // handshake response type high bit for USB endpoint X transmittal (IN)
+#define RB_UEP_T_RES0 0x01 // handshake response type low bit for USB endpoint X transmittal (IN)
+#define MASK_UEP_T_RES 0x03 // bit mask of handshake response type for USB endpoint X transmittal (IN)
+#define UEP_T_RES_ACK 0x00
+#define UEP_T_RES_TOUT 0x01
+#define UEP_T_RES_NAK 0x02
+#define UEP_T_RES_STALL 0x03
+// bUEP_T_RES1 & bUEP_T_RES0: handshake response type for USB endpoint X transmittal (IN)
+// 00: DATA0 or DATA1 then expecting ACK (ready)
+// 01: DATA0 or DATA1 then expecting no response, time out from host, for non-zero endpoint isochronous transactions
+// 10: NAK (busy)
+// 11: STALL (error)
+
+#define R8_UH_SETUP R8_UEP1_CTRL // host aux setup
+#define RB_UH_PRE_PID_EN 0x80 // USB host PRE PID enable for low speed device via hub
+#define RB_UH_SOF_EN 0x40 // USB host automatic SOF enable
+
+#define R32_USB_EP2_CTRL (*((PUINT32V)(0x40023438))) // endpoint 2 control & transmittal length
+#define R16_UEP2_T_LEN (*((PUINT16V)(0x40023438))) // endpoint 2 transmittal length(16-bits for ch32v10x)
+#define R8_UEP2_CTRL (*((PUINT8V)(0x4002343a))) // endpoint 2 control
+
+#define R8_UH_EP_PID (*((PUINT8V)(0x40023438))) // host endpoint and PID
+#define MASK_UH_TOKEN 0xF0 // bit mask of token PID for USB host transfer
+#define MASK_UH_ENDP 0x0F // bit mask of endpoint number for USB host transfer
+
+#define R8_UH_RX_CTRL R8_UEP2_CTRL // host receiver endpoint control
+#define RB_UH_R_TOG 0x80 // expected data toggle flag of host receiving (IN): 0=DATA0, 1=DATA1
+#define RB_UH_R_AUTO_TOG 0x10 // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle
+#define RB_UH_R_RES 0x04 // prepared handshake response type for host receiving (IN): 0=ACK (ready), 1=no response, time out to device, for isochronous transactions
+
+#define R32_USB_EP3_CTRL (*((PUINT32V)(0x4002343c))) // endpoint 3 control & transmittal length
+#define R16_UEP3_T_LEN (*((PUINT16V)(0x4002343c))) // endpoint 3 transmittal length(16-bits for ch32v10x)
+#define R8_UEP3_CTRL (*((PUINT8V)(0x4002343e))) // endpoint 3 control
+#define R8_UH_TX_LEN (*((PUINT16V)(0x4002343c))) //R8_UEP3_T_LEN // host transmittal endpoint transmittal length
+
+#define R8_UH_TX_CTRL R8_UEP3_CTRL // host transmittal endpoint control
+#define RB_UH_T_TOG 0x40 // prepared data toggle flag of host transmittal (SETUP/OUT): 0=DATA0, 1=DATA1
+#define RB_UH_T_AUTO_TOG 0x10 // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle
+#define RB_UH_T_RES 0x01 // expected handshake response type for host transmittal (SETUP/OUT): 0=ACK (ready), 1=no response, time out from device, for isochronous transactions
+
+#define R32_USB_EP4_CTRL (*((PUINT32V)(0x40023440))) // endpoint 4 control & transmittal length
+#define R16_UEP4_T_LEN (*((PUINT16V)(0x40023440))) // endpoint 4 transmittal length(16-bits for ch32v10x)
+#define R8_UEP4_CTRL (*((PUINT8V)(0x40023442))) // endpoint 4 control
+
+#define R32_USB_EP5_CTRL (*((PUINT32V)(0x40023444))) // endpoint 5 control & transmittal length
+#define R16_UEP5_T_LEN (*((PUINT16V)(0x40023444))) // endpoint 5 transmittal length(16-bits for ch32v10x)
+#define R8_UEP5_CTRL (*((PUINT8V)(0x40023446))) // endpoint 5 control
+
+#define R32_USB_EP6_CTRL (*((PUINT32V)(0x40023448))) // endpoint 6 control & transmittal length
+#define R16_UEP6_T_LEN (*((PUINT16V)(0x40023448))) // endpoint 6 transmittal length(16-bits for ch32v10x)
+#define R8_UEP6_CTRL (*((PUINT8V)(0x4002344a))) // endpoint 6 control
+
+#define R32_USB_EP7_CTRL (*((PUINT32V)(0x4002344c))) // endpoint 7 control & transmittal length
+#define R16_UEP7_T_LEN (*((PUINT16V)(0x4002344c))) // endpoint 7 transmittal length(16-bits for ch32v10x)
+#define R8_UEP7_CTRL (*((PUINT8V)(0x4002344e))) // endpoint 7 control
+
+/* USB constant and structure define */
+
+/* USB PID */
+#ifndef USB_PID_SETUP
+ #define USB_PID_NULL 0x00 /* reserved PID */
+ #define USB_PID_SOF 0x05
+ #define USB_PID_SETUP 0x0D
+ #define USB_PID_IN 0x09
+ #define USB_PID_OUT 0x01
+ #define USB_PID_ACK 0x02
+ #define USB_PID_NAK 0x0A
+ #define USB_PID_STALL 0x0E
+ #define USB_PID_DATA0 0x03
+ #define USB_PID_DATA1 0x0B
+ #define USB_PID_PRE 0x0C
+#endif
+
+/* USB standard device request code */
+#ifndef USB_GET_DESCRIPTOR
+ #define USB_GET_STATUS 0x00
+ #define USB_CLEAR_FEATURE 0x01
+ #define USB_SET_FEATURE 0x03
+ #define USB_SET_ADDRESS 0x05
+ #define USB_GET_DESCRIPTOR 0x06
+ #define USB_SET_DESCRIPTOR 0x07
+ #define USB_GET_CONFIGURATION 0x08
+ #define USB_SET_CONFIGURATION 0x09
+ #define USB_GET_INTERFACE 0x0A
+ #define USB_SET_INTERFACE 0x0B
+ #define USB_SYNCH_FRAME 0x0C
+#endif
+
+/* USB hub class request code */
+#ifndef HUB_GET_DESCRIPTOR
+ #define HUB_GET_STATUS 0x00
+ #define HUB_CLEAR_FEATURE 0x01
+ #define HUB_GET_STATE 0x02
+ #define HUB_SET_FEATURE 0x03
+ #define HUB_GET_DESCRIPTOR 0x06
+ #define HUB_SET_DESCRIPTOR 0x07
+#endif
+
+/* USB HID class request code */
+#ifndef HID_GET_REPORT
+ #define HID_GET_REPORT 0x01
+ #define HID_GET_IDLE 0x02
+ #define HID_GET_PROTOCOL 0x03
+ #define HID_SET_REPORT 0x09
+ #define HID_SET_IDLE 0x0A
+ #define HID_SET_PROTOCOL 0x0B
+#endif
+
+/* USB CDC Class request code */
+#ifndef CDC_GET_LINE_CODING
+#define CDC_GET_LINE_CODING 0X21 /* This request allows the host to find out the currently configured line coding */
+#define CDC_SET_LINE_CODING 0x20 /* Configures DTE rate, stop-bits, parity, and number-of-character */
+#define CDC_SET_LINE_CTLSTE 0X22 /* This request generates RS-232/V.24 style control signals */
+#define CDC_SEND_BREAK 0X23 /* Sends special carrier modulation used to specify RS-232 style break */
+#endif
+
+/* Bit define for USB request type */
+#ifndef USB_REQ_TYP_MASK
+ #define USB_REQ_TYP_IN 0x80 /* control IN, device to host */
+ #define USB_REQ_TYP_OUT 0x00 /* control OUT, host to device */
+ #define USB_REQ_TYP_READ 0x80 /* control read, device to host */
+ #define USB_REQ_TYP_WRITE 0x00 /* control write, host to device */
+ #define USB_REQ_TYP_MASK 0x60 /* bit mask of request type */
+ #define USB_REQ_TYP_STANDARD 0x00
+ #define USB_REQ_TYP_CLASS 0x20
+ #define USB_REQ_TYP_VENDOR 0x40
+ #define USB_REQ_TYP_RESERVED 0x60
+ #define USB_REQ_RECIP_MASK 0x1F /* bit mask of request recipient */
+ #define USB_REQ_RECIP_DEVICE 0x00
+ #define USB_REQ_RECIP_INTERF 0x01
+ #define USB_REQ_RECIP_ENDP 0x02
+ #define USB_REQ_RECIP_OTHER 0x03
+ #define USB_REQ_FEAT_REMOTE_WAKEUP 0x01
+ #define USB_REQ_FEAT_ENDP_HALT 0x00
+#endif
+
+/* USB request type for hub class request */
+#ifndef HUB_GET_HUB_DESCRIPTOR
+ #define HUB_CLEAR_HUB_FEATURE 0x20
+ #define HUB_CLEAR_PORT_FEATURE 0x23
+ #define HUB_GET_BUS_STATE 0xA3
+ #define HUB_GET_HUB_DESCRIPTOR 0xA0
+ #define HUB_GET_HUB_STATUS 0xA0
+ #define HUB_GET_PORT_STATUS 0xA3
+ #define HUB_SET_HUB_DESCRIPTOR 0x20
+ #define HUB_SET_HUB_FEATURE 0x20
+ #define HUB_SET_PORT_FEATURE 0x23
+#endif
+
+/* Hub class feature selectors */
+#ifndef HUB_PORT_RESET
+ #define HUB_C_HUB_LOCAL_POWER 0
+ #define HUB_C_HUB_OVER_CURRENT 1
+ #define HUB_PORT_CONNECTION 0
+ #define HUB_PORT_ENABLE 1
+ #define HUB_PORT_SUSPEND 2
+ #define HUB_PORT_OVER_CURRENT 3
+ #define HUB_PORT_RESET 4
+ #define HUB_PORT_POWER 8
+ #define HUB_PORT_LOW_SPEED 9
+ #define HUB_C_PORT_CONNECTION 16
+ #define HUB_C_PORT_ENABLE 17
+ #define HUB_C_PORT_SUSPEND 18
+ #define HUB_C_PORT_OVER_CURRENT 19
+ #define HUB_C_PORT_RESET 20
+#endif
+
+/* USB descriptor type */
+#ifndef USB_DESCR_TYP_DEVICE
+ #define USB_DESCR_TYP_DEVICE 0x01
+ #define USB_DESCR_TYP_CONFIG 0x02
+ #define USB_DESCR_TYP_STRING 0x03
+ #define USB_DESCR_TYP_INTERF 0x04
+ #define USB_DESCR_TYP_ENDP 0x05
+ #define USB_DESCR_TYP_QUALIF 0x06
+ #define USB_DESCR_TYP_SPEED 0x07
+ #define USB_DESCR_TYP_OTG 0x09
+ #define USB_DESCR_TYP_HID 0x21
+ #define USB_DESCR_TYP_REPORT 0x22
+ #define USB_DESCR_TYP_PHYSIC 0x23
+ #define USB_DESCR_TYP_CS_INTF 0x24
+ #define USB_DESCR_TYP_CS_ENDP 0x25
+ #define USB_DESCR_TYP_HUB 0x29
+#endif
+
+/* USB device class */
+#ifndef USB_DEV_CLASS_HUB
+ #define USB_DEV_CLASS_RESERVED 0x00
+ #define USB_DEV_CLASS_AUDIO 0x01
+ #define USB_DEV_CLASS_COMMUNIC 0x02
+ #define USB_DEV_CLASS_HID 0x03
+ #define USB_DEV_CLASS_MONITOR 0x04
+ #define USB_DEV_CLASS_PHYSIC_IF 0x05
+ #define USB_DEV_CLASS_IMAGE 0x06
+ #define USB_DEV_CLASS_PRINTER 0x07
+ #define USB_DEV_CLASS_STORAGE 0x08
+ #define USB_DEV_CLASS_HUB 0x09
+ #define USB_DEV_CLASS_VEN_SPEC 0xFF
+#endif
+
+/* USB endpoint type and attributes */
+#ifndef USB_ENDP_TYPE_MASK
+ #define USB_ENDP_DIR_MASK 0x80
+ #define USB_ENDP_ADDR_MASK 0x0F
+ #define USB_ENDP_TYPE_MASK 0x03
+ #define USB_ENDP_TYPE_CTRL 0x00
+ #define USB_ENDP_TYPE_ISOCH 0x01
+ #define USB_ENDP_TYPE_BULK 0x02
+ #define USB_ENDP_TYPE_INTER 0x03
+#endif
+
+#ifndef USB_DEVICE_ADDR
+ #define USB_DEVICE_ADDR 0x02
+#endif
+#ifndef DEFAULT_ENDP0_SIZE
+ #define DEFAULT_ENDP0_SIZE 8 /* default maximum packet size for endpoint 0 */
+#endif
+#ifndef MAX_PACKET_SIZE
+ #define MAX_PACKET_SIZE 64 /* maximum packet size */
+#endif
+#ifndef USB_BO_CBW_SIZE
+ #define USB_BO_CBW_SIZE 0x1F
+ #define USB_BO_CSW_SIZE 0x0D
+#endif
+#ifndef USB_BO_CBW_SIG0
+ #define USB_BO_CBW_SIG0 0x55
+ #define USB_BO_CBW_SIG1 0x53
+ #define USB_BO_CBW_SIG2 0x42
+ #define USB_BO_CBW_SIG3 0x43
+ #define USB_BO_CSW_SIG0 0x55
+ #define USB_BO_CSW_SIG1 0x53
+ #define USB_BO_CSW_SIG2 0x42
+ #define USB_BO_CSW_SIG3 0x53
+#endif
+
+#define DEF_STRING_DESC_LANG 0x00
+#define DEF_STRING_DESC_MANU 0x01
+#define DEF_STRING_DESC_PROD 0x02
+#define DEF_STRING_DESC_SERN 0x03
+
+/* ch32v10x_usb_host.h -----------------------------------------------------------*/
+
+#define ERR_SUCCESS 0x00
+#define ERR_USB_CONNECT 0x15
+#define ERR_USB_DISCON 0x16
+#define ERR_USB_BUF_OVER 0x17
+#define ERR_USB_DISK_ERR 0x1F
+#define ERR_USB_TRANSFER 0x20
+#define ERR_USB_UNSUPPORT 0xFB
+#define ERR_USB_UNKNOWN 0xFE
+#define ERR_AOA_PROTOCOL 0x41
+
+#define ROOT_DEV_DISCONNECT 0
+#define ROOT_DEV_CONNECTED 1
+#define ROOT_DEV_FAILED 2
+#define ROOT_DEV_SUCCESS 3
+#define DEV_TYPE_KEYBOARD (USB_DEV_CLASS_HID | 0x20)
+#define DEV_TYPE_MOUSE (USB_DEV_CLASS_HID | 0x30)
+#define DEF_AOA_DEVICE 0xF0
+#define DEV_TYPE_UNKNOW 0xFF
+
+#define HUB_MAX_PORTS 4
+#define WAIT_USB_TOUT_200US 3000
+
+#endif
+
/* ch32v00x_wwdg.h -----------------------------------------------------------*/
@@ -10606,6 +11406,18 @@ typedef struct
__IO uint64_t CMP;
} SysTick_Type;
+#elif defined(CH32V10x)
+
+/* memory mapped structure for SysTick */
+typedef struct
+{
+ __IO uint32_t CTLR;
+ __IO uint32_t CNTL;
+ __IO uint32_t CNTH;
+ __IO uint32_t CMPL;
+ __IO uint32_t CMPH;
+} SysTick_Type;
+
#endif
@@ -11160,7 +11972,7 @@ static inline void __set_MCAUSE(uint32_t value)
__ASM volatile("csrw mcause, %0":: "r"(value));
}
-#if defined(CH32V20x) || defined(CH32V30x)
+#if defined(CH32V20x) || defined(CH32V30x) || defined(CH32V10x)
/*********************************************************************
* @fn __get_MTVAL
@@ -11289,7 +12101,7 @@ extern "C" {
* more info at https://github.com/cnlohr/ch32v003fun/wiki/Time
*/
-#ifdef SYSTICK_USE_HCLK
+#if defined(SYSTICK_USE_HCLK) && !defined(CH32V10x)
#define DELAY_US_TIME ((SYSTEM_CORE_CLOCK)/1000000)
#define DELAY_MS_TIME ((SYSTEM_CORE_CLOCK)/1000)
#define SETUP_SYSTICK_HCLK SysTick->CTLR = 5;
@@ -11349,6 +12161,12 @@ void SystemInitHSEPLL( int HSEBYP );
void SystemInit144HSI( void );
void SystemInit144HSE( void );
+#elif defined(CH32V10x)
+
+// Initialization functions
+void SystemInit72HSI( void );
+void SystemInit72HSE( void );
+
#endif
#ifdef CH32V003
diff --git a/ch32v003fun/ch32v10xfun.ld b/ch32v003fun/ch32v10xfun.ld
new file mode 100644
index 0000000..509b9f1
--- /dev/null
+++ b/ch32v003fun/ch32v10xfun.ld
@@ -0,0 +1,166 @@
+ENTRY( Init )
+
+__stack_size = 2048;
+
+PROVIDE( _stack_size = __stack_size );
+
+
+MEMORY
+{
+ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 64K
+ RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K
+}
+
+
+SECTIONS
+{
+
+ .init :
+ {
+ _sinit = .;
+ . = ALIGN(4);
+ KEEP(*(SORT_NONE(.init)))
+ . = ALIGN(4);
+ _einit = .;
+ } >FLASH AT>FLASH
+
+ .vector :
+ {
+ *(.vector);
+ . = ALIGN(64);
+ } >FLASH AT>FLASH
+
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text)
+ *(.text.*)
+ *(.rodata)
+ *(.rodata*)
+ *(.gnu.linkonce.t.*)
+ . = ALIGN(4);
+ } >FLASH AT>FLASH
+
+ .fini :
+ {
+ KEEP(*(SORT_NONE(.fini)))
+ . = ALIGN(4);
+ } >FLASH AT>FLASH
+
+ PROVIDE( _etext = . );
+ PROVIDE( _eitcm = . );
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } >FLASH AT>FLASH
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
+ KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } >FLASH AT>FLASH
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
+ KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } >FLASH AT>FLASH
+
+ .ctors :
+ {
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ } >FLASH AT>FLASH
+
+ .dtors :
+ {
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ } >FLASH AT>FLASH
+
+ .dalign :
+ {
+ . = ALIGN(4);
+ PROVIDE(_data_vma = .);
+ } >RAM AT>FLASH
+
+ .dlalign :
+ {
+ . = ALIGN(4);
+ PROVIDE(_data_lma = .);
+ } >FLASH AT>FLASH
+
+ .data :
+ {
+ *(.gnu.linkonce.r.*)
+ *(.data .data.*)
+ *(.gnu.linkonce.d.*)
+ . = ALIGN(8);
+ PROVIDE( __global_pointer$ = . + 0x800 );
+ *(.sdata .sdata.*)
+ *(.sdata2.*)
+ *(.gnu.linkonce.s.*)
+ . = ALIGN(8);
+ *(.srodata.cst16)
+ *(.srodata.cst8)
+ *(.srodata.cst4)
+ *(.srodata.cst2)
+ *(.srodata .srodata.*)
+ . = ALIGN(4);
+ PROVIDE( _edata = .);
+ } >RAM AT>FLASH
+
+ .bss :
+ {
+ . = ALIGN(4);
+ PROVIDE( _sbss = .);
+ *(.sbss*)
+ *(.gnu.linkonce.sb.*)
+ *(.bss*)
+ *(.gnu.linkonce.b.*)
+ *(COMMON*)
+ . = ALIGN(4);
+ PROVIDE( _ebss = .);
+ } >RAM AT>FLASH
+
+ PROVIDE( _end = _ebss);
+ PROVIDE( end = . );
+
+ .stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size :
+ {
+ PROVIDE( _heap_end = . );
+ . = ALIGN(4);
+ PROVIDE(_susrstack = . );
+ . = . + __stack_size;
+ PROVIDE( _eusrstack = .);
+ } >RAM
+
+}
+
+
diff --git a/ch32v003fun/ch32v10xfun.mk b/ch32v003fun/ch32v10xfun.mk
new file mode 100644
index 0000000..35c51e4
--- /dev/null
+++ b/ch32v003fun/ch32v10xfun.mk
@@ -0,0 +1,59 @@
+
+PREFIX?=riscv64-unknown-elf
+
+CH32V003FUN?=../../ch32v003fun
+MINICHLINK?=../../minichlink
+
+CFLAGS+= \
+ -g -Os -flto -ffunction-sections -fdata-sections \
+ -static-libgcc \
+ -march=rv32imac \
+ -mabi=ilp32 \
+ -msmall-data-limit=8 \
+ -mno-save-restore \
+ -fmessage-length=0 \
+ -fsigned-char \
+ -I/usr/include/newlib \
+ -I$(CH32V003FUN) \
+ -nostdlib \
+ -DCH32V10x \
+ -I. -Wall
+
+LDFLAGS+=-T $(CH32V003FUN)/ch32v10xfun.ld -Wl,--gc-sections -L$(CH32V003FUN)/../misc -lgcc
+
+SYSTEM_C:=$(CH32V003FUN)/ch32v003fun.c
+
+$(TARGET).elf : $(SYSTEM_C) $(TARGET).c $(ADDITIONAL_C_FILES)
+ $(PREFIX)-gcc -o $@ $^ $(CFLAGS) $(LDFLAGS)
+
+$(TARGET).bin : $(TARGET).elf
+ $(PREFIX)-size $^
+ $(PREFIX)-objdump -S $^ > $(TARGET).lst
+ $(PREFIX)-objdump -t $^ > $(TARGET).map
+ $(PREFIX)-objcopy -O binary $< $(TARGET).bin
+ $(PREFIX)-objcopy -O ihex $< $(TARGET).hex
+
+ifeq ($(OS),Windows_NT)
+closechlink :
+ -taskkill /F /IM minichlink.exe /T
+else
+closechlink :
+ -killall minichlink
+endif
+
+terminal : monitor
+
+monitor :
+ $(MINICHLINK)/minichlink -T
+
+gdbserver :
+ -$(MINICHLINK)/minichlink -baG
+
+cv_flash : $(TARGET).bin
+ make -C $(MINICHLINK) all
+ $(MINICHLINK)/minichlink -w $< flash -b
+
+cv_clean :
+ rm -rf $(TARGET).elf $(TARGET).bin $(TARGET).hex $(TARGET).lst $(TARGET).map $(TARGET).hex || true
+
+build : $(TARGET).bin
diff --git a/examples_v10x/blink/Makefile b/examples_v10x/blink/Makefile
new file mode 100644
index 0000000..9200f86
--- /dev/null
+++ b/examples_v10x/blink/Makefile
@@ -0,0 +1,10 @@
+all : flash
+
+TARGET:=blink
+
+include ../../ch32v003fun/ch32v10xfun.mk
+
+flash : cv_flash
+clean : cv_clean
+
+
diff --git a/examples_v10x/blink/blink.c b/examples_v10x/blink/blink.c
new file mode 100644
index 0000000..8861461
--- /dev/null
+++ b/examples_v10x/blink/blink.c
@@ -0,0 +1,26 @@
+// Could be defined here, or in the processor defines.
+#define SYSTEM_CORE_CLOCK 72000000
+
+#include "ch32v003fun.h"
+#include <stdio.h>
+
+int main()
+{
+ SystemInit72HSE();
+
+ // Enable GPIOs
+ //RCC->APB2PCENR |= RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOC;
+ RCC->APB2PCENR |= RCC_APB2Periph_GPIOA;
+
+ // GPIO A0 Push-Pull
+ GPIOA->CFGLR &= ~(0xf<<(4*0));
+ GPIOA->CFGLR |= (GPIO_Speed_10MHz | GPIO_CNF_OUT_PP)<<(4*0);
+
+ while(1)
+ {
+ GPIOA->BSHR = (1<<0); // Turn on GPIO
+ Delay_Ms( 1000 );
+ GPIOA->BSHR = (1<<(16+0)); // Turn off GPIO
+ Delay_Ms( 1000 );
+ }
+}
--
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