diff --git a/firmware/rust1/src/rs485.rs b/firmware/rust1/src/rs485.rs
index 3aa39a2b7db8931dd490868006c16f92d321aa84..cbb7b4fa4c08b7ed3cc8795248c988aab1f8234a 100644
--- a/firmware/rust1/src/rs485.rs
+++ b/firmware/rust1/src/rs485.rs
@@ -242,10 +242,10 @@ impl<H: RS485Handler> RS485<H> {
         // We need two clocks for each loop.
         //let timeout_start_value = (SM_FREQ as f32 * 0.86e-3 / 2.) as u32;
         let symbols_per_byte = if self.uart_parity == Parity::ParityNone { 10 } else { 11 };
-        let timeout_seconds = 1.5 * symbols_per_byte as f32 * 1000. / self.uart_baud_rate as f32;
+        let timeout_seconds = 1.5 * symbols_per_byte as f32 / self.uart_baud_rate as f32;
         let timeout_start_value = (SM_FREQ as f32 * timeout_seconds / 2.) as u32;
         sm.tx().push(timeout_start_value);
-        info!("timeout_start_value: {} = 0x{:08x}", timeout_start_value, timeout_start_value);
+        info!("timeout_start_value: {} = 0x{:08x}, {} sec, clkdiv 0x{:08x}", timeout_start_value, timeout_start_value, timeout_seconds, cfg.clock_divider.to_bits());
 
         // switch to the real program and join FIFOs
         unsafe { common.free_instr(loaded_program.used_memory); };