From 0af55994405a9a91a99e5f7219f49fefa0926d1d Mon Sep 17 00:00:00 2001
From: Jochen Vothknecht <jochen3120@gmail.com>
Date: Tue, 8 Feb 2022 08:39:11 +0100
Subject: [PATCH] Adding spring terminals
---
pcb/CyanStripe/CyanStripe.kicad_pcb | 154 +++++++++++++++++++++++++++-
pcb/CyanStripe/CyanStripe.sch | 33 ++++++
pcb/CyanStripe/RT7272.sch | 26 ++---
pcb/lib/TripwireHook | 2 +-
4 files changed, 199 insertions(+), 16 deletions(-)
diff --git a/pcb/CyanStripe/CyanStripe.kicad_pcb b/pcb/CyanStripe/CyanStripe.kicad_pcb
index 984bfad..f13c8fc 100644
--- a/pcb/CyanStripe/CyanStripe.kicad_pcb
+++ b/pcb/CyanStripe/CyanStripe.kicad_pcb
@@ -5,8 +5,8 @@
(drawings 0)
(tracks 72)
(zones 0)
- (modules 67)
- (nets 75)
+ (modules 70)
+ (nets 84)
)
(page A4)
@@ -181,6 +181,15 @@
(net 72 CB_RX)
(net 73 CB_DE)
(net 74 CB_~RE)
+ (net 75 "Net-(J5-Pad3)")
+ (net 76 "Net-(J5-Pad1)")
+ (net 77 "Net-(J5-Pad2)")
+ (net 78 "Net-(J6-Pad3)")
+ (net 79 "Net-(J6-Pad1)")
+ (net 80 "Net-(J6-Pad2)")
+ (net 81 "Net-(J7-Pad3)")
+ (net 82 "Net-(J7-Pad1)")
+ (net 83 "Net-(J7-Pad2)")
(net_class Default "This is the default net class."
(clearance 0.2)
@@ -227,6 +236,15 @@
(add_net "Net-(J3-PadRN)")
(add_net "Net-(J3-PadT)")
(add_net "Net-(J3-PadTN)")
+ (add_net "Net-(J5-Pad1)")
+ (add_net "Net-(J5-Pad2)")
+ (add_net "Net-(J5-Pad3)")
+ (add_net "Net-(J6-Pad1)")
+ (add_net "Net-(J6-Pad2)")
+ (add_net "Net-(J6-Pad3)")
+ (add_net "Net-(J7-Pad1)")
+ (add_net "Net-(J7-Pad2)")
+ (add_net "Net-(J7-Pad3)")
(add_net "Net-(R10-Pad1)")
(add_net "Net-(R11-Pad2)")
(add_net "Net-(R13-Pad2)")
@@ -265,6 +283,138 @@
(add_net ~RESET)
)
+ (module TripwireHook:PZK3101_3_5.00 (layer F.Cu) (tedit 62021C43) (tstamp 6203042D)
+ (at 208 125 270)
+ (path /62039F65)
+ (fp_text reference J7 (at 0 6.6 90) (layer F.SilkS)
+ (effects (font (size 1 1) (thickness 0.15)))
+ )
+ (fp_text value Conn_01x03 (at 0 -8.2 90) (layer F.Fab)
+ (effects (font (size 1 1) (thickness 0.15)))
+ )
+ (fp_text user Front (at 0 -6.1 90) (layer F.SilkS)
+ (effects (font (size 1 1) (thickness 0.2)))
+ )
+ (fp_poly (pts (xy -2.5 5.5) (xy -8.1 5.5) (xy -8.1 -5.1) (xy -2.5 -5.1)) (layer F.SilkS) (width 0.1))
+ (fp_line (start -8.1 -5.1) (end 8.1 -5.1) (layer F.SilkS) (width 0.25))
+ (fp_line (start 8.1 -7.1) (end 8.1 5.5) (layer F.SilkS) (width 0.25))
+ (fp_line (start -8.1 -7.1) (end -8.1 5.5) (layer F.SilkS) (width 0.25))
+ (fp_line (start -8.1 5.5) (end 8.1 5.5) (layer F.SilkS) (width 0.25))
+ (fp_line (start -8.1 -7.1) (end 8.1 -7.1) (layer F.SilkS) (width 0.25))
+ (pad 3 thru_hole oval (at 5 2.5 270) (size 2.2 3) (drill 1.2) (layers *.Cu *.Mask)
+ (net 81 "Net-(J7-Pad3)"))
+ (pad 3 thru_hole oval (at 5 -2.5 270) (size 2.2 3) (drill 1.2) (layers *.Cu *.Mask)
+ (net 81 "Net-(J7-Pad3)"))
+ (pad 1 thru_hole custom (at -5 2.5 270) (size 1.524 1.524) (drill 1.2) (layers *.Cu *.Mask)
+ (net 82 "Net-(J7-Pad1)") (zone_connect 0)
+ (options (clearance outline) (anchor circle))
+ (primitives
+ (gr_poly (pts
+ (xy -1.4 -0.8) (xy 0 -1.6) (xy 1.4 -0.8) (xy 1.4 0.8) (xy 0 1.6)
+ (xy -1.4 0.8)) (width 0))
+ ))
+ (pad 1 thru_hole custom (at -5 -2.5 270) (size 1.524 1.524) (drill 1.2) (layers *.Cu *.Mask)
+ (net 82 "Net-(J7-Pad1)") (zone_connect 0)
+ (options (clearance outline) (anchor circle))
+ (primitives
+ (gr_poly (pts
+ (xy -1.4 -0.8) (xy 0 -1.6) (xy 1.4 -0.8) (xy 1.4 0.8) (xy 0 1.6)
+ (xy -1.4 0.8)) (width 0))
+ ))
+ (pad 2 thru_hole oval (at 0 2.5 270) (size 2.2 3) (drill 1.2) (layers *.Cu *.Mask)
+ (net 83 "Net-(J7-Pad2)"))
+ (pad 2 thru_hole oval (at 0 -2.5 270) (size 2.2 3) (drill 1.2) (layers *.Cu *.Mask)
+ (net 83 "Net-(J7-Pad2)"))
+ )
+
+ (module TripwireHook:PZK3101_3_5.00 (layer F.Cu) (tedit 62021C43) (tstamp 6202EF8C)
+ (at 208 105 270)
+ (path /62033270)
+ (fp_text reference J6 (at 0 6.6 90) (layer F.SilkS)
+ (effects (font (size 1 1) (thickness 0.15)))
+ )
+ (fp_text value Conn_01x03 (at 0 -8.2 90) (layer F.Fab)
+ (effects (font (size 1 1) (thickness 0.15)))
+ )
+ (fp_text user Front (at 0 -6.1 90) (layer F.SilkS)
+ (effects (font (size 1 1) (thickness 0.2)))
+ )
+ (fp_poly (pts (xy -2.5 5.5) (xy -8.1 5.5) (xy -8.1 -5.1) (xy -2.5 -5.1)) (layer F.SilkS) (width 0.1))
+ (fp_line (start -8.1 -5.1) (end 8.1 -5.1) (layer F.SilkS) (width 0.25))
+ (fp_line (start 8.1 -7.1) (end 8.1 5.5) (layer F.SilkS) (width 0.25))
+ (fp_line (start -8.1 -7.1) (end -8.1 5.5) (layer F.SilkS) (width 0.25))
+ (fp_line (start -8.1 5.5) (end 8.1 5.5) (layer F.SilkS) (width 0.25))
+ (fp_line (start -8.1 -7.1) (end 8.1 -7.1) (layer F.SilkS) (width 0.25))
+ (pad 3 thru_hole oval (at 5 2.5 270) (size 2.2 3) (drill 1.2) (layers *.Cu *.Mask)
+ (net 78 "Net-(J6-Pad3)"))
+ (pad 3 thru_hole oval (at 5 -2.5 270) (size 2.2 3) (drill 1.2) (layers *.Cu *.Mask)
+ (net 78 "Net-(J6-Pad3)"))
+ (pad 1 thru_hole custom (at -5 2.5 270) (size 1.524 1.524) (drill 1.2) (layers *.Cu *.Mask)
+ (net 79 "Net-(J6-Pad1)") (zone_connect 0)
+ (options (clearance outline) (anchor circle))
+ (primitives
+ (gr_poly (pts
+ (xy -1.4 -0.8) (xy 0 -1.6) (xy 1.4 -0.8) (xy 1.4 0.8) (xy 0 1.6)
+ (xy -1.4 0.8)) (width 0))
+ ))
+ (pad 1 thru_hole custom (at -5 -2.5 270) (size 1.524 1.524) (drill 1.2) (layers *.Cu *.Mask)
+ (net 79 "Net-(J6-Pad1)") (zone_connect 0)
+ (options (clearance outline) (anchor circle))
+ (primitives
+ (gr_poly (pts
+ (xy -1.4 -0.8) (xy 0 -1.6) (xy 1.4 -0.8) (xy 1.4 0.8) (xy 0 1.6)
+ (xy -1.4 0.8)) (width 0))
+ ))
+ (pad 2 thru_hole oval (at 0 2.5 270) (size 2.2 3) (drill 1.2) (layers *.Cu *.Mask)
+ (net 80 "Net-(J6-Pad2)"))
+ (pad 2 thru_hole oval (at 0 -2.5 270) (size 2.2 3) (drill 1.2) (layers *.Cu *.Mask)
+ (net 80 "Net-(J6-Pad2)"))
+ )
+
+ (module TripwireHook:PZK3101_3_5.00 (layer F.Cu) (tedit 62021C43) (tstamp 6202DB2A)
+ (at 208 85 270)
+ (path /6202A604)
+ (fp_text reference J5 (at 0 6.6 90) (layer F.SilkS)
+ (effects (font (size 1 1) (thickness 0.15)))
+ )
+ (fp_text value Conn_01x03 (at 0 -8.2 90) (layer F.Fab)
+ (effects (font (size 1 1) (thickness 0.15)))
+ )
+ (fp_text user Front (at 0 -6.1 90) (layer F.SilkS)
+ (effects (font (size 1 1) (thickness 0.2)))
+ )
+ (fp_poly (pts (xy -2.5 5.5) (xy -8.1 5.5) (xy -8.1 -5.1) (xy -2.5 -5.1)) (layer F.SilkS) (width 0.1))
+ (fp_line (start -8.1 -5.1) (end 8.1 -5.1) (layer F.SilkS) (width 0.25))
+ (fp_line (start 8.1 -7.1) (end 8.1 5.5) (layer F.SilkS) (width 0.25))
+ (fp_line (start -8.1 -7.1) (end -8.1 5.5) (layer F.SilkS) (width 0.25))
+ (fp_line (start -8.1 5.5) (end 8.1 5.5) (layer F.SilkS) (width 0.25))
+ (fp_line (start -8.1 -7.1) (end 8.1 -7.1) (layer F.SilkS) (width 0.25))
+ (pad 3 thru_hole oval (at 5 2.5 270) (size 2.2 3) (drill 1.2) (layers *.Cu *.Mask)
+ (net 75 "Net-(J5-Pad3)"))
+ (pad 3 thru_hole oval (at 5 -2.5 270) (size 2.2 3) (drill 1.2) (layers *.Cu *.Mask)
+ (net 75 "Net-(J5-Pad3)"))
+ (pad 1 thru_hole custom (at -5 2.5 270) (size 1.524 1.524) (drill 1.2) (layers *.Cu *.Mask)
+ (net 76 "Net-(J5-Pad1)") (zone_connect 0)
+ (options (clearance outline) (anchor circle))
+ (primitives
+ (gr_poly (pts
+ (xy -1.4 -0.8) (xy 0 -1.6) (xy 1.4 -0.8) (xy 1.4 0.8) (xy 0 1.6)
+ (xy -1.4 0.8)) (width 0))
+ ))
+ (pad 1 thru_hole custom (at -5 -2.5 270) (size 1.524 1.524) (drill 1.2) (layers *.Cu *.Mask)
+ (net 76 "Net-(J5-Pad1)") (zone_connect 0)
+ (options (clearance outline) (anchor circle))
+ (primitives
+ (gr_poly (pts
+ (xy -1.4 -0.8) (xy 0 -1.6) (xy 1.4 -0.8) (xy 1.4 0.8) (xy 0 1.6)
+ (xy -1.4 0.8)) (width 0))
+ ))
+ (pad 2 thru_hole oval (at 0 2.5 270) (size 2.2 3) (drill 1.2) (layers *.Cu *.Mask)
+ (net 77 "Net-(J5-Pad2)"))
+ (pad 2 thru_hole oval (at 0 -2.5 270) (size 2.2 3) (drill 1.2) (layers *.Cu *.Mask)
+ (net 77 "Net-(J5-Pad2)"))
+ )
+
(module TripwireHook:SSOP-8_3.9x5.05mm_P1.27mm_ExposedPad_ThermalVias (layer F.Cu) (tedit 6200CA0F) (tstamp 61E49DEF)
(at 185 87.555 180)
(descr "SSOP, 8 Pin (http://www.fujitsu.com/downloads/MICRO/fsa/pdf/products/memory/fram/MB85RS16-DS501-00014-6v0-E.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py")
diff --git a/pcb/CyanStripe/CyanStripe.sch b/pcb/CyanStripe/CyanStripe.sch
index 32999a3..65d32cf 100644
--- a/pcb/CyanStripe/CyanStripe.sch
+++ b/pcb/CyanStripe/CyanStripe.sch
@@ -1041,4 +1041,37 @@ F 3 "~" H 11200 2600 50 0001 C CNN
1 11200 2600
1 0 0 -1
$EndComp
+$Comp
+L Connector_Generic:Conn_01x03 J5
+U 1 1 6202A604
+P 9800 5700
+F 0 "J5" H 9880 5742 50 0000 L CNN
+F 1 "Conn_01x03" H 9880 5651 50 0000 L CNN
+F 2 "TripwireHook:PZK3101_3_5.00" H 9800 5700 50 0001 C CNN
+F 3 "~" H 9800 5700 50 0001 C CNN
+ 1 9800 5700
+ 1 0 0 -1
+$EndComp
+$Comp
+L Connector_Generic:Conn_01x03 J6
+U 1 1 62033270
+P 9800 6100
+F 0 "J6" H 9880 6142 50 0000 L CNN
+F 1 "Conn_01x03" H 9880 6051 50 0000 L CNN
+F 2 "TripwireHook:PZK3101_3_5.00" H 9800 6100 50 0001 C CNN
+F 3 "~" H 9800 6100 50 0001 C CNN
+ 1 9800 6100
+ 1 0 0 -1
+$EndComp
+$Comp
+L Connector_Generic:Conn_01x03 J7
+U 1 1 62039F65
+P 9800 6500
+F 0 "J7" H 9880 6542 50 0000 L CNN
+F 1 "Conn_01x03" H 9880 6451 50 0000 L CNN
+F 2 "TripwireHook:PZK3101_3_5.00" H 9800 6500 50 0001 C CNN
+F 3 "~" H 9800 6500 50 0001 C CNN
+ 1 9800 6500
+ 1 0 0 -1
+$EndComp
$EndSCHEMATC
diff --git a/pcb/CyanStripe/RT7272.sch b/pcb/CyanStripe/RT7272.sch
index 331f131..836eab2 100644
--- a/pcb/CyanStripe/RT7272.sch
+++ b/pcb/CyanStripe/RT7272.sch
@@ -21,7 +21,7 @@ AR Path="/61F237B3" Ref="U?" Part="1"
AR Path="/61F15DE6/61F237B3" Ref="U7" Part="1"
AR Path="/61F43542/61F237B3" Ref="U8" Part="1"
AR Path="/61F470ED/61F237B3" Ref="U9" Part="1"
-F 0 "U7" H 3050 1815 50 0000 C CNN
+F 0 "U9" H 3050 1815 50 0000 C CNN
F 1 "RT7272B" H 3050 1724 50 0000 C CNN
F 2 "TripwireHook:SSOP-8_3.9x5.05mm_P1.27mm_ExposedPad_ThermalVias" H 4100 1050 50 0001 C CNN
F 3 "https://www.richtek.com/assets/product_file/RT7272B/DS7272B-05.pdf" H 2950 1000 50 0001 C CNN
@@ -40,7 +40,7 @@ AR Path="/61F237C1" Ref="L?" Part="1"
AR Path="/61F15DE6/61F237C1" Ref="L1" Part="1"
AR Path="/61F43542/61F237C1" Ref="L2" Part="1"
AR Path="/61F470ED/61F237C1" Ref="L3" Part="1"
-F 0 "L1" V 4490 1300 50 0000 C CNN
+F 0 "L3" V 4490 1300 50 0000 C CNN
F 1 "6.8µH" V 4399 1300 50 0000 C CNN
F 2 "TripwireHook:MCS0630-6R8MN2" H 4300 1300 50 0001 C CNN
F 3 "~" H 4300 1300 50 0001 C CNN
@@ -55,7 +55,7 @@ AR Path="/61F237CD" Ref="C?" Part="1"
AR Path="/61F15DE6/61F237CD" Ref="C12" Part="1"
AR Path="/61F43542/61F237CD" Ref="C20" Part="1"
AR Path="/61F470ED/61F237CD" Ref="C28" Part="1"
-F 0 "C12" V 5200 1800 50 0000 R CNN
+F 0 "C28" V 5200 1800 50 0000 R CNN
F 1 "22µF" V 5100 1800 50 0000 R CNN
F 2 "TripwireHook_Capacitor:0805_1206_combo" H 5188 1700 50 0001 C CNN
F 3 "~" H 5150 1850 50 0001 C CNN
@@ -70,7 +70,7 @@ AR Path="/61F237D4" Ref="#PWR?" Part="1"
AR Path="/61F15DE6/61F237D4" Ref="#PWR017" Part="1"
AR Path="/61F43542/61F237D4" Ref="#PWR018" Part="1"
AR Path="/61F470ED/61F237D4" Ref="#PWR019" Part="1"
-F 0 "#PWR017" H 3050 2250 50 0001 C CNN
+F 0 "#PWR019" H 3050 2250 50 0001 C CNN
F 1 "GND" H 3055 2327 50 0000 C CNN
F 2 "" H 3050 2500 50 0001 C CNN
F 3 "" H 3050 2500 50 0001 C CNN
@@ -85,7 +85,7 @@ AR Path="/61F237DA" Ref="R?" Part="1"
AR Path="/61F15DE6/61F237DA" Ref="R9" Part="1"
AR Path="/61F43542/61F237DA" Ref="R13" Part="1"
AR Path="/61F470ED/61F237DA" Ref="R17" Part="1"
-F 0 "R9" V 4450 1550 50 0000 L CNN
+F 0 "R17" V 4450 1550 50 0000 L CNN
F 1 "27kΩ" V 4650 1550 50 0000 L CNN
F 2 "Resistor_SMD:R_0402_1005Metric" V 4480 1600 50 0001 C CNN
F 3 "~" H 4550 1600 50 0001 C CNN
@@ -102,7 +102,7 @@ AR Path="/61F237E1" Ref="R?" Part="1"
AR Path="/61F15DE6/61F237E1" Ref="R10" Part="1"
AR Path="/61F43542/61F237E1" Ref="R14" Part="1"
AR Path="/61F470ED/61F237E1" Ref="R18" Part="1"
-F 0 "R10" V 4450 2050 50 0000 L CNN
+F 0 "R18" V 4450 2050 50 0000 L CNN
F 1 "5.1kΩ" V 4650 2000 50 0000 L CNN
F 2 "Resistor_SMD:R_0402_1005Metric" V 4480 2100 50 0001 C CNN
F 3 "~" H 4550 2100 50 0001 C CNN
@@ -119,7 +119,7 @@ AR Path="/61F237E8" Ref="C?" Part="1"
AR Path="/61F15DE6/61F237E8" Ref="C7" Part="1"
AR Path="/61F43542/61F237E8" Ref="C17" Part="1"
AR Path="/61F470ED/61F237E8" Ref="C25" Part="1"
-F 0 "C7" V 3600 1700 50 0000 R CNN
+F 0 "C25" V 3600 1700 50 0000 R CNN
F 1 "2.7nF" V 3500 1700 50 0000 R CNN
F 2 "Capacitor_SMD:C_0603_1608Metric" H 3588 1600 50 0001 C CNN
F 3 "~" H 3550 1750 50 0001 C CNN
@@ -134,7 +134,7 @@ AR Path="/61F237EE" Ref="R?" Part="1"
AR Path="/61F15DE6/61F237EE" Ref="R4" Part="1"
AR Path="/61F43542/61F237EE" Ref="R12" Part="1"
AR Path="/61F470ED/61F237EE" Ref="R16" Part="1"
-F 0 "R4" V 3450 2150 50 0000 C CNN
+F 0 "R16" V 3450 2150 50 0000 C CNN
F 1 "24kΩ" V 3650 2150 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" V 3480 2150 50 0001 C CNN
F 3 "~" H 3550 2150 50 0001 C CNN
@@ -149,7 +149,7 @@ AR Path="/61F237F4" Ref="C?" Part="1"
AR Path="/61F15DE6/61F237F4" Ref="C13" Part="1"
AR Path="/61F43542/61F237F4" Ref="C21" Part="1"
AR Path="/61F470ED/61F237F4" Ref="C29" Part="1"
-F 0 "C13" V 5500 1800 50 0000 R CNN
+F 0 "C29" V 5500 1800 50 0000 R CNN
F 1 "22µF" V 5400 1800 50 0000 R CNN
F 2 "TripwireHook_Capacitor:0805_1206_combo" H 5488 1700 50 0001 C CNN
F 3 "~" H 5450 1850 50 0001 C CNN
@@ -164,7 +164,7 @@ AR Path="/61F237FA" Ref="C?" Part="1"
AR Path="/61F15DE6/61F237FA" Ref="C4" Part="1"
AR Path="/61F43542/61F237FA" Ref="C14" Part="1"
AR Path="/61F470ED/61F237FA" Ref="C22" Part="1"
-F 0 "C4" V 1350 1800 50 0000 R CNN
+F 0 "C22" V 1350 1800 50 0000 R CNN
F 1 "10µF" V 1250 1800 50 0000 R CNN
F 2 "TripwireHook_Capacitor:0805_1206_combo" H 1338 1700 50 0001 C CNN
F 3 "~" H 1300 1850 50 0001 C CNN
@@ -179,7 +179,7 @@ AR Path="/61F23800" Ref="R?" Part="1"
AR Path="/61F15DE6/61F23800" Ref="R3" Part="1"
AR Path="/61F43542/61F23800" Ref="R11" Part="1"
AR Path="/61F470ED/61F23800" Ref="R15" Part="1"
-F 0 "R3" V 2400 1850 50 0000 C CNN
+F 0 "R15" V 2400 1850 50 0000 C CNN
F 1 "180kΩ" V 2184 1850 50 0000 C CNN
F 2 "Resistor_SMD:R_0402_1005Metric" V 2230 1850 50 0001 C CNN
F 3 "~" H 2300 1850 50 0001 C CNN
@@ -203,7 +203,7 @@ AR Path="/61F23812" Ref="C?" Part="1"
AR Path="/61F15DE6/61F23812" Ref="C5" Part="1"
AR Path="/61F43542/61F23812" Ref="C15" Part="1"
AR Path="/61F470ED/61F23812" Ref="C23" Part="1"
-F 0 "C5" V 1650 1800 50 0000 R CNN
+F 0 "C23" V 1650 1800 50 0000 R CNN
F 1 "10µF" V 1500 1800 50 0000 R CNN
F 2 "TripwireHook_Capacitor:0805_1206_combo" H 1638 1700 50 0001 C CNN
F 3 "~" H 1600 1850 50 0001 C CNN
@@ -261,7 +261,7 @@ AR Path="/61F23849" Ref="C?" Part="1"
AR Path="/61F15DE6/61F23849" Ref="C8" Part="1"
AR Path="/61F43542/61F23849" Ref="C18" Part="1"
AR Path="/61F470ED/61F23849" Ref="C26" Part="1"
-F 0 "C8" H 3915 1146 50 0000 L CNN
+F 0 "C26" H 3915 1146 50 0000 L CNN
F 1 "100nF" H 3915 1055 50 0000 L CNN
F 2 "Capacitor_SMD:C_0603_1608Metric" H 3838 950 50 0001 C CNN
F 3 "~" H 3800 1100 50 0001 C CNN
diff --git a/pcb/lib/TripwireHook b/pcb/lib/TripwireHook
index 851e1eb..50cddc3 160000
--- a/pcb/lib/TripwireHook
+++ b/pcb/lib/TripwireHook
@@ -1 +1 @@
-Subproject commit 851e1eb298f655c132243fb229a5cbc87106c6d2
+Subproject commit 50cddc3372b132d22f465b96a5a79baa345629a3
--
GitLab