From 8e34f990941eff3b12fbe11dceafb96a1e5cd79b Mon Sep 17 00:00:00 2001
From: Jochen Vothknecht <j.vothknecht@alphaelectronic.de>
Date: Mon, 31 Jan 2022 17:41:33 +0100
Subject: [PATCH] Logic gate refactorings; Adding single AND gate

---
 TripwireHook.dcm | 20 +++++++++++++-------
 TripwireHook.lib | 23 +++++++++++++++++++++++
 2 files changed, 36 insertions(+), 7 deletions(-)

diff --git a/TripwireHook.dcm b/TripwireHook.dcm
index c3a7d9e..5b6690c 100644
--- a/TripwireHook.dcm
+++ b/TripwireHook.dcm
@@ -5,43 +5,49 @@ D 8x8 RGB LED Matrix
 $ENDCMP
 #
 $CMP 74HC00
-D CMOS Quad 2-Input NAND gate
+D Quad 2-Input NAND CMOS gate
 K cmos nand gate
 F https://assets.nexperia.com/documents/data-sheet/74HC_HCT00.pdf
 $ENDCMP
 #
 $CMP 74HC02
-D CMOS Quad 2-Input NOR gate
+D Quad 2-Input NOR CMOS gate
 K cmos nor gate
 F https://assets.nexperia.com/documents/data-sheet/74HC_HCT02.pdf
 $ENDCMP
 #
 $CMP 74HC04
-D CMOS Hex Inverter gate
+D Hex Inverter CMOS gate
 K cmos inverter gate
 F https://assets.nexperia.com/documents/data-sheet/74HC_HCT04.pdf
 $ENDCMP
 #
 $CMP 74HC08
-D CMOS Quad 2-Input AND gate
+D CMOS Quad 2-Input AND CMOS gate
 K cmos and gate
 F https://assets.nexperia.com/documents/data-sheet/74HC_HCT08.pdf
 $ENDCMP
 #
 $CMP 74HC08_Split
-D CMOS Quad 2-Input AND gate
+D CMOS Quad 2-Input AND CMOS gate
 K cmos and gate
 F https://assets.nexperia.com/documents/data-sheet/74HC_HCT08.pdf
 $ENDCMP
 #
+$CMP 74HC1G08_Split
+D Single 2-Input CMOS AND gate
+K cmos and gate
+F https://assets.nexperia.com/documents/data-sheet/74HC_HCT1G08.pdf
+$ENDCMP
+#
 $CMP 74HC32
-D CMOS Quad 2-Input OR gate
+D CMOS Quad 2-Input OR CMOS gate
 K cmos or gate
 F https://assets.nexperia.com/documents/data-sheet/74HC_HCT32.pdf
 $ENDCMP
 #
 $CMP 74HC86
-D CMOS Quad 2-Input XOR gate
+D CMOS Quad 2-Input XOR CMOS gate
 K cmos xor gate
 F https://assets.nexperia.com/documents/data-sheet/74HC_HCT86.pdf
 $ENDCMP
diff --git a/TripwireHook.lib b/TripwireHook.lib
index 606733a..6b0af5e 100644
--- a/TripwireHook.lib
+++ b/TripwireHook.lib
@@ -275,6 +275,7 @@ F1 "74HC08_Split" 0 -150 50 H V C CNN
 F2 "Package_SO:SOIC-14_3.9x8.7mm_P1.27mm" 0 -300 50 H I C CNN
 F3 "" 0 0 50 H I C CNN
 DRAW
+T 0 0 20 24 0 0 0 74HC08 Normal 1 C C
 T 0 0 0 59 0 1 0 & Normal 1 C C
 T 0 0 100 50 0 5 0 Vcc Normal 0 C C
 T 0 0 0 59 0 2 1 & Normal 1 C C
@@ -304,6 +305,28 @@ X GND EP 0 -200 100 U 50 50 5 1 W N
 ENDDRAW
 ENDDEF
 #
+# 74HC1G08_Split
+#
+DEF 74HC1G08_Split U 0 40 Y N 2 L N
+F0 "U" -150 150 50 H V C CNN
+F1 "74HC1G08_Split" 150 0 50 V V C CNN
+F2 "Package_TO_SOT_SMD:SOT-23-5" 0 -300 50 H I C CNN
+F3 "" -510 -220 50 H I C CNN
+DRAW
+T 0 0 0 59 0 1 0 & Normal 1 C C
+T 0 0 0 24 0 2 1 74HC08 Normal 1 C C
+T 0 0 -100 50 0 2 1 GND Normal 0 C C
+T 0 0 100 50 0 2 1 Vcc Normal 0 C C
+S -100 150 100 -150 2 1 0 f
+P 5 1 0 12 -100 100 100 100 100 -100 -100 -100 -100 100 f
+X B 1 -200 50 100 R 50 50 1 1 I
+X A 2 -200 -50 100 R 50 50 1 1 I
+X Z 4 200 0 100 L 50 50 1 1 O
+X GND 3 0 -250 100 U 50 50 2 1 W
+X VCC 5 0 250 100 D 50 50 2 1 W
+ENDDRAW
+ENDDEF
+#
 # 74HC32
 #
 DEF 74HC32 U 0 40 Y Y 1 F N
-- 
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