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Commit 9acbde4e authored by Benjamin Koch's avatar Benjamin Koch
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make RS485 logging less verbose

parent 8e0305f4
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......@@ -287,7 +287,7 @@ impl<REGS: ModbusRegisters> RS485Handler for ModbusServer<REGS> {
where F: FnOnce(&[u8]) {
match rx {
Ok(rx_char) => {
info!("RX {:?}", rx_char);
//info!("RX {:?}", rx_char);
self.rxcrc.update(&[rx_char]);
if !self.rxbuf.is_full() {
......
......@@ -292,6 +292,8 @@ impl<H: RS485Handler> RS485<H> {
).await;
match x {
Either4::First(_) => {
let debug_autobaud = false;
let mut sum = 0;
let mut first = 0;
let mut ok = false;
......@@ -299,7 +301,9 @@ impl<H: RS485Handler> RS485<H> {
for i in 0..din.len() {
if din[i] == 0 {
bit_index = 0;
info!("SM in {}: {:08x} -> start", i, din[i]);
if debug_autobaud {
info!("SM in {}: {:08x} -> start", i, din[i]);
}
} else {
let mut delay = timeout_start_value - din[i];
if bit_index == 0 {
......@@ -312,7 +316,9 @@ impl<H: RS485Handler> RS485<H> {
}
let millis = (delay) as f32 / SM_FREQ as f32 * 1000. * 2.;
let baud = 1000. / millis;
info!("SM in {} ({}): {:08x} -> {} -> {} ms -> {}", i, bit_index, din[i], delay, millis, baud);
if debug_autobaud {
info!("SM in {} ({}): {:08x} -> {} -> {} ms -> {}", i, bit_index, din[i], delay, millis, baud);
}
if bit_index == 0 {
sum = 0;
first = delay;
......@@ -339,7 +345,9 @@ impl<H: RS485Handler> RS485<H> {
}
let millis = (delay) as f32 / SM_FREQ as f32 * 1000. * 2.;
let baud = 1000. / millis;
info!("SM in ({}): {:08x} -> {} -> {} ms -> {}", bit_index, x, delay, millis, baud);
if debug_autobaud {
info!("SM in ({}): {:08x} -> {} -> {} ms -> {}", bit_index, x, delay, millis, baud);
}
if bit_index == 0 {
sum = 0;
first = delay;
......
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