Routing settins; IC placement

Bell.pro

-update=Mo 24 Mai 2021 12:53:04 CEST
+update=Mi 09 Jun 2021 10:08:06 CEST
 version=1
 last_client=kicad
 [general]
@@ -17,34 +17,39 @@ version=1
 PageLayoutDescrFile=
 LastNetListRead=
 CopperLayerCount=2
-BoardThickness=1.6
+BoardThickness=0.8
 AllowMicroVias=0
 AllowBlindVias=0
 RequireCourtyardDefinitions=0
 ProhibitOverlappingCourtyards=1
-MinTrackWidth=0.2
-MinViaDiameter=0.4
+MinTrackWidth=0.127
+MinViaDiameter=0.6
 MinViaDrill=0.3
 MinMicroViaDiameter=0.2
 MinMicroViaDrill=0.09999999999999999
 MinHoleToHole=0.25
 TrackWidth1=0.25
-TrackWidth2=0.5
-TrackWidth3=1
-TrackWidth4=1.5
-TrackWidth5=2
+TrackWidth2=0.127
+TrackWidth3=0.5
+TrackWidth4=1
+TrackWidth5=1.5
+TrackWidth6=2
 ViaDiameter1=0.8
 ViaDrill1=0.4
+ViaDiameter2=0.6
+ViaDrill2=0.3
+ViaDiameter3=0.7
+ViaDrill3=0.35
 dPairWidth1=0.2
 dPairGap1=0.25
 dPairViaGap1=0.25
 dPairWidth2=0.25
 dPairGap2=0.25
 dPairViaGap2=0.5
-SilkLineWidth=0.12
+SilkLineWidth=0.2
 SilkTextSizeV=1
 SilkTextSizeH=1
-SilkTextSizeThickness=0.15
+SilkTextSizeThickness=0.2
 SilkTextItalic=0
 SilkTextUpright=1
 CopperLineWidth=0.2
@@ -243,3 +248,14 @@ uViaDrill=0.1
 dPairWidth=0.2
 dPairGap=0.25
 dPairViaGap=0.25
+[pcbnew/Netclasses/1]
+Name=Signal
+Clearance=0.127
+TrackWidth=0.127
+ViaDiameter=0.6
+ViaDrill=0.3
+uViaDiameter=0.3
+uViaDrill=0.1
+dPairWidth=0.2
+dPairGap=0.25
+dPairViaGap=0.25