Skip to content
GitLab
Explore
Sign in
Primary navigation
Search or go to…
Project
Bell
Manage
Activity
Members
Labels
Plan
Issues
Issue boards
Milestones
Wiki
Code
Merge requests
Repository
Branches
Commits
Tags
Repository graph
Compare revisions
Snippets
Build
Pipelines
Jobs
Pipeline schedules
Artifacts
Deploy
Releases
Package Registry
Container Registry
Model registry
Operate
Environments
Terraform modules
Monitor
Incidents
Analyze
Value stream analytics
Contributor analytics
CI/CD analytics
Repository analytics
Model experiments
Help
Help
Support
GitLab documentation
Compare GitLab plans
Community forum
Contribute to GitLab
Provide feedback
Keyboard shortcuts
?
Snippets
Groups
Projects
Show more breadcrumbs
fxk8y
Bell
Commits
581ce26d
Commit
581ce26d
authored
3 years ago
by
fxk8y
Browse files
Options
Downloads
Patches
Plain Diff
Routing settins; IC placement
parent
698e0919
No related branches found
No related tags found
No related merge requests found
Changes
2
Expand all
Hide whitespace changes
Inline
Side-by-side
Showing
2 changed files
Bell.kicad_pcb
+568
-550
568 additions, 550 deletions
Bell.kicad_pcb
Bell.pro
+26
-10
26 additions, 10 deletions
Bell.pro
with
594 additions
and
560 deletions
Bell.kicad_pcb
+
568
−
550
View file @
581ce26d
This diff is collapsed.
Click to expand it.
Bell.pro
+
26
−
10
View file @
581ce26d
update
=
M
o
24
Mai
2021
1
2
:
53
:
0
4
CEST
update
=
M
i
09
Jun
2021
1
0
:
08
:
0
6
CEST
version
=
1
last_client
=
kicad
[
general
]
...
...
@@ -17,34 +17,39 @@ version=1
PageLayoutDescrFile
=
LastNetListRead
=
CopperLayerCount
=
2
BoardThickness
=
1.6
BoardThickness
=
0.8
AllowMicroVias
=
0
AllowBlindVias
=
0
RequireCourtyardDefinitions
=
0
ProhibitOverlappingCourtyards
=
1
MinTrackWidth
=
0.
2
MinViaDiameter
=
0.
4
MinTrackWidth
=
0.
127
MinViaDiameter
=
0.
6
MinViaDrill
=
0.3
MinMicroViaDiameter
=
0.2
MinMicroViaDrill
=
0.09999999999999999
MinHoleToHole
=
0.25
TrackWidth1
=
0.25
TrackWidth2
=
0.5
TrackWidth3
=
1
TrackWidth4
=
1.5
TrackWidth5
=
2
TrackWidth2
=
0.127
TrackWidth3
=
0.5
TrackWidth4
=
1
TrackWidth5
=
1.5
TrackWidth6
=
2
ViaDiameter1
=
0.8
ViaDrill1
=
0.4
ViaDiameter2
=
0.6
ViaDrill2
=
0.3
ViaDiameter3
=
0.7
ViaDrill3
=
0.35
dPairWidth1
=
0.2
dPairGap1
=
0.25
dPairViaGap1
=
0.25
dPairWidth2
=
0.25
dPairGap2
=
0.25
dPairViaGap2
=
0.5
SilkLineWidth
=
0.
1
2
SilkLineWidth
=
0.2
SilkTextSizeV
=
1
SilkTextSizeH
=
1
SilkTextSizeThickness
=
0.
15
SilkTextSizeThickness
=
0.
2
SilkTextItalic
=
0
SilkTextUpright
=
1
CopperLineWidth
=
0.2
...
...
@@ -243,3 +248,14 @@ uViaDrill=0.1
dPairWidth
=
0.2
dPairGap
=
0.25
dPairViaGap
=
0.25
[
pcbnew
/
Netclasses
/
1
]
Name
=
Signal
Clearance
=
0.127
TrackWidth
=
0.127
ViaDiameter
=
0.6
ViaDrill
=
0.3
uViaDiameter
=
0.3
uViaDrill
=
0.1
dPairWidth
=
0.2
dPairGap
=
0.25
dPairViaGap
=
0.25
This diff is collapsed.
Click to expand it.
Preview
0%
Loading
Try again
or
attach a new file
.
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Save comment
Cancel
Please
register
or
sign in
to comment