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Commit 05c7960f authored by fxk8y's avatar fxk8y :spider:
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Begin routing. Puzzle solved :smirk:

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CyanLight.kicad_pcb
+ 311
− 230
View file @ 05c7960f
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CyanLight.pro
+ 230
− 20
View file @ 05c7960f
update=22/05/2015 07:44:53
update=Do 29 Jul 2021 17:24:41 CEST
version=1
last_client=kicad
[general]
version=1
RootSch=
BoardNm=
[pcbnew]
version=1
LastNetListRead=
UseCmpFile=1
PadDrill=0.600000000000
PadDrillOvalY=0.600000000000
PadSizeH=1.500000000000
PadSizeV=1.500000000000
PcbTextSizeV=1.500000000000
PcbTextSizeH=1.500000000000
PcbTextThickness=0.300000000000
ModuleTextSizeV=1.000000000000
ModuleTextSizeH=1.000000000000
ModuleTextSizeThickness=0.150000000000
SolderMaskClearance=0.000000000000
SolderMaskMinWidth=0.000000000000
DrawSegmentWidth=0.200000000000
BoardOutlineThickness=0.100000000000
ModuleOutlineThickness=0.150000000000
[cvpcb]
version=1
NetIExt=net
......@@ -31,3 +12,232 @@ NetIExt=net
version=1
LibDir=
[eeschema/libraries]
[pcbnew]
version=1
PageLayoutDescrFile=
LastNetListRead=
CopperLayerCount=2
BoardThickness=1.6
AllowMicroVias=0
AllowBlindVias=0
RequireCourtyardDefinitions=0
ProhibitOverlappingCourtyards=1
MinTrackWidth=0.2
MinViaDiameter=0.4
MinViaDrill=0.3
MinMicroViaDiameter=0.2
MinMicroViaDrill=0.09999999999999999
MinHoleToHole=0.25
TrackWidth1=0.25
TrackWidth2=0.5
TrackWidth3=0.7
TrackWidth4=1.025
TrackWidth5=1.4
TrackWidth6=1.6
ViaDiameter1=0.8
ViaDrill1=0.4
dPairWidth1=0.2
dPairGap1=0.25
dPairViaGap1=0.25
SilkLineWidth=0.12
SilkTextSizeV=1
SilkTextSizeH=1
SilkTextSizeThickness=0.15
SilkTextItalic=0
SilkTextUpright=1
CopperLineWidth=0.2
CopperTextSizeV=1.5
CopperTextSizeH=1.5
CopperTextThickness=0.3
CopperTextItalic=0
CopperTextUpright=1
EdgeCutLineWidth=0.05
CourtyardLineWidth=0.05
OthersLineWidth=0.15
OthersTextSizeV=1
OthersTextSizeH=1
OthersTextSizeThickness=0.15
OthersTextItalic=0
OthersTextUpright=1
SolderMaskClearance=0
SolderMaskMinWidth=0
SolderPasteClearance=0
SolderPasteRatio=-0
[pcbnew/Layer.F.Cu]
Name=F.Cu
Type=0
Enabled=1
[pcbnew/Layer.In1.Cu]
Name=In1.Cu
Type=0
Enabled=0
[pcbnew/Layer.In2.Cu]
Name=In2.Cu
Type=0
Enabled=0
[pcbnew/Layer.In3.Cu]
Name=In3.Cu
Type=0
Enabled=0
[pcbnew/Layer.In4.Cu]
Name=In4.Cu
Type=0
Enabled=0
[pcbnew/Layer.In5.Cu]
Name=In5.Cu
Type=0
Enabled=0
[pcbnew/Layer.In6.Cu]
Name=In6.Cu
Type=0
Enabled=0
[pcbnew/Layer.In7.Cu]
Name=In7.Cu
Type=0
Enabled=0
[pcbnew/Layer.In8.Cu]
Name=In8.Cu
Type=0
Enabled=0
[pcbnew/Layer.In9.Cu]
Name=In9.Cu
Type=0
Enabled=0
[pcbnew/Layer.In10.Cu]
Name=In10.Cu
Type=0
Enabled=0
[pcbnew/Layer.In11.Cu]
Name=In11.Cu
Type=0
Enabled=0
[pcbnew/Layer.In12.Cu]
Name=In12.Cu
Type=0
Enabled=0
[pcbnew/Layer.In13.Cu]
Name=In13.Cu
Type=0
Enabled=0
[pcbnew/Layer.In14.Cu]
Name=In14.Cu
Type=0
Enabled=0
[pcbnew/Layer.In15.Cu]
Name=In15.Cu
Type=0
Enabled=0
[pcbnew/Layer.In16.Cu]
Name=In16.Cu
Type=0
Enabled=0
[pcbnew/Layer.In17.Cu]
Name=In17.Cu
Type=0
Enabled=0
[pcbnew/Layer.In18.Cu]
Name=In18.Cu
Type=0
Enabled=0
[pcbnew/Layer.In19.Cu]
Name=In19.Cu
Type=0
Enabled=0
[pcbnew/Layer.In20.Cu]
Name=In20.Cu
Type=0
Enabled=0
[pcbnew/Layer.In21.Cu]
Name=In21.Cu
Type=0
Enabled=0
[pcbnew/Layer.In22.Cu]
Name=In22.Cu
Type=0
Enabled=0
[pcbnew/Layer.In23.Cu]
Name=In23.Cu
Type=0
Enabled=0
[pcbnew/Layer.In24.Cu]
Name=In24.Cu
Type=0
Enabled=0
[pcbnew/Layer.In25.Cu]
Name=In25.Cu
Type=0
Enabled=0
[pcbnew/Layer.In26.Cu]
Name=In26.Cu
Type=0
Enabled=0
[pcbnew/Layer.In27.Cu]
Name=In27.Cu
Type=0
Enabled=0
[pcbnew/Layer.In28.Cu]
Name=In28.Cu
Type=0
Enabled=0
[pcbnew/Layer.In29.Cu]
Name=In29.Cu
Type=0
Enabled=0
[pcbnew/Layer.In30.Cu]
Name=In30.Cu
Type=0
Enabled=0
[pcbnew/Layer.B.Cu]
Name=B.Cu
Type=0
Enabled=1
[pcbnew/Layer.B.Adhes]
Enabled=1
[pcbnew/Layer.F.Adhes]
Enabled=1
[pcbnew/Layer.B.Paste]
Enabled=1
[pcbnew/Layer.F.Paste]
Enabled=1
[pcbnew/Layer.B.SilkS]
Enabled=1
[pcbnew/Layer.F.SilkS]
Enabled=1
[pcbnew/Layer.B.Mask]
Enabled=1
[pcbnew/Layer.F.Mask]
Enabled=1
[pcbnew/Layer.Dwgs.User]
Enabled=1
[pcbnew/Layer.Cmts.User]
Enabled=1
[pcbnew/Layer.Eco1.User]
Enabled=1
[pcbnew/Layer.Eco2.User]
Enabled=1
[pcbnew/Layer.Edge.Cuts]
Enabled=1
[pcbnew/Layer.Margin]
Enabled=1
[pcbnew/Layer.B.CrtYd]
Enabled=1
[pcbnew/Layer.F.CrtYd]
Enabled=1
[pcbnew/Layer.B.Fab]
Enabled=1
[pcbnew/Layer.F.Fab]
Enabled=1
[pcbnew/Layer.Rescue]
Enabled=0
[pcbnew/Netclasses]
[pcbnew/Netclasses/Default]
Name=Default
Clearance=0.2
TrackWidth=0.25
ViaDiameter=0.8
ViaDrill=0.4
uViaDiameter=0.3
uViaDrill=0.1
dPairWidth=0.2
dPairGap=0.25
dPairViaGap=0.25
CyanLight.sch
+ 119
− 42
View file @ 05c7960f
......@@ -54,7 +54,7 @@ U 1 1 60FD4E02
P 4500 3250
F 0 "C5" H 4550 3350 50 0000 L CNN
F 1 "10µF" H 4550 3150 50 0000 L CNN
F 2 "TripwireHook_Capacitor:0805_1206_1812_combo" H 4538 3100 50 0001 C CNN
F 2 "TripwireHook_Capacitor:0805_1206_combo" H 4538 3100 50 0001 C CNN
F 3 "~" H 4500 3250 50 0001 C CNN
1 4500 3250
1 0 0 -1
......@@ -65,7 +65,7 @@ U 1 1 60FD6203
P 4250 3250
F 0 "C4" H 4300 3350 50 0000 L CNN
F 1 "10µF" H 4300 3150 50 0000 L CNN
F 2 "TripwireHook_Capacitor:0805_1206_1812_combo" H 4288 3100 50 0001 C CNN
F 2 "TripwireHook_Capacitor:0805_1206_combo" H 4288 3100 50 0001 C CNN
F 3 "~" H 4250 3250 50 0001 C CNN
1 4250 3250
1 0 0 -1
......@@ -76,7 +76,7 @@ U 1 1 60FD656E
P 4000 3250
F 0 "C3" H 4050 3350 50 0000 L CNN
F 1 "10µF" H 4050 3150 50 0000 L CNN
F 2 "TripwireHook_Capacitor:0805_1206_1812_combo" H 4038 3100 50 0001 C CNN
F 2 "TripwireHook_Capacitor:0805_1206_combo" H 4038 3100 50 0001 C CNN
F 3 "~" H 4000 3250 50 0001 C CNN
1 4000 3250
1 0 0 -1
......@@ -128,56 +128,39 @@ Connection ~ 6500 2750
$Comp
L Device:D_Schottky D2
U 1 1 60FD9D56
P 7400 3000
F 0 "D2" V 7354 3080 50 0000 L CNN
F 1 "SK36A" V 7445 3080 50 0000 L CNN
F 2 "TripwireHook_Diode:SMA" H 7400 3000 50 0001 C CNN
F 3 "~" H 7400 3000 50 0001 C CNN
1 7400 3000
P 7600 3000
F 0 "D2" V 7554 3080 50 0000 L CNN
F 1 "SK36A" V 7645 3080 50 0000 L CNN
F 2 "TripwireHook_Diode:SMA" H 7600 3000 50 0001 C CNN
F 3 "~" H 7600 3000 50 0001 C CNN
1 7600 3000
0 1 1 0
$EndComp
Wire Wire Line
6250 3350 7400 3350
7600 3350 7600 3250
Wire Wire Line
7400 3350 7400 3250
Wire Wire Line
7400 2850 7400 2750
Wire Wire Line
7400 2750 6500 2750
7600 2850 7600 2750
Wire Wire Line
6500 2750 6350 2750
$Comp
L Device:L L1
U 1 1 60FDCEAC
P 7150 3250
F 0 "L1" V 7340 3250 50 0000 C CNN
F 1 "L" V 7249 3250 50 0000 C CNN
F 2 "TripwireHook:MCS0630-6R8MN2" H 7150 3250 50 0001 C CNN
F 3 "~" H 7150 3250 50 0001 C CNN
1 7150 3250
P 7350 3250
F 0 "L1" V 7540 3250 50 0000 C CNN
F 1 "L" V 7449 3250 50 0000 C CNN
F 2 "TripwireHook_Inductor:MPIT8040" H 7350 3250 50 0001 C CNN
F 3 "~" H 7350 3250 50 0001 C CNN
1 7350 3250
0 -1 -1 0
$EndComp
$Comp
L Device:LED D1
U 1 1 60FDD5EC
P 6750 3250
F 0 "D1" H 6750 3050 50 0000 C CNN
F 1 "LED" H 6750 3150 50 0000 C CNN
F 2 "TripwireHook_Connector_Handmade:PinHeader254_01x02" H 6750 3250 50 0001 C CNN
F 3 "~" H 6750 3250 50 0001 C CNN
1 6750 3250
-1 0 0 1
$EndComp
Wire Wire Line
6500 3250 6600 3250
Connection ~ 6500 3250
Wire Wire Line
6900 3250 7000 3250
7100 3250 7150 3250
Wire Wire Line
7300 3250 7400 3250
Connection ~ 7400 3250
7500 3250 7600 3250
Connection ~ 7600 3250
Wire Wire Line
7400 3250 7400 3150
7600 3250 7600 3150
$Comp
L power:+24V #PWR03
U 1 1 60FE49CA
......@@ -272,10 +255,104 @@ Wire Wire Line
4250 3500 4250 3600
Text GLabel 6350 2850 0 50 Input ~ 0
Vin
Text GLabel 6500 3450 3 50 Input ~ 0
CSN
Text GLabel 7150 3350 3 50 Input ~ 0
Text GLabel 7350 3350 3 50 Input ~ 0
SW
Wire Wire Line
6500 3250 6500 3450
6500 3250 6750 3250
Wire Wire Line
6500 2750 7600 2750
Wire Wire Line
6250 3350 7600 3350
Connection ~ 7150 3250
Wire Wire Line
7150 3250 7200 3250
Text GLabel 6650 3700 0 50 Input ~ 0
Anode
Text GLabel 7250 3700 2 50 Input ~ 0
Cathode
$Comp
L Device:C C1
U 1 1 61032649
P 3750 3250
F 0 "C1" H 3800 3350 50 0000 L CNN
F 1 "10µF" H 3800 3150 50 0000 L CNN
F 2 "TripwireHook_Capacitor:0805_1206_combo" H 3788 3100 50 0001 C CNN
F 3 "~" H 3750 3250 50 0001 C CNN
1 3750 3250
1 0 0 -1
$EndComp
$Comp
L Device:C C2
U 1 1 61032B36
P 4750 3250
F 0 "C2" H 4800 3350 50 0000 L CNN
F 1 "10µF" H 4800 3150 50 0000 L CNN
F 2 "TripwireHook_Capacitor:0805_1206_combo" H 4788 3100 50 0001 C CNN
F 3 "~" H 4750 3250 50 0001 C CNN
1 4750 3250
1 0 0 -1
$EndComp
Wire Wire Line
3750 3100 3750 3000
Wire Wire Line
3750 3000 4000 3000
Connection ~ 4000 3000
Wire Wire Line
4500 3000 4750 3000
Wire Wire Line
4750 3000 4750 3100
Connection ~ 4500 3000
Wire Wire Line
3750 3400 3750 3500
Wire Wire Line
3750 3500 4000 3500
Connection ~ 4000 3500
Wire Wire Line
4500 3500 4750 3500
Wire Wire Line
4750 3500 4750 3400
Connection ~ 4500 3500
$Comp
L Device:C C6
U 1 1 61038131
P 6950 3600
F 0 "C6" H 7000 3700 50 0000 L CNN
F 1 "10µF" H 7000 3500 50 0000 L CNN
F 2 "TripwireHook_Capacitor:0805_1206_combo" H 6988 3450 50 0001 C CNN
F 3 "~" H 6950 3600 50 0001 C CNN
1 6950 3600
0 1 1 0
$EndComp
Connection ~ 6750 3250
Wire Wire Line
6750 3250 6800 3250
Wire Wire Line
6750 3600 6800 3600
Wire Wire Line
6750 3250 6750 3600
Wire Wire Line
7150 3600 7100 3600
Wire Wire Line
7150 3250 7150 3600
$Comp
L Device:LED D1
U 1 1 60FDD5EC
P 6950 3250
F 0 "D1" H 6950 3050 50 0000 C CNN
F 1 "LED" H 6950 3150 50 0000 C CNN
F 2 "TripwireHook_Diode:3W_LED" H 6950 3250 50 0001 C CNN
F 3 "~" H 6950 3250 50 0001 C CNN
1 6950 3250
-1 0 0 1
$EndComp
Wire Wire Line
7150 3600 7150 3700
Wire Wire Line
7150 3700 7250 3700
Connection ~ 7150 3600
Wire Wire Line
6750 3600 6750 3700
Wire Wire Line
6750 3700 6650 3700
Connection ~ 6750 3600
$EndSCHEMATC
TripwireHook @ c2d90e79
Compare e24219b9...c2d90e79
Subproject commit e24219b9408615c786a4b801f4fcc79131704086
Subproject commit c2d90e7970e3a8dd85c91092769cb9ffc5025965
fp-lib-table
+ 1
− 0
View file @ 05c7960f
......@@ -4,4 +4,5 @@
(lib (name TripwireHook_Connector_Handmade)(type KiCad)(uri ${KIPRJMOD}/TripwireHook/TripwireHook_Connector_Handmade.pretty)(options "")(descr ""))
(lib (name TripwireHook_Capacitor)(type KiCad)(uri ${KIPRJMOD}/TripwireHook/Capacitor.pretty)(options "")(descr ""))
(lib (name TripwireHook_Diode)(type KiCad)(uri ${KIPRJMOD}/TripwireHook/Diode.pretty)(options "")(descr ""))
(lib (name TripwireHook_Inductor)(type KiCad)(uri ${KIPRJMOD}/TripwireHook/Inductor.pretty)(options "")(descr ""))
)
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