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Andreas Horn
ch32v003fun
Commits
c01ffcd2
Commit
c01ffcd2
authored
1 year ago
by
Alexander Mandera
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Add 80MHz init for V103
parent
bcaf9581
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3 changed files
ch32v003fun/ch32v003fun.c
+59
-0
59 additions, 0 deletions
ch32v003fun/ch32v003fun.c
ch32v003fun/ch32v003fun.h
+2
-0
2 additions, 0 deletions
ch32v003fun/ch32v003fun.h
examples_v10x/blink/blink.c
+2
-2
2 additions, 2 deletions
examples_v10x/blink/blink.c
with
63 additions
and
2 deletions
ch32v003fun/ch32v003fun.c
+
59
−
0
View file @
c01ffcd2
...
@@ -1352,6 +1352,65 @@ void SystemInit72HSE( void )
...
@@ -1352,6 +1352,65 @@ void SystemInit72HSE( void )
while
((
RCC
->
CFGR0
&
(
uint32_t
)
RCC_SWS
)
!=
(
uint32_t
)
0x08
)
{}
while
((
RCC
->
CFGR0
&
(
uint32_t
)
RCC_SWS
)
!=
(
uint32_t
)
0x08
)
{}
}
}
void
SystemInit80HSI
(
void
)
{
EXTEN
->
EXTEN_CTR
|=
EXTEN_PLL_HSI_PRE
;
/* Enable Prefetch Buffer */
FLASH
->
ACTLR
|=
FLASH_ACTLR_PRFTBE
;
/* Flash 1 wait state */
FLASH
->
ACTLR
&=
(
uint32_t
)((
uint32_t
)
~
FLASH_ACTLR_LATENCY
);
FLASH
->
ACTLR
|=
(
uint32_t
)
FLASH_ACTLR_LATENCY_1
;
RCC
->
CFGR0
=
RCC_HPRE_DIV1
|
RCC_PPRE2_DIV1
|
RCC_PPRE1_DIV2
;
RCC
->
CFGR0
&=
(
uint32_t
)((
uint32_t
)
~
(
RCC_PLLSRC
|
RCC_PLLXTPRE
|
RCC_PLLMULL
));
RCC
->
CFGR0
|=
(
uint32_t
)(
RCC_PLLSRC_HSI_Div2
|
RCC_PLLMULL10
);
/* Enable PLL */
RCC
->
CTLR
|=
RCC_PLLON
;
/* Wait till PLL is ready */
while
((
RCC
->
CTLR
&
RCC_PLLRDY
)
==
0
)
{}
/* Select PLL as system clock source */
RCC
->
CFGR0
&=
(
uint32_t
)((
uint32_t
)
~
(
RCC_SW
));
RCC
->
CFGR0
|=
(
uint32_t
)
RCC_SW_PLL
;
/* Wait till PLL is used as system clock source */
while
((
RCC
->
CFGR0
&
(
uint32_t
)
RCC_SWS
)
!=
(
uint32_t
)
0x08
)
{}
}
void
SystemInit80HSE
(
void
)
{
RCC
->
CTLR
|=
((
uint32_t
)
RCC_HSEON
);
while
(
!
(
RCC
->
CTLR
&
RCC_HSERDY
));
/* Enable Prefetch Buffer */
FLASH
->
ACTLR
|=
FLASH_ACTLR_PRFTBE
;
/* Flash 2 wait state */
FLASH
->
ACTLR
&=
(
uint32_t
)((
uint32_t
)
~
FLASH_ACTLR_LATENCY
);
FLASH
->
ACTLR
|=
(
uint32_t
)
FLASH_ACTLR_LATENCY_2
;
RCC
->
CFGR0
=
RCC_HPRE_DIV1
|
RCC_PPRE2_DIV1
|
RCC_PPRE1_DIV2
;
RCC
->
CFGR0
&=
(
uint32_t
)((
uint32_t
)
~
(
RCC_PLLSRC
|
RCC_PLLXTPRE
|
RCC_PLLMULL
));
RCC
->
CFGR0
|=
(
uint32_t
)(
RCC_PLLSRC_HSE
|
RCC_PLLMULL10
);
/* Enable PLL */
RCC
->
CTLR
|=
RCC_PLLON
;
/* Wait till PLL is ready */
while
((
RCC
->
CTLR
&
RCC_PLLRDY
)
==
0
)
{}
/* Select PLL as system clock source */
RCC
->
CFGR0
&=
(
uint32_t
)((
uint32_t
)
~
(
RCC_SW
));
RCC
->
CFGR0
|=
(
uint32_t
)
RCC_SW_PLL
;
/* Wait till PLL is used as system clock source */
while
((
RCC
->
CFGR0
&
(
uint32_t
)
RCC_SWS
)
!=
(
uint32_t
)
0x08
)
{}
}
#endif // defined(CH32V10x)
#endif // defined(CH32V10x)
#ifdef CH32V003
#ifdef CH32V003
...
...
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ch32v003fun/ch32v003fun.h
+
2
−
0
View file @
c01ffcd2
...
@@ -12173,6 +12173,8 @@ void SystemInit144HSE( void );
...
@@ -12173,6 +12173,8 @@ void SystemInit144HSE( void );
// Initialization functions
// Initialization functions
void SystemInit72HSI( void );
void SystemInit72HSI( void );
void SystemInit72HSE( void );
void SystemInit72HSE( void );
void SystemInit80HSI( void );
void SystemInit80HSE( void );
#endif
#endif
...
...
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examples_v10x/blink/blink.c
+
2
−
2
View file @
c01ffcd2
// Could be defined here, or in the processor defines.
// Could be defined here, or in the processor defines.
#define SYSTEM_CORE_CLOCK
72
000000
#define SYSTEM_CORE_CLOCK
80
000000
#include
"ch32v003fun.h"
#include
"ch32v003fun.h"
#include
<stdio.h>
#include
<stdio.h>
int
main
()
int
main
()
{
{
SystemInit
72
HSE
();
SystemInit
80
HSE
();
// Enable GPIOs
// Enable GPIOs
//RCC->APB2PCENR |= RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOC;
//RCC->APB2PCENR |= RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOC;
...
...
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